JPH04121896A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable an arbitrary alternation of the quantity of bits for an output data by providing a bits quantity settingmeans arbitrarily specifying the bit widths of output data for a memory array from the outside and an address offsetting means dividing a memory space of the aforementioned array in accordance with the aforementioned setting. CONSTITUTION:A code CB for setting the bits quantity is outputted by the bits quantity setting means 6 in the manner of inputting control signals D0,D1 specifying the bit widths to be outputted from the memory cell array 3, to the means 6. By this code CB, the address offsetting means 1 outputs an apparent address signal Aout for, e.g., equally dividing the memory space of array 3. By this signal Aout, the memory space is divided to the area in the bits quantity corresponding to an input address signal Ain, and the memory space only corresponding to the bit specified by the code CB is regarded as effective, then the output is produced. The unused memory spaces are left in the usable state as they are. Thus, one array 3 can be used freely alterable by the code CB, and the outputs of the bits quantity in the wide variety are obtainable.

Description

[Detailed description of the invention] [Summary] DRAM, SRAM, EFROM or EEFROM
Regarding semiconductor storage devices (hereinafter referred to as memories) such as
In particular, regarding a semiconductor memory device that has a degree of freedom in the number of bits of output data, the purpose is to provide a semiconductor memory device in which the number of bits of output data can be arbitrarily changed even if it is a single memory. a memory cell array having a memory space consisting of; a bit number setting means for outputting a bit number setting code for arbitrarily specifying the bit width of output data of the memory cell array by an external control signal; and address offset means for outputting a signal for dividing the memory space of the memory cell array.

[Industrial application field]

The present invention applies to DRAM, SRAM SEPROM or E
Semiconductor storage devices (hereinafter referred to as memory) such as EFROM.

), and particularly relates to a semiconductor memory device having a degree of freedom in the number of bits of output data.

In recent years, memories have been trending toward larger capacities due to advances in miniaturization technology in semiconductor manufacturing technology, and memories with larger memory capacities per chip are now mainstream. Therefore, small capacity memories are on the decline.

However, depending on the application, not only large-capacity memory but also small-capacity memory may be required. Particularly in cases where the number of bits of the data bus is set first, large-capacity memory may be necessary. It is not economical to use it, and it is also difficult to use. The present invention relates to a memory configuration suitable for such cases.

[Conventional technology]

Conventionally, memory has generally been based on standards set at the time of design, such as m
Usually, a single usage is specified, such as word X bits, and the degree of freedom for different usages is not considered. Even if there is some degree of freedom,
Approximately two types of word X bit configurations were possible by setting external pins. Moreover, most of these memories have a large capacity.

[Problem to be solved by the invention]

However, depending on the user, although a certain amount of memory capacity is sufficient, a memory with an output data width that matches the number of bits (width) of the data node to be used may be required. In this case, it is difficult to find memory that is compatible with the data bus, and even if you try to match the required number of data bus bits by using multiple small-capacity memories, it is difficult to find a memory that is compatible with the data bus. Problems such as increase in space and cost arise.

An object of the present invention is to provide a semiconductor memory device in which the number of bits of output data of a single memory can be arbitrarily changed.

[Means to solve the problem]

As shown in FIG. 1, the present invention provides a memory cell array 100 having a memory space made up of a plurality of memory cells, and the bit width of output data of the memory cell array 100 is arbitrarily designated by an external control signal D SD . a bit number setting means 102 that outputs a bit number setting code CB; and a bit number setting means 102 that outputs a bit number setting code CB;
and address offset means 101 for outputting an address signal for dividing the memory space of 00.

[Effect]

According to the present invention, by inputting the control signal Do1D1 specifying the bit width to be output from the memory cell array 100 to the bit number setting means 1,
02 outputs a bit number setting code CB. With this bit number setting code CB, the address offset means 1
01 is an apparent address signal A for equally dividing the memory space of the memory cell array 100, for example.
Outputs On+. This address signal A divides the memory On+ space into areas with the number of bits corresponding to the input address signal A, and only the memory space corresponding to the bit specified by the bit number setting code CB is made valid and produces an output. Become. Memory space that is not used remains in use. In this way, the bit number setting code C
B allows one memory cell array 100 to be freely changed and used, making it possible to output various numbers of bits.

〔Example〕

Next, preferred embodiments of the present invention will be described based on the drawings.

FIG. 2 shows an embodiment of the present invention. In FIG. 1, a memory cell array 3 has a predetermined memory capacity (for example, IMb
It has a memory cell of (it), and an input buffer 2 is connected to its input stage. The input buffer 2 is composed of a register for temporarily holding the input output address A. An address offset unit 1 is connected upstream of the input buffer 2 . The address offset unit 1 equally divides the memory space of the memory cell array 3 according to the number of bits set by the bit number setting unit 6 from the input address A, and assigns an apparent value to each divided memory space. This is for outputting the output address A to the input buffer 72, and its details are explained in the third section along with the configuration of the bit number setting section 6.
This will be described later using figures.

On the other hand, a data position conversion buffer 4 and an input/output switching buffer 5 are connected to the output stage of the memory cell array 3. The data position conversion buffer 4 is a register that rearranges the data output from the memory cell array 3 according to the bit width to be output based on the bit number code CB from the bit number setting section 6. The input/output switching buffer 5 is a register for switching between data output to the data bus and data input from the data bus.

FIG. 3 shows an example of the address offset section 1 and the bit number setting section 6. The bit number setting unit 6 includes a bit number setting register 7 that outputs a bit number code CB (see FIG. 4) according to the logic combination of bit number switching control data (input from the outside) DolDl, and a bit number setting register 7 that outputs a bit number code CB (see FIG. 4). The offset address corresponding to the number of output bits is 16 bit area 9.
ROM8 which is stored in separate areas such as area 10 for 8 bits, area 11 for 4 bits, area 9 for each 16 bits, area 10 for gbits, area 11 for 4 bits.
A selector 12 selects and outputs the offset address of the bit number code CB from the bit number setting register 7 as a switching signal.

ROM8 16bit area 9.8bit area 1
In the 0.4 bit area 11, offset addresses are set for setting the desired bit width. For example, when the bit width is 16 bits, 16 addresses, 8 bits are set.
If it is t, there are eight addresses, and if it is 4 bits, there are four addresses, and the memory space of the memory cell array 3 is divided into the number of offset addresses. Therefore, if it is 16 bits, the memory space is divided into 16, 8 bits.
If it is t, it is divided into 8 parts, if it is 4 bits, it is divided into 4 parts, and so on. A specific example thereof will be described later with reference to FIGS. 5 and 6.

The address offset unit 1 includes an address adder 13 that adds the address value from the selector 12 to the target address ADR in accordance with the bit number code CB from the bit number setting register 7, and outputs the output address A to the memory cell array. Output nj to 3.

Next, the operation will be explained with reference to FIGS. 2 and 3.

First, in the case of writing from the data bus to the memory cell array 3, the input/output switching buffer 5 is switched to the input mode. At this time, the memory cell array 3 is selected by the chip select signal C8, and the write enable signal W
When is given, the bit number setting section 6 outputs the bit number code CB corresponding to the combination of data D and D1 on the data bus to the address offset section 1) input buffer 2) memory cell array 3 and data position conversion buffer 4. .

The form of the bit number code CB specified by the combination of data Do and data Dl is as shown in FIG. With this bit number code CB, as shown in FIG.
One of the offset addresses of the bit area 10 and the 4-bit area 11 is selected and given to the address adder 13. The address adder 13 adds the offset address to the sudden address ADH and provides it to the input buffer 2 as an output address A. The input buffer 2 equally divides the memory space of the memory cell array 3 based on the output address A and the bit number code CB, and for each divided memory space (area),
The added output addresses A are respectively assigned and output. Due to this division, the bit number setting unit 6 acts as a memory having a memory space for each bit number obtained by dividing the total number of bits (for example, IMbit) by the number of bit number codes CB (16 bits, 8 bits, 4 bits, etc.). Become. For example, if the bit number code CB represents 4 bits, the bit number setting section 6 of IMbit is 256K.
Forms 4 memory spaces for each bit, 8bit
In the case of 16 bits, 8 memory spaces are formed for each 128 Kbit, and in the case of 16 bits, 16 memory spaces are formed for each 64 Kbit. Then, the data position conversion buffer 4 rearranges the data according to the bit number code CB so that only the bit position corresponding to the bit number is valid, and puts the terminal corresponding to the unused bit into a high impedance state, for example. .

For example, when the bit number code CB is 4 bits, the valid data is D o "-D 3, and the remaining D4 to D are in a high impedance state. Similarly, when the bit number code CB is 8t)it, .

~D is valid and D''=D 1s is no 1 impedance, and if the bit number code CB is 16 bits, DO
-D16 are all valid. Only the data designated in this way is made valid, and data from the data bus with the number of bits corresponding to the number of bits code CB is written into the memory cell array 3. The above is an operation for writing, but the same is true for reading, and the same operation is performed when the input/output switching buffer 5 is switched to the output mode.

Next, specific examples are shown in FIGS. 5 and 6. Note that, to simplify the explanation, only the main parts are shown. First, the fifth
The figure shows an example in which an IMbit memory cell array 3 is connected to a 4-bit data bus. If input address Ain is “0OOOH”, output address A
is set to "0OOOH", "4000H", "8000H" by the bit number setting section 6 and address offset section 1.
The four addresses "COOOH'" are simultaneously output and applied to the memory cell array 3. Note that H indicates hexa (16 paths).

At this time, the memory cell array 3 has 4 cells each having 256 Kbits.
divided into two memory spaces. Then, the output data is read out one by one from each memory space, and the 4bit data of Do to D3 are read out one by one from each memory space.
It is output to the data bus with a width of t. Figure 6 shows IMbit
An example is shown in which a memory cell array 3 is connected to an 8-bit data bus. In this case as well, it is the same as the 4-bit case, and the memory cell array 3 is output at the output address A.
The memory is divided into eight memory wj spaces of 128 Kbit each, and the 8-bit output data D from D to D7 is
occurs. The same holds true for 16 bits.

In this way, by setting the bit number code CB, even large-capacity memories can be used according to the number of bits of the data bus used, so the arrangement space can be reduced compared to using multiple small-capacity memories. This also makes it possible to reduce costs.

In addition, there is no need to manufacture large-capacity memories with different capacities, and it is sufficient to manufacture large quantities of the same capacity, making it possible to prevent the manufacturing process from becoming complicated and reduce unit costs. From the user side, it is easy to use because there is a degree of freedom in setting the number of input and output bits.

〔Effect of the invention〕

As described above, according to the present invention, the number of input/output bits of the memory cell array can be arbitrarily changed by the address offset means and the bit number setting means. As a result, there is no need to manufacture semiconductor storage devices with a wide variety of memory capacities, and there is no need to unnecessarily combine small-capacity memories, contributing to miniaturization of installation space and cost reduction.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a block diagram showing an example of an address offset section and a bit number setting section, and Fig. 4 is a block diagram showing an example of the bit number setting section. An explanatory diagram of the operation of the setting register, FIG. 5 is a block diagram showing a specific example when the width is set to 4 bits, and FIG. 6 is a block diagram showing a specific example when the width is set to 8 bits. 100...Memory cell array 101...Address offset means 102...Bit number setting means 103...Output switching means 1...Address offset section 2...Input buffer 3...Memory cell array 4...・Data position conversion buffer 5...Input/output switching buffer 6...Bit number setting section 7...Bit number setting register 8...ROM 9...16 bit area 10...Gbit area 11...4-bit area 12...Selector 13...Address adder A...Input address A...Output address n ADR...Output address D...Output data 0U) DO""DI5 ...Data C8...Chip select signal CB...Bit number code

Claims (1)

[Scope of Claims] 1) A memory cell array (100) having a memory space made up of a plurality of memory cells, and a bit width of output data of the memory cell array (100) can be arbitrarily set by an external control signal (D_0, D_1). a bit number setting means (102) for outputting a bit number setting code (CB) specified for the bit number setting code (CB);
a semiconductor memory device comprising: address offset means (101) for outputting an address signal for dividing the memory space of the memory cell array (100) according to the memory cell array (CB); 2) The semiconductor memory device according to claim 1, wherein the address offset means (101) equally divides the memory space according to a bit number setting code (CB). 3) In the semiconductor memory device according to claim 1 or 2,
Between the memory cell array (100) and the data bus,
A semiconductor memory device comprising a switching means (103) for switching the input/output state of data to the memory cell array (100).