JPH04125687A - Plane display device and gradation displaying system - Google Patents

Abstract

PURPOSE:To enable a gradation display more than the number of the gradations of the driving circuit of a pulse width modulation by inputting a part of gradation display data of plural bits to a dot pattern generating circuit which generates the patterns driving and thining by a dot unit, and controlling the gradation displaying data of other pulse width modulations by the output. CONSTITUTION:The above system is equipped with a thining pattern generating circuit 1, and a thining drive controlling circuit 2. Then, a part of the display data of the plural bits is divided in order to operate a gradation expression, the weighting of the gradation expression is operated from the data, and the thining drive control to indicate a gradation degree according to how many times the data are driven as the display data in a unit time, is executed. Moreover, the display data of the plural bits of the other groups having the same number of bits with the driving circuit IC of the pulse width modulation are inputted to a pulse width modulating circuit, and the display data of the other groups are controlled by the signals of the thining drive control of the thining drive controlling circuit 2, so that the thining drive control is combined with the pulse width modulation. Thus, the gradation display more than the gradation function of the driving circuit IC of the pulse width modulating system can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flat display device equipped with a pulse width modulation driving IC, and a gradation display method thereof.

[Summary of the invention]

The present invention aims to provide a display method for realizing a gradation display that is higher than the gradation function of a pulse width modulation type drive circuit IC. In other words, by dividing a part of multiple bits of display data to express gradation, weighting the gradation expression from that data and determining the degree of gradation based on how many times it is driven as display data within a unit time. Executes thinning drive control for displaying. Then, display data of multiple bits of other groups having the same number of bits as the pulse width modulation drive circuit IC is generated by the manual power of the pulse width modulation circuit, and the display data of other groups is controlled by the thinning drive control signal. By combining thinning drive control and pulse width modulation, it is possible to eliminate flicker, which has been a problem in the past, and to provide a multi-gradation display system that exceeds the performance of the drive circuit IC.

(Prior Art) FIG. 4 is a system configuration diagram showing a display system in a conventional two-gradation display system.

In FIG. 4, 41 is a personal computer, 42
43 is an interface circuit, and 43 is a flat display device such as a liquid crystal. Video signals such as display data D, horizontal synchronization signal Hsyc, and vertical synchronization signal Vsyc from the personal computer 41 are input to an interface circuit 42 . An interface circuit 42 converts data DA necessary for operating the flat display device from the video signal.
TA, noft clock signal CL2, latch signal CLI,
This is a circuit for generating interface signals such as a frame signal FRM and a polarity inversion signal M. The flat display device 43 incorporates a display element using a liquid crystal display element, a light emitting diode, or the like, and a circuit for driving the display element. The drive circuit of the flat panel display device t43 performs a 0N10FF display drive operation on input display data, and because it does not have a gradation Sj1 function, it displays two gradations.

[Problem to be solved by the invention] As mentioned above, the conventional display dot 0N10FF
When a drive circuit for display operation was used, since there was no gradation display function, gradation display was performed by frame thinning.

The gradation display method using frame thinning is possible with up to 8 gradation levels in the case of non-active baffles, which have a slow response speed, but because the response speed is slow and the viewing angle range is narrow, etc. The display quality could not be said to be fully satisfactory. No flicker, fast response time,
In order to display a display with a wide viewing angle range and a large number of gradations, there is a method of inputting an analog voltage as in the TPT pocket TV that uses drive voltage modulation, but this method is not suitable for large screens such as those used in OA equipment. It is difficult to faithfully express gradations due to waveform distortion at the analog input terminal. On the other hand, when performing pulse width modulation in which a digital signal is input and a decoding circuit built into the drive circuit selects and outputs the drive pulse width, the number of pulse widths must be prepared in accordance with the number of gradations. There is a need. Therefore, in the case of 32-gradation display, 32 types of pulse widths had to be prepared. In this way, in the case of a driving method in which 32 types of pulse widths are prepared and one of them is selected for output, the scale of the output section of the driving circuit 1c becomes large, which increases the 1,000-knob size and increases costs. Ta. The method using frame thinning is effective for non-active liquid crystal display devices, but it is effective for non-linear resistance two-terminal elements or TP
In the case of an active panel with a built-in T, the response speed is about 1/3 times faster than that of a non-active panel, so flicker becomes noticeable, so the limit is 4 gradations, and 8 or 8 gradations. There was a problem in that it could not be used as a display method for 16 gradations.

[Means to solve the problem]

The present invention has been made to solve the above-mentioned problems. The solution to this problem is not the conventional gradation control method using frequency modulation of frame thinning, but a means of controlling 0N10FF on a dot basis by changing the frequency of drive thinning from the gradation display data on a display dot basis, and a 3-bit By combining pulse width modulation means that can display only eight gray levels based on gray scale data, 32 gray levels can be displayed without flickering.

[Effect]

As mentioned above, because drive is thinned out in units of display dots, which is the minimum time unit interval, conventional flicker may occur even in panels with fast response speeds such as active panels with built-in nonlinear two-terminal resistance elements. This method performs gradation display without causing any turbulence. As mentioned above, the display function of the pulse drive circuit has exceeded the limit of 8 gradations using 3-bit gradation data, and the number of gradations has been increased by combining the 4 gradations of the drive interval modulation. This realizes a method that can be expanded to 32 gradations.

(Example) FIG. 1 is a circuit diagram showing one embodiment of the present invention.

1 is a thinning pattern generation circuit, and 2 is a thinning drive control circuit. 3 is a display data control circuit.

The thinning pattern generation circuit 1 is a Frisopfrombe circuit 8.
, 9. Two-stage shift register circuit IL consists of two ring counter circuits made up of 12 NOR circuits 13 and 14, and an AND/sum circuit made up of AND circuits 15, 16, and 17 and an OR circuit. The thinning drive control circuit 2 includes a decoder circuit 19 and an AND circuit 2L 22
．． 23. It is constituted by an AND/sum circuit including an OR circuit 24. The display data control circuit 3 is a switching circuit composed of AND circuits 25, 26, and 27. Next, the operation of FIG. 1 of the present invention will be explained.

The A/D converter circuit 4 is a circuit for converting the data analog signal D+7 voltage from the digital signal Do to D3. Dot clock signal DDCK
is input to the flip-flop circuit 8 and frequency-divided by 1.72.

Similarly, the vertical synchronizing signal Vsyc is input to the flip-flop circuit 9 and frequency-divided by 1/2. These output signals are input to an exclusive OR circuit 10, which outputs an output signal A. The dot clock signal DCK is input to a ternary ring power counter circuit consisting of a shift register circuit 11 and a NOR circuit 13. Further, the vertical synchronizing signal Vsyc is inputted to a ternary ring power counter circuit consisting of a register circuit 12 and a NOR circuit 14. These signals described above are input to the A, ND circuits 15, 16, and 17, and are logically ANDed, and then logically summed by the OR circuit 18. Further, the inverter circuit 20 generates an inverted output signal B.

In FIG. 2, A1 shows a waveform diagram of the output signal of FIG. 1 for an odd numbered frame, and A-2 shows a waveform diagram of an even numbered frame. These timings are repeatedly inverted for each frame by 1/2 thinning. B-1, 8-2, and 8-3 of the output signal B are 1.
2. It can be seen that waveforms in three frames are shown, and 1/3 thinning is performed, and the thinning timing is shifted by 1 dont for each frame. In these waveform diagrams, the H level means that the display data is valid, and the L level means that the display data is invalid. The upper two bits D3. of the gradation display data in FIG.
D4 is input to the decoder circuit, and is decoded to produce output signals XO, X1X2 . Outputs X3. And AN
, D circuit 212223 selects the signals A, B, and the inverted signal of B of the thinning pattern. Therefore, the output signal of the OR circuit 24 is thinned out at a ratio of 1/3.1/2.2/3 times according to the selection of the decode signals XO to X3. The output signal of the OR circuit 24 is input to the AND circuits 25, 26, and 27 in the display data control circuit 3, thereby operating to perform 0N10FF control of D2 from other gradation display data Do. Therefore, when the decoder output signal x3 is the signal "H", the display data is always output as is. Furthermore, when the decoder output signal XO is "H", the gradation display data is thinned out 1/3 times, so even if the gradation display data is the same, the gradation can be displayed with different contrasts. becomes possible. Therefore, even if the pulse width modulation drive circuit has a function of only 8 gray levels with 3-bit gray level display data input, it is possible to combine the 4 gray levels by the dot thinning modulation and the 8 gray levels by the pulse width modulation. This makes it possible to realize 32-gradation display.

FIG. 3 is a system configuration diagram showing an embodiment of a display system using the gradation display circuit shown in FIG. 1 of the present invention. In FIG. 3, DCK is a dot clock signal, Vsyc is a vertical synchronization signal, and D is display data of an analog signal. Display data D from the personal computer 31 is input to the llWl modulation circuit 32 described above. As a result, the A/D-converted digital signal and the spread-out modulated gradation display data BO to B2 are input to the interface circuit 33 together with other interface signals. The interface circuit 33 uses a frame signal FRM and a latch signal CL1 as timing signals.
．． Soft clock signal CL2. B2 is outputted from the alternating current signal M and the gradation display data BO to the flat display device 34. The flat display device is equipped with a drive circuit IC for pulse width modulation driving to drive the display element, so it is possible to realize flicker-free gradation display.

〔Effect of the invention〕

As described above, according to the present invention, thinning is performed for each dot, which is the smallest time unit, and this process is repeated while shifting the timing of thinning for each frame, so that the thinning can be uniformly performed over the entire screen. It is possible to minimize the impact on Therefore, even in an active panel with a fast response speed, four gradations are possible without causing any flicker. Even if the function of the drive circuit mounted on the flat display device is limited to eight gray levels, the gray scale display capability can be increased to 32 gray levels. Therefore, it has become possible to provide the market with laptop-type personal computers that are comparable to CRT display devices. Further, according to this method, the circuit scale of the drive circuit Ic is significantly reduced, so that it has great effects such as reducing the cost of the flat display device.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing waveforms of a thinning pattern generation circuit of the present invention, and FIG. 3 is a flat display system showing an embodiment of the present invention. figure,
FIG. 4 shows the system configuration of a conventional flat display device. 1 ・ ・ 2 ・ ・ 3 ・ 4 ・ ・ C12 Thinning pattern generation circuit/Thinning drive control circuit Display data control circuit A/D converter circuit...Shift register circuit Decoder circuit 41...Personal computer gradation modulation circuit 42...・Interface circuit 43...Flat type display device creator Keisuke Hayashi, patent attorney, Seiko Electronic Industries Co., Ltd.

Claims (2)

[Claims] (1) In a display method that uses multiple bits of gradation display data corresponding to display brightness to display gradations on a flat display device equipped with a pulse width modulation drive circuit, the multiple bits of gradation display data are A part is input to a dot pattern generation circuit for generating a pattern to be thinned out in dot units, and the output of the dot pattern generation circuit is generated by controlling other multi-bit pulse width modulation gradation display data. A gradation display method for a display device, characterized in that a gradation display method for a display device is characterized in that a gradation display is performed in a number of gradations greater than the number of gradations of the pulse width modulation drive circuit. (2) A thinning pattern generating circuit for generating a pattern for thinning out dots in a flat display device that displays gray scales using multiple bits of gray scale display data and implementing a pulse width modulation drive circuit; A thinning control means comprising a decoding means for decoding a part of bit grayscale display data and a thinning pattern of the thinning pattern generation circuit selected from the output of the decoding means, the grayscale of a plurality of bits of brown is A display device comprising a configuration for controlling display data.