JPH04118958A - Multilayered wiring board for surface mounting - Google Patents
Multilayered wiring board for surface mountingInfo
- Publication number
- JPH04118958A JPH04118958A JP2239289A JP23928990A JPH04118958A JP H04118958 A JPH04118958 A JP H04118958A JP 2239289 A JP2239289 A JP 2239289A JP 23928990 A JP23928990 A JP 23928990A JP H04118958 A JPH04118958 A JP H04118958A
- Authority
- JP
- Japan
- Prior art keywords
- outer lead
- pad
- lead
- area
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000012856 packing Methods 0.000 abstract 1
- 230000008859 change Effects 0.000 description 7
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は表面実装用多層型配線基板に係り、特に回路特
性を損なうことなく、回路変更ないし回路修正を容易に
なし得る表面実装用多層型配線基板に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a multilayer wiring board for surface mounting, and in particular allows circuit changes or corrections to be easily made without impairing circuit characteristics. The present invention relates to a multilayer wiring board for surface mounting.
（従来の技術）
たとえば多ピンベアチップＩＣなど、所要の各種電子部
品を配線基板の所定面に、搭載・実装して成る実装回路
基板ないし実装回路装置は、電子回路の小形化などの点
から注目され、広く実用に供されている。(Prior art) Mounted circuit boards or mounted circuit devices, which are made by mounting and mounting various necessary electronic components such as multi-pin bare chip ICs on a predetermined surface of a wiring board, are attracting attention from the viewpoint of miniaturization of electronic circuits. It has been widely used in practical applications.
ところで、多ピンベアチップＩＣを含む複数個の電子部
品を搭載・実装する配線基板の場合は、配線構成など複
雑になり、設計や製造に多くの時間を要するばかりでな
く、回路変更ないし回路修正を要することがしばしばあ
る。このような回路変更などの要求に対し、その都度配
線基板を開発・製造するなど、短期的な対応は事実上困
難である。By the way, in the case of a wiring board that mounts and mounts multiple electronic components, including multi-pin bare chip ICs, the wiring configuration becomes complex, and not only does it take a lot of time to design and manufacture, but it also requires circuit changes or modifications. It is often necessary. It is practically difficult to respond to such requests for circuit changes in the short term, such as by developing and manufacturing wiring boards each time.
こうした事情に対処して、たとえば第３図（ａ）に要部
を断面的に、また第３図（ｂ）に要部を平面的に示すよ
うな構成の表面実装用多層型配線基板が開発されている
。すなわち、絶縁層１を介して所要の内層パターン２が
配設され、また搭載・実装されるベアチップＩＣ３のイ
ンナー１ツートノく・ノド３ａに対応するとともに配線
チエ・ツク端子と回路の機能チェック端子の機能を成す
アウター１ノードパツド４および回路変更用パターン５
が表面に配設されて成る表面実装用多層型配線基板６カ
（使用されている。In response to these circumstances, a multilayer wiring board for surface mounting has been developed, with the main parts shown in cross-section in Figure 3(a) and the main parts shown in plan in Figure 3(b). has been done. That is, the required inner layer pattern 2 is arranged through the insulating layer 1, and corresponds to the inner 1-to-node 3a of the bare chip IC 3 to be mounted and mounted, as well as the wiring check terminal and the circuit function check terminal. Functional outer 1 node pad 4 and circuit modification pattern 5
Six surface-mount multilayer wiring boards (currently in use) have
しかして、前記アウターリードノく・ノド４および回路
変更用パターン５は、互いに離隔して配設され、スルホ
ール接続７ａ、 ７ｂおよび内層）くターン２ａを介し
て電気的に接続し、またＩ／Ｏリード８番よスルホール
接続７Ｃによって前記回路変更用／＜ターン５に接続し
た構成を成している。なお、回路変更など要する場合は
、たとえばダイ、＜ノド９上１こ配置されたベアチップ
ＩＣ３のアウターリード、（ノド３ａとアウターリード
バッド４とを接続するＡＵワイヤーｌＯのボンディング
変更によって行うようになっている。Thus, the outer lead nozzle/node 4 and the circuit change pattern 5 are arranged apart from each other, and are electrically connected via the through hole connections 7a, 7b and the inner layer turn 2a. The O lead No. 8 is connected to the circuit change/< turn 5 by a through-hole connection 7C. If a circuit change is required, for example, it can be done by changing the bonding of the die, the outer lead of the bare chip IC3 placed once on the node 9, and the AU wire lO connecting the node 3a and the outer lead pad 4. ing.
（発明が解決しようとする課題）
しかしながら、上記構成の表面実装用多層配線基板６の
場合は、実用上次のような不具合力くある。すなわち回
路変更用ノくターン５とアウターリ−ドバッド４とが、
前記したよう；；分離した形でそれぞれ配線基板６表面
に形設されて−）るため、電子部品の搭載・実装可能な
面積が低減する。つまり、所要電子部品の実装密度が制
約され、実装回路装置ないし実装回路基板のコンノ々ク
トイヒの支障となっている。しかも、前記回路変更用、
＜ターン５は、回路変更を要しないと無用の長物であり
、むしろ信号配線の長尺化となって特性的１こ悪影響を
及ぼす恐れもある。(Problems to be Solved by the Invention) However, in the case of the surface mounting multilayer wiring board 6 having the above structure, there are the following practical problems. In other words, the circuit change turn 5 and the outer lead pad 4 are
As described above, since they are separately formed on the surface of the wiring board 6, the area on which electronic components can be mounted and mounted is reduced. In other words, the mounting density of the required electronic components is restricted, which is a hindrance to the interconnection of mounted circuit devices or mounted circuit boards. Moreover, for changing the circuit,
<Turn 5 is an unnecessary long piece unless a circuit change is required, and if anything, the signal wiring becomes longer, which may have an adverse effect on the characteristics.
本発明は上記事情に対処して成されたもので、電子部品
の搭載・実装領域面を比較的広く確保でき、しかも配線
パターン（信号配線）の長尺イヒも防止された表面実装
用多層配線基板の提供を目的とする。The present invention has been developed in response to the above-mentioned circumstances, and is capable of securing a relatively wide mounting/mounting area for electronic components, and also prevents the occurrence of long wiring patterns (signal wiring). The purpose is to provide substrates.
［発明の構成］
（課題を解決するための手段）
本発明は、少な（とも表面にベアチ・ノブＩＣを含む複
数個の電子部品を搭載する領域および前記搭載する電子
部品のアウターリードボンディングパッドを有し、かつ
前記アウターリードボンディングパッド側に一端が接続
して導出された！／Ｏリードを具備して成る表面実装用
多層型配線基板において、
前記アウターリードボンディング／り・ノドがベアチッ
プＩＣのアウターリードボンディング領域とＩ／Ｏリー
ド接続領域とに切り離し可能に表面に一体に形成され、
かつ配線チェック端子および回路機能チェック端子とし
て使用されることを特徴とするものである。[Structure of the Invention] (Means for Solving the Problems) The present invention provides a small area (on the surface of which a plurality of electronic components including Beati-Knob ICs are mounted and an outer lead bonding pad of the electronic components to be mounted). In a multilayer wiring board for surface mounting comprising an !/O lead having one end connected to the outer lead bonding pad side and led out, A lead bonding area and an I/O lead connection area are separably formed integrally on the surface,
Moreover, it is characterized in that it is used as a wiring check terminal and a circuit function check terminal.
（作用）
上記構成においては、ベアチップＩＣのアウターリード
ボンディングされるアウターリードボンディングパッド
と配線チェック端子および回路機能チェック端子として
使用されるＩ／Ｏリード接続用パターンとが切り離し可
能に一体に形設されている。つまり、アウターリードボ
ンディングパッドとＩ／Ｏリード接続用パターンと基板
表面で直接連接し、スルホール接続および内層パターン
を不要としている。このため、電子部品の搭載・実装可
能な表面積の確保は容易となり、実装密度の向上を図り
得るとともに、信号配線の抵抗低減なども達成し得る。(Function) In the above configuration, the outer lead bonding pad to which the outer lead of the bare chip IC is bonded and the I/O lead connection pattern used as the wiring check terminal and circuit function check terminal are integrally formed in a separable manner. ing. In other words, the outer lead bonding pad and the I/O lead connection pattern are directly connected on the substrate surface, eliminating the need for through-hole connections and inner layer patterns. Therefore, it is easy to secure a surface area on which electronic components can be mounted and mounted, and it is possible to improve the packaging density and reduce the resistance of signal wiring.
（実施例）
以下第１図（ａ） 、 （ｂ）および第２図を参照して
本発明の詳細な説明する。(Example) The present invention will be described in detail below with reference to FIGS. 1(a) and 2(b) and FIG.
第１図（ａ）は本発明に係る表面実装用多層型配線基板
の要部構成を断面的に、また第１図（ｂ）は同じく要部
構成を平面的に示したもので、絶縁層１１を介して所要
の内層パターン１２が配設され、また表面には、搭載・
実装されるベアチップＩＣｌ３のインナーリードバッド
１８ａに対応するアウターリードバッド１４が配設され
た構成を成している。FIG. 1(a) shows a cross-sectional view of the main part of a multilayer wiring board for surface mounting according to the present invention, and FIG. 1(b) shows a planar view of the main part of the same, showing the A required inner layer pattern 12 is disposed through the layer 11, and the surface is provided with mounting and
It has a configuration in which outer lead pads 14 corresponding to inner lead pads 18a of the bare chip ICl3 to be mounted are provided.
しかして、この表面実装用多層型配線基板１６において
は、前記アウターリードバッド１４は、ベアチップＩＣ
ＩＩのインナーリードバッド１８ａに対応するアウター
リードバッド領域１４ａとＩ／Ｏリード接続領域１４ｂ
とが一体化した形を成して形設されており、またこのア
ウターリードノく・ソド１４は配線チェック端子および
回路の機能チェック端子の機能をもなす。つまり、アウ
ターリードボンディングパッド１４は、ベアチップＩＣ
ｌ３に対するアウターリードボンディング領域１４ａと
Ｉ／Ｏリード接続領域１４ｂとに、たとえばレーザーカ
ットによって容易に切り離しできるように、両端側を膨
大とし中央の幅狭の部分で切り離し可能な形状に形成さ
れている。しかも、このアウターリードバッド１４ 、
たとえば前記Ｉ／Ｏリード接続領域１４ｂが配線チェッ
ク端子および回路機能チェック端子として使用される構
成となっている。なお、図において１８はスルホール接
続１７ｃを介して前記のＩ／Ｏリード接続領域１４ｂに
接続し、導出されたＩ／Ｏリード端子であり、１９はダ
イパッドである。Therefore, in this multilayer wiring board 16 for surface mounting, the outer lead pad 14 is connected to a bare chip IC.
Outer lead pad area 14a and I/O lead connection area 14b corresponding to inner lead pad 18a of II
The outer lead terminal 14 also functions as a wiring check terminal and a circuit function check terminal. In other words, the outer lead bonding pad 14 is connected to the bare chip IC.
The outer lead bonding area 14a and the I/O lead connection area 14b for l3 are formed in a shape that is enlarged at both ends and can be separated at a narrow part in the center so that they can be easily separated by laser cutting, for example. . Moreover, this outer lead bad 14,
For example, the I/O lead connection area 14b is configured to be used as a wiring check terminal and a circuit function check terminal. In the figure, 18 is an I/O lead terminal connected to the I/O lead connection area 14b via a through-hole connection 17c and led out, and 19 is a die pad.
このように構成された本発明に係る表面実装用多層配線
基板１６においては、たとえばベアチップＩＣｌ３に対
するワイヤーボンディング２０が、前記アウターリード
バッド１４のアウターリードボンディング領域１４ａと
の間でなされる。しかして、回路変更ないし修正を要す
る場合には、前記アウターリードバッド１４をたとえば
レーザーカットによって、アウターリードボンディング
領域１４ａとＩ／Ｏリード接続−領域１４ｂとに切り離
し、他の所要のアウターリードボンディング領域１４ａ
とＩ／Ｏリード接続領域１４ｂとの間をワイヤーボンデ
ィングすれば、容易に所望の回路変更を行ない得る。In the multilayer wiring board 16 for surface mounting according to the present invention configured in this way, wire bonding 20 to the bare chip ICl3 is performed between the outer lead bonding region 14a of the outer lead pad 14, for example. If a circuit change or modification is required, the outer lead pad 14 is separated into an outer lead bonding area 14a and an I/O lead connection area 14b by, for example, laser cutting, and other required outer lead bonding areas are cut. 14a
By wire bonding between the I/O lead connection area 14b and the I/O lead connection area 14b, desired circuit changes can be easily made.
なお、この場合はアウターリードボンディング領域１４
ａが回路の機能チェック端子の役割をなす。Note that in this case, the outer lead bonding area 14
A serves as a function check terminal of the circuit.
上記したように本発明に係る表面実装用多層配線基板は
、回路変更などが可能であるばかりでなく、電子部品の
表面実装領域を十分確保し得る。As described above, the multilayer wiring board for surface mounting according to the present invention not only allows circuit changes, etc., but also allows a sufficient surface mounting area for electronic components to be secured.
しかも、冗長パターンを最小限に抑え得るので、配線抵
抗も低く保持でき、実装回路装置を構成した場合も良好
な特性を発揮する。Furthermore, since redundant patterns can be minimized, wiring resistance can be kept low, and good characteristics can be exhibited when a mounted circuit device is constructed.
第２図は本発明に係る表面実装用多層配線基板の他の構
成例の要部を断面的に示したもので、たとえばゲートア
レイなど大面積ベアチップＩＣの搭載・実装用に適する
ビングリッドアレイ型配線基板である。この表面実装用
多層配線基板においては、多ビン化に伴いＩ／Ｏリード
端子１８が、前記大面積ベアチップＩＣｌ３を搭載・実
装する位置の下側にも導出する場合がある。この場合、
前記Ｉ／Ｏリード端子１８ケースは、スルホール接続１
７ｃ１内層パターン１２ａおよびスルホール接続１７ａ
を介してアウターリードバッド１４のＩ／Ｏリード接続
領域１４ｂに接続されているが、前記アウターリードボ
ンディング領域１４ａとＩ／Ｏリード接続領域１４ｂと
の一体化によって、配線パターンの冗長も大幅に改善さ
れる。つまり、従来の場合のように、配線パターンの迂
回的な配役が回避され、配線（信号配線）抵抗もそれだ
け低減し、良好な特性を有する実装回路装置の構成が可
能となる。FIG. 2 is a cross-sectional view of the main part of another example of the structure of the multilayer wiring board for surface mounting according to the present invention. It is a wiring board. In this multilayer wiring board for surface mounting, as the number of bins increases, the I/O lead terminals 18 may be led out below the position where the large-area bare chip ICl3 is mounted and mounted. in this case,
The I/O lead terminal 18 case has through-hole connection 1
7c1 inner layer pattern 12a and through hole connection 17a
The wiring pattern is connected to the I/O lead connection area 14b of the outer lead pad 14 through the integration of the outer lead bonding area 14a and the I/O lead connection area 14b, which greatly improves the redundancy of the wiring pattern. be done. In other words, as in the conventional case, the detouring of the wiring pattern is avoided, the wiring (signal wiring) resistance is reduced accordingly, and a mounted circuit device having good characteristics can be constructed.
［発明の効果］
上記説明したように、回路変更用の表面パターン層（Ｉ
／Ｏリード接続領域）とアウターリードボンディング領
域とを切離可能に一体化し、これらの占有面積を全体的
に低減するとともに、スルホール接続数などの低減によ
る配線パターンの冗長化を回避した、本発明に係る表面
実装用多層型配線基板は、電子部品の実装可能な面積を
比較的広く確保でき、これによって実装密度の向上も容
易に図り得る。しかも、スルホール接続の低減などによ
り配線抵抗も低下するため、実装回路として良好な機能
ないし性能の保持発揮にも大きく寄与する。[Effect of the invention] As explained above, the surface pattern layer (I
/O lead connection area) and the outer lead bonding area are separably integrated, thereby reducing the area occupied by these as a whole, and avoiding redundancy in wiring patterns due to reduction in the number of through-hole connections, etc. The multilayer wiring board for surface mounting according to the above can secure a relatively large area on which electronic components can be mounted, and thereby can easily improve the mounting density. In addition, wiring resistance is also reduced by reducing through-hole connections, which greatly contributes to maintaining and exhibiting good functionality and performance as a mounted circuit.
第１図（ａ）は本発明に係る表面実装用多層型配線基板
の要部構成例を示す断面図、第１図（１））は第１図（
ａ）に図示した表面実装用多層型配線基板の要部平面図
、第２図は本発明に係る表面実装用多層型配線基板の他
の要部構成例を示す断面図、第３図（ａ）は従来の表面
実装用多層型配線基板の要部構成を示す断面図、第３図
（ｂ）は第３図（ａ）に図示した表面実装用多層型配線
基板の要部平面図である。
１．１１・・・・・・絶縁層
２、２ａ、１２，１２ａ −内層パターン３．１３・・
・・・・ベアチップＩＣ
３ａ、１３ａ・・・・・・ベアチップＩＣのアウターリ
ードパッド
４ １４・・・・・・アウターリードパッド１４ａ・・
・・・・・・・アウターリードボンディング領域１４ｂ
・・・・・・・・・Ｉ／Ｏリード接続領域５・・・・・
・・・・・・・回路変更用パターン６．１６・・・・・
・表面実装用多層配線基板７ａ、７ｂ、７ｃ、１７ｃｍ
・−・−・スルホール接続８．１８・・・・・・Ｉ／Ｏ
リード
９．１９・・・・・・ダイパッド
／Ｏ．２０・・・・・・ボンディングワイヤ出願人
株式会社 東芝
代理人 弁理士 須 山 佐 −
第３図
℃、FIG. 1(a) is a cross-sectional view showing an example of the main part configuration of a multilayer wiring board for surface mounting according to the present invention, and FIG.
FIG. 2 is a cross-sectional view showing another example of the structure of the main part of the multilayer wiring board for surface mounting according to the present invention, and FIG. ) is a sectional view showing the configuration of the main parts of a conventional multilayer wiring board for surface mounting, and FIG. 3(b) is a plan view of the main parts of the multilayer wiring board for surface mounting shown in FIG. 3(a). . 1.11... Insulating layer 2, 2a, 12, 12a - inner layer pattern 3.13...
...Bare chip IC 3a, 13a...Bare chip IC outer lead pad 4 14...Outer lead pad 14a...
...Outer lead bonding area 14b
......I/O lead connection area 5...
......Circuit change pattern 6.16...
・Multilayer wiring board for surface mounting 7a, 7b, 7c, 17cm
・−・−・Through hole connection 8.18・・・・・・I/O
Lead 9.19...Die pad/O. 20・・・Bonding wire applicant
Toshiba Corporation Representative Patent Attorney Sasa Suyama - Figure 3℃,
Claims (1)
部品を搭載する領域および前記搭載する電子部品のアウ
ターリードボンディングパッドを有し、かつ前記アウタ
ーリードボンディングパッド側に一端が接続して導出さ
れたＩ／Ｏリードを具備して成る表面実装用多層型配線
基板において、前記アウターリードボンディングパッド
がベアチップＩＣのアウターリードボンディング領域と
Ｉ／Ｏリード接続領域とに切り離し可能に表面に一体的
に形成され、かつ配線チェック端子および回路機能チェ
ック端子として使用されることを特徴とする表面実装用
多層型配線基板。An I/O device having at least a surface area for mounting a plurality of electronic components including bare chip ICs and an outer lead bonding pad for the electronic components to be mounted, and having one end connected to the outer lead bonding pad side and led out. In a multilayer wiring board for surface mounting comprising an O-lead, the outer lead bonding pad is integrally formed on the surface of the bare chip IC so as to be separable into an outer lead bonding area and an I/O lead connection area, and A multilayer wiring board for surface mounting, characterized in that it is used as a wiring check terminal and a circuit function check terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2239289A JPH04118958A (en) | 1990-09-10 | 1990-09-10 | Multilayered wiring board for surface mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2239289A JPH04118958A (en) | 1990-09-10 | 1990-09-10 | Multilayered wiring board for surface mounting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04118958A true JPH04118958A (en) | 1992-04-20 |
Family
ID=17042524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2239289A Pending JPH04118958A (en) | 1990-09-10 | 1990-09-10 | Multilayered wiring board for surface mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04118958A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5757078A (en) * | 1995-04-27 | 1998-05-26 | Nec Corporation | Semiconductor device with increased multi-bumps and adhered multilayered insulating films and method for installing same |
| US6376906B1 (en) | 1997-02-12 | 2002-04-23 | Denso Corporation | Mounting structure of semiconductor element |
| CN114900953A (en) * | 2022-04-19 | 2022-08-12 | 微智医疗器械有限公司 | Method and assembly for connecting multiple electronic elements and circuit board and electronic equipment |
-
1990
- 1990-09-10 JP JP2239289A patent/JPH04118958A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5757078A (en) * | 1995-04-27 | 1998-05-26 | Nec Corporation | Semiconductor device with increased multi-bumps and adhered multilayered insulating films and method for installing same |
| US6376906B1 (en) | 1997-02-12 | 2002-04-23 | Denso Corporation | Mounting structure of semiconductor element |
| CN114900953A (en) * | 2022-04-19 | 2022-08-12 | 微智医疗器械有限公司 | Method and assembly for connecting multiple electronic elements and circuit board and electronic equipment |
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