JPH04118734A - Interruption controller - Google Patents

Abstract

PURPOSE:To inform the generation of abnormality to a CPU by sending out an error interruption vector, in the case an input channel corresponding to an interruption vector to be sent out does not exist, and the interruption vector comes to indefinite even if there is an interruption request. CONSTITUTION:The controller is provided with an arbitrating means 3 for determining an input channel for sending out an interruption vector, a selecting means 11 for selecting and sending out the interruption vector corresponding to the input channel determined by the arbitrating means 3, and an error interruption vector storage means 13 for storing an error interruption vector sent out instead of the interruption vector in the case the input channel for sending out the interruption vector is not determined at the time of interrupting receiving cycle. In such a state, at the time of interruption receiving cycle, in the case the channel corresponding to the interruption vector to be sent out does not exist, and the interruption vector becomes indefinite, the error interruption vector stored in the erroneous interruption vector storage means 13 is sent out to a CPU. In such a way, it can be informed to the CPU that the abnormality is generated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an interrupt control device that receives a plurality of interrupt signals and sends an interrupt vector in response to a request from a central processing unit. .

(Prior Art) An interrupt control device that inputs and arbitrates multiple interrupt signals from peripheral devices and notifies a central processing unit (hereinafter referred to as CPU) of a processing request is used for a device control device. There is. In particular, an interrupt control device that allows the CPU to set the priority order and interrupt vector in detail for each interrupt input channel is called a programmable interrupt control device (hereinafter abbreviated as PIC).

FIG. 6 shows the configuration of a conventional interrupt control device.

When the interrupt request input signals INTO to INTn-1 are input to the interrupt input section 1, a signal indicating the presence or absence of an interrupt is output to the interrupt priority arbitration circuit (hereinafter abbreviated as arbitration circuit) 3. The arbitration circuit 3 arbitrates priorities between the mask level and channels making other interrupt requests.

If even one of the channels requesting an interrupt has a priority higher than the mask level, the arbitration circuit 3 recognizes that there is an interrupt and sends an interrupt request signal 103 to the CPU.

When the CPU receives the interrupt request signal 103 and becomes ready to accept an interrupt, it starts an "interrupt acceptance cycle."

In the "interrupt acceptance cycle", the vector selection unit 11
The interrupt vector corresponding to the channel with the highest priority selected by is sent to the CPU via data bus 105.

On the other hand, the types of interrupt request input signals include level types and edge types. For level type, the signal “
High- or "Low" indicates the presence or absence of an interrupt input. For edge type, from “High” to “Low”
A falling change from “LOW” to “HIGH”
A rising edge change to "h" indicates the presence or absence of an interrupt input.

If the interrupt request input signal is an edge type, an interrupt request is recognized by a rising edge change, so an interrupt vector can be sent even if it falls before an interrupt acceptance cycle.

However, in the case of the level type, if all interrupt request input signals are canceled before the interrupt acceptance cycle, even if the PIC can recognize that an interrupt request has been made, it cannot determine the channel to which the interrupt vector should be output. , the transmitted vector becomes undefined. That is, during the interrupt acceptance cycle, the vector selection signal 101 output from the arbitration circuit 3 indicates that there is no interrupt request input, so the vector selection unit 11 can only send an interrupt vector. This can occur due to a failure of the interrupt source or a programming error (for example, if the interrupt source device is an edge type but is programmed as a level type).

(Problem to be Solved by the Invention) As described above, when the interrupt request input signal is of the level type, if all the interrupt request input signals are canceled before the interrupt acceptance cycle, the interrupt vector to be sent becomes undefined. As a result, there is a problem in that the interrupt control device cannot control the peripheral devices.

Therefore, the present invention was made in view of the conventional circumstances, and its purpose is that when the interrupt vector to be sent becomes undefined, the interrupt control device recognizes this and interrupts the interrupt vector. An object of the present invention is to provide an interrupt control device that can send an erroneous interrupt vector instead of a vector and notify a CPU of the occurrence of an abnormality.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention inputs interrupt input signals from a plurality of input channels, and generates interrupts for each input channel based on the interrupt input signals. arbitration means for arbitrating priorities and determining an input channel to which an interrupt vector should be sent; selection means for selecting and sending an interrupt vector corresponding to the input channel determined by the arbitration means during an interrupt acceptance cycle; and an erroneous interrupt vector storage means for storing an erroneous interrupt vector that is sent instead of the interrupt vector when the input channel to which the interrupt vector is to be sent has not been determined during the interrupt acceptance cycle.

Furthermore, the present invention is configured by adding an abnormality occurrence notification means to the above configuration, which counts the number of times an erroneous interrupt vector is sent, and when the count value reaches a preset value, sends a notification signal of an abnormality occurrence. has been done.

(Function) With the above configuration, the present invention is capable of storing an error stored in the error interrupt vector storage means when there is no channel corresponding to the interrupt vector to be sent during an interrupt acceptance cycle and the interrupt vector becomes undefined. Sends the interrupt vector to the CPU.

In addition, this invention counts the number of times an erroneous interrupt vector is sent each time it is sent, and when a preset number of times is reached,
NMI (non-maskable interrupt) that notifies abnormality occurrence
A request signal is sent to the CPU.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an interrupt control device of the present invention.

The interrupt control device shown in the figure has a configuration in which an erroneous interrupt vector storage section 13 is added to the conventional interrupt control device shown in FIG.

The interrupt input section 1 receives an interrupt request input signal INTO~
After receiving INTn-1 and removing noise from these input signals, it outputs a signal to the interrupt priority arbitration circuit (hereinafter abbreviated as arbitration circuit) 3 indicating that there is an interrupt.

The arbitration circuit 3 recognizes from the interrupt input section 1 which channel is issuing the interrupt request.

Then, the mask level storage section 5 is referred to to check the mask level, and the priority storage section 7 is checked to check the respective priorities of the channels making the interrupt request.

Arbitration is performed between the priority and mask level of each of these channels.

That is, if even one of the channels requesting an interrupt has a priority higher than the mask level, the arbitration circuit 3 sends the vector selection signal 101 representing that channel to the vector selection unit 11, and also sends the vector selection signal 101 representing that channel to the vector selection unit 11. It has the role of activating an interrupt request signal 103 to the central processing unit.

The mask level storage section 5 stores a specific level for masking an interrupt request with respect to the interrupt request input signal. This mask level storage section 5 is constituted by a mask register 5a, which will be described later.

The priority storage unit 7 stores interrupt priorities determined depending on the cause of the interrupt. This priority storage section 7 is composed of a plurality of mode registers 7a, which will be described later.

The interrupt vector storage unit 9 stores an interrupt vector, which is information indicating an address to which the CPU should jump when jumping to an interrupt processing routine.

This interrupt vector storage section 9 is composed of a plurality of vector registers 9a, which will be described later.

The vector selection section 11 receives the vector selection signal 101 sent from the arbitration circuit 3 and outputs an interrupt vector to the CPU. That is, the vector selection unit 11
When the CPU enters an interrupt acceptance cycle, the interrupt vector corresponding to the channel to which the interrupt vector is to be sent is read out from the interrupt vector storage section 9 in accordance with the vector selection signal 101, and sent to the CPU via the data bus 105. Furthermore, when there is no channel to which the vector should be sent, the vector selection unit 11 reads the erroneous interrupt vector from the erroneous interrupt vector storage unit 13, and selects a
It has a function to send to PU.

The erroneous interrupt vector storage section 13 stores an erroneous interrupt vector that is sent to the CPU instead of the interrupt vector when the interrupt vector to be sent from the vector selection section 11 is undefined.

This erroneous interrupt vector storage section 13 is constituted by an erroneous interrupt vector register 13a, which will be described later.

FIG. 2 shows a mask level storage section 5, a priority order storage section 7,
2 is a layout diagram of each register that constitutes an interrupt vector storage section 9 and an erroneous interrupt vector storage section 13. FIG.

A plurality of mode registers 7a and vector registers 9a are arranged corresponding to each input channel. Vector register 9a is placed at an address next to mode register 7a. Similarly, the erroneous interrupt vector register 13a is placed at an address adjacent to the mask register 5a.

The mode register 7a contains an interrupt request input signal INT.
An interrupt input type indicating whether O to INTn-1 is a level type or an edge type, and an interrupt priority determined by the cause of the interrupt are set.

Information indicating the address at which the CPU should jump to the interrupt processing routine is set in the vector register 9a.

Note that the interrupt vector, interrupt input type, false interrupt vector, priority, and mask level can be set to 0 by the CPU.

As described above, the interrupt control device of the present invention has a general structure.Next, the present invention will be explained in detail.

FIG. 3(A) is a timing waveform diagram when a normal interrupt vector is sent to the CPU. Here, a case is shown in which interrupt request input signals INTO to INT2 are input from the 0th channel, the 1st channel, and the 2nd channel.

Interrupt request input signal INTo-I is input to interrupt input section 1.
When NT2 is input, a signal indicating that there is an interrupt is output to the arbitration circuit 3.

In the arbitration circuit 3, arbitration of priorities of channels for transmitting mask levels and interrupt vectors is performed every clock. Here, the priority of each channel is higher than the mask level, and the 0th channel is the highest, the first and second
Let's go down in order of channels. That is, 0th>1st>
2nd> mask level. Note that the interrupt input type of all channels is set to level type.

Since the channels making interrupt requests all have a higher priority than the mask level, the vector selection signal 101 as the arbitration result is sent from the arbitration circuit 3 to the vector selection unit 11.
sent to.

Furthermore, the interrupt request signal 103 becomes active,
An interrupt request is made to the CPU.

When the process currently being executed by the CPU ends, the CPU status signal becomes an "interrupt acceptance cycle" by the CPU.

The arbitration result immediately after the interrupt acceptance cycle is
The first channel is considered to be the channel with the highest priority. As a result, the interrupt vector corresponding to the first channel of the "X° bright period" in the figure is sent from the vector selection unit 11 to the CPU via the data bus 105. Here, the interrupt request signal 103 is output to the CPU. Time point (“Y” in the figure)
period), the 0th channel had the highest priority in terms of arbitration results. However, since this arbitration result is canceled before entering the interrupt acceptance cycle, the interrupt vector corresponding to the first channel is sent based on the arbitration result of the "X" period.

Next, the case where an erroneous interrupt vector is sent is shown in Figure 3C.
This will be explained with reference to the timing waveform diagram of B).

In this case, the interrupt request input signals INTO to INT
2 are all canceled before entering the interrupt acceptance cycle. Also, influenced by this, the interrupt request signal 103 also falls after the interrupt acceptance cycle.

As a result, the arbitration result for the "X° light period is that there is no channel to which an interrupt vector should be sent."

This is recognized by the vector selection unit 11, and the erroneous interrupt vector previously stored in the erroneous interrupt vector storage unit 13 is sent to the CPU via the data bus 105.

Note that in the conventional interrupt control device, the data bus 105
Indeterminate was output where indicated by the error interrupt vector above.

In this way, when there is no interrupt vector to be sent, an erroneous interrupt vector is sent instead of an interrupt vector, so that malfunctions of the CPU can be prevented.

(Application Example) By providing the erroneous interrupt vector storage section 13, when an interrupt vector does not exist, it is possible to send out an erroneous interrupt vector and prevent malfunction of the CPU. However, it is conceivable that the erroneous interrupt vector is sent out many times due to an error in setting the erroneous interrupt vector or an abnormality in the erroneous interrupt processing routine. To prevent this, when an erroneous interrupt vector is sent a preset number of times, an NMI (non-maskable interrupt) request can be output to the CPU to notify the CPU of the occurrence of an abnormal situation.

FIG. 4 is a block diagram showing the configuration of an interrupt control device that realizes this.

The interrupt control device shown in the figure has a configuration in which a counter 15 and a zero detection circuit 17 are added to the interrupt control device shown in FIG.

The counter 15 decrements a preset number of times each time an erroneous interrupt vector is sent from the vector selection section 11, and when the count value reaches "0", notifies the zero detection circuit 17 of this. This counter 15 is
There is a down counter with a parallel load function, and an arbitrary number of times is set in advance by the CPU.

The zero detection circuit 17 detects that the count value of the counter 15 is “0”.
”, it has a function to output an NMI request to the CPU.

As shown in FIG. 5, when the vector selection section 11 sends out an erroneous interrupt vector many times, the signal 107 output from the vector selection section 11 to the counter 15 becomes active each time. As a result, the count value is decremented by the counter 15.

When the count value reaches "0", the output of the zero detection circuit 17 becomes active and the NMI request signal 109 is sent to the CPU. The CPU receives this NM* request signal 109 and restarts the process.

In this way, by simply adding the counter 15 and the zero detection circuit 17, it is possible to reliably notify the CPU of the occurrence of an abnormal situation.

[Effects of the Invention] As described above, according to the interrupt control device of the present invention, even though there is an interrupt request, there is no input channel corresponding to the interrupt vector to be sent, and the interrupt vector is When it becomes undefined, a false interrupt vector is now sent instead of the interrupt vector. Thereby, it is possible to notify the CPU that an abnormality has occurred, and the peripheral devices can be controlled normally.

Furthermore, when the number of times that an erroneous interrupt vector is sent reaches a specific number, an NMI request signal is output to the CPU to notify that an abnormality has occurred in the interrupt control device. Thereby, the CPU can reliably detect the occurrence of an abnormality and maintain normal operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the interrupt control device of the present invention, FIG. 2 is a layout diagram showing the arrangement of registers constituting each storage section shown in FIG. 1, and FIG. A waveform diagram showing the timing to send an interrupt vector. Figure 3 (B) is a waveform diagram showing the timing to send an erroneous interrupt vector. Figure 4 shows the configuration of an application example with an added function to output an NMI request signal. FIG. 5 is a waveform diagram showing the timing at which the NMI request signal is output, and FIG. 6 is a block diagram showing the configuration of a conventional interrupt control device. 1... Interrupt input section 3... Interrupt priority arbitration circuit 5... Mask level storage section 5a... Level register 7... Priority storage section 7a... Mode register 9... Interrupt vector Storage unit 9a...Vector register 11--Vector selection unit 13...False interrupt vector 2 Self-storage unit 13a...False interrupt vector register 15...Counter 17...Zero detection circuit

Claims (2)

[Claims] (1) Arbitration means that inputs interrupt input signals from a plurality of input channels, arbitrates the interrupt priority for each input channel based on the interrupt input signals, and determines the input channel to which the interrupt vector should be sent; a selection means for selecting and transmitting an interrupt vector corresponding to the input channel determined by the arbitration means during an acceptance cycle; and a selection means for selecting and transmitting an interrupt vector corresponding to the input channel determined by the arbitration means; An interrupt control device comprising: an erroneous interrupt vector storage means for storing an erroneous interrupt vector sent instead of a vector. (2) arbitration means for inputting interrupt input signals from a plurality of input channels, arbitrating the interrupt priority for each input channel based on the interrupt input signals, and determining the input channel to which the interrupt vector should be sent; selection means for selecting and transmitting an interrupt vector corresponding to the input channel determined by the arbitration means during an acceptance cycle, and an interrupt vector for selecting and transmitting an interrupt vector corresponding to the input channel determined by the arbitration means; an erroneous interrupt vector storage means for storing an erroneous interrupt vector sent in place of the erroneous interrupt vector; and a erroneous interrupt vector storage means that counts the number of times the erroneous interrupt vector is sent, and when the count value reaches a preset value, sends an abnormality notification signal. An interrupt control device comprising: abnormality occurrence notification means.