JPH04116849A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04116849A JPH04116849A JP23642490A JP23642490A JPH04116849A JP H04116849 A JPH04116849 A JP H04116849A JP 23642490 A JP23642490 A JP 23642490A JP 23642490 A JP23642490 A JP 23642490A JP H04116849 A JPH04116849 A JP H04116849A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- semiconductor
- wafer
- semiconductor element
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 150000001875 compounds Chemical class 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 6
- 229920003986 novolac Polymers 0.000 abstract description 2
- 239000003960 organic solvent Substances 0.000 abstract description 2
- 229910015844 BCl3 Inorganic materials 0.000 abstract 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 abstract 1
- 230000002950 deficient Effects 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、例えば砒化ガリウムGaAs半導体を用いる
電界効果トランジスタ(以下FETと称す)やモノリシ
ック・マイクロ波集積回路(以下MMICと称す)等の
半導体装置に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to field effect transistors (hereinafter referred to as FETs) and monolithic microwave integrated circuits (hereinafter referred to as MMICs) using, for example, gallium arsenide GaAs semiconductors. related to semiconductor devices such as
(従来の技術) 従来、GaAs等の化合物半導体を用いたFET。(Conventional technology) Conventionally, FETs use compound semiconductors such as GaAs.
モノリシック型マイクロ波集積回路(MにICと略称)
等は次に述べるように形成されていた。Monolithic microwave integrated circuit (abbreviated as IC in M)
etc. were formed as described below.
すなわち、第2図(a)に示されるように、つ二一ハ1
と称する円盤状の半導体基板上に選択的イオン注入、各
種電極材料や絶縁体の選択的形成、熱処理等を施して複
数個を同時に構成した後、スクライブライン2に沿って
ダイヤモンドブレードなどにより分割して個々の半導体
素子3(第2図(b))を形成している。That is, as shown in FIG. 2(a),
After performing selective ion implantation, selective formation of various electrode materials and insulators, heat treatment, etc. on a disk-shaped semiconductor substrate known as a semiconductor substrate to form multiple pieces at the same time, they are divided along scribe lines 2 using a diamond blade or the like. Thus, individual semiconductor elements 3 (FIG. 2(b)) are formed.
このようにして得られた半導体素子3は、長方形の形状
を示している。そして、この半導体素子は、通常パッケ
ージやキャリアプレート上にはんだや接着剤を用いてマ
ウントした後、金線またはアルミ線により半導体素子の
電極と外部の電極端子とを接続して実用に供されるが、
マウント作業を行なう際には第4図に示すように、半導
体素子3を真空ビンセット4で取扱うことが多い。The semiconductor element 3 thus obtained has a rectangular shape. This semiconductor element is usually mounted on a package or carrier plate using solder or adhesive, and then put into practical use by connecting the electrodes of the semiconductor element and external electrode terminals with gold or aluminum wires. but,
When performing mounting work, semiconductor devices 3 are often handled in a vacuum bin set 4, as shown in FIG.
ところが叙上のGaAsなどの化合物半導体は比較的も
ろい材質であるため、その製造工程において真空ピンセ
ット4と接触した時に、長方形の角部の部分が欠は易い
という問題点があった。第3図は、1つの角部の部分に
欠損部5が生じた半導体素子13を例示している。この
ような欠損部5が生じた半導体素子13は通例、性能の
劣化が観測され、また、直ちに検出されなくても経時的
に劣化が進行することが予想されるため、不良品と判定
している。However, since the above-mentioned compound semiconductor such as GaAs is a relatively brittle material, there is a problem in that the corners of the rectangle are easily chipped when it comes into contact with the vacuum tweezers 4 during the manufacturing process. FIG. 3 illustrates a semiconductor element 13 in which a defective portion 5 has occurred at one corner portion. Semiconductor elements 13 with such defective parts 5 are usually observed to have degraded performance, and even if they are not detected immediately, the deterioration is expected to progress over time, so they are judged to be defective. There is.
従って上記従来の鋭い角部のある半導体素子ではマウン
ト時に不良品が多く発生するという欠点があった。Therefore, the above-mentioned conventional semiconductor devices having sharp corners have a disadvantage in that many defective products are generated during mounting.
(発明が解決しようとする課題)
以上述べたように従来の半導体装置では、その半導体素
子がその4つの角部が鋭い角をなしている。その結果、
真空ピンセットを用いるマウント時に角に欠損が生じる
ことが避けられず、マウント時の不良発生が多かった。(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device, the semiconductor element has four sharp corners. the result,
When mounting using vacuum tweezers, it was inevitable that the corners would be damaged, resulting in many failures during mounting.
本発明は上記の欠点を除去すべくなされたもので、真空
ピンセットを用いるマウント時における欠損の発生を防
ぐようにした半導体素子を備えた半導体装置を提供する
ことを目的とする。The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor device including a semiconductor element that prevents the occurrence of damage during mounting using vacuum tweezers.
〔発明の構成〕
(11題を解決するための手段)
本発明に係る半導体装置は、化合物半導体ウェーハを長
方形に分割して得られる半導体素子を備えた半導体装置
において、半導体素子における長方形の角部が丸く形成
されてなることを特徴とする。[Structure of the Invention] (Means for Solving Problem 11) A semiconductor device according to the present invention is a semiconductor device including a semiconductor element obtained by dividing a compound semiconductor wafer into rectangular parts. It is characterized by being formed into a round shape.
(作 用)
本発明の半導体装置では、半導体素子の4つの角部にア
ールを設けまたは鈍角に形成することにより、真空ピン
セットとの接触による欠損を生じにくくなっている。。(Function) In the semiconductor device of the present invention, the four corners of the semiconductor element are rounded or formed at obtuse angles, thereby making it difficult to cause damage due to contact with vacuum tweezers. .
したがって、真空ピンセットを用いるマウント工程にお
ける不良品の発生が防止できる。Therefore, the occurrence of defective products in the mounting process using vacuum tweezers can be prevented.
(実施例)
以下、本発明に係る半導体装置の一実施例につき図面を
参照して説明する。(Example) Hereinafter, an example of a semiconductor device according to the present invention will be described with reference to the drawings.
第1図(b)に示す半導体素子23は4つの角部にアー
ルが設けられたものである。この例では半導体素子の角
部が丸められており、そのアールの大きさは一定で、そ
の曲率半径rは半導体素子の短辺(a)の約176、長
辺(b)の約l/12である。The semiconductor element 23 shown in FIG. 1(b) has four corners rounded. In this example, the corners of the semiconductor element are rounded, the size of the radius is constant, and the radius of curvature r is about 176 on the short side (a) of the semiconductor element and about 1/12 on the long side (b). It is.
上記の構成によれば、真空ピンセットで取扱う際に接触
する部分に鋭い角部がないため、マウント時に欠損が生
じることによる不良発生が防止できる。According to the above configuration, since there are no sharp corners in the portions that come into contact when handling with vacuum tweezers, it is possible to prevent defects caused by defects during mounting.
このような構成を実現するためには、従来のダイヤモン
ドブレードを用いる分割方法に代えて。To realize such a configuration, instead of the conventional dividing method using a diamond blade.
異方性のある選択エツチングによる分割方法を採用すれ
ばよい、この時に重要なことは、選択エツチングを行う
際に用いるマスクを角部にアールを設けた形状に形成す
ることである。具体的には第1図(a)に示すように、
ウェーハ1の表面に例えばノボラック系ポジ形フォトレ
ジストを塗布した後、フォトマスクを介して紫外線を照
射して半導体素子として残す部分に対応した部分以外の
フォトレジストを露光し、現像する。フォトマスクのパ
ターンを半導体素子の4つの角部にアールが設けられた
形状に対応させることにより、第1図(a)に示すフォ
トレジスト6のパターンを形成できる。A dividing method using anisotropic selective etching may be employed; what is important at this time is to form the mask used for selective etching into a shape with rounded corners. Specifically, as shown in Figure 1(a),
After applying, for example, a novolak positive photoresist to the surface of the wafer 1, ultraviolet rays are irradiated through a photomask to expose the photoresist other than the portions corresponding to the portions to be left as semiconductor elements, and the photoresist is developed. By making the pattern of the photomask correspond to the shape in which the four corners of the semiconductor element are rounded, the pattern of the photoresist 6 shown in FIG. 1(a) can be formed.
次にフォトレジスト6をエツチングマスクとして用い、
ウェーハにBCQ、とCQ、を含む反応ガスを使った選
択エツチングを施して、ウェーハを分割し、さらに、有
機溶剤によりフォトレジストを溶解除去して第1図(b
)に示す半導体素子23を得ることができる。Next, using the photoresist 6 as an etching mask,
The wafer is subjected to selective etching using a reactive gas containing BCQ, and CQ to divide the wafer, and then the photoresist is dissolved and removed using an organic solvent to form the photoresist shown in Figure 1 (b).
) can be obtained.
以上述べたように本発明によれば、真空ピンセットによ
り取扱う際に化合物半導体からなる半導体素子に欠損が
生じることが防止でき、半導体素子をパッケージやキャ
リアプレートにマウントする際の不良発生が防止できる
半導体装置を提供できる。As described above, according to the present invention, a semiconductor element made of a compound semiconductor can be prevented from being damaged when handled with vacuum tweezers, and a semiconductor element can be prevented from being defective when the semiconductor element is mounted on a package or a carrier plate. equipment can be provided.
第1図(a)は本発明に係る半導体素子の一実施例の形
成手段を説明するための平面図、第1図(b)は本発明
に係る半導体素子の一実施例を示す斜視図、第2図(a
)は従来の半導体素子の形成手段を説明するための平面
図、第2図(b)は従来の半導体素子を示す斜視図、第
3v4は従来の半導体素子における欠損を説明するため
の斜視図、第4図は真空ピンセットによって取扱いされ
た後の半導体素子の状態を説明するための斜視図である
。
1・・・ウェーハ、
2・・・スクライブライン、
3.13゜
23・・・半導体素子。
4・・・真空ピンセット、
5・・・欠損部。FIG. 1(a) is a plan view for explaining the forming means of an embodiment of the semiconductor element according to the present invention, FIG. 1(b) is a perspective view showing an embodiment of the semiconductor element according to the present invention, Figure 2 (a
) is a plan view for explaining a conventional semiconductor device forming means, FIG. 2(b) is a perspective view showing a conventional semiconductor device, and 3v4 is a perspective view for explaining defects in a conventional semiconductor device FIG. 4 is a perspective view for explaining the state of a semiconductor element after being handled by vacuum tweezers. 1... Wafer, 2... Scribe line, 3.13°23... Semiconductor element. 4...Vacuum tweezers, 5...Defected part.
Claims (1)
導体素子を備えた半導体装置において、半導体素子にお
ける長方形の角部が丸く形成されてなることを特徴とす
る半導体装置。1. A semiconductor device comprising a semiconductor element obtained by dividing a compound semiconductor wafer into rectangles, characterized in that the corners of the rectangles in the semiconductor element are rounded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23642490A JPH04116849A (en) | 1990-09-06 | 1990-09-06 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23642490A JPH04116849A (en) | 1990-09-06 | 1990-09-06 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04116849A true JPH04116849A (en) | 1992-04-17 |
Family
ID=17000553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23642490A Pending JPH04116849A (en) | 1990-09-06 | 1990-09-06 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04116849A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1439578A3 (en) * | 2003-01-20 | 2004-09-15 | Shinko Electric Industries Co., Ltd. | Method for dicing wafer |
US6861176B2 (en) * | 2002-07-18 | 2005-03-01 | Macronix International Co., Ltd. | Hole forming by cross-shape image exposure |
US6933211B2 (en) | 2002-10-17 | 2005-08-23 | Kabushiki Kaisha Toshiba | Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same |
-
1990
- 1990-09-06 JP JP23642490A patent/JPH04116849A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6861176B2 (en) * | 2002-07-18 | 2005-03-01 | Macronix International Co., Ltd. | Hole forming by cross-shape image exposure |
US6933211B2 (en) | 2002-10-17 | 2005-08-23 | Kabushiki Kaisha Toshiba | Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same |
US6933606B2 (en) | 2002-10-17 | 2005-08-23 | Kabushiki Kaisha Toshiba | Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same |
EP1439578A3 (en) * | 2003-01-20 | 2004-09-15 | Shinko Electric Industries Co., Ltd. | Method for dicing wafer |
US7211370B2 (en) | 2003-01-20 | 2007-05-01 | Shinko Electric Industries Co., Ltd. | Method for dicing wafer |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7129427B2 (en) | Processed lamination die | |
US5324981A (en) | Field effect transistor device with contact in groove | |
JP4387007B2 (en) | Method for dividing semiconductor wafer | |
US9595504B2 (en) | Methods and systems for releasably attaching support members to microfeature workpieces | |
JP2003257896A (en) | Method for dicing semiconductor wafer | |
JP2004055684A (en) | Semiconductor device and its manufacturing method | |
JPH08293476A (en) | Semiconductor wafer and photomask and manufacture of semiconductor integrated circuit device | |
WO2002067300A2 (en) | Singulation apparatus and method for manufacturing semiconductors | |
JPH04116849A (en) | Semiconductor device | |
JP2000091274A (en) | Formation of semiconductor chip and manufacture of semiconductor device using the same | |
JPS59220947A (en) | Manufacture of semiconductor device | |
KR20020068608A (en) | Semiconductor Wafer Working Process Using Plasma Etching Methode | |
JPH03239346A (en) | Manufacture of semiconductor device | |
JPH01133703A (en) | Semiconductor wafer and semiconductor device using the same | |
JPH02106947A (en) | Manufacturing method of semiconductor device | |
JPH03139862A (en) | semiconductor equipment | |
JPH03205846A (en) | Manufacturing method of semiconductor device | |
KR100366725B1 (en) | Method for fabricating polymer film patterns on surface of a semiconductor wafer | |
JP2004259936A (en) | Treatment method of qfn substrate | |
US20060289966A1 (en) | Silicon wafer with non-soluble protective coating | |
JPH042136A (en) | Manufacturing method of semiconductor device | |
JPS6118955A (en) | Reticle mask | |
JPH02208954A (en) | Manufacturing method of semiconductor device | |
JPH0231416A (en) | Semiconductor wafer for direct lithography | |
JPH05235333A (en) | Manufacture of semiconductor element |