JPH04115570A - Master-slice semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a pull-down resistor whose resistance value is variable by a wiring process only by a method wherein the drain diffused regions of one or more N-type channel transistors are electrically connected to an I/O cell. CONSTITUTION:In a basic cell, N-type MOS-FET's 25 and 26 are formed on the parts where a N<+>-type diffused region 21 overlaps polycrystalline silicon layers 23 and 24 which are to be gate electrodes. If a wiring layer is added to the basic cell to utilize it as an N-type channel transistor for a pull-down resistor, the source electrodes 32 of one or more N-type channel transistors among a plurality of the N-type channel transistors whose gate electrodes are fixed to Vdd+ are fixed to a potential Vss-. The drain electrodes 33 of one or more N-type channel transistors are connected to an input inverter circuit 13 and an I/O terminal 11 with signal lines 34. With this constitution, a pull- down resistor can be obtained by a wiring process only and its resistance value can be varied if necessary.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a master slice semiconductor integrated circuit that includes:
This is used in the configuration of a pull-down resistor transistor.

[Conventional technology] Conventional master slice semiconductor integrated circuit.

When a pull-down resistor was required, a dedicated type was used, either by attaching a resistor to the outside of the chip, or by using an input/output cell to fix an N-channel transistor as a pull-down resistor transistor.

[Problems to be solved by the invention] However, in the conventional technology described above, when a resistor is attached to the outside of the chip, the wiring around the chip becomes complicated and the mounting efficiency including the chip decreases, and external attachment increases the number of parts and costs. There was a problem with becoming. Furthermore, when an input/output cell has a built-in pull-down resistor, since it is a fixed, dedicated type, it requires a chip area even when not in use, and the resistance value is fixed.

The present invention is intended to solve these problems, and its purpose is to provide a master slice semiconductor integrated circuit in which a pull-down resistor can be created only by the wiring process when realizing a dedicated logic circuit using a mask slice type gate array. The purpose is to provide

[Means for Solving the Problems] The master slice semiconductor integrated circuit of the present invention has the following features: a
) In a master slice semiconductor integrated circuit formed by arranging a large number of internal logic gate cells (hereinafter referred to as basic cells) in a two-dimensional matrix, b) P of the input/output cells into which signals from outside the chip are input.
C) an N-channel transistor using the basic cell 3; and d) a plurality of the N-channel transistors whose gate electrodes are fixed to Vdd+.
The sos electrode of one or more of the N-channel transistors among the channel transistors is fixed at a potential of Vss-, and the drain diffusion region of the one or more N-channel transistor and the input/output cell are electrically connected. [Example] The present invention will be described in detail based on Examples below.

FIG. 1 shows the configuration of an N-channel transistor for a pull-down resistor built into a master slice semiconductor integrated circuit according to the present invention.

In FIG. 1, 11 is an input/output terminal, 12 is an N-channel transistor for a pull-down resistor, and 13 is an input inverter circuit. N-channel transistor 12 for pull-down resistor is connected to input/output terminal 11 and input inverter circuit 1
Connected to 3. Further, the gate electrode of the pull-down resistor N-channel transistor 12 is connected to Vdd+, and the source electrode is connected to VsS-. Next, a description will be given of means for configuring the pull-down resistor N-channel transistor in the master slice semiconductor integrated circuit.

First, FIG. 2 is a pattern diagram showing an example of basic cells, which are internal logic gate cells arranged in an array in a master slice semiconductor integrated circuit. 23 in Figure 2
．． 24 is an insulated gate field effect transistor (hereinafter MO
3FET), 21 is an N+ diffusion, and 22 is a P+ diffusion. 2
N-type MO3FETs 25 and 26 are formed in the overlapping portions of 3.24 and N+ diffusion 21, respectively. Furthermore, P-type MO8FETs 27 and 28 are formed in the overlapping portions of the polysilicon 23 and 24 and the P+ diffusion 22, respectively.

FIG. 3 shows a case where a wiring layer is added to the basic cell shown in FIG. 2 and used as an N-channel transistor for a pull-down resistor. In Fig. 3, for simplification, contact holes connecting polysilicon and aluminum wiring and N:
A contact hole connecting the + diffusion or P+ diffusion and the aluminum wiring is represented by an X mark, and the aluminum wiring taken out from the contact hole is represented by a straight line. Now, the gate tf of N-type MOSFET25! is 31. The source electrode is 32. The drain electrode is 33.

Further, the gate of the P-type MOSFET 27 is located at the pole 31, and the source electrode and the train electrode are located at the pole 31. The sos electrode 32 of the N-type MOSFET 25 is connected to the negative power supply potential Vss, the gate electrode 31 of the N-type MOSFET 25 is connected to the positive power supply potential Vdd, and the drain electrode 33 of the N-type MOSFET 25 is connected to the negative power supply potential Vss. It is connected to the input inverter circuit and the input/output terminals through a signal 34.

The above configuration constitutes an N-channel transistor circuit for a pull-down resistor.

Figure 4 shows multiple basic cells lined up.

It is a configuration diagram in which four N-type MOSFETs are connected in parallel.

FIG. 5 is a circuit diagram of FIG. 4.

If the resistor 51 is 100 kilohms, then the pull-down resistance value will be 25 kilohms since it is a quadruple subarray.

Figure 6 shows multiple basic cells lined up.

It is a configuration diagram in which four N-type MOSFETs are connected in series.

FIG. 7 is a circuit diagram of FIG. 6.

If the resistor 71 is 100 kilohms, there are four resistors connected in series, so the pull-down resistance value is 400 kilohms.

Furthermore, although FIG. 2 has been given as an example of a basic cell, the above explanation is not limited to a specific pattern of basic cells and can therefore be applied to other basic cells.

[Effects of the Invention] As described above, according to the master slice semiconductor integrated circuit having the circuit configuration of the present invention, there is an effect that a pull-down resistor can be created only by the wiring process when realizing a dedicated logic circuit with a master slice type gate array. . Furthermore, since the resistance value of the pull-down resistor can be varied as needed, the chip area can be reduced, resulting in an integrated circuit with excellent cost performance.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an N-channel transistor for pull-down resistor, Figure 2 is a pattern diagram of a basic cell, Figure 3,
4 and 6 are configuration diagrams of an N-channel transistor circuit for a pull-up resistor, and FIG. 5 and FIG. 7 are circuit diagrams of a pull-down resistor. 3°3

Claims (1)

[Claims] (1) a) In a master slice semiconductor integrated circuit formed by arranging a large number of internal logic gate cells (hereinafter referred to as basic cells) in a two-dimensional matrix, b) P of an input/output cell into which signals from outside the chip are input.
c) an N-channel transistor using a basic cell; and d) a plurality of the N-channel transistors with gate electrodes fixed to Vdd+.
The source electrode of one or more of the N-channel transistors among the channel transistors is fixed at a potential of Vss-, and the drain diffusion region of the one or more N-channel transistor is electrically connected to the input/output cell. master slice semiconductor integrated circuit.