JPH04101235A - Parity generation-check circuit - Google Patents

Abstract

PURPOSE:To obtain a new parity generation.check circuit which can be designed and added as the peripheral circuit of a second processor by latching the data of the origin of a parity error, and reading out the data at the time of the occurrence of the error in the case that a first processor detects the parity error. CONSTITUTION:A system is constituted of the parity generation.check circuit 11 incorporated in the first processor 10, the second processor 12 with no built-in parity generation.check circuit, and the parity generation.check circuit 14 newly designed and added as the peripheral circuit of the second processor 12. Then, in the case that the parity error occurs in the parity generation.check circuit 11 of the first processor 10, the data of the origin of the error can be latched by the parity generation.check circuit 14 of the second processor 12, and can be taken out to the outside. Thus, the data of the origin of the occurrence of the parity error is specified, and the parity generation.check circuit is incorporated by combining it with the peripheral circuit necessary for the second processor.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a parity generation/check circuit, especially in a multi-master system consisting of a plurality of processors, etc., which is incorporated as a peripheral circuit of a processor that does not have a built-in parity generation/check circuit. , relates to a parity generation/check circuit that can identify data when a parity error occurs.

[Prior Art] In the past, in personal computers and the like, data errors were often detected by a parity check in order to ensure the reliability of processed data. The principle of detecting data errors using parity check is that when writing data, one bit of parity pit (this parity bit is one of the data bits) is detected for every 8 bits of data.
or added so that the sum of the number of 0 bits is always an even or odd number), the parity pits and data bits are stored together, and the next time the corresponding data is read, they are read together and the data bits are added. The immutability of data is confirmed by checking that the sum of the number of 1 or 0 bits in the parity bits is always an even number or an odd number.

By the way, in general, personal computers
O that you want to run on the system as a processor
In consideration of compatibility with 8, commercially available MPUs from other companies are often used. For example, Intel's 180486
An example of this is the increase in the number of personal computers that use worldwide processors.

Many conventional commercially available processors did not include a parity generation/check circuit inside the processor.

However, with recent improvements in semiconductor integration technology, a single processor device is increasingly incorporating other functions in addition to the CPU section. For example, in the 180486 processor, the CPU section, cache memory, coprocessor section, and parity generation and check circuits are combined into one device, so when a parity error occurs, it is necessary to identify the data that actually caused the parity error. However, there was a problem in that it was not possible to efficiently troubleshoot parity errors.

On the other hand, recently, demands for performance and functions have become more sophisticated even for personal computers, and in order to meet these demands, personal computers are increasingly being configured into multi-master systems. When configuring such a multi-master system, a first processor that has a built-in parity generation/check circuit such as the Intel i80486, a second processor that does not have a built-in parity generation/check circuit, and A multi-master system including a RAM shared as a main memory by a first processor and a second processor may be configured.

In such a case, the R A used as the main memory
Since the data stored in the Fvl is also used by the second processor, the interface bus between the first processor and the RAM is taken into the second processor, and the reliability of the data of the second processor is improved. In order to ensure this, it was necessary to newly design and add a parity generation/check circuit as a peripheral circuit of the second processor.

FIG. 2 is a block diagram of a conventional multi-master system including a newly designed and added parity generation/check circuit as a peripheral circuit of a second processor.

In the figure, the conventional multi-master system includes a first processor 10, a parity generation/check circuit 11 built into the first processor 10, a second processor 12 that does not include a parity generation/check circuit, and a parity generation/check circuit 11 built into the first processor 10. It consists of a RAM 13 that is shared and accessed by the first processor 10 and the second processor 12, and a parity generation/check circuit 14 newly designed and added as a peripheral circuit of the second processor. The check circuit 14 includes a data buffer 21 and a parity generation/check section 22.

Note that the second processor sends a master signal to the first processor, halts the first processor, and performs memory transfer to the second processor.

A DMA or the like may be considered as the second processor.

Next, the operation will be explained. The conventional parity generation/check circuit 14 configured as described above inputs and outputs the data line 101 of the interface bus and the parity line 102, and also inputs and outputs the data line 103 from the second processor. The data buffer 21 of the parity generation/check circuit 14 is a transfer data buffer located between the data line 101 and the data line 103. The data buffer 21 inputs a signal line 104 output from the first processor 10 indicating that the first processor 10 is in the process of transferring data with the RAM 13,
During data transfer with AM1B, data is not output to the data line 101 and parity line 102, so as not to cause redundancy to the data line 101 and parity line 102.

Furthermore, during input/output with the RAM 1B of the second processor, the parity generation/check unit 22 connects the data line 101 and the parity line 102 via the data buffer 21 at the time of input.
A parity check operation is performed manually, and at the time of output, the data line 103 is input to perform a parity generation operation, and the data is output to the data line 101 and the parity data is output to the parity line 102 via the data buffer 21. .

Note that the first
In the first processor 10, when the parity generation/check circuit 11 detects a parity error, an NMI (Non-Maskable Interrupted) interrupt occurs and the first processor enters a halt state.

[The problem that the invention tries to solve! ] In the parity generation/check circuit newly designed and added as a peripheral circuit of the conventional second processor configured as described above, a parity error was detected in the data read from the RAM by the second processor. In this case, is it possible to identify the data that caused the parity error by reading out the contents of the data buffer 21?If a parity error occurs in the data read from the RAM in the first processor, Either the system simply stops, or a parity error signal line (not shown) is simply output to a second processor, for example, to know which data byte of the transferred data caused a parity error. There was a problem that it could not be done.

In this way, when a parity error is detected, there are many possible problems when it is not possible to identify the data that caused the parity error. Troubleshooting can be time consuming and can be costly.

This is because, at the beginning of device development, many problems related to parity checks occur due to processor clock problems, noise problems, etc., so it is often important to deal with these problems.

The present invention was made in order to solve the above-mentioned problems, and it is possible to analyze the cause of the parity error that occurred in the first processor in a short time. The purpose is to obtain a parity generation/check circuit that is newly designed and added as a peripheral circuit of the second processor, which can specify data.

[Means for Solving the Problems] In order to achieve the above object, a parity generation/check circuit according to the present invention includes a first processor having a built-in parity generation/check circuit and a first processor having no built-in parity generation/check circuit. inputting data from a RAM shared as main memory by the second processor and data from the second processor, and indicating whether or not the first processor is in the process of data transfer with the RAM; a selector that selects both data in response to a selection signal output from the first processor; and a parity generation/check section that receives the output of the selector as input and performs parity generation/checking; R
When the first processor detects a parity error during data transfer with the AM, the data causing the parity error can be latched and the data at the time of the error can be read out. It is.

[Operation] Therefore, according to the second invention, while data is being transferred between the first processor having a built-in parity generation/check circuit and the RAM, the newly designed and added peripheral circuit of the second processor is The parity generation/check circuit operates in the same way as the parity generation/check circuit of the first processor, and if a parity error occurs in the parity generation/check circuit of the first processor, the parity generation/check circuit of the second processor operates in the same manner as the parity generation/check circuit of the first processor. Since the generation/check circuit is configured to latch the data that caused the error and take it out, it becomes possible to determine which data caused the error when a parity error occurs.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a multi-master system showing one embodiment of the present invention.

In FIG. 1, the multi-master system of the present invention includes a first processor 10, a parity generation/check circuit 11 built in the first processor 10, and a second processor 12 that does not include a parity generation/check circuit. and,
It consists of a RAM 1B that is shared and accessed by the first processor 10 and the second processor 12, and a parity generation/check circuit 14 newly designed and added as a peripheral circuit of the second processor 12. .

The parity generation/check circuit 14 is a data buffer 21
, the data from the RAM 13 and the data from the second processor 12 are input, and the first processor 10 inputs the data from the RAM 13 and the data from the second processor 12.
13 and a selector 23 separated by a signal line 104, which is a selection signal output from the first processor 10, indicating whether or not data is being transferred. a parity generation/check section 22 , a parity buffer 24 that outputs the parity bits output from the parity generation/check section 22 , a parity buffer 25 that inputs the parity bits from the parity line 102 ; A data latch 26 for holding data that is outputted from the signal line 105 and which notifies the occurrence of a parity error and causes a parity error when a parity error occurs, and NOT circuits 27 and 28.
It is composed of.

In the multi-master system configured as above,
When the first processor 10 is transferring data to the RAM 13, the first processor 10 inputs data from the data line 101 and the parity line 102, and the parity generation/check circuit 11 performs a parity check operation. At this time, the parity generation/check circuit 14 does not need to operate for the second processor, but operates as follows in order to identify the byte causing the parity error.

That is, when the first processor 10 is transferring data to the RAM 13, the signal line 104 indicating that the first processor 10 is transferring data to the RAM 13 goes to LOW level, so the selector 23 transfers data to the RAM 13. 12
The data on the data line 103 from the interface bus is suppressed, and the data on the data line 101 and the parity line 102 from the interface bus are input as valid. Therefore, parity generation
The checking unit 22 checks the data line 1 from the interface bus.
01, the data on the parity line 102 is input and a parity check operation is performed.
This is the same operation as the parity check performed in .

Next, after the parity generation/check section 22 executes a parity check operation, the data after the check can be stored in the data latch 26. In this way, the first processor 1 with a built-in parity generation/check circuit
As long as a parity error does not occur at point o, the data stored in the data latch 26 is replaced with new data one after another every time the input data changes.

Note that the parity buffer 24 is connected to the first processor 10.
Signal line 1 indicates that data is being transferred to RAM 13.
04, the parity buffer 25 operates so as not to output the parity bit output from the parity generation/check unit 22 to the parity line 102, and the parity buffer 25
It inputs the output of the NOT circuit 27 that inverts , and operates to input the parity bit of the parity line 102 to the parity generation/check section 22 while the first processor 10 is transferring data to the RAM 1B.

In such a state, the first processor 1°
When a parity error is detected in the data input from 13, the first processor 10 generates a LOW level pulse on the signal line 105 indicating the occurrence of a parity error and notifies the parity generation/check circuit 14. The parity generation/check circuit 14 is a NOT circuit 28
Since the signal line 105 is inverted and supplied to the data buffer 26, the data buffer 26 latches the data at that point. Even if data from the parity generation/check unit 22 is subsequently transferred, the data buffer 26 does not store new data, so it retains the data that caused the error. By configuring the system so that the data at the time of error occurrence can be taken out from 26, it becomes possible to notify the software of the cause data at the time of error occurrence.

[Effects of the Invention] As explained above, according to the present invention, parity generation and
When a parity error is detected in the first processor having a built-in check circuit, a parity generation/check circuit is installed in the second processor so as to be able to identify the data that caused the parity error. By incorporating it together with the peripheral circuits required for the system, it becomes possible to deal with many problems related to parity checks that occur especially at the beginning of device development. In addition, for mass-produced products limited to the initial stage of device development, by incorporating the parity generation/check circuit into an LSI, this function can be implemented without having to worry about cost or space, thereby eliminating the cause of parity errors. This has the effect of being able to identify the data that has changed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a multi-master system showing an embodiment of the present invention. Figure 2 is a conventional multi-master system including a newly designed and added parity generation/check circuit as a peripheral circuit of a second processor. FIG. 10 ... First processor 11 degree circuit 12 ... 13 ... 21 ... 26 ... 22 ... 23 ... 24.25 27.28 101 ... 102 ... 14゜15... Parity generation/check Second processor AM Data buffer Data latch Parity generation/check section selector... Parity buffer... Data line of NOT circuit interface bus Parity line of interface bus

Claims (1)

[Scope of Claims] A first processor with a built-in parity generation/check circuit, a second processor without a built-in parity generation/check circuit, and a RAM shared by the first processor and the second processor. A multi-master system comprising: a parity generation/check circuit provided between the second processor and the RAM, the parity generation/check circuit indicating whether the first processor is in operation; a selector that selects data from the RAM and data from the second processor according to a selection signal from the first processor; and a parity generation/check section that performs parity generation/checking using the output of the selector as input. and when the first processor is transferring data to the RAM, when the first processor detects a parity error, it latches the data that caused the parity error, and when the error occurs, A parity generation/check circuit characterized by reading out data.