JPH04107614A - Hot line loading/unloading protection system - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a package caused by the loading/ unloading operations of a hot line by providing a CPU holding control circuit which inhibits an access of the CPU to a control bus with use of a loading/ unloading detection signal. CONSTITUTION:A loading/unloading detection circuit 2 detects a loading/ unloading signal 9 and outputs a loading/unloading detection signal 14 to a CPU holding control circuit 3. The circuit 3 inhibits a CPU 6 from having an access to a system control bus 13 with a CPU holding signal 15 while the signal 14 is kept active. Thus the CPU 6 is set in a holding mode. At the same time, the CPU 6 outputs a control inhibiting signal 12 through a control inhibiting signal output circuit 4 to all packages connected to a back board 8 in order to neglect the control instruction given from the bus 13. Thus it is possible to prevent the operating abnormality of the package contained in a device that is caused by the malfunction of the bus 13 when a hot line is loaded an unloaded.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is a method for removing and inserting packages from equipment until the place where the equipment is turned on for failure replacement, etc. (hereinafter referred to as hot-swapping)
This invention relates to a hot-swap protection method for protecting equipment operation when

[Conventional technology]

When replacing a faulty package for maintenance or the like, it is normal to turn off the power to the device in question and then recover from the fault. However, in devices that require 24-hour operation, such as data transmission devices, a redundant circuit can functionally isolate a faulty package, and the faulty package can then be replaced.

In such devices, it is possible to power down the device without powering it off.

It is necessary to replace the damaged package.

In consideration of hot insertion and removal, in conventional data transmission equipment, the interface between packages in the device is designed so that only adjacent packages are connected. there was.

[Problem to be solved by the invention]

However, with the spread of microcomputers in recent years,
System control of data transmission devices has come to be performed by program control by a CPU.

For this reason, node connections have come to be used for inter-package interfaces, and malfunctions in node access due to hot insertion and removal have become a problem.

In conventional data transmission devices, if hot insertion or removal is performed while the CPU is accessing a package in the device using a bus interface, the package in question may malfunction or other packages connected to the control bus may This may cause malfunction of the CPU or the CPU itself to run out of control.

[Means to solve the problem]

The hot-line insertion and removal protection method of the present invention is a hot-line insertion and removal protection method for a data transmission device controlled by a CPU, and includes a backboard, a system control package, and an internal package, and the backboard receives insertion and removal control signals. ,
The system control package includes a control inhibition signal and a system control bus; the system control package includes an insertion/extraction detection circuit that detects insertion/extraction of the package from the insertion/extraction control signal; a CPU hold control circuit that prohibits the CPU from accessing the control bus based on the insertion/extraction detection signal; A control inhibit signal output circuit is provided for outputting a signal to invalidate a control command from the backboard via the system control bus when the CPU is held, and the internal package is inserted into or removed from the backboard when the corresponding package is inserted or removed from the backboard. The device includes an insertion/extraction signal generation circuit that outputs an insertion/extraction state of the package as the insertion/extraction control signal, a control command decoder that prohibits control commands from the system control bus based on the control prohibition signal, and a bus connector having long terminals and short terminals. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a system control package incorporating a CPU and a backboard in an embodiment of the present invention;
FIG. 2 is a circuit block diagram of an in-device package connected to a backboard according to an embodiment of the present invention, and FIG. 3 is a connector having long terminals and short terminals used in the package according to an embodiment of the present invention. FIG. Further, FIG. 4 is a timing chart illustrating an example of circuit operation in an embodiment of the present invention.

First, each component shown in FIGS. 1 to 3 will be explained.

Each control package in the device connects to the CP of the system control package 1 via the system control bus 13 of the backboard 8.
Controlled by U6.

In the system control package l shown in FIG.
U6 controls each package in the device connected to bus connectors 7-1 to 7-4 of backboard 8 according to a control program. An internal control bus 16 directly connected to the CPU 6 is connected to the backboard 8 via a control bus buffer 5.
It is connected to the system control bus 13 of. backboard 8
A system control bus 13 is connected between the system control package 1 and each package in the device, and is composed of bus signals and bus connectors 7-1 to 7-4.

The insertion/extraction detection circuit 2 detects the insertion/extraction signal 9 in the insertion/extraction control bus and outputs the insertion/extraction detection signal 14 to the CPU hold control circuit 3. As a result, the CPU hold control circuit 3 controls the CPU hold signal 1 while the insertion/removal detection signal 14 is active.
5 prohibits the CPU 6 from accessing the system control bus 13, and the CPU 6 enters the hold mode.

At the same time, during the hold mode, the CPU 6 causes the control prohibition signal output circuit 4 to output a control prohibition signal 12 for causing all packages connected to the backboard 8 to ignore control commands from the system control bus 13.

In the control package 17 shown in FIG. 2, when the control inhibit signal 12 is inactive, the control command decoder 19
Control commands from the system control bus 13 are decoded to generate control signals 20 within the board.

Short terminals A and long terminals B of the bus connector 7 having the structure shown in FIG. 3 are used for an insertion/extraction control bus. The insertion/extraction signal generation circuit 18 generates an insertion/extraction signal 9 when the corresponding package is inserted into and removed from the backboard 8 using the contact time difference between these terminals.

The components described above operate according to the timing chart shown in FIG.

Now, the operation of pulling out the control package 17 while it is powered on will be explained according to the timing shown in FIG. 4.

When the removal operation begins, the signal of the short terminal A of the bus connector becomes an oven at point a due to the connector structure shown in FIG. When it is pulled out further, the long terminal B also becomes open at 5 points. The insertion/extraction signal generation circuit 18 assigns G110 to the short terminal A and insertion/extraction signals 9 and G211 to the long terminal B as shown in FIG.
The transistor Q is cut off when the base current is connected to the ground through the 01 terminal, and the insertion/extraction signal 9 is kept at a high level.When the base current is supplied through the resistor R2 at point a, the transistor Q is cut off. Turns on and sets the insertion/extraction signal 9 to low level. When the insertion/extraction signal 9 is further removed from the control package 17 at five points, the insertion/extraction signal of the backboard 8 becomes high level again.

When the insertion/extraction signal 9 becomes low level at point a, the insertion/extraction detection circuit 2 of the system control package 1 is transmitted via the backboard 8.
is detected, outputs the insertion/removal detection signal 14, and activates the CPU hold control circuit 3. In response to this, CPU7
enters the hold mode, stops access to the system control bus 13, and outputs the control prohibition signal 12.

Each control package ignores access from the system control bus 13 while the control inhibit signal 12 is active;
Prevents malfunctions during the extraction operation period.

When the insertion/extraction signal 9 becomes high level again at point 5, the CPU hold control circuit 3 determines the time (T) for the connector to be completely disconnected.
time), then release the hold mode and return to normal operation.

Next, consider the operation of inserting a package while it is powered on.

When the insertion operation is started, the insertion/extraction signal of the control package 17 and G211 are connected to the insertion/extraction control bus at point 0. At this point, the short terminal A G110 is not yet connected to the insertion/extraction control bus, so the base current of the transistor Q is supplied from the insertion/extraction signal 9, and the transistor Q becomes conductive and the insertion/extraction signal 9 becomes low level. The subsequent control bus access protection operation is the same as the control package removal operation.

The insertion/removal signal generation circuit 18 used in the above explanation is one example and does not limit the implementation means of the present invention. Further, the structures of the long terminals and short terminals of the connectors of the control package and the backboard are also shown as an example, and are not intended to limit the means for realizing the present invention. The terminal for bus signals other than the insertion/extraction control bus may be long terminal B, short terminal A, or intermediate terminals C and D between these terminals.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to protect the malfunction of the package in the device due to the malfunction of the system control bus during hot insertion and removal, and system control of fault-tolerant data transmission equipment etc. can be performed using the CPtJ control bus. This has the effect of making it possible to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system control package incorporating a CPU and a backboard in an embodiment of the present invention;
FIG. 2 is a block diagram of an in-device package connected to a backboard in an embodiment of the present invention, and FIG. 3 is a long terminal used in the package in an embodiment of the present invention.
FIG. 4 is a structural diagram of a connector having short terminals, and is a timing chart illustrating an example of circuit operation in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... System control package, 2... Insertion/removal detection circuit, 3... CPU hold control circuit, 4... Control prohibition signal output circuit, 5... Control bus buffer, 6...
CPU, 7.7-1 to 7-4...Bus connector, 8.
...Backboard, 9...Insertion/removal signal, 10...G1
．． 11...G2.12...Control prohibition signal, 13...
・System control bus, 14... Insertion/removal detection signal, 15.
...CPU hold signal, 16...Internal control bus, 1
7... Control package, 18... Insertion/removal signal generation circuit, 19... Control command decoder, 20... Control signal,
A: Short terminal, B: Long terminal, C, D: Intermediate long terminal.

Claims (1)

[Claims] A hot-swap protection system for a data transmission device controlled by a CPU is composed of a backboard, a system control package, and an internal package, and the backboard transmits a hot-swap control signal, a control inhibit signal, and a system control bus. The system control package includes an insertion/extraction detection circuit that detects insertion/extraction of the package from the insertion/extraction control signal, a CPU hold control circuit that prohibits the CPU from accessing the control bus based on the insertion/extraction detection signal, and a A control inhibit signal output circuit is provided for outputting a signal to invalidate a control command by the system control bus, and when the package in the device is inserted or removed from the backboard, the insertion/removal control signal is used to control the insertion/removal of this package. A hot insertion/extraction protection system comprising an insertion/extraction signal generation circuit that outputs a status, a control command decoder that inhibits control commands from the system control bus based on the control prohibition signal, and a bus connector having long terminals and short terminals. .