JPH0410699Y2 - - Google Patents
Info
- Publication number
- JPH0410699Y2 JPH0410699Y2 JP729882U JP729882U JPH0410699Y2 JP H0410699 Y2 JPH0410699 Y2 JP H0410699Y2 JP 729882 U JP729882 U JP 729882U JP 729882 U JP729882 U JP 729882U JP H0410699 Y2 JPH0410699 Y2 JP H0410699Y2
- Authority
- JP
- Japan
- Prior art keywords
- plating film
- resin
- lead frame
- metal plate
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007747 plating Methods 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910000510 noble metal Inorganic materials 0.000 claims description 5
- 239000010970 precious metal Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 10
- 229910052709 silver Inorganic materials 0.000 description 10
- 239000004332 silver Substances 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置に利用するリードフレーム
の改良に関するものである。[Detailed Description of the Invention] The present invention relates to an improvement of a lead frame used in a semiconductor device.
シリコン、ゲルマニウム、化合物半導体等の半
導体材料を用いて構成する半導体装置は、上記半
導体材料に拡散、エツチング等の処理を施こして
作製する半導体チツプに対して、これらのチツプ
を外部回路と接続するためにリードフレームが用
いられる。 Semiconductor devices constructed using semiconductor materials such as silicon, germanium, and compound semiconductors require semiconductor chips that are manufactured by subjecting the semiconductor materials to processes such as diffusion and etching, and connecting these chips to external circuits. A lead frame is used for this purpose.
例えば半導体装置が発光ダイオード（LED）
である場合、第１図に示すようなリードフレーム
１が用いられている。即ちリードフレーム１は、
半導体素子２を搭載するための第１リード１ａ
と、半導体素子２に一端が接続されたワイヤ３の
他端を接続する第２リード１ｂが１対をなして、
連結帯１ｃに連結されながら２次元的に多数対設
けられている。上記リードフレーム１は金属板を
上記形状に打抜いて作製されるが、金属板はチツ
プ２及びワイヤ３とのボンデイング性を得るた
め、表面に金又は銀による貴金属メツキが施こさ
れている。ここで貴金属メツキは、従来のリード
フレームでは上記第１及び第２リードの先端部分
だけではなく、アウターリード部にも施こされて
いる。しかしアウターリード部のメツキ膜は、装
置の組立て作業や保管中に酸化や変質を起こし、
そのままでは安定した表面状態が得られない。従
つて実際の半導体装置では、上記貴金属メツキの
上に更にアウターリードとなる部分に錫又は半田
メツキや半田デイツプを行つている。このように
従来のリードフレームは表面処理が繁雑であり、
工程数が多くなるという欠点があつた。 For example, the semiconductor device is a light emitting diode (LED)
In this case, a lead frame 1 as shown in FIG. 1 is used. That is, the lead frame 1 is
First lead 1a for mounting semiconductor element 2
and a pair of second leads 1b connecting one end of which is connected to the semiconductor element 2 and the other end of the wire 3,
A large number of pairs are provided two-dimensionally while being connected to the connecting band 1c. The lead frame 1 is manufactured by punching a metal plate into the shape described above, and the surface of the metal plate is plated with a noble metal of gold or silver in order to obtain bondability with the chip 2 and the wire 3. Here, in conventional lead frames, noble metal plating is applied not only to the tip portions of the first and second leads but also to the outer lead portions. However, the plating film on the outer leads can oxidize and deteriorate during device assembly and storage.
If left as is, a stable surface condition cannot be obtained. Therefore, in actual semiconductor devices, tin or solder plating or solder dipping is further applied to the portions that will become the outer leads on top of the noble metal plating. In this way, conventional lead frames require complicated surface treatment,
The disadvantage was that the number of steps was increased.
本考案は上記従来のリードフレームにおける欠
点を除去し、製造工程を簡単にし、半田付性の良
好な表面をもつリードフレームを提供するもので
ある。次に図を用いて本考案の実施例を説明す
る。 The present invention eliminates the drawbacks of the conventional lead frames, simplifies the manufacturing process, and provides a lead frame with a surface with good solderability. Next, an embodiment of the present invention will be described using the drawings.
第２図において１１は従来装置と同様に、第１
リード１１ａと第２リード１１ｂを１対として連
結帯１１ｃによつて複数対連結させて打抜かれた
金属板である。上記第１及び第２リード１１ａ，
１１ｂの各先端部分には銀メツキ膜１２が形成さ
れている。該銀メツキ膜１２は少なくともボンデ
イング部分に形成されておれば目的を達成し得る
が、本実施例では後述する封止用樹脂で被われる
リード表面に被着される。第１及び第２リード１
１ａ，１１ｂの延長した他の金属表面は、上記メ
ツキ工程に続いて或いは同時に錫メツキ又は半田
メツキ１３が施こされている。該錫メツキ又は半
田メツキ１３を施こすことにより、従来のリード
フレームに要求されていた外装メツキ又は半田デ
イツプを省くことができる。貴金属メツキされた
リード１１ａ先端にはチツプ１４がタイボンドさ
れ、該チツプ１４と他のリード１１ｂとの間には
ワイヤ１５のボンデイングが行われている。チツ
プボンデイングされたリードフレームは、第３図
の如く無色、或いは着色等の透光性樹脂１６でモ
ールドされ、外部環境から保護される。樹脂１６
から外部に露出したアウターリード１１ａ，１１
ｂは、樹脂１６に埋設された部分が銀メツキされ
ているため、銀メツキ１２の一部が露出した状態
にある。個々の半導体装置を得るにあたつては連
結部分１１ｃが切断される。 In FIG. 2, 11 is the first
This is a metal plate punched with a plurality of pairs of leads 11a and second leads 11b connected by a connecting band 11c. the first and second leads 11a,
A silver plating film 12 is formed on each tip portion of 11b. The purpose of the silver plating film 12 can be achieved if it is formed at least on the bonding portion, but in this embodiment, it is applied to the lead surface covered with a sealing resin to be described later. 1st and 2nd lead 1
The other extended metal surfaces of 1a and 11b are tin-plated or solder-plated 13 subsequent to or simultaneously with the above-mentioned plating process. By applying the tin plating or solder plating 13, the exterior plating or solder dip required for conventional lead frames can be omitted. A chip 14 is tie-bonded to the tip of the lead 11a plated with a noble metal, and a wire 15 is bonded between the chip 14 and another lead 11b. The chip-bonded lead frame is molded with transparent resin 16, which may be colorless or colored, as shown in FIG. 3, and is protected from the external environment. resin 16
Outer leads 11a, 11 exposed to the outside from
In b, since the part buried in the resin 16 is silver plated, a part of the silver plating 12 is exposed. To obtain individual semiconductor devices, the connecting portion 11c is cut.
個々の半導体装置にあつては、上記したよう
に、樹脂１６から外部にさらに銀メツキ膜１２が
露出した状態でその先にSnメツキ又は半田メツ
キ膜１３が被着されるので、回路基板等にこの半
導体装置を半田付けにより取り付ける際には、半
田は仮にリードフレームの上方に昇って行くとし
ても、材質の異なる銀メツキ膜１２との境部分で
とまり、樹脂１６に悪影響を及ぼすことがない。
また、樹脂１６との界面は銀メツキ膜１２であり
リードフレームとの密着性等がよくチツプ１４に
対する信頼性も高い。 In the case of individual semiconductor devices, as described above, the silver plating film 12 is further exposed to the outside from the resin 16, and the Sn plating or solder plating film 13 is applied to the tip of the silver plating film 12, so that the circuit board etc. When this semiconductor device is attached by soldering, even if the solder rises above the lead frame, it stops at the boundary with the silver plating film 12, which is made of a different material, and does not adversely affect the resin 16.
Further, the interface with the resin 16 is a silver plating film 12, which has good adhesion to the lead frame and provides high reliability for the chip 14.
上記実施例はLED用のリードフレームを示し
たが、IC，LSI等のリードフレームにも本考案は
適用し得る。 Although the above embodiment shows a lead frame for LED, the present invention can also be applied to lead frames for IC, LSI, etc.
以上本考案による多色メツキリードフレームに
よれば、従来のように樹脂モールド後に外装メツ
キ又は半田デイツプを行う必要がなく工程数が少
なくなると共に、外装メツキや半田デイツプによ
る薬品や熱の影響を心配する必要がなく、半導体
装置の組立てに適用した場合装置の信頼性を損う
惧れがない。また貴金属メツキの範囲を少なくす
ることができ、経費の節減を図り得る。更にリー
ドフレームは金属板の状態で貴金属メツキ膜及び
Snメツキ又は半田メツキ膜を作製するため、素
子や樹脂に悪影響を及ぼすことがなく、安定した
表面状態のリードフレームが得られる。また、樹
脂封止においては樹脂外に貴金属メツキ膜が露出
するようになるので、リードフレームとの密着性
を良くしてチツプに対する信頼性を保持できると
ともに、回路基板等への半田付けの際には、半田
付けの半田は樹脂封止部分外の半田付性をもつメ
ツキ膜部分でとめることができ、半田付け時の樹
脂に対する悪影響も防止できる。 As described above, according to the multicolor plating lead frame of the present invention, there is no need to perform exterior plating or solder dip after resin molding as in the past, reducing the number of steps, and there is no need to worry about the effects of chemicals or heat due to exterior plating or solder dip. There is no need to do so, and there is no risk of damaging the reliability of the device when applied to the assembly of semiconductor devices. Furthermore, the range of precious metal plating can be reduced, leading to cost savings. Furthermore, the lead frame is a metal plate with precious metal plating film and
Since a Sn plating or solder plating film is produced, a lead frame with a stable surface condition can be obtained without adversely affecting the element or resin. In addition, in resin encapsulation, the precious metal plating film is exposed outside of the resin, which improves adhesion to the lead frame and maintains reliability of the chip, as well as making it easier to solder to circuit boards, etc. In this case, the solder can be stopped at the plating film part having solderability outside the resin-sealed part, and an adverse effect on the resin at the time of soldering can be prevented.
第１図は従来のリードフレームを示す平面図、
第２図は本考案による一実施例のリードフレーム
を示す平面図、第３図は同実施例を用いた半導体
装置の平面図である。
１１……リードフレーム、１１ａ……第１リー
ド、１１ｂ……第２リード、１２……銀メツキ
膜、１３……錫メツキ膜、１４……チツプ、１５
……ワイヤ、１６……樹脂。
Figure 1 is a plan view showing a conventional lead frame.
FIG. 2 is a plan view showing a lead frame according to an embodiment of the present invention, and FIG. 3 is a plan view of a semiconductor device using the same embodiment. 11... Lead frame, 11a... First lead, 11b... Second lead, 12... Silver plating film, 13... Tin plating film, 14... Chip, 15
...Wire, 16...Resin.
Claims (1)
体チツプをダイボンドする領域及び半導体チツプ
に一端が接続されたワイヤの他端を接続する領域
で、かつ樹脂封止領域外まで延長された領域のそ
れぞれの平面に被着された貴金属メツキ膜と、上
記貴金属メツキ膜が被着された樹脂封止部の領域
外から延びた金属板のアウターリード面に直ちに
被着された半田付性をもつSnメツキ又は半田メ
ツキ膜とを備えたことを特徴とする半導体装置の
リードフレーム。 A region where a semiconductor chip is die-bonded and a region where the other end of a wire whose one end is connected to the semiconductor chip is connected, and which extends outside the resin-sealed region, of a metal plate into which leads of a desired shape are punched. a noble metal plating film deposited on the flat surface of the metal plate, and a solderable Sn plating film immediately deposited on the outer lead surface of the metal plate extending from outside the area of the resin sealing portion to which the precious metal plating film was deposited. or a solder plating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982007298U JPS58111958U (en) | 1982-01-21 | 1982-01-21 | Lead frame for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982007298U JPS58111958U (en) | 1982-01-21 | 1982-01-21 | Lead frame for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58111958U JPS58111958U (en) | 1983-07-30 |
| JPH0410699Y2 true JPH0410699Y2 (en) | 1992-03-17 |
Family
ID=30020054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982007298U Granted JPS58111958U (en) | 1982-01-21 | 1982-01-21 | Lead frame for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58111958U (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4316019B2 (en) * | 1996-10-01 | 2009-08-19 | 株式会社東芝 | Semiconductor device and semiconductor device manufacturing method |
| JP4815708B2 (en) * | 1999-01-05 | 2011-11-16 | 日亜化学工業株式会社 | Display device using light emitting diode |
| JP3685057B2 (en) * | 1999-12-08 | 2005-08-17 | 日亜化学工業株式会社 | LED lamp and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51115775A (en) * | 1975-04-04 | 1976-10-12 | Nec Corp | Semiconductor apparatus |
| JPS574183A (en) * | 1980-06-10 | 1982-01-09 | Toshiba Corp | Metallic thin strip for installing semiconductor light-emitting element |
-
1982
- 1982-01-21 JP JP1982007298U patent/JPS58111958U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51115775A (en) * | 1975-04-04 | 1976-10-12 | Nec Corp | Semiconductor apparatus |
| JPS574183A (en) * | 1980-06-10 | 1982-01-09 | Toshiba Corp | Metallic thin strip for installing semiconductor light-emitting element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58111958U (en) | 1983-07-30 |
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