JP7537599B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device having an active layer for use as an optical device.

Communications traffic is steadily increasing with the use of cloud technology and the diversification of IP services such as online business, but the optical communications devices that support this traffic are required to have higher capacity, lower power consumption, and smaller, more dense modules than ever before.

These optical communication devices are classified by the communication distance they can provide depending on their application, but their basic configuration consists of a semiconductor laser that generates light as a carrier wave, an optical modulator to modulate the carrier wave, an optical amplifier to amplify the intensity of the modulated light, and a photoreceiver to convert the modulated light into an electrical signal.

Depending on the application, these optical communication devices are monolithically integrated on the same semiconductor substrate for the purposes of miniaturization and improved power efficiency. In particular, for optical modulators, differential modulation drive is required to increase the efficiency of use of the modulation voltage and improve the S/N ratio of the optical waveform by suppressing common mode noise.

Conventional semiconductor optical modulator integrated lasers used as optical communication devices have a laser and an optical modulator monolithically integrated on the same substrate, and the GND of the elements is wired to a common semiconductor layer. However, with this configuration, it is not possible to achieve differential modulation operation of the optical modulator section for the following reasons. Because the GND between the laser and the optical modulator is shorted, when the optical modulator is operated in differential modulation operation, one-phase modulation voltage flows into the laser, making it difficult to supply the desired voltage to the optical modulator, and at the same time, unnecessary voltage is supplied to the laser, making it difficult to stably operate the laser.

Normally, to achieve differential modulation drive in semiconductor optical devices, a semi-insulating (SI) substrate is used, and the drive terminals of the device are open to GND. In this configuration, to form a laser or optical modulator, a p-polarity semiconductor layer is formed on the SI substrate, an active layer is formed on top of this, and an n-polarity semiconductor layer is formed on top of this. However, with this configuration, although it is possible to fabricate a device with one function on the SI substrate (such as a directly modulated laser), it is not possible to achieve monolithic integration of devices with multiple functions on the same substrate.

In response to this, it is conceivable to integrate a laser and an optical modulator using a butt-joint process in which a p-polarity semiconductor layer, a semi-insulating semiconductor layer and a p-polarity semiconductor layer are formed side by side on an SI substrate, an active layer is formed on top of these, and an n-polarity semiconductor layer is further formed on top of this.

However, with this technology, different semiconductor layers are grown on top of a silicon-insulated substrate, which impairs the flatness between the different semiconductor layers. The active layers of each element are then grown on top of this, which inevitably impairs the flatness of the crystals in the upper layers, degrading in-plane uniformity. Furthermore, when the active layer is used as an optical waveguide, problems such as waveguide loss occur at the joints.

As explained above, conventional technology had the problem that it was not easy to monolithically integrate multiple elements with different functions, such as lasers and optical modulators, while maintaining the crystal quality of each element and electrically isolating the elements from each other.

The present invention has been made to solve the problems described above, and aims to monolithically integrate multiple elements, each with different functions, while maintaining the crystal quality of each element and electrically isolating the elements from each other.

A semiconductor device according to the present invention has a substrate made of a semi-insulating III-V compound semiconductor, a first element region, a second element region, and an isolation region disposed between the first element region and the second element region to isolate the first element region from the second element region, the semiconductor device having a first semiconductor layer made of a carbon-doped III-V compound semiconductor formed on the substrate, a first active layer made of a III-V compound semiconductor and formed on the first semiconductor layer in the first element region, a second active layer made of a III-V compound semiconductor and formed on the first semiconductor layer in the second element region, a first isolation layer made of a semi-insulating III-V compound semiconductor and formed between the first active layer and the second active layer on the first semiconductor layer in the isolation region, and an n-type III-V compound semiconductor the first n-type semiconductor layer formed on the first active layer, a second n-type semiconductor layer formed on the second active layer and made of an n-type III-V compound semiconductor, and a second separation layer formed on the first separation layer and sandwiched between the first n-type semiconductor layer and the second n-type semiconductor layer, the first semiconductor layer being integrally formed across the first element region, the separation region, and the second element region, the activation rate of carbon doped into the first semiconductor layer in the separation region being lower than the activation rate of carbon doped into the first semiconductor layer in the first element region and the second element region , and the activation rate of carbon doped into the first semiconductor layer in the separation region being within a range that allows electrical separation to be achieved between the first element region and the second element region .

As described above, according to the present invention, in a first semiconductor layer formed on a substrate by doping with carbon, the activation rate of carbon doped into the first semiconductor layer in the isolation region is set lower than the activation rate of carbon doped into the first semiconductor layer in the first element region and the second element region, so that multiple elements each having different functions can be monolithically integrated while maintaining the crystal quality of each element and electrically isolating the elements from each other.

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2B is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2C is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a characteristic diagram showing the relationship between the resistance A of the first semiconductor layer 102 and the cross-sectional area of the first semiconductor layer 102 in the first element region 121 and the second element region 122 for each length of the isolation region 123. FIG. 4A is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 4B is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 4C is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 5A is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 5B is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a characteristic diagram showing the relationship between the resistance of the isolation region 123 and the length of the isolation region 123. As shown in FIG. FIG. 7A is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 7B is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment of the present invention. FIG. 7C is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. FIG. 7D is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. FIG. 8 is a cross-sectional view showing a configuration of another semiconductor device according to an embodiment of the present invention.

The following describes a semiconductor device relating to an embodiment of the present invention.

[First embodiment]
First, a semiconductor device according to a first embodiment of the present invention will be described with reference to Figures 1, 2A, 2B, and 2C. This semiconductor device includes a substrate 101 made of a semi-insulating III-V compound semiconductor, and a first semiconductor layer 102 made of a III-V compound semiconductor doped with carbon (C) and formed on the substrate 101. The first semiconductor layer 102 can be made of any of InGaAsP, InGaAs, InGaAlAs, and InAlAs.

The first semiconductor layer 102 has a first element region 121, a second element region 122, and an isolation region 123 disposed between the first element region 121 and the second element region 122 to separate the first element region 121 and the second element region 122. The first semiconductor layer 102 is integrally formed across the first element region 121, the isolation region 123, and the second element region 122.

In addition, the activation rate of C doped into the first semiconductor layer 102 of the isolation region 123 is set lower than the activation rate of C doped into the first semiconductor layer 102 of the first element region 121 and the second element region 122. Therefore, the first semiconductor layer 102 of the isolation region 123 has a higher resistance than the regions of the first element region 121 and the second element region 122. The activation rate of C doped into the first semiconductor layer 102 of the isolation region 123 is set to a range in which electrical isolation can be achieved between the first element region 121 and the second element region 122.

This semiconductor device also includes a first active layer 103a made of a III-V compound semiconductor and formed on the first semiconductor layer 102 in the first element region 121, and a second active layer 103b made of a III-V compound semiconductor and formed on the first semiconductor layer 102 in the second element region 122. Also, a first isolation layer 103c made of a semi-insulating III-V compound semiconductor is provided on the first semiconductor layer 102 in the isolation region 123. The first isolation layer 103c is formed between the first active layer 103a and the second active layer 103b.

For example, the first active layer 103a, the first separation layer 103c, and the second active layer 103b are each formed separately. The first active layer 103a, the first separation layer 103c, and the second active layer 103b are also formed to the same thickness. The same thickness means that the thickness is substantially the same, and includes the case where the thicknesses differ by, for example, 10 nm due to manufacturing constraints. It is important that the thicknesses of the first active layer 103a, the first separation layer 103c, and the second active layer 103b are each set so that the optical coupling efficiency of the optical waveguide between each part is sufficiently high.

This semiconductor device also includes a first n-type semiconductor layer 104a made of an n-type III-V compound semiconductor and formed on the first active layer 103a, and a second n-type semiconductor layer 104b made of an n-type III-V compound semiconductor and formed on the second active layer 103b. Also, a second separation layer 104c made of a semi-insulating III-V compound semiconductor is provided on the first separation layer 103c. The second separation layer 104c is sandwiched between the first n-type semiconductor layer 104a and the second n-type semiconductor layer 104b.

For example, the first n-type semiconductor layer 104a, the second separation layer 104c, and the second n-type semiconductor layer 104b are each formed separately (separately). In addition, in manufacturing, the first n-type semiconductor layer 104a and the second n-type semiconductor layer 104b can be formed from the same layer. In addition, the first n-type semiconductor layer 104a, the second separation layer 104c, and the second n-type semiconductor layer 104b are formed to the same thickness. In addition, the same thickness indicates substantially the same thickness, and includes the case where each is different by, for example, 10 nm due to manufacturing constraints. In addition, these do not need to be the same thickness, and even if the second separation layer 104c is 100 nm thicker than the first n-type semiconductor layer 104a, there is no effect on the characteristics.

This semiconductor device is an optical communication device in which the first element region 121 is a laser, the second element region 122 is an optical modulator, and these optical elements are electrically isolated on the substrate 101 by the isolation region 123. This optical communication device has an optical waveguide structure in which the first active layer 103a, the first isolation layer 103c, and the second active layer 103b are used as cores, and the direction of their arrangement is the waveguiding direction.

Figure 1 shows a cross section parallel to the waveguide direction. Figure 2A shows a cross section perpendicular to the waveguide direction in the first element region 121. Figure 2B shows a cross section perpendicular to the waveguide direction in the second element region 122. Figure 2C shows a cross section perpendicular to the waveguide direction in the separation region 123.

2A, 2B, and 2C, the first active layer 103a, the first isolation layer 103c, the second active layer 103b, the first n-type semiconductor layer 104a, the second isolation layer 104c, and the second n-type semiconductor layer 104b are sandwiched (buried) at their sides in the waveguiding direction by the first SI layer 105 and the second SI layer 106 made of semi-insulating semiconductors. This is a well-known buried heterostructure structure. The first SI layer 105 and the second SI layer 106 are formed on the first semiconductor layer 102.

In the first element region 121, a first p-electrode 107a is formed on the first semiconductor layer 102 in an area where the first SI layer 105 and the second SI layer 106 are not formed, and the first p-electrode 107a is ohmically connected to the first semiconductor layer 102. In the first element region 121, a first n-electrode 108a is formed on the first n-type semiconductor layer 104a, and the first n-electrode 108a is ohmically connected to the first n-type semiconductor layer 104a.

In the second element region 122, a second p-electrode 107b is formed on the first semiconductor layer 102 in an area where the first SI layer 105 and the second SI layer 106 are not formed, and the second p-electrode 107b is ohmic-connected to the first semiconductor layer 102. In the second element region 122, a second n-electrode 108b is formed on the second n-type semiconductor layer 104b, and the second n-electrode 108b is ohmic-connected to the second n-type semiconductor layer 104b.

In this example, the first SI layer 105 and the second SI layer 106 are formed so as to penetrate into a portion of the first semiconductor layer 102 in the thickness direction. Note that the first SI layer 105 and the second SI layer 106 can also be formed without penetrating into a portion of the first semiconductor layer 102 in the thickness direction.

Because the first semiconductor layer 102 is composed of one layer, the flatness of the first active layer 103a, the first separation layer 103c, and the second active layer 103b is not impaired even if the first active layer 103a, the first separation layer 103c, and the second active layer 103b are formed by a so-called butt joint process. Therefore, the optical waveguide formed by the first active layer 103a, the first separation layer 103c, and the second active layer 103b does not cause waveguide loss at each joint portion.

Thus, according to the first embodiment, a plurality of elements each having different functions can be monolithically integrated while maintaining the crystal quality of each element and electrically isolating the elements from each other. As a result, according to the first embodiment, it becomes possible to realize differential modulation driving of monolithically integrated optical elements. The effects of being able to realize differential modulation driving are, first, that the modulation amplitude voltage can be halved, and, second, that the S/N ratio of the optical signal can be improved by reducing common mode noise (Reference 1).

Here, Zn and Be have been widely used as p-polarity dopants for InP materials (Reference 2). On the other hand, C has a smaller diffusion coefficient in semiconductors than Zn and Be (Reference 3), and is characterized by the possibility of high-concentration doping in InGaAlAs (InAlAs) and InGaAsP (InGaAs) materials formed on an InP substrate.

C doped into a semiconductor layer such as InGaAs is activated by heat treatment in a _N2 atmosphere and acts as a p-polarity (Reference 4). It is also known that C acts as an n-polarity/p-polarity depending on the composition of InGaAsP (Reference 5). However, there have been no reports of controlling resistivity by locally changing the activation rate of C by generating a heat distribution in the wafer during heat treatment.

Here, the resistance R [Ω] of the semiconductor layer can be expressed as "R = ρ (L/S)" where ρ [Ωμm] is the resistivity of the semiconductor layer, S [ ^μm2 ] is the cross-sectional area of the semiconductor layer, and L [μm] is the length of the resistive portion of the semiconductor layer. For example, if the semiconductor layer is made of p-InP and 1× ¹⁰¹⁸ cm ^-3 of p dopant is introduced, ρ is 0.066 [Ωcm], and with a cross-sectional area of 2 μm×2 μm and a length of the resistive portion of 50 μm, the isolation resistance is approximately 8.2 kΩ.

According to Fig. 1 in Reference 4, when 7×10 ¹⁹ cm ^-3 of C dopant is introduced into InGaAs and the heat treatment time in N ₂ atmosphere is 20 minutes, the amount of C activated under the conditions of 450° C. and 500° C. is estimated to be about 2.5×10 ¹⁹ cm ^-3 (35%) and 6×10 ¹⁹ cm ^-3 (85%), respectively. From this, if the heat treatment temperature can be changed by 50° C. in the same semiconductor layer (InGaAs layer), a difference of 50% can be given as the activation rate, and as a result, the resistivity ρ can be partially changed in the same semiconductor layer.

In the semiconductor device according to the first embodiment, the area (cross-sectional area) S _iso of the cross section perpendicular to the waveguide direction of the first semiconductor layer 102 in the isolation region 123 and the length L _iso in the waveguide direction of the first semiconductor layer 102 are determined. For example, the first semiconductor layer 102 is formed from InGaAs doped with C, and a gradient is applied to the heat treatment temperature between the first element region 121, the second element region 122, and the isolation region 123. This allows the first semiconductor layer 102 in the first element region 121 and the second element region 122 to be p ⁺ and the first semiconductor layer 102 in the isolation region 123 to be p ^- .

The activated C dopant in the first semiconductor layer 102 in the first element region 121 and the second element region 122, which are p ⁺ , is 75 to 85%. The activated C dopant in the first semiconductor layer 102 in the isolation region 123, which is ^p- , is 35 to 45%. At this time, the resistivity ρ of the first semiconductor layer 102 is approximately 0.01 Ωcm in the first element region 121 and the second element region 122, and 0.02 Ωcm in the isolation region 123. A first p electrode 107a and a second p electrode 107b are formed in the first semiconductor layer 102 in the first element region 121 and the second element region 122, which are p ⁺ .

The cross-sectional area of the first semiconductor layer 102 in the isolation region 123 is denoted by S _iso , and the length of the isolation region 123 is denoted by L _iso . The resistance of the first semiconductor layer 102 in the first element region 121 and the second element region 122 is denoted by A. Furthermore, the resistance of the first n-type semiconductor layer 104a and the second n-type semiconductor layer 104b is denoted by B.

Because the second isolation layer 104c in the isolation region 123 between the first element region 121 and the second element region 122 is made of a semi-insulating semiconductor, the resistivity of resistance B is sufficiently smaller than that of the region of resistance A, and only resistance A needs to be considered.

Calculated values of resistance A are shown in FIG. 3. A typical value of 0.066 Ωcm was used for ρ. As the length L of the isolation region 123 increases from 50 μm to 150 μm, the resistance value increases. To obtain an isolation resistance of 10 kΩ for each functional part of the semiconductor, when L is 100 μm, the cross-sectional area S _iso must be approximately 7 μm ² , and when L is 150 μm, the cross-sectional area S _iso must be approximately 9 μm ² .

Incidentally, as shown in Figures 4A, 4B, and 4C, a structure can be formed in which the first SI layer 105 and the second SI layer 106 are embedded (sandwiched) up to the side surface in the waveguiding direction of the first semiconductor layer 102. Even in this configuration, it is important to have a structure in which S _iso is 10 μm ² or less, as shown in Figure 3. On the other hand, a p-electrode must be formed in the first element region 121 and the second element region 122. The cross-sectional area of the first semiconductor layer 102 as p ⁺ in the first element region 121 and the second element region 122 must be maintained to a size that allows the p-electrode to be maintained, and the S _iso of the first semiconductor layer 102 in the isolation region 123 must be made small. Since the cross-sectional area of the first semiconductor layer 102 that is p ⁺ in the first element region 121 and the second element region 122 becomes S _iso of the first semiconductor layer 102 that is ^p- in the isolation region 123, it is necessary to realize the formation of a p-electrode while maintaining p ⁺ so that S _iso is small. Note that even in the configuration described using Figures 2A, 2B, and 2C in which a p-electrode can be easily formed, it is possible to realize S _iso of ¹⁰ μm2 or less in terms of design.

Next, a manufacturing method will be described. First, a substrate 101 made of InP that has been doped with Fe to make it semi-insulating is prepared. Next, the first semiconductor layer 102 is formed on the substrate 101 by crystal growth of C-doped InGaAs. The doping amount of C can be, for example, 1×10 ¹⁹ cm ⁻³ .

Next, a first active layer 103a with a multiple quantum well structure that functions as a laser and a second active layer 103b with a multiple quantum well structure that functions as an electroabsorption (EA) modulator are formed on the first semiconductor layer 102 made of C-doped InGaAs by a known butt joint process. In addition, between these, InGaAsP with a photoluminescence wavelength of 1.1 mm that functions as electrical isolation is crystal-grown to form a first isolation layer 103c.

Next, Si-doped n-InP is grown by crystal growth on the first active layer 103a and the second active layer 103b to form the first n-type semiconductor layer 104a and the second n-type semiconductor layer 104b, and Fe-doped InP is grown by crystal growth on the first separation layer 103c to form the second separation layer 104c.

Next, in order to form the first SI layer 105 and the second SI layer 106, the first active layer 103a, the first isolation layer 103c, the second active layer 103b, the first n-type semiconductor layer 104a, the second isolation layer 104c, and the second n-type semiconductor layer 104b are processed into a ridge pattern, for example, by wet etching. Also, for example, in the isolation region 123, the first semiconductor layer 102 is also formed into a ridge shape. Next, the first SI layer 105 and the second SI layer 106 are formed by crystal regrowth of InP that is semi-insulating by doping Fe on the first semiconductor layer 102 exposed on the side of the ridge-shaped portion and on the substrate 101.

Next, the first p electrode 107a and the second p electrode 107b are formed in the first element region 121 and the second element region 122. First, an insulating film is formed on the entire surface of the first SI layer 105, the second SI layer 106, the first n-type semiconductor layer 104a, and the second n-type semiconductor layer 104b. Next, the insulating film on the first n-type semiconductor layer 104a and the second n-type semiconductor layer 104b that ensures electrical contact is removed. Next, the first p electrode 107a and the second p electrode 107b are formed so as to extend over the first n-type semiconductor layer 104a, the second n-type semiconductor layer 104b, the first SI layer 105, and the second SI layer 106. The first p electrode 107a and the second p electrode 107b are electrically connected to the first n-type semiconductor layer 104a and the second n-type semiconductor layer 104b at the location where the insulating film was removed. Thereafter, although not shown, wiring is connected to each electrode.

In addition, as an activation process of C in the first semiconductor layer 102, a metal mask made of Au was formed only on the isolation region 123 for protection, and a heat treatment was performed in a _N2 atmosphere at 500°C for 5 minutes. This heat treatment is performed by radiant heat. In this heat treatment, the first element region 121 and the second element region 122 rise to 500°C, but in the isolation region 123, the temperature rises only to about 450°C due to the effect of radiant heat being reflected by the metal mask.

As a result of this process, the activation rate of C in the first semiconductor layer 102 in the first element region 121 and the second element region 122 becomes approximately 85%. Furthermore, as a result of this process, the activation rate of C in the first semiconductor layer 102 in the isolation region 123 becomes approximately 35%. As a result of these, the concentration of activated C in the first semiconductor layer 102 in the first element region 121 and the second element region 122 becomes approximately 8×10 ¹⁸ cm ^-3 . Furthermore, the concentration of activated C in the first semiconductor layer 102 in the isolation region 123 becomes approximately 3×10 ¹⁸ cm ^-3 .

The length of the separation region 123 in the waveguide direction was set to 50 μm. The cross-sectional area of the first semiconductor layer 102 was set to 0.8 μm ² .

When the electrical isolation between the first element region 121 (LD section) and the second element region 122 (EA modulator section) of the semiconductor device according to the first embodiment, which was fabricated as described above, was measured, it was found to be 12.5 kW or more between the first p electrode 107a and the second p electrode 107b, and 50 kW or more between the first n electrode 108a and the second n electrode 108b. Reflecting this electrical isolation, the LD section achieved stable DC operation, and the EA modulator achieved differential modulation operation at 50 Gb/s.

[Embodiment 2]
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to Figures 5A and 5B. This semiconductor device includes a substrate 101 made of a semi-insulating III-V compound semiconductor, a lower first semiconductor layer 102a made of a C-doped III-V compound semiconductor and formed on the substrate 101, and an upper first semiconductor layer 102b made of a C-doped III-V compound semiconductor and formed on the lower first semiconductor layer 102a. Each of the lower first semiconductor layer 102a and the upper first semiconductor layer 102b can be made of any of InGaAsP, InGaAs, InGaAlAs, and InAlAs. The other configurations are the same as those of the first embodiment described above.

In the second embodiment, the semiconductor layer doped with C is composed of two layers. In the first element region 121 and the second element region 122, as shown in FIG. 5A, the first SI layer 105 and the second SI layer 106 are formed on the upper first semiconductor layer 102b. On the other hand, in the isolation region 123, the first SI layer 105 and the second SI layer 106 are formed on the lower first semiconductor layer 102a. The activation rate of C in the lower first semiconductor layer 102a and the upper first semiconductor layer 102b is lower in the isolation region 123 than in the first element region 121 and the second element region 122. For example, in the first element region 121 and the second element region 122, the lower first semiconductor layer 102a and the upper first semiconductor layer 102b are p ⁺ , and in the isolation region 123, the lower first semiconductor layer 102a and the upper first semiconductor layer 102b are ^p- .

The first p electrode 107a and the second p electrode 107b are formed on the upper first semiconductor layer 102b in an area where the first SI layer 105 and the second SI layer 106 are not formed. By configuring in this way, it is possible to increase the electrical isolation in the isolation region 123.

In the isolation region 123, the upper first semiconductor layer 102b in the region where the first SI layer 105 and the second SI layer 106 are to be formed is etched away to expose the lower first semiconductor layer 102a, on which the first SI layer 105 and the second SI layer 106 are formed. Note that in the isolation region 123, it is not necessary to form an electrode on the lower first semiconductor layer 102a in the region where the second SI layer 106 is not formed.

The isolation resistance in the isolation region 123 can be calculated by considering the lower first semiconductor layer 102a and the upper first semiconductor layer 102b, each of which is ^p- , to be connected in parallel. If the resistance of the isolation region 123 is _Riso and the resistances of the lower first semiconductor layer 102a and the upper first semiconductor layer 102b, each of which is p- ^, are _R1 and _R2 , respectively, then the isolation resistance is calculated as follows: 1/ _Riso = (1/ _R1 ) + (1/ _R2 ). The length of the isolation region 123 in the waveguiding direction is L, the cross-sectional area of the lower first semiconductor layer 102a is 0.4 ^μm2 , and the cross-sectional area of the upper first semiconductor layer 102b is ¹⁰ μm2.

The results of calculating the above formula with the resistivity of the upper first semiconductor layer 102b set to 0.02 and the resistivity ρ2 of the lower first semiconductor layer 102a changed to 0.12, 0.1, and 0.033 Ωcm are shown in Fig. 6. The lower first semiconductor layer 102a has a large S _iso , which has a large effect on the resistance, and it is difficult to ensure 10 kΩ in the isolation region 123 unless the resistivity ρ2 of the lower first semiconductor layer 102a in the isolation region 123 is 0.1 or more. On the other hand, if the resistivity ρ2 of the lower first semiconductor layer 102a in the isolation region 123 is 0.12, it is possible to ensure a resistance value of 10 kΩ even if the length of the isolation region 123 is 100 µm.

[Embodiment 3]
Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to Figures 7A, 7B, and 7C. This semiconductor device includes a substrate 101 made of a semi-insulating III-V compound semiconductor, and a first semiconductor layer 102 made of a C-doped III-V compound semiconductor and formed on the substrate 101. The first semiconductor layer 102 can be made of any of InGaAsP, InGaAs, InGaAlAs, and InAlAs.

In addition, in the third embodiment, a p-type semiconductor layer 110 made of p-type InP doped with Zn is further provided between the substrate 101 and the first semiconductor layer 102. The other configurations are the same as those of the above-mentioned embodiments. After the p-type semiconductor layer 110 is formed on the substrate 101, each layer is formed on the p-type semiconductor layer 110 in the same manner as in the above-mentioned manufacturing method, thereby obtaining the semiconductor device according to the third embodiment.

In the third embodiment, the activation rate of C in the first semiconductor layer 102 in the first element region 121 and the second element region 122 is approximately 85% by the heat treatment similar to that described above. Furthermore, this process results in an activation rate of C in the first semiconductor layer 102 in the isolation region 123 of approximately 35%. However, in the third embodiment, the concentration of activated C in the first semiconductor layer 102 in the first element region 121 and the second element region 122 is approximately 4×10 ¹⁸ cm ⁻³ . Furthermore, the concentration of activated C in the first semiconductor layer 102 in the isolation region 123 is approximately 2×10 ¹⁸ cm ⁻³ .

In the third embodiment, the length of the isolation region 123 in the waveguiding direction was set to 120 μm. The cross-sectional area of the first semiconductor layer 102 was set to 0.4 μm ^2. As a result, when the electrical isolation between the first element region 121 (LD section) and the second element region 122 (EA modulator section) of the semiconductor device according to the third embodiment was measured, it was found that the electrical isolation between the first p electrode 107a and the second p electrode 107b was 10.5 kW or more, and between the first n electrode 108a and the second n electrode 108b was 50 kW or more. Reflecting this electrical isolation, the LD section achieved stable DC operation, and the EA modulator achieved differential modulation operation of 50 Gb/s.

Incidentally, as shown in FIG. 7D, in the isolation region 123, in the region where the first SI layer 105 and the second SI layer 106 are not formed, the first semiconductor layer 102 can be removed to expose the p-type semiconductor layer 110, and an ohmic-connected electrode 107c can be formed on top of the p-type semiconductor layer 110, so that the electrode 107c is at ground potential.

In the above configuration, a voltage of about +2.0V is applied to the first p electrode 107a of the first element region 121, which is the LD section. On the other hand, a DC voltage of -0.5 to -1.5V is applied to the second p electrode 107b of the second element region 122, which is the EA modulator, and a modulation amplitude voltage of about 1.0V is superimposed to operate it. As a result, positive and negative voltages are applied to the first semiconductor layer 102 of the first element region 121 and the first semiconductor layer 102 of the second element region 122, respectively. In such a driving configuration, the electrode 107c is set to ground potential, thereby strengthening the separation between the first element region 121 and the second element region 122.

The above-mentioned embodiment 3 makes it possible to improve the optical waveform quality of the differential modulation operation between the first element region 121 (LD section) and the second element region 122 (EA modulator section).

8, the isolation region 123 may have a high mesa structure formed by a stack of the p-type semiconductor layer 110, the first semiconductor layer 102, the first isolation layer 103c, and the second isolation layer 104c without forming the first SI layer 105 and the second SI layer 106. By forming such a high mesa structure, further improvement of electrical isolation in the isolation region 123 can be realized. In addition, in the structure shown in FIG. 8, the cross-sectional area of the connection region of the p-type semiconductor layer 110 is smaller than that of the configuration described using FIG. 7A, FIG. 7B, and FIG. 7C, so that it is easier to ensure electrical resistance in the isolation region 123.

In the above, the first element region 121 is an LD, the second element region 122 is an EA modulator, and they are differentially driven, but this is not limited to the above. The separation region 123 formed continuously with the first element region 121 as an LD can be formed as a branched waveguide structure that branches into multiple parts in a plan view, and the second element region 122 can be connected to each of these to form an MZ modulator. In this case, the layer structure of the separation region 123 is the same as in the above-mentioned embodiment. In addition, mainly the second active layer 103b of the second element region 122 can be designed for the MZ modulator.

As described above, according to the present invention, in a first semiconductor layer doped with carbon and formed on a substrate, the activation rate of the carbon doped into the first semiconductor layer in the isolation region is set lower than the activation rate of the carbon doped into the first semiconductor layer in the first element region and the second element region, making it possible to monolithically integrate multiple elements each having different functions while maintaining the crystal quality of each element and electrically isolating the elements from each other.

It is to be understood that the present invention is not limited to the embodiments described above, and that many modifications and combinations can be implemented by a person having ordinary knowledge in the art within the technical concept of the present invention.

[References]
[Reference 1] W. Kobayashi et al., "Design and Fabrication of Wide Wavelength Range 25.8-Gb/S, 1.3-μM, Push-Pull-Driven DMLs", Journal of Lightwave Technology, vol. 32, no. 1, pp. 3-9, 2014.
[Reference 2] D. Cui et al., "Impact of doping and MOCVD conditions on minority carrier lifetime of zinc-and carbon-doped InGaAs and its applications to zinc- and carbon-doped InP/InGaAs heterostructure bipolar transistors", Semiconductor Science and Technology, vol. 17, pp. 503-509, 2002.
[Reference 3] N. Kobayashi et al., "Abrupt p-type doping profile of carbon atomic layer doped GaAs grown by flow-rate modulation epitaxy", Applied Physics Letters, vol. 50, no. 20, pp. 1435-1437, 1987.
[Reference 4] N. Watanabe et al., "Annealing effect on C-doped InGaAs grown by metalorganic chemical vapor deposition", Journal of Crystal Growth, vol. 195, no. 48-53, 1998.
[Reference 5] H. Sugiura et al., "Characterization of heavily carbon-doped InGaAsP layers grown by chemical beam epitaxy using tetrabromide", Applied Physics Letters, vol. 73, no. 17, pp. 2482-2484, 1998.

101... Substrate, 102... First semiconductor layer, 103a... First active layer, 103b... Second active layer, 103c... First separation layer, 104a... First n-type semiconductor layer, 104b... Second n-type semiconductor layer, 104c... Second separation layer, 105...first SI layer, 106...second SI layer, 107a...first p electrode, 107b...second p electrode, 108a...first n electrode, 108b...second n electrode, 121...first element region, 122... Second element region, 123...isolation region.

Claims (4)

A substrate made of a semi-insulating III-V compound semiconductor;
a first semiconductor layer formed on the substrate, the first semiconductor layer including a first element region, a second element region, and an isolation region disposed between the first element region and the second element region to isolate the first element region from the second element region, the first semiconductor layer being made of a carbon-doped III-V compound semiconductor;
a first active layer made of a III-V compound semiconductor and formed on the first semiconductor layer in the first element region;
a second active layer formed on the first semiconductor layer in the second element region, the second active layer being made of a III-V compound semiconductor;
a first isolation layer made of a semi-insulating III-V compound semiconductor and formed on the first semiconductor layer in the isolation region and sandwiched between the first active layer and the second active layer;
a first n-type semiconductor layer formed on the first active layer and made of an n-type III-V compound semiconductor;
a second n-type semiconductor layer formed on the second active layer and made of an n-type III-V compound semiconductor;
a semi-insulating III-V compound semiconductor on the first separation layer;
a second separation layer formed between the first n-type semiconductor layer and the second n-type semiconductor layer,
the first semiconductor layer is integrally formed across the first element region, the isolation region, and the second element region;
an activation rate of carbon doped into the first semiconductor layer in the separation region is lower than an activation rate of carbon doped into the first semiconductor layer in the first element region and the second element region ;
a first semiconductor layer having a first insulating layer and a second insulating layer, the first insulating layer being electrically isolated from the first semiconductor layer; 2. The semiconductor device according to claim 1 ,
The semiconductor device according to claim 1, wherein the first active layer, the first isolation layer, and the second active layer are formed to the same thickness. 3. The semiconductor device according to claim 1 ,
The semiconductor device according to claim 1, wherein the first n-type semiconductor layer, the second isolation layer, and the second n-type semiconductor layer are formed to the same thickness. The semiconductor device according to any one of claims 1 to 3 ,
The semiconductor device, wherein the first semiconductor layer is made of any one of InGaAsP, InGaAs, InGaAlAs, and InAlAs.

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