JP7506922B2 - Power Cycle Test Equipment - Google Patents

Description

The present invention relates to a semiconductor testing device that performs power cycle testing on semiconductor elements such as SiC, IGBT, MOS-FET, GaN, and bipolar transistors, and a method for testing semiconductor elements.

To provide a semiconductor testing device and a semiconductor element testing method that can efficiently reproduce stresses similar to failure modes in the environment in which semiconductor elements are used, and can evaluate power semiconductor elements and the like with high reliability.

Power semiconductors are semiconductors that can handle high voltages and large currents. For example, HEVs/EVs, which are "advanced technologies" that combine inverters incorporating the latest power semiconductors with motors, are currently becoming more and more popular. In the future, this combination is expected to become the "core" that will contribute to the electrification of various types of transportation equipment, including trains, ships, aircraft, and satellites.

Power semiconductors come in a wide variety of sizes and types, as they are used for everything from small amounts of power supply for CPUs and memory to large amounts of power supply to drive motors.

To further improve energy conversion efficiency, development of new materials for wide-gap power semiconductors, such as SiC (silicon carbide) and GaN (gallium nitride), is also progressing.

Because power semiconductors can handle large amounts of electricity, they also generate a lot of heat and need to be cooled efficiently. For this reason, many factors must be considered when it comes to mounting reliability.

The lifespan of a power semiconductor element can be determined by thermal fatigue caused by heat generation within the power semiconductor element itself, or by thermal fatigue caused by temperature changes in the external environment of the power semiconductor element. There is also a lifespan due to voltage fatigue caused by the voltage applied to the gate insulating film of the power semiconductor element.

Generally, life tests for power semiconductor elements are performed by repeatedly turning current on and off to the semiconductor element. For example, tests are performed by setting an applied voltage and current to the emitter terminal (source terminal) and collector terminal (drain terminal) of the transistor of the semiconductor element, and applying a periodic on-off signal (operation/non-operation signal) to the gate terminal.

The current applied to the semiconductor element during testing is large, at several hundred amperes, and requires low-resistance wiring to avoid heat generation and voltage drop. Because the test current is large, the connections between the semiconductor element and the wiring must be made with low resistance.

The semiconductor elements being tested are often connected in multiple stages, and when the semiconductor elements are transistors, the voltage between the channels varies greatly depending on the test conditions. If the test signal applied to the semiconductor element is not appropriate, the test signal may destroy the semiconductor element.

There are many types of semiconductor device tests, and it is necessary to change the wiring connections to correspond to the type of test. Changing the wiring connections takes a lot of time and can lead to poor connections and connection errors.
The packages of power semiconductor elements are also becoming smaller, and as the packages become smaller, the areas of the connection parts of the terminals of the packages are also becoming smaller.

Patent Publication 2014-138488

In conventional semiconductor testing equipment, tests are performed on power semiconductor elements (transistors, etc.) by turning transistor 117 on and off and passing a constant current Id through the transistor channel.

There are a wide variety of test items performed using semiconductor device test equipment (power cycle test equipment), and the settings or test conditions must be changed to accommodate the test items.

Power semiconductors require a wide variety of reliability tests, but conventional semiconductor element testing equipment has the problem of being unable to efficiently perform a wide variety of reliability tests.

The test items performed by semiconductor test equipment (power cycle test equipment) are diverse, and it is necessary to change the connection (wire connection) to transistor 117 to correspond to the test items.

The constant current Id is often several hundred amperes or more, and the connection wiring 211 and power supply wiring 212 that carry this current must be made of thick wire. In addition, a large current Id flows through the semiconductor electrode terminal. If there is contact resistance between the connection electrode terminal of the semiconductor element and the connection wiring, the contact will generate heat, which can destroy the semiconductor element.

In recent years, power semiconductor elements have also been getting smaller in packaging. As power semiconductor elements get smaller in packaging, the size of the connection electrodes of the power semiconductor elements has also become smaller.

When the connection terminals of a power semiconductor element become smaller, it becomes difficult to connect to the connection wiring of the connection board. In addition, the connection resistance also increases. Because a large current flows through the power semiconductor element, if the connection resistance increases, the connection will heat up and the power semiconductor element will burn out.

Test equipment for power semiconductor elements cannot be fixed by soldering or other methods. It is necessary for test equipment for power semiconductor elements to be able to detach the power semiconductor elements to be tested.

Changing the connections of thick wires to accommodate test items takes a long time, and because it requires work space to change the wiring connections, there is an issue that the test equipment becomes large.

The semiconductor device testing apparatus of the present invention comprises a current switching section that energizes one device while the other device is in a power-off state, a plurality of power supply devices, a plurality of temperature measuring devices, and a noise control device.
In the semiconductor device of the present invention, the cycle and time for turning on (operating) the semiconductor device can be set arbitrarily.

By changing or controlling the cycle tc, on time ton, or off time toff of the power semiconductor element, the time and interval during which a specified current flows through the power semiconductor element is controlled.

When a current is applied to a power semiconductor element for an on-time ton1, the temperature of the power semiconductor element gradually rises. Temperature information of the power semiconductor element is acquired in real time and converted into temperature. When the power semiconductor element reaches the target temperature Ta, the time for turning on the power semiconductor element is changed to ton2, and the on-time of the power semiconductor element is controlled so that the temperature of the power semiconductor element remains at a constant value Ta.

The power semiconductor element 117 has electrode terminals 226 formed or disposed on a flat portion of the back surface and signal terminals 227 formed or disposed on a side surface. Alternatively, the electrode terminals 226 and the signal terminals 227 are formed or disposed on the flat portion of the back surface of the power semiconductor element 117.
On the connection board 514, an electrode pattern 505 that connects to the electrode terminal 226 is formed, and an electrode pattern 506 that connects to the signal terminal 227 is formed.
The power semiconductor element 117 is inserted into the sample hole 512 of the sample placement plate 511 with the electrode terminal 226 facing upward, and positioned.

An anisotropic conductive rubber 504 is disposed between the signal terminal 227 and the connection board 514. The connection board 514 is pressed, so that the signal terminal 227 and the electrode pattern 506 are electrically connected.

As described above, the anisotropic conductive rubber 504 is sandwiched between the electrode terminal 226 and signal terminal 227 of the semiconductor element 117 and the electrode pattern 506 and signal terminal 227 of the connection board 514. The anisotropic conductive rubber 504 electrically connects the electrode pattern 506 and the signal terminal 227. A heat-resistant resist 523 is formed between the electrode pattern 505 and the electrode pattern 506. The electrode pattern is connected to the connection portion 507, and a test current is applied to the connection portion 507 to test the semiconductor element 117.

The semiconductor element testing apparatus and semiconductor testing method of the present invention can display the device state in real time, accurately measure the temperature of the semiconductor device, and can stop the test before the semiconductor device is completely destroyed, and can measure the thermal resistance in real time and automatically measure the K-factor.
In the semiconductor device testing apparatus of the present invention, the signal terminals 227 and the electrode patterns 506 are electrically connected by the anisotropic conductive rubber 504 when pressed.

The power semiconductor element 117 to be tested can be removed by removing the anisotropic conductive rubber 504. In addition, by matching the wiring pattern of the connection board 514 to the shape of the power semiconductor element 117 to be tested and taking into consideration the wiring connection pattern, a wide variety of tests can be performed.

1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. 1A and 1B are a plan view and a cross-sectional view of a semiconductor element. 3A and 3B are an equivalent circuit diagram and an explanatory diagram of a connection board in the semiconductor testing device of the present invention; 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. 1A and 1B are a plan view and a cross-sectional view of a semiconductor element. 3A and 3B are an equivalent circuit diagram and an explanatory diagram of a connection board in the semiconductor testing device of the present invention; 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. FIG. 2 is an explanatory diagram of a sample placement plate in the semiconductor testing device of the present invention. 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; 4 is an explanatory diagram of a pressing plate in the semiconductor testing device of the present invention. 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing device of the present invention. 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing device of the present invention. 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing device of the present invention. 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing device of the present invention. 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. FIG. 2 is an explanatory diagram of a sample placement plate in the semiconductor testing device of the present invention. 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing device of the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing device of the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. 1A and 1B are an equivalent circuit diagram and a block diagram of a semiconductor testing device according to the present invention; FIG. 1 is a configuration diagram of a semiconductor testing device according to the present invention. FIG. 1 is a configuration diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; FIG. 2 is an explanatory diagram of a sample placement plate in the semiconductor testing device of the present invention. 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; FIG. 2 is an explanatory diagram of a semiconductor element. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor device testing device according to the present invention. FIG. 1 is an explanatory diagram of a semiconductor device testing device according to the present invention. 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; 1 is a structural diagram of a semiconductor device testing device according to the present invention; 1 is a structural diagram of a semiconductor device testing device according to the present invention; 1 is a structural diagram of a semiconductor device testing device according to the present invention; 1 is a structural diagram of a semiconductor device testing device according to the present invention; 1 is a structural diagram of a semiconductor device testing device according to the present invention;

The following describes a power semiconductor testing device and a power semiconductor element testing method for power cycle testing and the like according to an embodiment of the present invention, with reference to the attached drawings.

In the embodiments described in the specification, an IGBT is used as an example of a power semiconductor element. The present invention is not limited to IGBTs, and can be applied to various power semiconductor elements such as SiC, MOSFETs, JFETs, and transistors.

The present invention is not limited to being applied to transistors, but can also be applied to two-terminal elements such as diodes, etc. Also, the present invention can be applied to other power semiconductor elements such as thyristors and triacs.
The present invention is not limited to power semiconductor elements, but it goes without saying that the present invention can also be applied to low-power semiconductor elements and semiconductor elements for small-signal control.

The present invention applies a current or voltage to an element or component to perform testing. Therefore, the test subjects are not limited to power semiconductor elements. It goes without saying that the test can also be applied to power resistors, thermistors, posistors, ZNRs, phototransistors, photodiodes, Schottky diodes, high-speed diodes, speakers, motors, mechanical relays, etc.

In each drawing for explaining the embodiment of the invention, elements having the same function are given the same reference numerals, and the description may be omitted. In addition, the embodiments described in this specification may be combined with each other.

Figure 1 is an explanatory diagram and an equivalent circuit diagram of a semiconductor element 117 to be tested. Figure 1(a) is an explanatory diagram that shows a schematic diagram of an example of a semiconductor element 117 to be tested as viewed from the back side. Figure 1(b) is an equivalent circuit diagram of the semiconductor element.

In FIG. 1(a), an SOP (Small Outline Package) is shown as an example of the shape of a semiconductor element, etc. Electrode terminals 226a and 226b are formed on the back surface of the SOP. In the SOP, signal terminals 227 are formed or placed on the back surface (the surface on which electrode terminals 226 are formed) and side surfaces of the package.

A transistor is shown as an example of the semiconductor element 117. The transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied, and an N terminal (emitter terminal of the transistor 117) to which a large current is applied.

A plating film 524 (not shown) is formed on the electrode terminal 226. The plating film 524 is described as a Ni-P film, but a thin film of Ni or Ni-B may also be used. The plating film 524 (not shown) may be made of any material as long as it can be bonded closely to the electrode pattern. Examples of materials other than nickel (Ni) include tin, silver, gold, copper, lead, zinc, and alloys of these.

The thickness of the plating film 524 (not shown) is preferably 1 μm or more and 20 μm or less. In particular, it is preferably 2 μm or more and 6 μm or less. It is preferable to form a gold plating film 525 (not shown) on the plating film 524.

The plating film 524 formed on the electrode terminal 226 is made thicker than the plating film 524 formed on the terminal 227. Alternatively, the plating film 524 is formed on the electrode terminal 226, and the plating film 524 is not formed on the terminal 227. Alternatively, the plating film 524 formed on the signal terminal 227 is made thinner than the plating film 524 formed on the electrode terminal 226.

The thickness of the plating film 524 (not shown) plus the thickness of the gold plating film 525 (not shown) is preferably 1 μm or more and 10 μm or less. In particular, it is preferably 2 μm or more and 6 μm or less.

It is preferable to form gold plating 525 (not shown) on the plating film 524. If the plating film 524 is not formed on the electrode terminal 226 or the signal terminal 227, it is preferable to form the gold plating film 525 on the electrode terminal 226 or the signal terminal 227.

The thickness of the gold plating film 525 (not shown) is 0.01 μm or more. The gold plating film 525 (not shown) has the function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

Figure 2 is a cross-sectional view of the semiconductor element 117 in Figure 1. Figure 2(b) is a cross-sectional view taken along line AA' in Figure 2(a). Figure 2(c) is a cross-sectional view taken along line BB' in Figure 2(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side of the package of the semiconductor element 117.

Figure 3 is an explanatory diagram showing the connection state between the electrode terminal 226 of the semiconductor element 117 and the connection portion 507, and the connection state between the signal terminal 227 and the connection pin 502 of the connector 202.

The electrode terminal 226a and the connection portion 507a are electrically connected by a connection wiring 503. The electrode terminal 226b and the connection portion 507b are electrically connected by a connection wiring 503. Eight connection pins 502 are arranged inside the connector 202.

The connection pin 502a and the signal terminal 227d of the semiconductor element 117 are electrically connected by a signal wiring. The connection pin 502b and the signal terminal 227c of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502c and the signal terminal 227b of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502d and the signal terminal 227a of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502e and the signal terminal 227h of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502f and the signal terminal 227f of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502g and the signal terminal 227g of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502h and the signal terminal 227e of the semiconductor element 117 are electrically connected by a signal wiring 508.

Figure 4 shows an explanatory diagram and an equivalent circuit diagram of the semiconductor element 117 to be tested. Figure 4(a) is an explanatory diagram that shows a schematic diagram of the semiconductor element 117 as viewed from the back side. Figure 4(b) is an equivalent circuit diagram of the semiconductor element.

In FIG. 4(a), a QFN (Quad Flat No leaded package) is shown as an example of the shape of a semiconductor element, etc. Electrode terminals 226a and 226b are formed on the back surface of the QFN. In the QFN, signal terminals 227 are formed or placed on the back surface of the package (the surface on which electrode terminals 226 are formed).

A transistor is shown as an example of the semiconductor element 117. The transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied, and an N terminal (emitter terminal of the transistor 117) to which a large current is applied.

A plating film 524 (not shown) is formed on the electrode terminal 226. The plating film 524 is described as a Ni-P film, but a thin film of Ni or Ni-B may also be used. The plating film 524 (not shown) may be made of any material as long as it can be bonded closely to the electrode pattern. Examples of materials other than nickel (Ni) include tin, silver, gold, copper, lead, zinc, and alloys of these.

The thickness of the plating film 524 (not shown) is preferably 1 μm or more and 20 μm or less. In particular, it is preferable that the thickness is 2 μm or more and 6 μm or less. It is preferable to form a gold plating film 525 (not shown) on the plating film 524.

The plating film 524 formed on the electrode terminal 226 is made thicker than the plating film 524 formed on the signal terminal 227. Alternatively, the plating film 524 is formed on the electrode terminal 226, and the plating film 524 is not formed on the signal terminal 227. Alternatively, the plating film 524 formed on the signal terminal 227 is made thinner than the plating film 524 formed on the electrode terminal 226.

The thickness of the plating film 524 (not shown) plus the thickness of the gold plating film 525 (not shown) is preferably 1 μm or more and 10 μm or less. In particular, it is preferably 2 μm or more and 6 μm or less.

In addition, in either the SOP or QFN package shape, it is also preferable to make the electrode terminal 226 higher (thicker) than the signal terminal 227. For example, the electrode terminal 226 is made higher than the signal terminal 227 by about 10μ to 0.5 mm.

As in the case of the SOP in FIG. 1 etc., it is preferable to form gold plating 525 (not shown) on the plating film 524. If the plating film 524 is not formed on the electrode terminal 226 or the signal terminal 227, it is preferable to form the gold plating film 525 on the electrode terminal 226 or the signal terminal 227.

As with the SOP of FIG. 1, the thickness of the gold plating film 525 (not shown) is 0.01 μm or more. The gold plating film 525 (not shown) has the function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

Figure 5 is a cross-sectional view of the semiconductor element 117 in Figure 4. Figure 4(b) is a cross-sectional view taken along line AA' in Figure 4(a). Figure 4(c) is a cross-sectional view taken along line BB' in Figure 4(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side of the package of the semiconductor element 117.

In the example of FIG. 4, as shown in FIG. 4(b), two transistors 117 (transistor 117m, transistor 117s) are disposed or formed in the QFN. As shown in FIG. 4(a), an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226c of the O terminal of transistor 117m, and an electrode terminal 226b of the N terminal of transistor 117m are formed or disposed on the back surface of the QFN.

Transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em. Transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es.

In the example of FIG. 4, the semiconductor element (transistor) 117s is formed with a diode Ds for temperature measurement. The diode Ds is formed in the same process as the transistor 117. The diode Ds is used to measure the temperature information Tj of the transistor 117s. The diode Ds is connected to the anode terminal as and the cathode terminal ks. The anode terminal as is the signal terminal 227a, and the cathode terminal km is the signal terminal 227b.

The semiconductor element (transistor) 117m is formed with a diode Dm for temperature measurement. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure the temperature information Tj of the transistor 117m. The diode Dm is connected to the anode terminal am and the cathode terminal km. The anode terminal am is the signal terminal 227e, and the cathode terminal km is the signal terminal 227g.

Transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em. A signal Vgs that turns transistor 117 on and off is applied to the gate terminal gm. A constant current Icm is passed from the constant current circuit 118 to the anode terminal am and the cathode terminal km of diode Dm.

Transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es. The gate terminal gs is shorted to the emitter terminal es, and the semiconductor element is tested in a diode-connected state.

Figure 5 is a cross-sectional view of the semiconductor element 117 in Figure 4. Figure 5(b) is a cross-sectional view taken along line AA' in Figure 4(a). Figure 5(c) is a cross-sectional view taken along line BB' in Figure 4(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side of the package of the semiconductor element 117.

Figure 6 is an explanatory diagram showing the connection state between the electrode terminal 226 of the semiconductor element 117 and the connection portion 507, and the connection state between the signal terminal 227 and the connection pin 502 of the connector 202.

The electrode terminal 226a and the connection portion 507a are electrically connected by the connection wiring 503. The electrode terminal 226b and the connection portion 507b are electrically connected by the connection wiring 503. The electrode terminal 226c and the connection portion 507c are electrically connected by the connection wiring 503.

Eight connection pins 502 are arranged in the connector 202, and the connection pin 502a and the signal terminal 227d of the semiconductor element 117 are electrically connected by a signal wiring. The connection pin 502b and the signal terminal 227c of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502c and the signal terminal 227b of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502d and the signal terminal 227a of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502e and the signal terminal 227h of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502f and the signal terminal 227f of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502g and the signal terminal 227g of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502h and the signal terminal 227e of the semiconductor element 117 are electrically connected by a signal wiring 508.

In the embodiments of the present invention, the shapes of the semiconductor elements and the like are described by way of example with SOP and QFN, but are not limited to these. Any shape is acceptable as long as it is possible to connect the electrode terminals 226 and signal terminals 227 to the electrode patterns 505 and 506 of the connection board 514 using a substantially planar connection part such as anisotropic conductive rubber 504. It goes without saying that it is also acceptable to use, for example, BGA (Ball Grid Array), COG (Chip On Glass), flip chip bonding IC, pin grid array, etc.

The anisotropic conductive rubber 504 may be replaced with anisotropic conductive paste, anisotropic conductive adhesive, conductive paste, anisotropic conductive film, or conductive bonding material. It goes without saying that the above points can also be applied to other embodiments.

The P terminal is connected to the electrode terminal 226a. The N terminal is connected to the electrode terminal 226b. The electrode terminal 226 is formed in a flat shape on the back surface of the SOP or QFN. A nickel (Ni) plating film is formed on the surface of the electrode terminal 226 as required.
The electrode terminal 226 is electrically connected to the electrode pattern 505 of the connection board 514 via the anisotropic conductive rubber 504 .

In the example of FIG. 1, the semiconductor element (transistor) 117 is formed with a diode Dm for temperature measurement. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure the temperature information Tj of the transistor 117.

The diode Dm is connected to the anode terminal am and the cathode terminal km. The anode terminal am is the signal terminal 227e, and the cathode terminal km is the signal terminal 227g.

The collector terminal cm of the transistor 117 is connected to the signal terminal 227d, and the emitter terminal em of the transistor 117 is connected to the signal terminal 227h. The gate terminal gm of the transistor 117 is connected to the signal terminal 227f. The signal terminal 227 is formed or disposed on the side of the SOP. The back surface of the SOP is configured to be electrically connected to the electrode pattern 506 of the connection board 514.

Eight signal terminals 227 are arranged on the side of the SOP in the example of FIG. 1, and on the back of the QFN in the example of FIG. 4. The signal terminals 227 are electrically connected to the electrode pattern 506 of the connection board 514 via anisotropic conductive rubber 504. The signal terminals 227, the electrode terminals 226, and the electrode patterns 505 and 506 of the connection board 514 are simultaneously electrically connected by one sheet of anisotropic conductive rubber 504. Alternatively, only the signal terminals 227 and the electrode pattern 506 are electrically connected via the anisotropic conductive rubber 504.

The anisotropic conductive rubber 504 is, for example, a low-load compression type in which gold-plated metal wires are arranged at a narrow pitch on silicone rubber. The wire diameter of the metal wire is, for example, 0.02 mm or more and 0.04 mm or less. The thickness is, for example, 0.2 mm or more and 2 mm or less. The metal wire may be made of gold or a gold alloy.
The gold-plated metal wire is preferably of a non-magnetic type, which allows the semiconductor element 117 to be tested and evaluated at high frequencies.

The metal wires arranged in a sheet of silicone rubber or the like are, for example, arranged parallel to the thickness direction (perpendicular to the plane of the sheet). In particular, it is preferable to arrange the metal wires at an angle of 10° (DEG.) to 35° (DEG.) with respect to an axis perpendicular to the plane of the metal wire sheet.

By tilting the metal wire relative to the vertical axis, the sheet has good flexibility in the thickness direction. In addition, the metal wire penetrates obliquely between the electrode pattern 505 and the electrode terminal 226, and between the electrode pattern 506 and the signal terminal 227, resulting in good electrical contact (electrical connection). High-precision contact can be achieved with a low contact load. In addition, the maintenance cycle can be improved, allowing for repeated use over a long period of time.

In addition to silicone rubber, butyl rubber, ethylene propylene rubber, ethylene vinyl acetate copolymer material, epichlorohydrin rubber, acrylic rubber, etc. can also be used.

The anisotropic conductive rubber 504 is not limited to anisotropic conductive rubber. For example, it can be replaced with an anisotropic conductive film (ACF), an anisotropic conductive adhesive, etc. For ease of explanation, in this specification, 504 will be explained as anisotropic conductive rubber 504.

An anisotropic conductive film is a conductive film made by mixing fine metal particles with a thermosetting or thermoplastic resin and molding it into a film. In this semiconductor device, it is preferable to make the semiconductor element 117 to be tested removable, so it is preferable to use an ACF made of thermoplastic resin.

The conductive particles are mainly structured as spheres with a diameter of 3 to 5 μm, with a nickel layer on the inside, a gold plating layer, and an insulating layer on the outside. ACF is sandwiched between the electrode part and the electrode part of the component, and then thermocompressed using a heater or similar.

Anisotropic conductive adhesives can electrically connect and fix opposing electrodes together. They can also be used with materials that cannot be joined by soldering or that cannot withstand the high temperatures involved in soldering. Anisotropic conductive adhesive materials consist of an adhesive (binder) to fix the electrodes together, and conductive particles that are uniformly dispersed within this binder.

The binder component must have adhesive strength, as well as insulating properties to prevent electrical conduction between adjacent electrodes, and must be a reliable material. If these basic properties are satisfied, any resin can be used as the binder, depending on the specifications, including synthetic rubber, thermoplastic resin, and thermosetting resin.

Examples of conductive materials include metals (nickel or a gold-coated nickel composite), metal-plated plastic or resin cores, or materials with an insulating coating on top that breaks down when exposed to heat or pressure.
The shape is selected to be close to spherical, and the particle size is selected from a few μm to several tens of μm depending on the specifications, particularly the distance between the electrodes.

Transistor 117 has a collector terminal cm, a gate terminal gm, and an emitter terminal em. A signal Vgs that turns transistor 117 on and off is applied to the gate terminal gm. A constant current Icm is passed from the constant current circuit 118 to the anode terminal am and the cathode terminal km of diode Dm.

7A and 7B are explanatory diagrams and an equivalent circuit diagram of a semiconductor element 117 to be tested in another example. Fig. 7A is an explanatory diagram showing a schematic diagram of the semiconductor element 117 as viewed from the back side. Fig. 7B is an equivalent circuit diagram of the semiconductor element. Fig. 7 shows an example of an SOP package.
A transistor is illustrated as the semiconductor element 117. Note that, although similar to other examples, the semiconductor element 117 is not limited to a transistor.

For example, a wide variety of devices can be used, such as the semiconductor element in Figure 55, power resistors, posistors, and thermistors. It goes without saying that multiple elements, such as resistor elements and transistors, formed in a single SOP or QFN package can also be used.

In FIG. 7(b), transistor 117 has a P terminal (collector terminal of transistor 117) to which a large current is applied, and an N terminal (emitter terminal of transistor 117) to which a large current is applied. A diode Dm is formed or disposed between the emitter terminal em of transistor Qm and the collector terminal cm of transistor Qm. The cathode terminal of diode Dm is connected to the collector terminal cm of transistor Qm, and the anode terminal of diode Dm is connected to the emitter terminal em of transistor Qm.

7(a), electrode terminals 226a and 226b are formed on the back surface of the SOP. The P terminal is connected to electrode terminal 226a. The N terminal is connected to electrode terminal 226b. The electrode terminal 226 is formed in a flat shape on the back surface of the SOP. A nickel (Ni) plating film is formed on the surface of the electrode terminal 226 as required. Furthermore, the surface of the electrode terminal 226 is gold plated to prevent oxidation.
The electrode terminal 226 is electrically connected to the electrode pattern 505 of the connection board 514 via the anisotropic conductive rubber 504 .

In the example of FIG. 7, the semiconductor element (transistor) 117 is formed with a diode Dm for temperature measurement. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure the temperature information Tj of the transistor 117.

The diode Dm may be a parasitic diode of a transistor. Needless to say, obtaining temperature information Tj and the like using the parasitic diode Dm can also be applied to other embodiments of the present invention.

The collector terminal cm of the transistor 117 is connected to the signal terminal 227d, and the emitter terminal em of the transistor 117 is connected to the signal terminal 227h. The gate terminal gm of the transistor 117 is connected to the signal terminal 227f. The signal terminal 227 is formed or disposed on the side of the QFN. The signal terminal 227 is also configured so that it can be electrically connected to the electrode pattern 506 of the connection board 514 on the rear surface of the QFN.

In the example of FIG. 7, like the other examples, eight signal terminals 227 are arranged on the side and back of the SOP so that they can be connected to the electrode pattern 506. The signal terminals 227 are electrically connected to the electrode pattern 506 of the connection board 514 via the anisotropic conductive rubber 504. The signal terminals 227, the electrode terminals 226, and the electrode patterns 505 and 506 of the connection board 514 are simultaneously electrically connected by a single sheet of anisotropic conductive rubber 504, etc.

Incidentally, the signal terminal 227, the electrode terminal 226, and the electrode pattern 505 and the electrode pattern 506 of the connection substrate 514 are not limited to being electrically connected simultaneously by one piece of anisotropic conductive rubber 504 etc. It goes without saying that the anisotropic conductive rubber 504 etc. connecting the signal terminal 227 and the electrode pattern 506 of the connection substrate 514 and the anisotropic conductive rubber 504 etc. connecting the electrode terminal 226 and the electrode pattern 505 of the connection substrate 514 may be anisotropic conductive rubber 504 separate from each other.
The above points also apply to other embodiments of the present invention.

Transistor 117 has a collector terminal cm, a gate terminal gm, and an emitter terminal em. A signal Vgs that turns transistor 117 on and off is applied to the gate terminal gm. The emitter terminal em and collector terminal cm are configured to allow a constant current Icm to flow from an external constant current circuit 118 to diode Dm.

Fig. 8 is an explanatory diagram and an equivalent circuit diagram of a semiconductor element 117 to be tested in another example. The example in Fig. 8 is configured by arranging or forming two semiconductor elements 117 of Fig. 7(b) in one QFN. As described above, it goes without saying that two or more semiconductor elements 117 may be arranged or formed in one package such as a QFN.
A plurality of semiconductor elements 117 are arranged in the QFN, and signal terminals 227 and electrode terminals 226 are formed or arranged on the QFN in accordance with the number of semiconductor elements 117 .
Fig. 8A is an explanatory diagram showing a schematic diagram of the semiconductor element 117 as viewed from the backside, and Fig. 8B is an equivalent circuit diagram of the semiconductor element.

In the example of FIG. 8, as shown in FIG. 8(b), two transistors 117 (transistor 117m and transistor 117s) described in FIG. 7(b) are arranged or formed within the QFN.

As shown in FIG. 8(a), an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226c of the O terminal of transistor 117m, and an electrode terminal 226b of the N terminal of transistor 117m are formed or arranged on the rear surface of the QFN.

Diode Ds is connected between the emitter terminal es and collector terminal cs of transistor 117s. Diode Dm is connected between the emitter terminal em and collector terminal cm of transistor 117m.

Transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em. Transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es.

In the example of FIG. 8, the semiconductor element (transistor) 117s is formed with a diode Ds for measuring temperature. The semiconductor element (transistor) 117m is formed with a diode Dm for measuring temperature.

Diode Ds and diode Dm are formed in the same process as transistor 117. Diode Ds is used to measure temperature information Tj of transistor 117s. Diode Dm is used to measure temperature information Tj of transistor 117m. The present invention obtains temperature information Tj of transistor 117 (transistor 117m or transistor 117s) using one of the diodes D (diode Dm or diode Ds) that tests transistors 117s and 117m.

Transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em. A signal Vgs that turns transistor 117 on and off is applied to the gate terminal gm. Transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es.

When testing the transistor 117m, the gate terminal gs is shorted to the emitter terminal es, and the transistor 117s is placed in a diode-connected state, and the transistor 117m is tested. When testing the transistor 117s, the gate terminal gm is shorted to the emitter terminal em, and the transistor 117m is placed in a diode-connected state, and the transistor 117s is tested. It goes without saying that both the transistors 117m and 117s may be placed in a transistor operating state, and both transistors (transistor 117m, transistor 117s) may be tested simultaneously. The above matters are similar to those in other embodiments of the present invention.
FIG. 9 is a plan view and an explanatory diagram of a sample placement plate 511 in the semiconductor testing device of the present invention.

The semiconductor element 117 to be tested is placed in the sample hole 512 of the sample placement plate 511. Note that in this specification, the semiconductor element 117 is mainly described as an SOP-shaped package and a QFN-shaped package.

The thickness of the sample placement plate 511 is thinner than the thickness of the semiconductor element 117 to be tested. The sample placement plate is made of an insulating material.

In FIG. 9, fixing holes 510 are formed at the four corners of the sample placement plate 511. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the sample placement plate 511. The positioning holes 509 are through holes.

Figure 10 is a plan view and an explanatory diagram of the connection board 514. As shown in Figure 10 (a), fixing holes 510 are formed in the four corners of the connection board 514. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the sample placement plate 511. The positioning holes 509 are through holes.

Examples of materials for the heat-resistant substrate of the connection board 514 include glass epoxy material, ceramic material, phenolic resin material, insulated aluminum material, polyimide film, and PET material.

On the connection board 514, an electrode pattern 505 corresponding to the electrode terminals 226 of the semiconductor element 117 to be tested, and an electrode pattern 506 corresponding to the signal terminals 227 of the semiconductor element 117 are formed.
A connector 202 is mounted on the connection board 514 , and a control signal is applied to the terminal of the semiconductor element 117 via the connection pins 502 of the connector 202 .

A connection portion 507 is formed or disposed on the connection board 514. The basic material of the connection portion 507 is thick copper, and the surface is nickel (Ni) plated. In addition to copper for the connection portion 507, silver, copper alloy, silver alloy, and gold alloy can also be used.

Fig. 10(b) is a cross-sectional view of the connection board 514 taken along line CC' in Fig. 10(a). An electrode pattern 505, an electrode pattern 506, a signal wiring 508 (not shown), and a connection wiring 503 (not shown) are formed on a heat-resistant board 526. A heat-resistant resist 523 is formed between the electrode patterns 505 and 506. A two-component alkaline development type solder resist is exemplified, for example, the heat-resistant/heat-dissipating resist HRS-2-6 series by Yamashita Material Co., Ltd.
Copper is exemplified as the material of the electrode patterns 505 and 506. A plating film 524 is formed on the surfaces of the electrode patterns 505 and 506.
The plating film 524 is exemplified by a thin film (Ni--P film) formed by Ni--P plating, and a gold plating film 525 is formed on the surface of the Ni--P film.

Although the plating film 524 will be described as a Ni-P film, a thin film may also be formed from Ni or Ni-B. The plating film 524 may be made of any material as long as it can be bonded closely to the electrode pattern. Examples of the material other than nickel (Ni) include tin, silver, gold, copper, lead, zinc, and alloys of these.
The thickness of the plating film 524 is preferably 1 μm or more and 10 μm or less, and more preferably 2 μm or more and 6 μm or less.
The gold plating film 525 has a thickness of 0.01 μm or more. The gold plating film 525 has a function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

The thickness of the plating film 524 plus the thickness of the gold plating film 525 is preferably 1 μm or more and 10 μm or less. In particular, it is preferably 2 μm or more and 6 μm or less.

It is also preferable that the thickness of the plating film 524 plus the gold plating film 525 be 1 μm or more and 10 μm or less from the plane of the heat-resistant resist 523 to form the convex portion. It is particularly preferable that the thickness of the plating film 524 plus the gold plating film 525 be 2 μm or more and 6 μm or less to form the convex portion.

By forming the plating film 524 etc. on the electrode pattern 505 and the electrode pattern 506, the electrode pattern 505 etc. is formed to have a convex structure protruding from the heat-resistant resist 523 film. Therefore, the anisotropic conductive rubber 504 is deformed by the convex electrode pattern 505 etc. The deformation of the anisotropic conductive rubber 504 provides good electrical connection between the electrode terminal 226 and the electrode pattern 505, and between the signal terminal 227 and the electrode pattern 506.

The electrode pattern 505 has a large electrode area because a large current of several hundred amperes (A) or more flows through it. The electrode pattern 506 is often used as a terminal to which a control signal for the transistor 117 is applied. Therefore, a large current rarely flows through it, and the electrode pattern 506 has a relatively small area.

A large current can be applied by sharing multiple electrode patterns 506 (electrically connecting multiple electrode patterns 506). In this case, multiple signal terminals 227 that apply the same signal are formed or arranged.

In FIG. 10(b), plating 524 of the same thickness is formed or disposed on electrode pattern 505 and electrode pattern 506. In addition, a gold plating film 525 is formed on plating film 524.

In FIG. 10(c), plating 524 is formed or placed on electrode pattern 505 with a thickness greater than that on electrode pattern 506. In other words, plating film 524b is formed thicker than plating film 524a. In addition, gold plating film 525 with the same thickness is formed on plating film 524.

In the embodiment shown in FIG. 10(c), the anisotropic conductive rubber 504 is sandwiched between the signal terminal 227 and the electrode pattern 506 to electrically connect them. The electrode terminal 226 and the electrode pattern 505 are electrically connected directly and in close contact with each other.

10 shows an example in which the thickness of the plating film 524 is made different, and the electrode pattern 505 is configured to be more convex than the electrode pattern 506. It goes without saying that in addition to making the thickness of the plating film 525 different, the thicknesses of the electrode patterns 505 and 506 may be changed to make the electrode pattern 505 more convex than the electrode pattern 506.
Fig. 10 shows an embodiment in which the thickness of the connection substrate 514 is uniform (flat), while Fig. 57 shows an embodiment in which the thickness of the connection substrate 514 is varied.
Fig. 57(b) is a cross-sectional view taken along line CC' in Fig. 57(a). In Fig. 57, a mounting recess 239 is formed in a connection board 514.

As an example, the placement recess 239 is formed by removing the heat-resistant resist 523 of the connection board 514. In addition, when forming the heat-resistant resist 523, the placement recess 239 is formed using a molding die.

An electrode pattern 506 is formed in the placement recess 239. As shown in FIG. 57(b), the thickness of the electrode pattern 506 is formed to be thinner than the thickness of the electrode pattern 505.

A plating film 524 is formed on the electrode patterns 505 and 506, and a gold plating 525 is formed on the plating film 524. In Fig. 57(b), the plating film 525b and the plating film 525a are illustrated as having the same film thickness, but it goes without saying that the film thickness of the plating film 525b and the film thickness of the plating film 525a may be different, as shown in Fig. 10.
Other points are the same as or similar to other embodiments of the present invention, so a description thereof will be omitted.

Figure 57(c) is an explanatory diagram showing the state in which a semiconductor element 117 such as SOP117 or QFN117 is attached to the electrode pattern 505 and electrode pattern 506 in Figures 57(a) and 57(b).

Anisotropic conductive rubber 504a is inserted or placed in placement recess 239. Anisotropic conductive rubber 504a is sandwiched between signal terminal 227 and electrode pattern 506. Electrode terminal 226 and electrode pattern 505 are directly electrically connected.

As shown in FIG. 11, the anisotropic conductive rubber 504a is pressed to electrically connect the signal terminal 227 and the electrode pattern 506 via the conductive wire 230. In FIG. 13, a placement recess 239 is formed around the periphery of the anisotropic conductive rubber 504a.

In the embodiment of FIG. 57, since the placement recess 239 is formed, even if the anisotropic conductive rubber 504a has a thickness, it is stored within the placement recess 239 within the anisotropic conductive rubber 504a, and the electrode pattern 505 and the electrode terminal 226 are in close contact with each other, thereby achieving a closer and better electrical connection.

Figure 11(a) is an explanatory diagram of the SOP and QFN electrode terminals 226 and electrode pattern 505, and the SOP and QFN signal terminals 227 and electrode pattern 506 aligned via anisotropic conductive rubber 504.

In the embodiment of FIG. 11, one anisotropic conductive rubber 504 can simultaneously electrically connect the electrode terminal 226 to the electrode pattern 505 and the signal terminal 226 to the electrode pattern 506.

The first anisotropic conductive rubber 504 may be configured to electrically connect the electrode terminal 226 and the electrode pattern 505, and the second anisotropic conductive rubber 504 may be configured to electrically connect the signal terminal 226 and the electrode pattern 506.

The formation area of electrode pattern 505a is larger than the formation area of electrode terminal 226a. The formation area of electrode pattern 505b is larger than the formation area of electrode terminal 226b. The formation area of electrode pattern 505c is larger than the formation area of electrode terminal 226c.

As described above, by making the electrode area of the electrode pattern 505 larger than the formation area of the electrode terminal 226, alignment becomes easier and connection with the anisotropic conductive rubber 504 becomes easier.

The area of electrode pattern 506a is larger than the area of signal terminal 227a. The area of electrode pattern 506b is larger than the area of signal terminal 227b. The area of electrode pattern 506c is larger than the area of signal terminal 227c. The area of electrode pattern 506d is larger than the area of signal terminal 227d. The area of electrode pattern 506e is larger than the area of signal terminal 227e. The area of electrode pattern 506f is larger than the area of signal terminal 227f. The area of electrode pattern 506g is larger than the area of signal terminal 227g. The area of electrode pattern 506h is larger than the area of signal terminal 227h.

As described above, by making the electrode area of the electrode pattern 506 larger than the formation area of the signal terminal 227, alignment becomes easier and connection with the anisotropic conductive rubber 504 becomes easier.

The SOP or QFN semiconductor element 117 to be tested is placed in the sample hole 512 in the sample placement plate 511 with the electrode terminals 226 and signal terminals 227 facing upward. Anisotropic conductive rubber 504 is placed on the electrode terminals 226 and signal terminals 227. A connection board 514 is placed on the anisotropic conductive rubber 504.

It is preferable to use anisotropic conductive rubber 504 with a Shore hardness of 30 or more and 100 or less. If the Shore hardness is less than 30, it will deform when pressed, and if the Shore hardness is more than 100, it will not deform much when pressed, resulting in poor electrical connection.

The connection board 514 and the sample placement plate 511 are positioned by the positioning posts 518 inserted into the positioning holes 509, so that the electrode terminals 226 and the electrode patterns 505, and the signal terminals 227 and the electrode patterns 506 are aligned.

By pressing downward from the connection board 514 side, the anisotropic conductive rubber 504 is deformed, and the electrode terminal 226 and the electrode pattern 505 , and the signal terminal 227 and the electrode pattern 506 are electrically connected via the anisotropic conductive rubber 504 .
11B and 11C show schematic views of the direction of the conductive lines 230. FIG.

The anisotropic conductive rubber 504 is made of silicone rubber with gold-plated metal wires arranged at a narrow pitch as conductive wires 230. The wire diameter of the metal wire is 0.02 mm or more and 0.04 mm or less, and the thickness of the silicone rubber is 0.2 mm or more and 2 mm or less. When pressed, the silicone rubber becomes 10 μm or less in thickness.

The arrangement pitch of the conductive wires 230 is, for example, 0.05 mm or more and 0.4 mm or less. It is preferable that the metal wires arranged on a sheet of silicone rubber or the like are arranged so that the metal wires are tilted at an angle of 10° (DEG.) to 35° (DEG.) with respect to an axis perpendicular to the plane of the metal wire sheet.

Figure 11(b) shows a schematic diagram of the conductive wire 230 arranged in the vertical direction relative to the paper surface. Figure 11(c) is an explanatory diagram showing a schematic diagram of the arrangement direction of the conductive wire 230 within the cross section of the anisotropic conductive rubber 504.

By tilting the metal wire relative to the vertical axis, the sheet has good flexibility in the thickness direction. The gold-plated metal wire is preferably non-magnetic. By using a non-magnetic type, the semiconductor element 117 to be tested can be tested and evaluated at high frequencies.

As shown in FIG. 11(b), the signal terminal 227 has a rectangular shape, and the anisotropic conductive rubber 504 is arranged so that the longitudinal direction of the conductive wire 230 roughly coincides with the longitudinal direction of the rectangular shape.

When pressed, the conductive wire 230 in the anisotropic conductive rubber 504 penetrates the electrode pattern 506 and the signal terminal 227, and the electrode pattern 505 and the electrode terminal 226, achieving good electrical connection.

Figure 12 is a plan view and explanatory diagram of a connection board 514 in which there are three electrode terminals 226 (electrode terminal 226a, electrode terminal 226b, electrode terminal 226c) as shown in Figure 5. Three connection parts 507 (connection part 507a, connection part 507b, connection part 507c) are also formed or arranged. Other configurations or structures are the same or similar to those described in Figure 10, so description will be omitted.

FIG. 13A is an explanatory diagram of the state in which the SOP/QFN electrode terminals 226 and electrode pattern 505, and the SOP/QFN signal terminals 227 and electrode pattern 506 are aligned via anisotropic conductive rubber 504 when there are three electrode terminals 226 (electrode terminal 226a, electrode terminal 226b, electrode terminal 226c) as shown in FIG. 5 etc.
FIG. 13B diagrammatically illustrates a state in which the conductive wires 230 are arranged in the up-down direction relative to the paper surface.
13B, the anisotropic conductive rubber 504a is disposed on the signal terminal 227. The anisotropic conductive rubber 504 is not disposed on the electrode pattern 505.
The anisotropic conductive rubber 504 has a rectangular shape, and one anisotropic conductive rubber 504 covers (is layered on) a plurality of signal terminals 227 .
The conductive lines 230 in the anisotropic conductive rubber 504 are arranged and oriented in the longitudinal direction of the rectangular shape of the anisotropic conductive rubber 504 .

The anisotropic conductive rubber 504 shown in FIG. 13(b) expands and contracts when pressed, etc., but because it has a rectangular shape, it is particularly likely to expand and contract in the longitudinal direction. Therefore, the conductive wire 230 is likely to move in the longitudinal direction (orientation direction) of the conductive wire 230. The movement of the conductive wire 230 allows good electrical connection between the signal terminal 227 and the electrode pattern 506.

As described above, when the anisotropic conductive rubber 504 is rectangular, the conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the anisotropic conductive rubber 504, as shown in FIG. 13(b). Also, when the signal terminal 227 and the electrode pattern 506 are rectangular, the conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the signal terminal 227 and the electrode pattern 506.

The conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the signal terminal 227 and electrode pattern 506, but the direction of the formation of the conductive wire 230 may be within ±45° (DEG.) of the longitudinal direction. Preferably, the direction of the formation of the conductive wire 230 is within ±20° (DEG.) of the longitudinal direction.

Other configurations or structures are the same as or similar to those described in FIG. 11, and therefore will not be described here. Needless to say, the above points can also be applied to other embodiments in this specification, such as the embodiment in FIG. 57.

Figure 14 shows a plan view and an explanatory diagram of the pressure plate 515. It has a good flatness and a structure or configuration that can be insulated from at least the conductive part of the connection board. Examples of materials for the pressure plate include copper, stainless steel, aluminum, and brass. Other examples include ceramics and phenolic resin.

The pressure plate 515 is placed on the connection board 514. By applying pressure from above the pressure plate 515, the connection board 514 is evenly pressed. The pressure also presses the anisotropic conductive rubber 504, which is placed in close contact with the electrode patterns 505 and 506 of the connection board 514. The anisotropic conductive rubber 504 electrically connects the electrode pattern 505 and the electrode terminal 226. Also, the electrode pattern 506 and the signal terminal 227 are electrically connected.

Fixing holes 510 are formed at the four corners of the pressure plate 515. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the pressure plate 515. The positioning holes 509 are through holes.
FIG. 15 is an explanatory diagram of a connection state in which the SOP 117 or QFN 117 and the connection board 514 are connected with the anisotropic conductive rubber 504 .

As shown in FIG. 15, it is placed on the positioning support plate 519. The positioning support plate 519 is made of a material with good thermal conductivity. Examples of materials for the positioning support plate 519 include copper, stainless steel, aluminum, brass, and ceramics. Note that the surface plate 520 shown in FIG. 16 and other figures is also made of a material with good thermal conductivity, just like the positioning support plate 519. This is to ensure good transfer of heat from the heating/cooling plate 134.

The SOP117 or QFN117 is in close contact with the positioning support plate 519. If necessary, grease with good thermal conductivity is applied between the SOP117 or QFN117 and the positioning support plate 519.

The SOP117 or QFN117 is placed by fitting it into the sample hole 512 of the sample placement plate 511. In addition, a variable mechanism is configured and added to change the size of the sample hole 512 to match the size of the SOP117 or QFN117 so that various SOP117s or QFN117s can be clamped and fixed as necessary.

Anisotropic conductive rubber 504 is disposed on the electrode terminals 226 and signal terminals 227 of the SOP117 or QFN117. When pressed, the anisotropic conductive rubber 504 generates electrical conduction in the vertical direction.

The electrode patterns 505 and 506 of the connection board 514 are positioned on the anisotropic conductive rubber 504. Heat-resistant resist 523 is formed or placed between the electrode terminal 226 and the signal terminal 227, etc.

A plating film 524b is formed on the electrode patterns 505 and 506, and is convex by several μm from the surface of the heat-resistant resist 523. If the electrode patterns 505, etc. themselves are convex from the flat surface of the heat-resistant resist 523, etc., there is no need to make them convex with the plating film 524, etc. It is preferable to also make the signal terminals 227 and electrode terminals 226 of the SOP117 or QFN117 convex with the plating film 524a.

As shown by the dotted lines in FIG. 15, the anisotropic conductive rubber 504 is pressed more firmly by the plating film 524, electrically connecting the electrode pattern 505 of the connection board 514 to the electrode terminal 226, and the electrode pattern 506 to the signal terminal 227.

In the embodiment of FIG. 15, the electrode terminal 226 and the signal terminal 227 use a common (single) piece of anisotropic conductive rubber 504 to achieve electrical connection with the electrode pattern 505 or the electrode pattern 506.

However, the present invention is not limited to this, and the electrode pattern 505 and the electrode terminal 226 may be electrically connected by the first anisotropic conductive rubber 504, and the electrode pattern 506 and the signal terminal 227 may be electrically connected by the second anisotropic conductive rubber 504. Even in the above case, the matters described in Figs. 11 and 13 are implemented.
Fig. 56 is an explanatory diagram of a state in which the semiconductor element 117 is connected to a connection board 514. Basically, the state in Fig. 15 is applicable.
In FIG. 56, anisotropic conductive rubber 504 a is disposed between electrode pattern 506 of connection board 514 and signal terminal 227 .

A plating film 524 is formed on the electrode patterns 505 and 506, and gold plating 525 is formed on the plating film 524. In FIG. 56, the plating film 524 on the electrode pattern 505 is formed thicker than the plating film 524a on the electrode pattern 506.

In FIG. 56, the plating film 524b is formed thick, so even if the anisotropic conductive rubber 504 is thick, the electrode pattern 505 and the electrode terminal 226 are tightly attached by pressing, achieving good electrical connection.

Anisotropic conductive rubber 504 is sandwiched between the signal terminal 227 and the electrode pattern 506. The electrode terminal 226 and the electrode pattern 505 are directly electrically connected. As described in FIG. 13, the anisotropic conductive rubber 504 is pressed, and the signal terminal 227 and the electrode pattern 506 are electrically connected by the conductive wire 230.

In the embodiment of FIG. 56, even if the anisotropic conductive rubber 504 has a thickness, the electrode pattern 505 and the electrode terminal 226 are in close contact with each other, and a closer and better electrical connection can be achieved.
Needless to say, the configuration or structure of FIG. 56 can also be applied to the arrangement recess 239 of FIG.

Figures 16 and 17 are explanatory diagrams explaining the mounting portion of the semiconductor element 117 to be tested by the semiconductor testing device of the present invention. Figure 16(a) is an explanatory diagram showing a schematic view of the mounting portion as seen from above. Figure 16(b) is a cross-sectional view taken along line AA' in Figure 16(a).

In FIG. 17, a thick plating film 524 is formed on the electrode pattern 505. Anisotropic conductive rubber 504a is placed between the signal terminal 227 and the electrode pattern 506. The electrode pattern 505 and the electrode terminal 226 are in close contact with each other, and an electrical connection is made by pressing them.

Two supports 518 (support 518a, support 518b) are attached to the positioning support plate 519. Support 518a is inserted into positioning hole 509a of sample placement plate 511, positioning hole 509a of connection board 514, and positioning hole 509a of pressure plate 515. Support 518b is inserted into positioning hole 509b of sample placement plate 511, positioning hole 509b of connection board 514, and positioning hole 509b of pressure plate 515.

The SOP 117 and QFN 117 are inserted into the sample holes 512. The electrode patterns of the connection board 514 and the electrode terminals 226 and signal terminals 227 of the QFN are positioned by inserting the support posts 518 into the positioning holes. Pressing is performed in the B direction from the pressing plate 515 side.
FIG. 18 is an explanatory diagram for explaining a method of mounting a test semiconductor element 117 on the semiconductor testing apparatus of the present invention.
As shown in FIG. 18A, a sample placement plate 511 has sample holes 512, positioning holes 509, and fixing holes 510 formed therein.

As shown in FIG. 18(b), a semiconductor element 117 is placed in a sample hole 512 of a sample placement plate 511. The QFN or SOP semiconductor element 117 is placed with the electrode terminals 226 facing upward. Anisotropic conductive rubber 504 is placed on the electrode terminals 226.

As shown in FIG. 18(c), a connection board 514 is placed on the anisotropic conductive rubber 504. The connection board 514 is positioned so that a current power supply device can be connected to the connection portion 507.

Next, as shown in FIG. 18(d), the pressure plate 515 is placed on the connection substrate 514. The sample placement plate 511, the connection substrate 514, and the pressure plate 515 are positioned by the positioning posts 518 inserted into the positioning holes 509.

Next, as shown in FIG. 18(e), a fixed support (not shown) or the like is inserted into the fixing hole 510, and a pressing tool 516 is attached to the fixed support, thereby pressing the anisotropic conductive rubber 504.

In Fig. 9 and other figures, there is one sample hole 512 in the sample placement plate 511, but the present invention is not limited to this. Fig. 19 shows an embodiment in which two semiconductor elements 117 are connected and tested in the connected state. In the embodiment of Fig. 9(b), two semiconductor elements 117 of Fig. 1 are connected. The electrode terminal 226b of the semiconductor element 117s and the electrode terminal 226a of the semiconductor element 117m are connected by a connection wiring 503. The connection wiring 503 is formed on a connection board 514. Other configurations are explained in other examples in the specification, so explanations are omitted.

In the case of the embodiment of FIG. 19, as shown in the sample placement plate 511 of FIG. 20, a sample hole 512a for the semiconductor element 117s and a sample hole 512b for the semiconductor element 117m are formed in the sample placement plate 511. The present invention allows multiple semiconductor elements 117 to be tested by forming an appropriate number of sample holes 512 in the sample placement plate 511.

Figure 27 is a diagram showing the configuration of the power cycle test device (semiconductor test device) of the present invention. The power cycle test device has a chiller (cooling/warming device) 136, a heating/cooling plate 134, and a circulating water pipe 135 that circulates between the heating/cooling plate 134 and the chiller 136. The heating/cooling plate 134 is loaded with transistors 117 as semiconductor elements to be tested. In practice, to accommodate a wide variety of shapes of semiconductor elements 117, a surface plate 520 is attached to the heating/cooling plate 134, a positioning support plate 519 is attached to the surface plate 520, and the semiconductor element 117 is placed on the positioning support plate 519.

The device fixing and connecting apparatus 610 includes a heating and cooling plate 134 and a circulating water pipe 135 that circulates water between the heating and cooling plate 134 and a chiller 136. In addition, a transistor 117 is mounted on the heating and cooling plate 134 as a semiconductor element to be tested, and a sample connecting circuit 203 (not shown) is configured or arranged therein.
Heat from the heating/cooling plate 134 is transferred to the semiconductor element 117 via the surface plate 520 and the positioning support plate 519 .

The heat from the heating/cooling plate 134 changes the current Id, gate voltage Vgs, and voltage Vce to set the test conditions so that the temperature information Tj of the transistor 117 being tested becomes a specified value.

When the temperature information Tj changes, it is determined that the transistor 117 has deteriorated or its characteristics have changed, and the test of the transistor 117 is stopped or the control method is changed.

Note that the current flowing through or applied to transistor 117 is described as a constant current Id, but the present invention is not limited to this. It goes without saying that Id may be a current that changes at a predetermined cycle or time. Also, it is not limited to a current, and may be a voltage.

The change in the characteristics of transistor 117 is judged or determined based on the change in temperature information Tj. In addition, the change in characteristics, reliability, and lifespan of transistor 117 are evaluated based on the time it takes for voltage Vce to reach a predetermined voltage, the time until transistor 117 is destroyed, etc.

In the semiconductor testing method of the present invention, the external conditions are changed according to the deterioration or characteristic changes of transistor 117. For example, if transistor 117 generates heat, the water temperature is lowered. By lowering the water temperature and reducing the current flowing through transistor 117, the deterioration and characteristic changes of transistor 117 do not progress, and as a result, the lifespan of transistor 117 is extended. Therefore, the lifespan and reliability characteristics of transistor 117 for specified set conditions can be quantitatively measured and determined.

The temperature of the transistor 117 is maintained at a specified or predetermined value by heating or cooling the circulating water in the chiller 136. The temperature of the transistor, etc. is also periodically changed in response to the test conditions, and the transistor is cooled or heated to a constant value. The temperature information Tj of the test transistor is also measured, and the chiller 136 is controlled to maintain the measured temperature information Tj at a constant value.

Chillers are designed to keep the temperature of equipment constant by circulating water or heat transfer medium while controlling its temperature. They are primarily used for cooling, but can also heat as well as cool. They are designed to allow for a variety of temperature controls.

The control rack 131 has a power supply unit 132 that supplies a test current and a test voltage to the transistor 117, and a control circuit 133 that controls the transistor 117 or sets the test conditions.

The control circuit 133 receives temperature information Tj of the transistor 117 and controls the chiller 136 based on the temperature information Tj. Alternatively, the control circuit 133 controls the chiller 136 so that the temperature information Tj becomes a predetermined value.

Note that although circulating water is described in this specification, it is not limited to water. It may be ethylene glycol, glycerin, freon, etc., or forced air cooling. The chiller 136 controls the liquid in the circulating water pipe 135 to a temperature range of, for example, -1°C to +100°C, and supplies it to the heating and cooling plate 134 of the test unit. The heating and cooling plate 134 has a sufficiently large heat capacity.

In the above embodiment, a heating/cooling plate 134 is used, but the heating plate and cooling plate may be separate, and heating and cooling may be performed using a heat source or cold source other than the heating/cooling plate.

Figure 68 shows a voltage and current application jig (apparatus) for a double-sided cooling sample (power semiconductor element). By using a double-sided cooling structure for semiconductor devices, it becomes possible to apply a large current.

38 and 43 show heat pipes 223 arranged on the back surface of connection structure 218. The present invention is not limited to this, and as shown in Figures 68 and 69, heat pipes 223 may be arranged on the side surface of connection structure 218, and the side surface of connection structure 218 may be pressed from above with a pressing member 608 to be fixed.
The voltage and current application jig (device) suppresses heat generation in the contacts and wiring and can reproduce test conditions according to the purpose.

In Fig. 68, a test current and a control signal are supplied from a device fixing and connecting device 610. The test current is applied to a connection structure 218. A terminal connection portion 609 for connecting to a connection terminal of a power semiconductor element is disposed at one end of the connection structure 218. A heat pipe 223 is disposed in the connection structure 218. A cooling fan 229 is disposed at the lower or upper part of the connection structure 218. The air flow generated by the cooling fan 229 passes between the connection structure 218, the heat pipe 223, and the pressing member 608, and suppresses the temperature rise of the connection portion with the device 117, the contact point, the connection structure 218, etc.
Within the device fixing and connecting device 610, a connecting structure 218

As shown in Figures 27, 28, and 29, the device fixing and connecting device 610 contains a heating and cooling plate 134, a semiconductor element 117 to be tested, a device for fixing or holding the semiconductor element 117 having a pressing head 530, etc., a sample connection circuit 203, etc. The cover of the device fixing and connecting device 610 is made of a structure that can provide electrostatic and electromagnetic shielding, and the cover is grounded.

The heat pipe 223 is in close contact with the connection structure 218. Thermally conductive grease or a heat dissipating silicone oil compound may be applied between the surface of the connection structure 218 and the heat pipe 223.

The material of the connection structure 218 will be described as copper, but is not limited to copper. Examples of materials for the connection structure 218 include copper (linear expansion coefficient 16.8), brass (linear expansion coefficient 19), iron (linear expansion coefficient 12.1), and stainless steel (SUS304) (linear expansion coefficient 17.3).

Examples of materials for the heat pipe 223 include those with a large linear expansion coefficient, such as aluminum (linear expansion coefficient 23), tin (linear expansion coefficient 26.9), and lead (linear expansion coefficient 29.1). Of these, it is preferable to use copper (linear expansion coefficient 16.8) as the material for the connection structure 218 and aluminum (linear expansion coefficient 23) as the material for the heat pipe. It is also possible to use an alloy made by mixing aluminum with a second metal such as molybdenum.

Figure 69 is a perspective view of the side of Figure 68 seen from the opposite direction. A circulating water pipe 135 that supplies or discharges circulating water is attached to the device fixing/connecting device 610. The cooling fan 229 may be placed on the top or side of the connection structure 218. Alternatively, it may be placed in two or more directions, such as up, down, left, or right.

A pressing member 608 is attached to the support 534, and fixes and holds the connection structure 218. The pressing member 608 can be moved up and down the support 534, and can be held with a predetermined pressure.

Figures 70, 71, and 72 show equipment for use with high heat dissipation general-purpose devices (TO packages, etc.) used in the semiconductor element testing equipment of the present invention. It is used when the power semiconductor element is a TO-247 package. A current application circuit and an on/off pulse driver circuit for applying to the gate terminal of the transistor are mounted or formed on the connection board 514.

The connection board 514 can be custom designed to match the semiconductor device to be tested, and can accommodate a variety of device shapes. For example, it can accommodate the chip shapes or structures of various semiconductor elements 117 described in Figures 2, 5, 7, 58, etc.

72, a heating/cooling plate 134b is disposed under a positioning support plate 519a. A power semiconductor device 117 to be tested is disposed on the positioning support plate 519a. The connection terminals of the power semiconductor device are electrically connected to the electrodes of a connection board 514. A gate signal and a test current from the connection board 514 are applied to the power semiconductor device 117.
The device stand 611 is a stand on which the semiconductor device element 117 is placed, and is made of a resin material that suppresses static electricity, and has flexibility and springiness.

The pressing posts 531 are arranged so that the connection terminals of the power semiconductor device 117 and the connection board 514 are in close contact with each other, and are pressed to provide a good electrical connection between the connection terminals of the power semiconductor device and the connection board 514. When the semiconductor element 117 has the configuration shown in FIG. 2, FIG. 5, etc., the connection board 514 may have the configuration shown in FIG. 10, FIG. 12, FIG. 54, FIG. 57, etc., and the anisotropic conductive rubber 504 may be used to connect the electrode pattern 506 and the signal terminal 227.

The positioning support plate 519b is placed on the top surface of the power semiconductor device 117 and fixes the position of the power semiconductor device. The heating/cooling plate 134a cools or heats the power semiconductor device from the top surface of the power semiconductor device 117.

Figures 70 and 71 are diagrams showing the structure of a surface mount component jig used in the semiconductor element test apparatus of the present invention, and an explanatory diagram of the mounting of device element 117. It can also be used for surface mount devices such as QFN packages and SOP packages.

A surface plate 520 made of a metal material with good thermal conductivity is disposed on the heating/cooling plate 134b. A positioning support plate 519 is disposed on the surface plate 520. The semiconductor element 117 is disposed on a connection board 514 and also on a device stand 611. The connection terminals of the semiconductor element 117 are pressed by an insulating pressing plate 513, and the connection terminals of the conductive element 117 are connected to the electrodes of the connection board 514.
The connection is made with electrodes formed on the connection board 514. The positioning support plate 519 presses and fixes the connection board 514 so that the connection board 514 has a flatness.
22 is an explanatory diagram of the semiconductor testing device of the present invention. The heating/cooling plate 134 is disposed on a base 522. The base 522 is exemplified by a vibration-proof surface plate.

Figures 23 to 25 are explanatory diagrams of a method for testing a semiconductor element 117, mainly when it is attached to an SOP 117 or QFN 117, in the semiconductor testing device of the present invention. It goes without saying that this can also be applied to semiconductor chips such as those in Figure 58.

A surface plate 520 is attached to the base 522. The surface plate 520 is a plate to which the positioning support plate 519 is attached. By changing the surface plate 520, the positioning support plate 519 can be easily changed.

The positioning support plate 519 needs to be changed to correspond to the shape of the sample placement plate 511 and the position of the positioning hole 509. Also, the size and position of the sample hole 512 of the sample placement plate 511 are changed to correspond to the shapes of the SOP117 and QFN117.

As shown in FIG. 23, the positioning posts 518 of the positioning post plate 519 are inserted into the positioning holes 509 of the sample placement plate 511, and the sample placement plate 511 is fixed.

The thickness of the sample placement plate 511 is configured to be thinner than the thickness of the SOP117 and QFN117. The SOP117 and QFN117 are placed with the electrode terminals 226 of the sample holes 512 facing upward.

The positioning support plate 519 is made of a base material made of a metal material with good thermal conductivity. Examples include copper, stainless steel, and aluminum. The surface of the positioning support plate 519 is plated with nickel (Ni) or silver (Ag).

Anisotropic conductive rubber 504 (not shown) is disposed on the electrode terminals 226 of the SOP 117 and the QFN 117. The anisotropic conductive rubber 504 is rectangular, and its area is equal to or slightly larger than the area including the arrangement areas of the electrode terminals 226 and the signal terminals 227.
The sample placement plate 511 is countersunk, and configured so that the anisotropic conductive rubber 504 fits exactly into the countersunk portion.

As shown in FIG. 24, a connection board 514 is placed on anisotropic conductive rubber 504. The electrode patterns 505 of the connection board 514 are arranged to correspond to the electrode terminals 226 of the SOP117 and QFN117, and the electrode patterns 506 of the connection board 514 are arranged to correspond to the signal terminals 227 of the SOP117 and QFN117.

The support 534 is attached to the base 522. An arm stand 533 is attached to the support 534. An arm 532 is attached to the arm stand 533. The arm 532 is configured to be rotatable around a central axis. The length of the arm 532 is set and configured so that the pressing head 530 is positioned above the anisotropic conductive rubber 504, as shown in FIG. 21.

It goes without saying that the matters described above can also be applied to the devices of the present invention shown in Figures 68 and 72. It also goes without saying that the configurations, members, structures, and operations shown in Figures 25, 68, and 72 can be applied in whole or in part in combination with each other.

A pressing post 531 is attached to the pressing head 530, and an arm 532 and pressing post 531 are attached to the pressing head 530. By sliding the pressing post 531, the position of the pressing head 530 moves up and down. The pressing force of the anisotropic conductive rubber 504 is adjusted or set by moving the position of the pressing head 530 up and down.

A rubber 517 is attached to the pressing head 530. The rubber 517 may be made of any elastic material. By using an elastic material, the anisotropic conductive rubber 504 can be pressed uniformly over its entirety.

Examples of elastic materials or elastic objects include sponge, seaweed, soft plastic, air packs, liquid packs, gel packs, rubber metal, metal or resin springs, and leaf springs.

As an example, a pressure motor is used for pressing. Pressure motors are fluid machines that convert liquid pressure into mechanical motion, and include prime movers and actuators that convert rotational motion. Pressure cylinders are used to convert fluid pressure into linear motion.

Pumps convert rotational energy into pressure energy. Pressure motors convert pressure energy into rotational energy, so their basic structure is similar to that of pumps. Unlike electric motors, they can operate stably even in high-temperature environments. In addition, they can continue to operate even if the power source stops because pressure is stored in an accumulator or the like. A pressure sensor is provided to detect the pressure.

Figure 25 shows pressure being applied to the anisotropic conductive rubber 504 by a pressure head 530 from above the connection board 514. However, the connection board 514 is often made of a glass epoxy material or the like, and is thin and easily deformed when pressed.

14 is disposed on the connection board 514. The pressure plate 515 is made of a material and thickness that has good thermal conductivity, is smooth, and is not easily bent, such as a metal material.
By applying pressure from above the pressure plate 515 using the pressure head 530, pressure can be applied uniformly to the anisotropic conductive rubber 504 at a constant pressure.

Figure 21 is an explanatory diagram showing the state in which pressure is applied to anisotropic conductive rubber 504 using pressure head 530. Figure 21 shows the case in which pressure is applied from above connection board 514 via rubber 517. The pressure is indicated by the arrow.

At least one of the electrode patterns (electrode pattern 505, electrode pattern 506) and the plating film 524 is more convex than the flat portion composed of the heat-resistant resist 523, etc. Therefore, the anisotropic conductive rubber 504 is pressed against the convex portion, and the electrode pattern 505 and the electrode terminal 226, and the electrode pattern 506 and the signal terminal 227 are electrically connected via the anisotropic conductive rubber 504.

The connection board 514 is provided with monitor terminals (not shown) that measure the electrical connection state between the electrode pattern 505 and the electrode terminal 226, and between the electrode pattern 506 and the signal terminal 227. Pressing is performed with the pressing head 530, and the resistance value of the monitor terminal is monitored. When the resistance value falls below a predetermined value, the connection is completed and the pressing head 530 is maintained under pressure.

In FIG. 22, pressing is performed by a pressing head 530 supported by a one-way arm 532 attached to an arm stand 533. In this case, the pressing head 530 may become tilted.

To address this issue, arm 532 is provided between support posts 534a and 534b, as shown in FIG. 26. In other words, support posts 534a, 534b, and arm 532 form a "gate" shape.

The arm 532 is supported by left and right pillars (pillars 534a and 534b). Therefore, the pressing pillar 531 that moves the pressing head 530 can be stably maintained. The anisotropic conductive rubber 504 can be pressed evenly, so a good electrical connection can be achieved.

Figure 28 is a configuration diagram of a semiconductor testing device of the present invention (for example, a power cycle testing device for testing power transistors). Figure 44 is an equivalent circuit diagram or explanatory diagram of the semiconductor testing device.

The current power supply device 121 outputs a large constant current Id for testing the transistor 117. The current power supply device 121 supplies power (current, voltage) in synchronization with a control signal from the control circuit board 111, and uses the supplied power to drive the load at a set constant current or constant voltage. The current power supply device 121 can set the maximum voltage value to be output. The current power supply device 121 steadily outputs at least one of the current and voltage.

The switch circuit 122a (SWa) turns on (supply) and off (cut) the supply of the constant current output by the current power supply device 121. The switch circuit 122a is set or controlled to be on (output constant current) or off (cut off constant current) based on a signal from the control circuit board 111. Typically, the switch circuit 122a is turned on before the start of testing, and is constantly maintained in the on state during testing of the semiconductor elements.

In FIG. 28, one current power supply device 121 is shown. The number of current power supply devices 121 is not limited to one. For example, the semiconductor testing device of the present invention may have two or more current power supply devices 121. The more current power supply devices 121 are used, the more diverse the current waveforms Id or voltage waveforms that can be generated.

In the embodiment of the present invention, the current power supply device 121 is described, but the current power supply device 121 is not limited to one that outputs a constant current. For example, a current power supply device that can set a maximum voltage is used as the current power supply device 121. An example is one in which the device functions to output a predetermined constant current at a set maximum voltage under certain conditions. Another example is one in which the device is configured to be able to set the output terminal voltage to a predetermined maximum voltage when outputting a constant current. It goes without saying that in the semiconductor testing device of the present invention, the current power supply device 121 is not limited to a device that outputs only a constant current, but may be a power supply device that can output both voltage and current.

28 and other embodiments are described as generating the current Id using the current power supply device 121, but the current Id can also be realized by adjusting the applied voltage depending on the on-resistance state of the transistor 117. Therefore, it goes without saying that the semiconductor testing device of the present invention is not limited to the current power supply device 121 that outputs a current, and may be configured as a power supply device that outputs a voltage.

The current Id can also be realized by controlling the voltage value of the gate voltage of transistor 117. In this specification, a predetermined current is applied to transistor 117 by controlling current power supply device 121. However, this is not limited to this, and it goes without saying that the voltage of gate terminal g of transistor 117 and the voltage of collector terminal c of transistor 117 may also be adjusted or controlled.

In the embodiment of the semiconductor element testing method of the present invention, for ease of explanation, it is assumed that the constant current Id is generated by the current power supply device 121. The constant current Id flowing through the transistor 117 is supplied by operating the current power supply device 121. The current power supply device 121 is controlled to be turned on/off by a signal from the control circuit board 111. The device control circuit board 209 is timing-controlled by the control circuit board 111.

The emitter terminal e of the transistor 117 is grounded (connected to the ground line). The gate terminal g of the transistor 117 is connected to the gate driver circuit 113.

The gate driver circuit 113, the variable resistance circuit 125, the constant current circuit 118, and the operational amplifier (buffer circuit) 116 are arranged or formed within the sample connection circuit 203. The sample connection circuit 203 is arranged separately from the device control circuit board 209 so that it can be arranged in a position close to the transistor 117 to be tested.

It is preferable to provide one sample connection circuit 203 for each transistor 117 to be tested, but this is not limited thereto, and one sample connection circuit 203 including multiple signal circuits may be provided for multiple transistors 117.

The sample connection circuit 203 is connected to the transistor 117 by the connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminal g of the transistor 117 are arranged so that the distance between them is short, less than 30 mm. If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise and the like will be superimposed on the gate terminal g, causing the transistor 117 to malfunction and directly leading to the destruction of the transistor 117.

As shown in FIG. 29, the device control circuit board 209 is placed in room B of the housing 210 of the semiconductor test equipment. The housing 210 is a frame or device body in which the power supply unit 132, drive circuit, and heating/cooling plate 134 of the semiconductor test equipment are incorporated. The sample connection circuit 203 is placed in room C1 of the housing 210 of the semiconductor test equipment in order to be located close to the transistor 117 to be tested. The sample connection circuit 203 is connected to a connector 208 placed on the side of the housing 210. The wiring connected to the connection pin 206 of the connector 208 is connected to the device control circuit board 209 in room B.

The housing 210 need not necessarily be box-shaped, but may also be, for example, a room. The image is of the current power supply device 121 being placed inside the room. Partitions 214, 215, and 217 may be the walls of the room.

As shown in FIG. 29, the semiconductor element 117 (transistor, etc.) to be tested is placed in chamber C1. The transistor 117, etc. is placed and fixed on the heating and cooling plate 134.

The device fixing/connecting device 610 includes a heating/cooling plate 134 and a circulating water pipe 135 that circulates between the heating/cooling plate 134 and a chiller 136. In addition, a transistor 117 is mounted on the heating/cooling plate 134 as a semiconductor element to be tested, and a sample connection circuit 203 (not shown) is configured or arranged therein.

In FIG. 29, for ease of illustration and understanding, the SOP117, QFN117, etc. are shown as being arranged and fixed on the heating and cooling plate 134. In reality, as shown in FIG. 16(b), a surface plate 520 with good thermal conductivity and a positioning support plate 519 are arranged on the heating and cooling plate 134, and the SOP117 and QFN117 are arranged on the support plate 519. The above matters are the same in FIG. 27, FIG. 29, FIG. 30, FIG. 36, FIG. 38, FIG. 39, FIG. 43, etc.

As shown in FIG. 29, the connector 208 is provided on the side of the housing 210, and the connector 208 and the device control circuit board 209 arranged in the B room are connected by a signal wiring 235. The device control circuit board 209 inputs and outputs control signals or output signals of the gate driver circuit 113, the gate signal control circuit 112, the temperature measurement circuit 115, the variable resistance circuit 125, and the operational amplifier circuit 116.

If necessary, as shown in FIG. 36, the transistor 117 and the like are fixed by being sandwiched between the heating and cooling plates 134a and 134b. As described above, in the present invention, the housing 210 is divided into a plurality of regions, including the C1 chamber. The C1 chamber is configured to be injected with dry air (dry gas, gas with a low dew point temperature). Air pressure is applied to the C1 chamber, and the air injected into the C1 chamber is discharged through the opening 216 and the like.

The connection structure 218 is inserted from the C2 chamber through the opening 216 of the partition wall 217. By inserting the connection structure 218, an electrical connection is established between the connection portion 507 of the transistor 117 and the connection structure 218, and a constant current (test current) Id can be applied to the transistor 117.
The connection structure 218 is made of copper or a copper alloy and has a silver or nickel plated surface.

The partition wall 217 has a function of electrostatic shielding and holding the connection structure 218. It goes without saying that the partition wall 217 can be omitted when a separate electrostatic shielding functional component, a fixing or holding stand for the connection structure 218 is disposed or configured.
Furthermore, it goes without saying that when the partition wall 217 is not provided, the connection portion 507 of the transistor 117 may be positioned and fixed to the connection structure 218 .

The partitions (partitions 214, 215, 217) have the function of separating each chamber (chamber C1, chamber C2, chamber A, chamber B) and the function of preventing outside air from flowing in. In particular, since condensation may occur in chamber C1 during testing at low temperatures, dry air with a dew point of -20°C or less is flowed into chamber C1. The dry air that flows into chamber C1 is exhausted to the other chambers through opening 216. However, if the opening of opening 216 is large, a large amount of dry air will be required. Therefore, it is preferable that opening 216 is sized so that the fork plug 205 and connection structure 218 serving as the connecting member can be inserted.

As shown in FIG. 30, a fixing screw 221 is attached to the other end of the connection structure 218, and the connection wiring 211 is connected to the connection structure 218. A fork plug 205 shown in FIG. 31 etc. is attached to the other end of the connection wiring 211 as a connection member.

30, 38, and 43 show a pressing member 608 that fixes the connection structure 218. The pressing member 608 fixes the connection structure 218, and the terminal connection portion 609 consisting of the connection fittings 232 and 233 is stably engaged with the connection portion 507 of the device 117 to be tested. When separating the device 117 and the connection structure 218, the pressing member 608 is first removed.

The fixing screw 221 of the connection structure 218 is not limited to a screw, and may be anything that can electrically connect the connection wiring 211 to the connection structure 218. It goes without saying that the fixing screw 221 may be one that can make contact by pressing with a spring (not shown).

The sample connection circuit 203 is connected to a device control circuit board 209 by a connection pin 206 of a connector 208. The sample connection circuits 203 are individually arranged corresponding to each transistor 117 to be tested, and the sample connection circuits 203 are configured so as to be easily removable.
The connectors 208 and 213 are not limited to connectors, and may be any connector that can electrically connect and disconnect wiring.

Figure 35 is an explanatory diagram of the connection structure 218 in the semiconductor testing device of the present invention. A heat pipe 223 is in close contact with the recess 234 on the surface of the connection structure 218. Thermally conductive grease or a silicone oil compound for heat dissipation may be applied between the surface of the connection structure 218 and the heat pipe.

The recess 234 is formed in the heat pipe fitting 231. The heat pipe 223 is arranged so as to fit into the recess 234. By arranging the heat pipe 223 in the recess, the risk of damage to the heat pipe 223 is reduced.

The heat pipe fitting 231 is made of a metal that has good electrical and thermal conductivity. Examples of metals include copper and silver. Other non-metallic materials such as carbon can also be used.

It is preferable to use thermally conductive grease containing boron nitride (boron). It is preferable to use heat dissipating silicone oil compound that uses silicone oil as a base oil and is mixed with powder with good thermal conductivity such as alumina.
The heat pipe 223 is a sealed container in which a small amount of liquid (working liquid) is vacuum sealed, and which has a capillary structure (wick) on the inner wall.

When part of the heat pipe is heated, the working fluid evaporates in the heated area (absorbing the latent heat of evaporation), and the vapor moves to the low-temperature area at high speed (the speed of sound). The vapor condenses in the low-temperature area (releasing the latent heat of evaporation), and the condensed working fluid flows back to the heated area due to the capillary action of the wick. The above phase changes are repeated continuously without any external force, and heat is transferred instantly, allowing the heat generated at the terminals of the semiconductor element to be transferred quickly and efficiently.

The heat pipe 223 is composed of an array of multiple containers (copper pipes). The inside of the container is in a highly decompressed state, and contains a wick (capillary structure) and an appropriate amount of working fluid (pure water, etc.).
As the working fluid, in addition to pure water, methanol (methyl alcohol), acetone, sodium, mercury, a fluorocarbon-based refrigerant, or ammonia may be used.
Wick materials include aluminum, copper, stainless steel, sintered alloy, wire mesh, foamed metal, ceramics, and the like.

The connection structure 218 is not limited to metal. It goes without saying that it may be made of a nonmetallic material such as ceramic, graphite, or a composite material of graphite and copper or aluminum. In the case where a current is directly passed through the connection structure 218, the connection structure 218 is made of a metallic material such as copper. The surface of the connection structure 218 is preferably plated with silver, nickel, or the like.
Fig. 35 is an explanatory diagram of the configuration of the connection structure 218. Fig. 35(a) is a diagram that typically illustrates the back surface, and Fig. 35(b) is a diagram that typically illustrates the side surface.

The connection structure 218 mainly consists of a heat pipe fitting 231, a connection fitting 232, and a connection fitting 233. The connection fitting 232 and the connection fitting 233 etc. form the terminal connection part 609. The connection part 507 of the semiconductor element is inserted into the terminal connection part 609.

Contact parts 225a and 225b are disposed between the connecting fitting 232 and the connecting fitting 233. Platinum, gold, silver, tungsten, copper, nickel, or an alloy of a combination of these is used as the contact part 225. It is also preferable to use a silver-oxide contact material (Ag+ZnO, Ag+SnO ₂ , Ag+SnO ₂ In ₂ O ₃ , Ag+, Ag+SnO ₂ Sn ₂ Bi ₂ O ₇ ).

The connection fitting 233 is fixed to the heat pipe fitting 231 with a fixing screw 224a. The connection fitting 232 is fixed to the connection fitting 233 with a fixing screw 224b. The connection part 507 of the semiconductor element is fixed by tightening the fixing screw 224b. The connection wiring 211 is fixed to the left end of the heat pipe fitting 231 with a fixing screw 221.

Figure 36 is an explanatory diagram of the state in which the connection part 507 is connected to the connection structure 218. The connection part 507 is sandwiched between the contact part 225a and the contact part 225b. The connection fitting 232 is fixed to the connection part 507 by the fixing screw 224b.

The transistor 117 is fixed to the heating and cooling plate 134a and is further sandwiched between the heating and cooling plate 134b. The transistor 117 is appropriately maintained at the test temperature by the heating and cooling plate 134. A heat pipe 223 is attached in the recess 234.

A test constant current Id is applied from the connection structure 218 to the connection portion 507. The constant current Id is large, at several hundred amperes (A). The connection portion 507 usually has a relatively small area, and there is contact resistance between the contact portion 225 and the connection portion 507. Therefore, when a large current flows through the connection portion 507, heat is generated at the contact portion 225.

The heat is conducted to the transistor 117 being tested, overheating the transistor 117. Overheating may cause the transistor 117 to deteriorate or the connection part 507 to burn. Heat is also generated in the electrode terminals 226 of the SOP117 and QFN117, and the generated heat is conducted through the connection board 514. The conducted heat raises the temperature of the connection part 507. Therefore, it is necessary to quickly dissipate the heat generated at the contact part 225.

The connection structure 218 of the present invention has a heat pipe 223. The heat generated at the contact portion 225 is transferred by the heat pipe 223. Therefore, the heat of the contact portion 225 is quickly removed from the contact portion 225. In addition, the heat of the connection portion 507 and the heat of the connection board 514 are removed.

A partition wall 217 is disposed between the C1 and C2 chambers. As shown in FIG. 37, an opening 216 is formed in the partition wall 217. A connection structure 218a1 is inserted into the opening 216a1, and a connection structure 218b1 is inserted into the opening 216b1. A connection structure 218a2 is inserted into the opening 216a2, and a connection structure 218b2 is inserted into the opening 216b2. A connection structure 218an is inserted into the opening 216an, and a connection structure 218bn is inserted into the opening 216bn.

For example, in the semiconductor testing device of FIG. 37, the P terminal of the transistor 117Q1 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218a1. Also, the N terminal of the transistor 117Q1 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218b1.

Similarly, the P terminal of the transistor 117Q2 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218a2. Also, the N terminal of the transistor 117Q2 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218b2.

Similarly, the P terminal of the transistor 117Qn to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218an. Also, the N terminal of the transistor 117Qn to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218bn.

An electrostatic shield plate or electrostatic shield net is placed on the partition 217, blocking noise from the power supply 132 and the drive circuit system of chamber B, and the noise is not applied to chamber C1. In addition, noise generated by turning on and off the transistor 117 is not applied to the drive circuit system of chamber B.

Figure 38 is an explanatory diagram explaining the connection state between the transistor 117 and the connection structure 218. The transistor 117 is fixed to the heating and cooling plate 134a. In reality, a surface plate 520, a positioning support plate 519, etc. are arranged or formed on the heating and cooling plate 134a, but they are omitted for ease of understanding and drawing.

Fixation is achieved by a spring (not shown). Thermally conductive grease or a silicone oil compound for heat dissipation may be applied to achieve adhesion. If necessary, as shown in FIG. 36, a heating/cooling plate 134b may also be placed above the transistor 117 so that the transistor 117 can be set to a predetermined temperature condition. Note that this is not limited to a spring, and any structure or mechanism that allows for fixing may be used.

A connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is drawn out to the connector 202. A control signal Vgs to be applied to the gate terminal g of the transistor 117 and a constant current Ic from the constant current circuit 118 are applied to the signal wiring 222.

The connection structure 218a is inserted into the opening 216a of the partition 217 from the C2 chamber side. Similarly, the connection structure 218b is inserted into the opening 216b of the partition 217 from the C2 chamber side. When the connection structure 218 is inserted, the connection portion 507 is sandwiched between the connection fitting 232 and the connection fitting 233. In this state, the connection portion 507 of the transistor 117 and the connection structure 218 are electrically connected by tightening the fixing screw 224b.

The transistor 117 to be tested must be fixed in place by being in close contact with the heating and cooling plate 134 or the like. In addition, the anisotropic conductive rubber 504 positions the electrode pattern 505 and the electrode terminal 226 for electrical connection, making it difficult to remove.

The transistors 117 are attached by first fixing the multiple transistors 117 to be tested to the heating and cooling plate 134 or the like. Next, the transistor 117 to be tested first is selected and the connection structure 218 is attached to the connection portion 507.

The selected transistor 117 is electrically connected to the connection portion 507 by inserting the connection structure 218 from the C2 chamber side into the opening 216 in which the selected transistor 117 is located.

Electrical connection with the transistor 117 is easy since it is only necessary to select the position where the connection structure 218 is inserted. In addition, the test conditions and test contents of the transistor 117 can be easily changed by changing the signal applied to the connection wiring 211 connected to the connection structure 218.

As shown in FIG. 36, the connection portion 507 is clamped by applying pressure between the contact portions 225a and 225b. A connection wiring 211 is connected to one end of the connection structure 218, and a constant current Id is applied to the transistor 117 from the connection wiring 211. A heat pipe 223 is disposed on the back side of the connection structure 218.

A current of several hundred amperes (A) flows through connection 507. Even if there is a slight resistance in contact 225, a current of several hundred amperes (A) generates a large amount of heat, overheating connection 507. If this occurs, transistor 117 will also overheat, causing it to deteriorate or break down.

In the present invention, heat generated at the contact portion 225 is transferred to the connection wiring 211 side of the connection structure 218 by the heat pipe 223. Therefore, the contact portion 225 does not overheat. A cooling fan 229 is disposed below the connection structure 218 to dissipate heat from the heat pipe 223.
FIG. 38 is an explanatory diagram for explaining a method for cooling the connection structure 218 in the semiconductor testing device of the present invention.

38, a cooling fan 229 for removing heat from the heat pipe 223 is disposed on the back surface of the connection structure 218. The rotation speed of the cooling fan 229 is controlled according to the overheating state of the connection portion 507 and the heat pipe 223.
FIG. 39 is an explanatory diagram for explaining a method of connecting a semiconductor element 117 and a connection structure 218 in the semiconductor testing device of the present invention.

A partition 217 is provided between the C1 and C2 chambers. As shown in FIG. 37, an opening 216 is formed in the partition 217 corresponding to the position of the transistor 117 to be tested. The connection structure 218 is positioned and fixed horizontally or stably by the opening 216 of the partition 217 and a fixing base (not shown) for the connection structure 218.

As shown in FIG. 39(a), the transistor 117 to be tested is positioned and fixed in place by being in close contact with the heating and cooling plate 134a. Thermally conductive grease and silicone oil compound for heat dissipation are applied between the transistor 117 and the heating and cooling plate 134a.

A detachable connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is connected to the connector 202, and the signal wiring 222 is connected to the sample connection circuit 203.

The signal wiring 222 between the sample connection circuit 203 and the connector 202 is formed to be as short as possible. If the signal wiring 222 is long, noise will be superimposed on the signal wiring 222, causing the transistor 117 to malfunction. For example, if noise is superimposed on the gate terminal g of the transistor 117, the transistor 117 will turn on, which may destroy the transistor 117. The signal wiring 222 should be twisted, or a shielded wiring such as a coaxial cable should be used.

As shown in FIG. 39(b), the connection structure 218a is inserted into the opening 216a. By inserting the connection structure 218a into the opening 216a, the connection portion 507a of the transistor 117 is sandwiched between the connection fitting 232 and the connection fitting 233 at the tip of the connection structure 218a. After the connection structure 218a and the connection portion 507a are connected, the fixing screw 224b1 is tightened to achieve good electrical connection between the contact portion 225 and the connection portion 507.

Similarly, the connection structure 218b is inserted into the opening 216b. By inserting the connection structure 218b into the opening 216b, the connection portion 507b of the transistor 117 is sandwiched between the connection fitting 232 and the connection fitting 233 at the tip of the connection structure 218b. After the connection structure 218b and the connection portion 507b are connected, the fixing screw 224b2 is tightened to achieve a good electrical connection between the contact portion 225 and the connection portion 507.

In the embodiment shown in FIG. 38, the heat pipe 223 is attached to the recess 234 of the heat pipe fitting 231 of the connection structure 218. However, the present invention is not limited to this.

For example, the connection structure 218 may be configured as shown in FIG. 40. In FIG. 40, FIG. 40(a) is a schematic illustration of the back surface (lower surface) of the connection structure 218, and FIG. 40(a) is a schematic illustration of the front surface (upper surface) of the connection structure 218.

In FIG. 40, a heat pipe 223a is disposed on the concave surface 234a. The heat pipe 223a is formed or disposed up to the connecting fitting 233. By forming or disposing the heat pipe 223a up to the connecting fitting 233, the heat generated by the connecting portion 507 can be transferred more efficiently.

As shown in FIG. 40(b), the heat pipe 223b is disposed on the concave surface 234b. By disposing the heat pipe 223 on both sides of the connection structure 218, the heat generated by the connection portion 507 can be transferred more efficiently.

In the embodiment of FIG. 38, the heat pipe 223 and the like are cooled by a cooling fan 229, but the present invention is not limited to this. For example, as shown in FIG. 41, heat dissipation fins 228 may be formed or positioned so as to be in close contact with the heat pipe 223. Heat transferred within the heat pipe 223 is efficiently transferred to the heat dissipation fins 228, further improving the heat transfer and heat dissipation effect of the heat pipe 223.

The heat dissipation fins 228 in FIG. 41 are not formed or placed in the area corresponding to the opening 216. The connection structure 218 is inserted from the C2 chamber to the C1 chamber side through the opening 216. In order to maintain the airtightness of the C1 chamber, the opening 216 has a size equal to the cross-sectional area of the connection structure 218 + α. Therefore, if the heat dissipation fins 228 are formed or placed on the connection structure 218, they cannot be inserted into the opening 216. Therefore, the heat dissipation fins 228 are not formed or placed on the side connected to the connection portion 507 of the transistor 117 based on the partition wall 217.

As shown in FIG. 42, a circulating water pipe 135 may be formed or disposed within the connection structure 218 to cool the connection structure 218. The connection structure 218 is cooled by the refrigerant flowing through the circulating water pipe, and the heat transfer within the heat pipe 223 is efficiently transferred to the connection structure 218. Therefore, the heat generated in the connection portion 507 is efficiently dissipated.

In the transistor 117 (SOP117, QFN117, semiconductor element 117) in FIG. 1, as shown in FIG. 3, the electrode terminal 226a is connected to the connection portion 507a, and the electrode terminal 226b is connected to the connection portion 507b. Therefore, the connection portion 507 has two terminals, the connection portion 507a (P) and the connection portion 507b (N).

As shown in Fig. 6, the connection portion 507 of the transistor 117 may have three terminals, that is, a connection portion 507a (P), a connection portion 507b (N), and a connection portion 507c. As shown in Fig. 6, the electrode terminal 226a is connected to the connection portion 507a, the electrode terminal 226b is connected to the connection portion 507b, and the electrode terminal 226c is connected to the connection portion 507c.
The semiconductor testing apparatus and semiconductor device testing method of the present invention are capable of testing a wide variety of semiconductor devices 117.

The semiconductor element 117 in FIG. 6 is a semiconductor element in which two transistors, transistor 117m and transistor 117s, are arranged in a single SOP or QFN package, as shown in FIG. 4.

The collector terminal cs of transistor 117s is connected to connection part 507a. The emitter terminal es of transistor 117s and the collector terminal cm of transistor 117m are connected, with the midpoint connected to connection part 507c. The emitter terminal em of transistor 117m is connected to connection part 507b.

Transistor 117m is connected to emitter terminal em, gate terminal gm, and collector terminal cm. Transistor 117s is connected to emitter terminal es, gate terminal gs, and collector terminal cs.

Figure 43 is an explanatory diagram illustrating the connection state between a transistor 117 (semiconductor element 117) having three connection parts 507 (connection part 507a (P), connection part 507b (N), connection part 507c (O)) and a connection structure 218.

In FIG. 43, a placement recess 239 is formed or configured in a connection board 514, and an anisotropic conductive rubber 504a is placed in the placement recess 239. The anisotropic conductive rubber 504a electrically connects the signal terminal 227 and the electrode pattern 506. A pressure plate 515 is placed on the connection board 514, and the pressure plate 515 is pressed by a pressure head 530 via rubber (elastic material) 517.

In FIG. 43, the connection between connection structure 218a and connection portion 507a, and the connection between connection structure 218b and connection portion 507b are the same as those described in FIG. 38 and FIG. 39, so the description is omitted.

In FIG. 43, a heat pipe 223a is formed or arranged in the connection structure 218a, and a heat pipe 223b is formed or arranged in the connection structure 218b, whereas a heat pipe 223 is not formed or arranged in the connection structure 218c. The connection structure 218c is connected to the connection portion 507c.

A large current does not flow through the connection portion 507c (O) of the transistor 117. Therefore, the connection portion 507c does not overheat. There is no need to form a heat pipe 223 in the connection structure 218c. By forming the connection structure 218c thinner than the other connection structures 218 (connection structure 218a, connection structure 218b), it becomes easier to connect the connection structure 218 and the connection portion 507 of the transistor 117. In addition, since the space required to place the transistor 117 can be narrow, the number of transistors 117 that can be mounted on the heating/cooling plate 134 can be increased.

It goes without saying that a heat pipe 223 may be formed or disposed in the connection structure 218c. Other details are the same as or similar to the embodiments in Figures 38 and 39, so a description thereof will be omitted.

Figure 58 is a schematic diagram of a thermal cycle test (thermal shock test) in an embodiment of the semiconductor element test device of the present invention. In Figure 58, wiring electrodes 607a, 607b, and 607c are formed on an insulating substrate 602. A semiconductor chip 601 is connected to wiring electrode 607a with solder 605.

The bonding terminal (not shown) of the semiconductor chip 601 and the wiring electrode 607b are electrically connected by an aluminum wire 606. A wiring electrode 607c is formed or placed on the back surface of the insulating substrate 602 and is connected to the copper base 604 by solder 605.

The thermal cycle test (thermal shock test) shown in Figure 58 is a test that predicts the lifespan of a product or system against relatively mild temperature changes that occur when the product or system is started or stopped.

In power modules 117 (power semiconductor elements, power semiconductor chips, modules in which semiconductor elements are mounted), the case temperature (Tc) changes relatively slowly and significantly when the module is started and stopped. When this stress is repeated, cracks in the die bond (bonding material such as solder) reach the bottom of the power semiconductor chip, which increases the thermal resistance and leads to thermal runaway, destroying the power module.

The semiconductor element testing device of the present invention heats the power module 117 from outside, heats the power module itself by heat generation, or cools it from the outside. Heating or cooling is also performed using cooling water or hot water from a chiller.

In the semiconductor element testing device and semiconductor element testing method of the present invention, the temperature of the power semiconductor element (transistor, etc.) 117 is periodically changed in response to the test conditions, and is cooled and heated to a constant temperature. In addition, the temperature information Tj of the transistor being tested is measured, and the chiller 136 is controlled to maintain the measured temperature information Tj at a constant value.

The chiller 136 is designed to keep the temperature of equipment, etc. constant by circulating water or heat transfer medium while controlling its temperature. It is primarily used for cooling, but can also heat as well as cool. It is designed to be able to control a variety of temperatures.

The control rack 131 has a power supply unit 132 that supplies a test current and a test voltage to a power semiconductor element 117 (transistor, etc.), and a control circuit that controls the transistor 117 or sets the test conditions.

The control circuit 132 receives transistor temperature information Tj and controls the chiller based on the temperature information Tj. Alternatively, it controls the chiller 136 to set the temperature information Tj to a predetermined value.

Note that although circulating water is described in this specification, it is not limited to water. It may be ethylene glycol, glycerin, freon, etc., or forced air cooling. The chiller 136 controls the liquid in the circulating water pipe 135 to a temperature range of, for example, -1°C to +100°C, and supplies it to the cooling/heating heat sink of the test unit. The cooling/heating heat sink 134 has a sufficiently large thermal capacity.

Heating or cooling the power module 117 causes relatively gradual expansion and contraction. The semiconductor element testing device of the present invention can set the temperature and cycle of cooling or heating. A durability test of the semiconductor module can be performed by adjusting the temperature and cycle.
The number of test cycles can be set arbitrarily between 100 and 100,000 cycles. In addition, the cooling time and heating time can be set arbitrarily.

Figure 59 is a schematic diagram of a power cycle test in the semiconductor element testing device of the present invention. It is possible to perform tests on life and reliability in an operating pattern in which junction temperature changes occur frequently.

In the power cycle test, heat rises and falls depending on the operating conditions of the power semiconductor element 117. The change in case temperature (molding resin of the semiconductor chip, case of the module having the semiconductor chip 601, etc.) is small, and the test is performed on the life span under an operating pattern in which junction temperature changes frequently occur.

The heat generated by the semiconductor chip 601 is transferred to the aluminum wire 606 as shown by arrow A, and the heat generated by the semiconductor chip 601 is transferred in the direction of the insulating substrate 602 as shown by arrow B.

Power cycle testing is an essential test item for power semiconductor devices 117 and power semiconductor modules 117. In the structure of power module 117, when the operation of power semiconductor 117 causes a temperature change in the joint, cracks occur on the joint surface due to stress caused by the difference in linear expansion coefficient between aluminum wire 606 and power semiconductor chip (silicon chip, etc.) 601.

If the cracks grow, they can lead to failure due to peeling. In particular, for power semiconductors 117 used in inverters, etc., this power cycle failure must be taken into consideration from the equipment design stage.

The semiconductor element testing device of the present invention can arbitrarily set the rapid heat generation (expansion) temperature, change time, and retention time associated with the operation of the power semiconductor element 117, as well as the cooling (contraction) temperature, change time, and retention time. Therefore, durability testing against stress due to differences in linear expansion coefficients, etc. can be easily performed.

The number of test cycles can be set arbitrarily between 100 and 100,000. In addition, the cooling time, heating time, holding time, and temperature change time can be set arbitrarily.
The method for testing a semiconductor device according to the present invention will be described below. Figures 44, 45 and 46 are explanatory diagrams of the method for testing a semiconductor device according to the present invention.

The constant current circuit 118 supplies a constant current Ic to the diode Di of the transistor 117. The operational amplifier circuit 116 buffers and outputs the terminal voltage Vi of the diode Di. The terminal voltage Vi is applied to the temperature measurement circuit 115, which determines temperature information Tj of the transistor 117 from the terminal voltage Vi and transfers it to the controller circuit board 11. The temperature information is output from the connector 213 of the device control circuit board 209 to the mother board 207 and sent to the control circuit board 111 (see Figure 28, etc.).

The semiconductor element testing device and semiconductor element testing method of the present invention realize noise control technology. The noise control technology implements an inrush current elimination method and a surge voltage elimination method. Figure 61 is an explanatory diagram of the inrush current elimination method. Figure 62 is an explanatory diagram of the surge voltage elimination method.

New devices such as SiC/GaN have low on-resistance and high-speed switching performance. Due to their characteristics, they react sensitively to switching noise (surges, etc.) even during power cycle testing. Therefore, since there is a risk of device destruction, it is important to control noise in terms of test equipment and test methods.

The noise control method, inrush current removal method, surge voltage removal method, etc. specifically implement the test methods described in Figures 46, 48, 51, and 52, and the implementation circuits use the configurations or operations of Figures 28, 29, 44, 45, 49, 50, and 51.
Due to improvements in the performance of semiconductor elements or in response to demands for higher functionality, the margin for designing circuits using power semiconductor elements is decreasing.

In particular, the low on-resistance and high switching speed of new devices such as IGBT, SiC, and GaN increase switching noise, causing device destruction due to noise (surge, etc.).
In the semiconductor device testing apparatus of the present invention, techniques such as noise control have been established, making it possible to realize a testing state that is not affected by inrush currents and surge voltages.

In the inrush current removal method shown in Figure 61, as shown in Figures 44, 45, 49, 50, 51, etc., a switching circuit board 201 consisting of a MOS transistor or the like as a switching element is placed or connected between the drain terminal and source terminal (between channels) of the power semiconductor element 117 (power transistor) to be tested.

When the switch circuit 124b of the switch circuit board 201a is turned on, the drain terminal and source terminal of the transistor 117 are short-circuited. Due to the short circuit, no voltage or current is applied between the channel of the transistor 117. Furthermore, when the switch circuit 124b is turned on, the output terminal of the current power supply device 121 that supplies the test current to the transistor 117 is short-circuited, discharging the electric charge.

When the switch circuit 124b is turned on, a current flows, discharging the charge of the current power supply device 121. Alternatively, the current output by the current power supply device 121 flows to ground via the switch circuit 124b.

When an inrush current Is flows through the transistor being tested, the transistor is destroyed by the inrush current Is or surge voltage Vs. To prevent the inrush current Is or surge voltage Vs from occurring, the switch circuit is controlled to turn on and off, and the on and off sequence is controlled.

As shown in FIG. 61, in the conventional example, the current (drain current Id) flowing between the channels of the transistor occurs as an inrush current. In the present invention, by controlling the switch circuit 124, etc., no inrush current occurs.

Similarly, a surge voltage can be removed by controlling the switch circuit 124. As shown in Fig. 62, in the conventional example, a surge voltage occurs between the drain terminal and the source terminal of the transistor 117, but in the present invention, the surge voltage can be removed by controlling the switch circuit board 201.
The semiconductor device testing apparatus (power cycle tester) and semiconductor device testing method of the present invention can measure saturated thermal resistance.

The power cycle tester's multiple functions allow it to measure saturation thermal resistance at any set current and/or voltage. It is also possible to measure cycle time, number of cycles, and multiple devices simultaneously.

The thermal resistance of a semiconductor package is the amount of heat generated per 1W of power. With a power cycle tester, the thermal saturation resistance can be measured from the junction temperature (Tj) and ambient temperature (Ta) in a thermally saturated state at a specified power. The test flow is as follows:
1. Input the Ic (Id) current and Vce (Vds) voltage as test conditions.
2. By starting the saturated thermal resistance test, the ambient temperature (temperature before current is applied) and the junction temperature are measured.
3. Calculate the thermal resistance from steps 1 and 2 above. The thermal resistance value in the thermally saturated state is displayed.
Rth＝Tj－Ta／Pd
however,
Rth: Saturation thermal resistance (℃/W)
Tj: Junction temperature (°C)
Ta: Temperature before power is applied (℃)

The power cycle tester allows you to set the gate voltage according to the power control conditions. The gate voltage can be automatically varied to set the Vce voltage for the test conditions. The setting flow is as follows:
1. Applied current: Specify Ic (Id).
2. Specify the test power.
3. When the test starts, the gate voltage is automatically adjusted to the appropriate value for the specified power.
By using this gate voltage, testing can be easily performed at the collector-emitter voltage (Vce) and drain-source voltage (Vds) that match the test conditions.

Figure 63 is a graph showing the measured saturated thermal resistance transitions of eight devices (Dev1 to Dev8). The power cycle tester of the present invention can simultaneously measure the saturated thermal resistance transitions of multiple power devices and visualize them on a display or the like. It is also possible to print them out on a printer.

The semiconductor element testing device and semiconductor element testing method of the present invention can perform a short pulse power cycle test. Figure 64 shows an example of a measured waveform when measuring a power cycle test using a current pulse.

Figure 64 (a) shows the gate voltage waveform applied to the gate terminal g of the semiconductor element 117 to be tested. The gate voltage is generated in the device control circuit board 209 and applied to the semiconductor element 117 from the sample connection circuit 203. The gate on time ta and period tc can be variably set by the device control circuit board 209. Also, while 0 (V) is the off voltage, depending on the type of semiconductor element 117, it may be necessary to lower the off voltage level. In the semiconductor testing device of the present invention, in addition to the first off voltage of 0 (V), the magnitude of the second off voltage Vt and the application time tn2 can be set.

Figure 64 (b) is a graph illustrating the waveform of the current (voltage) applied to the collector terminal c or drain (source) terminal of the semiconductor element 117 to be tested. The current (voltage) to be applied can be realized by controlling the switch circuit 124a of the switch circuit board 201b of Figure 45 etc. Depending on the operation timing of the switch circuit 124a, the length and timing of the te time, td time, and tf time in Figure 62 (b) can be set and controlled.

The semiconductor testing device of the present invention can perform power cycle testing using current pulses as short as 10 ms (milliseconds). Even when a 10 ms pulse current is applied, the surge absorption circuit absorbs the surge current/voltage that occurs when the current is turned on/off, preventing damage to the test device.

In addition, measurement data can be logged during 10 ms pulse testing. For example, accurate Tj measurement is possible for devices equipped with temperature-sensitive diodes even when a 10 ms pulse current is applied. This makes it possible to trace the process that leads to the breakdown of semiconductor elements.

The semiconductor device testing apparatus and semiconductor device testing method of the present invention can implement the test methods according to the guidelines of JEITA, IEC, and AQG324 shown in FIG.
The semiconductor device testing apparatus and the semiconductor device testing method of the present invention are capable of carrying out a pulsed power cycle test.
Conventional semiconductor device testing apparatus and methods for testing semiconductor devices can only perform tests that involve turning transistors on and off.

For example, as shown in FIG. 66(a), a power semiconductor element (transistor, etc.) is turned on to cause a predetermined current to flow. Then, as shown in FIG. 66(b), the temperature of the power semiconductor element gradually rises from t1 when current is applied. At t2, the current Ia becomes constant. At t3, because the power semiconductor element is in the on state, the temperature exceeds the target temperature Ta.

To lower the temperature, it is necessary to change the cooling water temperature, etc. It takes time to change the cooling water temperature, and the specified test state cannot be maintained for the period during which the cooling water temperature exceeds the target temperature.
The present invention allows the transistor to be pulsed not only during the on and off times, but also during the on time of the transistor.

Figure 67 is an explanatory diagram of the semiconductor element testing device and semiconductor element testing method of the present invention. As shown in Figure 67 (a), by changing or controlling the cycle Tc, on time ton, or off time toff of the power semiconductor element, the time and interval at which a predetermined current flows through the power semiconductor element can be precisely controlled.

Figure 67 (a) shows an example in which the on time ton1 and the off time toff1 are set for the same cycle time tc, and then at time t4, the settings are changed to on time ton2 and off time toff2.

As shown in FIG. 67, the semiconductor testing apparatus of the present invention can acquire temperature information Tj in real time, compare it with a target temperature Ta, and perform testing of semiconductor elements.
Although ta, tc, and te are shown as the same time in Figures 64 and 67, it goes without saying that they may be changed with time.

By turning on the power semiconductor element 17 (transistor, etc.), a predetermined current flows. As shown in Fig. 67(b), the temperature of the power semiconductor element 117 gradually increases. If the power semiconductor element 117 is in the off state, the temperature of the power semiconductor element 117 decreases.
When the temperature of the power semiconductor element 117 reaches the target temperature Ta, the power semiconductor element 117 is turned off, and when the temperature of the power semiconductor element 117 exceeds the target temperature Ta, the power semiconductor element 117 is turned off.
The present invention can identify the location of a failure caused by pulse current passing. The semiconductor device testing apparatus of the present invention can also perform a pulse-type continuous current passing test.

Conventional continuous current tests use direct current, so it is not possible to pass a specified current through samples that generate a high amount of heat. The pulse current method of the present invention allows testing at a specified current density by changing the duty ratio.

The gate driver circuit 113 outputs an on-voltage Vg that turns on the gate of the transistor 117 at a set frequency and for a set on-voltage time. As an example, as shown in FIG. 46(a), the on-off cycle of the transistor 117 is tcycle, the on-time is ton, and the off-time is toff.

46(a), the transistor 117 is controlled to be turned on and off. The gate driver circuit 113 is controlled by the gate signal control circuit 112.
The current power supply 121 outputs a constant current Id, which is supplied to the transistor 117 .

The Vgs signal voltage output from the gate driver circuit 113 turns transistor 117 on and off, and a current Id flows between the channels of transistor 117 while transistor 117 is on.

The gate driver circuit 113 has a variable resistance circuit 125 inside. The value of the variable resistance circuit 125 is configured so that it can be set to a predetermined value or in steps between 0 (Ω) and 500 (Ω). The value of the variable resistance circuit 125 may be set by a control signal from the control circuit board 111 while observing the waveform of the gate terminal g.

A resistor R (not shown) may be placed between the gate terminal g and the emitter terminal e or collector terminal c of the transistor 117. By adjusting the value of the resistor R, the slope angle of the rising and falling voltage waveforms of the gate signal can be adjusted.

When the value of the variable resistance circuit 125 is large, the slope of the rising/falling waveform of the gate signal of transistor 117 applied to the gate terminal of transistor 117 becomes gentler.

On the other hand, if the resistance value of the variable resistance circuit 125 is small, the slope of the rising/falling waveform of the gate signal becomes steep. By changing the value of the variable resistance circuit 125 or setting it to a predetermined value, the on-time of the transistor 117 can be adjusted.

The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) for the gate voltage applied to the gate terminal g of the transistor 117. By separately adjusting the rise time Tr and the fall time Td, the on time of the transistor 117 can be adjusted as desired.

The resistance value of the variable resistance circuit 125 is set by the control circuit board 111. The setting is not limited to a constant value. The slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate driver circuit 113 may be changed. The resistance value at the rising edge and the resistance value at the falling edge of the gate signal may be changed. The resistance value may also be variably controlled in real time. By variably controlling the variable resistance circuit 125, the on time of the transistor 117 is stabilized.

When the resistance value at the rising edge of the gate signal is reduced, the waveform of the on-voltage applied to the gate terminal of transistor 117 becomes steeper, and transistor 117 turns on quickly. When the resistance value at the rising edge of the gate signal is increased, the waveform of the on-voltage applied to the gate terminal of transistor 117 becomes gentler, and transistor 117 turns on slowly.

When the resistance value at the falling edge of the gate signal is reduced, the waveform of the on-voltage applied to the gate terminal of transistor 117 becomes steeper, and transistor 117 turns off quickly. When the resistance value at the falling edge of the gate signal is increased, the waveform of the on-voltage applied to the gate terminal of transistor 117 becomes gentler, and transistor 117 turns off slowly.

As described above, it is possible to control, adjust, or set the value of the variable resistance circuit connected to the gate terminal of transistor 117, or the rise time/fall time of gate driver circuit 113. Therefore, as a function of gate driver circuit 113, it is possible to change or modify the inrush current Is and surge voltage Vs generated in transistor 117.

It goes without saying that the operation of transistor 117 can be achieved not only by controlling the on-voltage of the gate terminal of transistor 117, but also by changing or setting the value of the constant current Id or voltage Vm supplied to transistor 117 by current power supply device 121.

The variable resistance circuit 125 of the gate driver circuit 113 is controlled by the control circuit board 111. The cycle time tcycle, on time ton, and off time toff of the gate signal output by the gate driver circuit 113 shown in FIG. 46 are controlled by the gate signal control circuit 112, and the gate signal is applied to the gate terminal of the transistor 117. The gate signal control circuit 112 is also controlled by the control circuit board 111.

44, 45, etc., the resistance value of the variable resistance circuit 125 of the gate driver circuit 113 is variable, but this is not limiting. For example, it goes without saying that the variable resistance circuit 125 may be an external resistor, and the resistor may be connected to the gate terminal of the transistor 117 by a connector (not shown) or the like.
The value of the resistor to be connected is set by observing the waveform of the gate terminal of the transistor 117 and the waveform of the channel current Id.

In Figures 44 and 45, etc., a constant current circuit 118 is connected between the collector terminal c and the emitter terminal e of the transistor 117. The constant current circuit 118 passes a predetermined constant current Ic. The constant current Ic is for monitoring the temperature of the transistor 117.

In this specification, an IGBT is used as an example for explanation, so the terminals of the transistor 117 are the gate terminal g, the collector terminal c, and the emitter terminal e. In the case of a MOS transistor 117, the terminals of the transistor 117 are the gate terminal g, the drain terminal d, and the source terminal s.

A body diode or a channel diode Di is formed in the transistor 117. Note that the diode Di may be a diode of a separate semiconductor chip mounted on the semiconductor chip in which the transistor 117 is formed.

The diode Di may be a parasitic diode formed secondarily when the transistor 117 is formed. The parasitic diode is formed secondarily due to the layer structure of the transistor 117. The diode Di is formed near the channel portion of the transistor 117 due to its structure.

The diode Di may be any element that does not operate when the transistor 117 is operating. For example, it is not limited to a diode, and it goes without saying that a transistor may be used in a diode connection.

In addition, the device is not limited to a semiconductor such as a diode, but may be a device such as a resistor. A constant current Ic is applied to a device such as a resistor to measure the terminal voltage of the resistor. This voltage is measured as voltage Vi.

As described above, the element that acquires the temperature can be not only a semiconductor device, but also a resistor or other device. In other words, any device that can acquire a voltage value by passing a current, or a current value by applying a voltage, can be used.

The resistance value of the diode Di changes due to heat generation by the transistor 117. When a constant current Ic flows through the diode Di, the voltage between the terminals of the diode Di changes in proportion to the change in the resistance value of the diode Di. By monitoring or measuring the voltage between the terminals, the temperature or the change in temperature of the transistor 117 can be known.
In order to monitor the temperature of the transistor 117 from the voltage of the diode Di, it is necessary to obtain the temperature coefficient in advance.

The temperature coefficient is determined by setting the transistor 117 to a predetermined temperature in a thermostatic chamber, passing a constant current Ic through the diode Di, and measuring the terminal voltage of the diode Di. By varying the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage of the diode with respect to temperature can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be obtained from the terminal voltage of the diode Di with respect to temperature.

The temperature coefficient K may differ for each production lot of transistor 117, but generally it shows a constant value for each production lot. Therefore, if the transistor 117 to be tested is sampled from each production lot and the temperature coefficient K is calculated, it can be used for the temperature coefficient K of other transistors 117.

To obtain the temperature coefficient K with high accuracy, the temperature coefficient K of each transistor 117 is measured and tested individually, even for the same lot. Measurement of the temperature coefficient K is not limited to using a thermostatic bath. For example, the temperature coefficient K can be obtained by changing the temperature of the water flowing through the heat sink on which the transistor 117 is mounted.

During testing, a test current Id is applied intermittently to transistor 117. Immediately after the test current Id is turned off, or after a short, predetermined time has elapsed after it is turned off, a constant current Ic for temperature measurement is passed from constant current circuit 118.

To prevent the constant current Ic from heating the transistor 117 or to avoid any influence of the constant current Ic, the constant current Ic is set to a current value that is sufficiently smaller than the constant current Id passed through the channel of the transistor 117. The constant current Id is set to a current that does not generate heat that would affect the temperature measurement.

Specifically, the constant current Ic is set to 1/1000 or less of the current Id passed through the transistor 117 during testing. Preferably, the current Ic passed through the transistor 117 is set to 1/100000 or more and 1/10000 or less of the current Id. The constant current Ic is set to 0.1 mA or more and 100 mA or less.

The channel current Id is changed, the diode Di voltage (the voltage between the collector and emitter terminals of transistor 117) is measured, and the temperature coefficient K is calculated. The calculated temperature coefficient K is stored in the temperature measurement circuit 115.

When measuring temperature, if the diode Di is formed in the same chip as the transistor 117, the saturation voltage Vn may change depending on the gate voltage Vgs. It is preferable that the gate voltage Vgs be zero (0) voltage or a negative voltage (minus voltage).

As shown in FIG. 27, the control circuit board 111 controls the chiller 136 based on the temperature information Tj. The chiller 136 adjusts the temperature of the circulating water (circulating solution) and adjusts the temperature of the heating and cooling plate 134.

In the above embodiment, the temperature coefficient K is calculated in advance, but the semiconductor testing method of the present invention is not limited to this. Temperature information Tj of the transistor 117 is calculated from the temperature coefficient and the diode terminal voltage, etc.
The transistor 117 is disposed in close contact with the heating/cooling plate 134 so that the temperature of the heating/cooling plate 134 is substantially equal to that of the transistor 117 .

The control circuit board 111 controls the chiller 136 to set the temperature of the heating/cooling plate 134 to a predetermined temperature, applies a constant current Ic to the transistor 117, and measures the terminal voltage of the diode Di.

From the measurement results, the temperature coefficient K is calculated. The temperature of the heating/cooling plate 134 is set to multiple temperatures, and the temperature coefficient K at each temperature is calculated, and the accuracy of the temperature coefficient value is improved from the results.

The temperature coefficient K is obtained by heating the transistor 117 to a predetermined temperature using the heating/cooling plate 134, passing a constant current Ic through the diode Di, and measuring the terminal voltage. By varying the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage of the diode Di versus temperature can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be obtained from the terminal voltage of the diode Di versus temperature.

When testing transistor 117, constant current Ic is passed through diode Di when channel current Id is not flowing. In other words, when transistor 117 is not on, constant current Ic is passed and the voltage between the terminals of diode Di is measured.

The operational amplifier circuit (buffer circuit) 116 outputs the terminal voltage Vi (terminal c-terminal e) of the diode Di. The operational amplifier circuit 116 is not limited to being composed of an operational amplifier element. Any circuit having high input impedance and low output impedance may be used.
The temperature measuring circuit 115 obtains temperature information Tj of the transistor 117 being tested from the stored temperature coefficient K and voltage Vi.

The obtained temperature information Tj is sent to the control circuit board 111. When the temperature information Tj reaches or exceeds a predetermined set value, the control circuit board 111 determines that the transistor 117 is in a predetermined stress state or a deteriorated state, and changes the control of the test or stops the test.

The main area where a transistor deteriorates during testing is often the junctions within the transistor 117. The semiconductor itself does not deteriorate, but the junctions (bonding, die bonding, etc.) of the transistor 117 deteriorate, causing the resistance of the junctions to increase. As the resistance increases, the voltage Vce increases, generating heat and raising the temperature of the transistor 117.

When a semiconductor deteriorates, it is often the deterioration of the gate oxide film (insulating film) of transistor 117. When the gate oxide film deteriorates, the oxide film (insulating film) is short-circuited, and the voltage Vce drops. Alternatively, transistor 117 is turned off, no current flows through transistor 117, and the voltage Vce rises to the maximum value of the power supply voltage.

At the start of the test, the temperature information Tj varies between the minimum temperature T1 and the maximum temperature T2. When the transistor 117 is subjected to stress by the test, the Vce voltage of the transistor 117 varies, and the temperature information Tj generally varies in the increasing direction.
Therefore, as shown in FIG. 47(c), the minimum temperature rises above temperature T1, and the maximum temperature approaches temperature information Tm (Tjmax).
In the semiconductor testing method of the present invention, the test is terminated under any of the following conditions:
When the temperature information Tj falls outside a predetermined range.
When the channel voltage Vce falls outside a predetermined voltage range.
- If the thermal resistance is outside the specified range.

In the examples of Figures 44 and 45, the switch circuit Ssa124a and the switch circuit Sab124b use the symbols for the switch circuits. Any element can be used as the switch circuit for the switch circuit Ssa124a and the switch circuit Sab124b as long as the resistance (on resistance) when closed (on) is small. Examples include a transistor, a mechanical relay, a phototransistor, and a photodiode switch.

Figure 45 is an equivalent circuit diagram of a semiconductor testing device in the first embodiment of the present invention. In this embodiment, the switch circuit Ssa and the switch circuit Sab use a power MOSFET 124 as shown in Figure 45. The voltage (Vsd) between the channels of a power MOSFET is small.

Note that the switch circuit may be something other than a power MOSFET. Needless to say, the switch circuit Ssa and the switch circuit Sab may be power transistors or the like, in addition to power MOSFETs. Other examples include electromagnetic relays and electromagnetic switches.

The channel voltage (Vsdb) of the power MOSFET 124b when on is selected to be equal to or lower than the channel voltage (Vsda) of the power MOSFET 124a when on. In other words, the channel voltage (Vsdb) of the power MOSFET 124b when on is set to be smaller than the channel voltage (Vsda) of the power MOSFET 124a when on. This is to completely short-circuit the terminals of the current power supply device 121 when the switch circuit 124b is turned on, allowing the current Im to flow stably.
The above also applies when the switch circuit 124 is a power transistor, etc. In the case of the power transistor 124, the channel voltage is Vce.
When the switch circuit 124a is turned on, the current Id output by the current power supply device 121 can be supplied to the transistor 117 as a test current.

The switch circuit 124 is mounted on the switch circuit board 201. The switch circuit 124 is connected to a conductor plate 204 (metal plate, conductive plate). The conductor plate 204 is, for example, a copper plate with a thickness of 5 mm and a width of 50 mm. Its length is the width of the circuit board plus the width required to connect the fork plug 205.

Figure 31 illustrates the fork plug 205 and the connection (contact) state between the fork plug 205 and the conductor plate 204. Two conductor plates 204 are attached to the switch circuit board 201. The switch circuit board 201 has a full earth layer (not shown), and the full earth layer and the conductor plate 204 are thermally connected. Heat from the conductor plate 204 is dissipated via the full earth layer. The conductor plate 204 and the switch circuit board 201 are secured with screws.

The switch circuit 124 is connected to two conductor plates. As shown in FIG. 45, if the switch circuit 124 is a MOS transistor, the drain terminal and the source terminal are connected to different conductor plates 204. If the switch circuit 124 is a bipolar transistor, the collector terminal and the emitter terminal are connected to different conductor plates 204. When the switch circuit 124 is turned on (conductive), the two conductor plates 204 are electrically connected. An IGBT can also be used as the switch circuit 124.

The fork plug 205 and the conductor plate 204 are electrically connected by mechanically fitting them together. When the U-shaped portion of the fork plug 205 is inserted into the conductor plate 204, the U-shaped portion expands slightly, and the fork plug 205 and the conductor plate 204 are well joined. With a good joint or fit, the electrical resistance of the connection is extremely small, and no heat is generated or voltage drops occur even when a large current flows through the connection.

A connection bolt 219 is attached to the fork plug 205. A connection wiring 211 is connected to the connection bolt 219. A cross section taken along line AA' in Fig. 31(a) is shown in Fig. 31(b). The conductive plate 204 and the fork plug 205 are in contact with each other at contact parts 220a and 220b formed on the fork plug 205. The surface of the contact part 220 is silver plated. The contact part 220 is made of phosphor bronze and nickel alloy.
The connection bolt 219 is not limited to a bolt, and may be anything that can electrically connect the fork plug 205 and a wire.
At least the surface of the conductive plate 204 that comes into contact with the fork plug 205 is plated with silver.

Figure 30 is a diagram showing the configuration of a semiconductor testing device of the present invention. A connection structure 218a is inserted into the opening 216a of the partition 217, and a connection structure 218b is inserted into the opening 216b of the partition 217.

The connection structure 218a is connected to the connection portion 507a of the transistor 117, and the connection structure 218b is connected to the connection portion 507b of the transistor 117. A circulating water pipe 135 is incorporated into the heating/cooling plate 134.

A connector 202 is connected to the terminal of the transistor 117, and a signal wiring 222 connected to the connector 202 is connected to the sample connection circuit 203. The signal wiring 235 of the sample connection circuit 203 is connected to the device control circuit board 209 via the connector 208.

As shown in FIG. 30, the fork plug 205 and the conductive plate 204 are brought into contact by inserting the fork plug 205 through the opening 216 of the bulkhead 214. When they come into contact, the U-shaped portion of the fork plug 205 is expanded by the conductive plate 204, and they come into firm contact.

Figure 29 shows the layout of each component of the semiconductor testing device of the present invention. The housing 210 of the semiconductor testing device is separated into three parts. The lower part of the housing is separated into chamber A and chamber B. The power supply unit 132 is placed in chamber A. Chamber A and chamber B are separated by a partition wall 215.

Each chamber is shielded. The power supply 132, switch circuit board 201, and transistor 117 generate large noise as they repeatedly operate and deactivate. Noise can cause circuit boards and other components to malfunction, so shielding is used to prevent this. The shielding is achieved by placing conductive plates, metal plates, and metal films around each chamber.

In chamber C1, the heating and cooling plate 134, circulating water pipe 135, etc. shown in FIG. 27 are arranged, and the transistor 117 to be tested is placed on the heating and cooling plate 134.

Partitions 214 are formed between chamber C1 and chambers A and B. A water leakage sensor (not shown) is placed around the heating and cooling plate in chamber C1. If circulating water (cooling medium) or the like leaks, the water leakage sensor is activated and is configured to stop the semiconductor testing equipment or sound an alarm.

In addition, a drainage groove is formed around the periphery of the heating and cooling plate, so that if circulating water (cooling medium) leaks from the heating and cooling plate, the circulating water (cooling medium) flows into the drainage groove and is discharged outside the semiconductor testing equipment.
As described above, the partition wall 214 is configured so that even if the circulating water pipe 135 is damaged, the circulating water (cooling medium) and the like will not leak into the lower chambers A and B.

A partition wall 215 is formed between chamber A, in which the power supply unit 132 is located, and chamber B, in which the drive circuit system is located. Electrostatic shielding plates are placed on partition walls 214, 215, and 217 to block noise from the power supply unit 132 and prevent the noise from being applied to the drive circuit system in chamber B.

In the embodiment of the present invention, the fork plug 205 is inserted from the C2 chamber and connected to the conductive plate 204 in the B chamber. It is easy to push the fork plug 205 from the top to the bottom. However, the present invention is not limited to this. For example, the conductive plate 204 may be placed in the C2 chamber, and the fork plug 205 may be inserted from the B chamber to establish an electrical connection.
Furthermore, the connection structure 218 is inserted from the C2 chamber, and the connection portion 507 of the semiconductor element 117 and the connection structure 218 are connected.

As shown in FIG. 29 etc., the connection structure 218 is inserted from chamber C2 to chamber C1 and electrically connected to the connection portion 507 of the transistor 117. Also, the fork plug 205 is inserted from chamber C2 to chamber B and electrically connected to the fork plug 205 and the conductor plate 204. The transistor 117 is fixed to the heating and cooling plate 134, and the switch circuit board 201 is fixed at the mother board 207 position. The connection structure 218 and the fork plug 205 are electrically connected by the connection wiring 211.

The position of the opening 216 can be selected with the connection structure 218 to select the transistor 117 to be tested. By selecting the opening into which the fork plug 205 is inserted, the switch circuit board 201 to be controlled can be easily selected and the test method and test conditions can be changed. Therefore, by using the connection structure 218 and the fork plug 205, the present invention makes it easy to select the transistor 117 and to change the test method, etc., in a short time.

Note that partitions 214, 215, and 217 may be wall-shaped structures, plate-shaped structures, film-shaped objects, mesh-shaped objects, wire mesh-shaped objects, etc. One example is phenolic resin (phenolic resin, phenol-formaldehyde resin, phenolic resin). The partition may be any object that separates the first and second parts of the semiconductor testing device.

As shown in FIG. 28, a connector 213 is attached to the motherboard 207. A control circuit board 111, a device control circuit board 209, and a switch circuit board 201 are attached to the connector of the motherboard 207. The number of switch circuit boards 201 prepared according to the number of transistors 117 to be tested can be easily realized by changing the number of switch circuit boards 201 attached to the motherboard 207.

The gate terminal g, collector terminal c, emitter terminal e, etc. of the semiconductor element 117 are electrically connected by anisotropic conductive rubber 504a. The electrical connection is made by a pressing head 530, etc., as shown in FIG. 22.

Temperature information Tj, voltage Vi, a control signal for the variable resistance circuit 125, a control signal for the constant current circuit 118, etc. are transmitted to the mother board 207. In addition, power supply wiring and ground wiring for each circuit are formed and supplied to each circuit board via a connector 213.
The conductive plate 204 is disposed so as to protrude from the switch circuit board 201. A fork plug 205 is connected to this protruding portion.

The fork plug 205a is connected to the conductor plate 204a of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through the opening 216 of the bulkhead 215. The fork plug 205d is connected to the conductor plate 204c of the switch circuit board 201b. The power supply wiring 212 is connected to the switch circuit board 201b through the opening 216 of the bulkhead 215. The fork plug 205b is connected to the conductor plate 204b of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through the opening 216 of the bulkhead 215.

As shown in FIG. 44 etc., a switch circuit 124a is disposed between conductor plate 204d and conductor plate 204c of switch circuit board 201b, and short-circuits conductor plate 204d and conductor plate 204c. By short-circuiting, the current Id output by current power supply device 121 is supplied to transistor 117 as a test current.

Switch circuit 124b is disposed between conductor plate 204a and conductor plate 204b of switch circuit board 201a, and when switch circuit 124b is turned on, conductor plate 204a and conductor plate 204b are short-circuited. When this is done, current Id output by current power supply device 121 flows to ground as discharge current Im, and the channels of transistor 117 are short-circuited. When the channels are short-circuited, no overvoltage or overcurrent is applied to transistor 117.

Fork plug 205 is connected to conductor plate 204. Fork plug 205c is connected to conductor plate 204b. Fork plug 205b is connected to conductor plate 204a. Fork plug 205e is connected to conductor plate 204d. Fork plug 205d is connected to conductor plate 204c.

Figure 31 is a diagram of the configuration of the fork plug 205. Figure 31(a) shows the state in which the conductor plate 204 attached to the switch circuit board 201 and the fork plug 205 are connected. Figure 31(b) shows the connected state of the conductor plate 204 and the fork plug 205 when viewed from the direction of the arrow in the cross section of line AA' in Figure 31(a).

The fork plug 205 is made of metals such as aluminum, stainless steel, and copper. The surface is nickel-plated and then silver-plated. The fork plug 205 is threaded, and is configured so that the connection wiring 211 can be attached to the fork plug 205 with a connection bolt 219.

The convex contact portion 220 is made of phosphor bronze and copper alloy. The surface of the contact portion 220 is silver plated. The insertion force of the fork plug 205 into the conductor plate 204 is configured to be 40 to 60 N.

Platinum, gold, silver, tungsten, copper, nickel, or alloys of combinations thereof may be used for the contact 220. It is also preferred to use silver-oxide contact materials ( _Ag + _ZnO , Ag+ _SnO2 , Ag+ _SnO2In2O3 , Ag ₊ , _Ag + _{SnO2Sn2Bi2O7 )} .

In Figure 28, two switch circuit boards 201 are shown, but depending on the number of transistors 117 to be tested, two or more switch circuit boards 201 may be required, and the switch circuit boards 201 are connected to the connectors 213 of the mother board 207.

As shown in Fig. 30, the fork plug 205c is inserted through an opening 216 in a partition wall 214 provided between the C2 chamber and the B chamber, and the conductor plate 204b and the fork plug 205c are connected. The transistor 117 to be tested and the heating and cooling plate 134 are arranged in the C1 chamber, and a driving circuit for testing the transistor 117 and the like are arranged in the B chamber. Since the C1 chamber, the C2 chamber, and the B chamber are separated by the partition wall 214, even if the refrigerant liquid leaks from the heating and cooling plate 134, it will not leak into the B chamber. A water leakage sensor (not shown) is arranged around the heating and cooling plate 134. In addition, a groove is formed to discharge the refrigerant liquid to the outside of the testing device if the refrigerant leaks out.
An electrostatic shield plate is disposed on the partition 214 so as to prevent the drive circuit system in the chamber B from malfunctioning due to noise generated from the transistor 117 .

The current flowing through the transistor 117 to be tested is large, at several hundred amperes, so the connection wiring 211 used is also thick. As a result, the connection wiring 211 does not slide smoothly, and is also hard, making it difficult to change the connection of the connection wiring 211.

The semiconductor testing device of the present invention can be connected to the switch circuit board 201 by the fork plug 205 inserted from the C2 chamber. Therefore, changing the connection with the switch circuit board 201 used depending on the test conditions of the transistor 117 does not require changing the wiring of the connection wiring 211, but only requires changing the position of the opening 216 into which the fork plug 205 is inserted. Also, the switch circuit board 201 only requires changing the position of the connector 213 that connects to the mother board 207.

As shown in Figures 28, 29, 30, 31, 33, 34, 38, 44, 45, etc., the connection wiring 211b connected to the transistor 117 is connected to the fork plug 205c. The connection wiring 211a connected to the transistor 117 is connected to the fork plug 205e.

Even if there are multiple transistors 117 to be tested, the application is sufficient even if there is only one switch circuit board 201a. This is because the output current Id of the current power supply device 121 can be made to flow to the ground line as Im.

Switch circuit boards 201b are required for the number of transistors 117 to be tested. For example, if there are 12 transistors 117 to be tested, it is preferable to prepare 12 switch circuit boards 201b. It is also cost-effective to make switch circuit boards 201a and 201b have the same specifications.

A plurality of transistors or the like are mounted on the switch circuit board 201 as the switch circuits 124. The greater the number of switch circuits 124, the smaller the impedance of the short circuit between the two conductive plates 204. The number of switch circuits 124b mounted on the switch circuit board 201a is determined so that the on-resistance of the switch circuit 124b is smaller than the on-resistance of the transistor 117 to be tested.

Figures 33 and 34 show the state in which the fork plug 205 is inserted into the opening 216 of the partition wall 214. Figure 33 is a view from the front side of the partition wall 214, and Figure 34 is a view from the back side of the partition wall 214.

As an example, fork plug 205b and multiple fork plugs 205c (fork plugs 205c1 to 205c5) are connected to conductor plate 204b in FIG. 33. Fork plug 205e1 is connected to conductor plate 204d1, fork plug 205e2 is connected to conductor plate 204d2, fork plug 205e3 is connected to conductor plate 204d3, fork plug 205e4 is connected to conductor plate 204d4, and fork plug 205e5 is connected to conductor plate 204d5.

A transistor 117 to be tested is connected between the fork plug 205c and the fork plug 205e. The same number of switch circuit boards 201b as the number of transistors 117 to be tested are mounted on the mother board 207. The openings 216 are formed to correspond to the positions of the conductor plates 204 of the switch circuit boards 201.

Although not shown in the figure, large noise is generated when the switch circuit 124 of the switch circuit board 201 is turned on and off. As a countermeasure to this, a metal plate is placed between the switch circuit boards 201 and is earthed.

In each drawing, one switch circuit 124 is shown on the switch circuit board 201. However, in reality, multiple switch circuits 124 are arranged between the conductor plates 204. By arranging multiple switch circuits 124 on the switch circuit board 201, it is possible to short-circuit the conductor plates 204 (for example, between conductor plates 204c and conductor plates 204e) with low resistance.

The heat generated by the switch circuit 124 is dissipated to the conductor plate 204. A heat sink is also attached to the switch circuit 124. The ground terminal of the switch circuit 124 is connected to the ground of the switch circuit board 201, and heat is also dissipated through the copper foil of the ground.

As shown in FIG. 29, two conductive plates 204 are attached to the switch circuit board 201, and a switch circuit 124 is arranged to short the two conductive plates 204. Also, FIG. 44 is an equivalent circuit diagram of the semiconductor testing device of the present invention in the first embodiment.

As shown in Figures 29 and 30, conductive plates 204a and 204b are attached to switch circuit board 201a. Conductive plate 204a is connected to fork plug 205a. Fork plug 205a is connected to the output terminal of current power supply 121. Conductive plate 204b is connected to fork plug 205b. Fork plug 205b is connected to the ground terminal of current power supply 121.

When the switch circuit 124b is turned on, the output terminals of the current power supply device 121 are short-circuited, and a short-circuit current Im flows. Therefore, the output current of the current power supply device 121 is not supplied to the transistor 117. When the switch circuit 124b is open, the output current Id of the current power supply device 121 is supplied to the transistor 117.

Conductive plates 204c and 204d are attached to switch circuit board 201b. Conductive plate 204c is connected to fork plug 205d. Fork plug 205d is connected to the output terminal of current power supply 121. Conductive plate 204d is connected to fork plug 205e. Fork plug 205e is connected to the collector terminal of transistor 117 to be tested.

As shown in Figures 29, 30, 33, 34, etc., fork plug 205e is inserted into opening 216 in bulkhead 214 and is coupled to conductor plate 204d. Fork plug 205c is inserted into opening 216 in bulkhead 214 and is coupled to conductor plate 204d.

A switch circuit 124a is arranged on the switch circuit board 201b, and when the switch circuit 124a is turned on, the output current Id from the current power supply device 121 is supplied to the transistor 117 as a test current to be passed through the transistor 117.

The switch circuit board 201b is placed in the B room of the housing 210, and the switch circuit board 201b is electrically connected to the transistor 117 to be tested by a fork plug 205 inserted from the C2 room through the opening 216 in the partition wall 214.

As shown in Figures 29, 30, 33, 34, etc., the fork plug 205 and the conductor plate 204 are connected. In Figure 30, the switch circuit boards 201 are illustrated as being arranged in parallel. In reality, the switch circuit boards 201 are inserted in parallel and arranged in the board rack. A mother board is arranged on the side of the board rack, and control signals to each circuit board are applied from the mother board.

Figure 46 is an explanatory diagram of a method for testing a semiconductor element of the present invention in the first embodiment. In Figure 46, Vgs is a gate signal applied to the gate terminal of the transistor 117 to be tested. Id is a current passed through the transistor 117 during testing. For ease of explanation, it is assumed that a constant current Ia passes when the transistor 117 is on.

In FIG. 46 (c), St1 is a timing signal for passing a current Ic through the diode Di, and when St1 is at the H level, a current flows through the diode Di of the transistor 117. The operational amplifier circuit 116 acquires the terminal voltage of the diode Di, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 tests the transistor 117 (semiconductor element 117) according to the temperature information Tj.

Id is a current flowing through the transistor 117 to be tested, and is a current output from the current power supply device 121. St1 and St2 are times for which a measurement current is passed through a diode for temperature measurement, or times for which the temperature is measured.
In FIG. 46(e), Ssa is the on/off signal of the switch circuit 124a, and in FIG. 46(f), Sab is the on/off signal of the switch circuit 124b.

Figure 46 (g) Vce indicates the voltage at terminal c of transistor 117 (channel voltage of transistor 117), and temperature information Tj indicates the measured temperature change of transistor 117.

As shown in FIG. 46(a), a gate signal Vgs is applied from the gate driver circuit 113 to the gate terminal g of the transistor 117. The gate signal Vgs has a cycle time tcycle and an on-time ton. The cycle time tcycle and the on-time ton can be set to any value by the gate signal control circuit 112. The on-voltage Vg can also be set to any voltage.

Figure 46 (d) St2 is a timing signal for passing a current Ic through diode Dsa and diode Dsb in the embodiment shown in Figure 49. When St2 is at H level, a current flows through diode Dsa or Dsb of transistor 117. This is the case where a constant current Ic is passed through a device (diode) independent of transistor 117 to obtain temperature information Tj.

The operational amplifier circuit 116 acquires the terminal voltage of the diode Dsa or Dsb, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, which tests the transistor 117 based on the temperature information Tj. Note that matters related to St2 will be explained in FIG. 49 etc.

For ease of understanding, the measured temperature information Tj will be described as changing between T1 and T2 as shown in FIG. 46(h). The temperature information Tj increases when a current is passed through the transistor 117, and decreases when the current is stopped. The temperature information Tj also changes with changes in the characteristics of the transistor 117.

Figure 46 (e) Ssa shows the timing of the on/off control signal for the switch circuit Ssa. When Ssa becomes Von, the switch circuit Ssa closes (turns on). When it is 0, the switch circuit Ssa opens (turns off), and the application of current or voltage is cut off.

Figure 46 (f) Ssb shows the timing of the on/off control signal for the switch circuit Ssb. When Ssb becomes Von, the switch circuit Ssb closes (turns on). When it is 0, the switch circuit Ssb opens (turns off).

Figure 46 (g) Vce is the channel voltage (voltage between the emitter terminal and collector terminal) of transistor 117. As transistor 117 is turned on and off, surge voltage and surge current are generated, and the Vce waveform changes in a complex manner over time as the on-resistance of transistor 117 changes. In addition, the Vce waveform of transistor 117 changes as current Ic flows through diode Di.

In this specification and drawings, for ease of explanation or for ease of drawing, it is assumed that when the transistor 117 is on, the voltage is Vn, and when the transistor is off, the voltage is Ve.
The gate signal is applied to the gate terminal of the transistor 117 under test with a period tcycle, an on time ton, and an off time toff.

When transistor 117 is an N-channel transistor, the gate signal Vgs has a ground (earth) voltage of 0 (V) as its off voltage and Vg as its on voltage. When transistor 117 is a P-channel transistor, it changes the potential of the on voltage and the off voltage.

During a period tn2 before the transistor 117 is turned on, the Vt voltage is set to a voltage more negative than the off voltage, and during a period tn1 after the transistor 117 is turned off, the Vt voltage is set to a voltage more negative than the off voltage.
The Vt voltage is a voltage lower than 0 (V) and higher than −4 (V). Therefore, Vt is a voltage equal to or higher than −4 (V) and lower than 0 (V).

When the transistor 117 is SiC, the off voltage is the Vt voltage, and when it is an IGBT, the off voltage is 0 (V). As described above, the semiconductor testing device of the present invention is configured so that the off voltage supplied to the transistor 117 can be changed depending on the type of transistor 117 being tested.

When the Vt voltage is applied, St1 (St2) is set to H level to measure the temperature of transistor 117. A constant current Ic is passed through diode Di while the Vt voltage is being applied. In addition, a constant current Ic is passed while St1 (St2) is set to H level.

By applying the Vt voltage to the gate terminal of transistor 117, the off state of transistor 117 becomes stable, and the measurement of temperature information Tj can be performed stably. In addition, noise is less likely to be introduced when measuring the temperature information Tj, improving the measurement accuracy of the temperature information Tj.

By applying the Vt voltage to the gate terminal of transistor 117, the leakage current of transistor 117 is reduced, improving the measurement accuracy of the Vi voltage and stabilizing the measurement.

The gate signal Vgs is set to the Vt voltage during times tn1 and tn2. As an example, the times tn1 and tn2 are between 0.2 ms and 2 ms. Transistor 117 is turned off at 0 (V).

Therefore, three voltages, Vg, 0 (V), and Vt, are applied to the gate terminal g of transistor 117. During the period when Vt is being applied, a current is passed through the diode Di of the transistor to measure the temperature information Tj.

When a constant current Ic is passed through the diode Di, the switch circuit Ssa is turned off so that no current from the current power supply device 121 is applied to the transistor 117.

By passing a constant current Ic through the diode Di, the terminal voltage of the diode Di is obtained, and the operational amplifier circuit 116 outputs the Vi voltage corresponding to the terminal voltage. The Vi voltage is input to the temperature measurement circuit 115, which obtains temperature information Tj corresponding to the temperature of the transistor 117.

The temperature information Tj is transferred to the control circuit board 111, and the control circuit board 111 controls the test of the transistor 117 (semiconductor element 117) by continuing, stopping, changing the conditions of the test of the transistor 117, etc. based on the temperature information Tj.

Figure 46 (e) Ssa is a timing signal that controls the on/off state of switch circuit 124a. Figure 46 (f) Ssb is a timing signal that controls the on/off state of switch circuit 124b.

The switch circuit 124a turns on after a delay of tm2 from when the Vgs signal of the transistor 117 becomes Vg. The tm2 time can be changed and set by the control circuit board 111.

The switch circuit 124b turns on a time tb2 before the switch circuit 124a turns on. The on state of the switch circuit 124b is maintained until tb1 after the switch circuit 124a turns on. The times tb2 and tb1 can be changed independently.
In particular, the setting of tb1 is important. The time tb1 is appropriately set or changed by observing the waveform of the Vce voltage of the transistor 117.

The switch circuit 124a turns off tm1 before the Vgs signal of the transistor 117 becomes Vt. The tm1 time can be changed and set by the control circuit board 111.

The switch circuit 124b turns on a time ta2 before the switch circuit 124a turns off. The on state of the switch circuit 124b is maintained until ta1 after the switch circuit 124a turns off. The times ta2 and ta1 can be changed and set independently.
In particular, the setting of ta1 is important. The time ta1 is appropriately set or changed by observing or measuring the waveform of the Vce voltage of the transistor 117.

When the switch circuit Ssb is turned on, the output terminal of the current power supply device 121 is shorted to the ground (ground line), and the charge is discharged. As a result of the charge being discharged, the terminal voltage of the current power supply device 121 becomes 0 (V) (ground voltage). In addition, the current Id output by the current power supply device 121 flows to the ground (ground) as a current Im. Therefore, the current Ia is not applied to the transistor 117, and the collector voltage of the transistor 117 does not rise.

The time tb2 is set by observing or measuring the time when the output voltage of the current power supply device 121 becomes 0 (V) or close to 0 (V), or the time when the output voltage of the current power supply device 121 becomes lower than the collector voltage of the transistor 117.

At the time when the above voltage relationship reaches a predetermined value (after tb2 has elapsed), the switch circuit 124a is turned on to apply the current Id from the current power supply 121. However, since the switch circuit 124b is on at this time, the current Id from the current power supply 121 flows to the ground (ground line) as the current Im via the switch circuit 124b. Therefore, the constant current Id does not flow through the transistor 117.
After the switch circuit 124 a is turned on and a time tb 1 has elapsed, the switch circuit 124 b is turned off and the test current Id is supplied to the transistor 117 .
The test current Id is supplied to the transistor 117 in synchronization with the switch circuit 124a as shown in FIG.

By operating the switch circuits 124a and 124b as described above, the surge voltage Vs or inrush current Is is not applied to the transistor 117. Alternatively, the surge voltage Vs or inrush current Is is suppressed, allowing a good test of the transistor 117 to be performed.

When the test current Id to the transistor 117 is stopped, the switch circuit 124b is turned on before the switch circuit 124a is turned off (ta2). The constant current Id output by the current power supply device 121 flows to ground as the current Im via the switch circuit Ssb and is not supplied to the transistor 117.

The time ta2 is set by observing the time when the output voltage of the current power supply device 121 becomes 0 (V) or close to 0 (V), or the time when the output voltage of the current power supply device 121 becomes lower than the collector voltage of the transistor 117.

When the above voltage relationship reaches a predetermined value (after ta2 has elapsed), switch circuit 124a is turned off. After ta1 time has elapsed since switch circuit 124a was turned off, switch circuit 124b is turned off.

By operating or controlling the switch circuits 124a and 124b as described above, the surge voltage Vs or inrush current Is is not applied to the transistor 117. Alternatively, the surge voltage Vs or inrush current Is is suppressed, and a good test of the transistor 117 can be performed.

The temperature information Tj increases when the constant current Id is supplied to the transistor 117. The temperature information Tj decreases when the constant current Id to the transistor 117 is stopped. The temperature information Tj fluctuates between T1 and T2. When the characteristics of the transistor 117 fluctuate due to the test, the temperature information Tj gradually increases.
In order to apply a constant current Id to the transistor 117 , the current power supply device 121 is operated to apply the current Id to the transistor 117 .

As shown in Figures 44, 45, 47, 49, 50, etc., the resistance value of the variable resistor circuit 125 of the gate driver circuit 113 can also be set. By increasing the resistance value, the rising/falling waveform of the gate signal Vgs can be changed as shown by the dotted line or dashed line in Figure 47(a).

By changing or setting the gate signal Vgs, the current Id flowing through the transistor 117 can also be changed as shown by the dotted line or the dashed dotted line in FIG.
By changing the rising and falling waveforms of the current Id, it is possible to adjust or suppress the surge voltage or inrush current.

As shown in FIG. 47(c), the temperature information Tj changes from a solid line to a dotted line and from a dotted line to a dashed line as the characteristics of the transistor 117 change due to the test. The test is stopped when the temperature information Tj reaches the level of Tm. Alternatively, the test is stopped when the rate of change of the temperature information Tj reaches a predetermined value. The test conditions are also changed.

As shown in FIG. 48, when the switch circuit Ssa (switch circuit 124a) is in the off state, the St1 signal is set to H and the temperature information Tj is measured. The St1 signal is set to H level when the gate signal is Vt. During the tn2 period, the signal is set to H level during the tc2 period and the temperature information Tj is measured. During the tn1 period, the temperature information Tj is measured during the tc1 period.

The temperature information Tj measured during the period tc2 is the temperature information Tj at the time when the transistor 117 is cooled down. The temperature information Tj measured during the period tc1 is the temperature information Tj immediately after the current Id to the transistor 117 is stopped.
Stopping the test, changing the conditions, changing the control, etc. are determined based on the temperature information Tj measured during the period tc2 and the temperature information Tj measured during the period tc1.

If the rate of change of the temperature information Tj measured during the tc1 period is greater than that of the temperature information Tj measured during the tc2 period, or if the difference in absolute value between the temperature information Tj measured during the tc1 period and the temperature information Tj measured during the tc2 period is large, the test is controlled and modified in response to the measurement value temperature information Tj.

Furthermore, if the temperature information Tj measured during the period tc2 differs from the standard value by a predetermined value, it is determined whether there is a problem with the connection state of the transistor 117 or the test equipment, and a decision is made to "not start the test", etc.
During the period tc2 or tc1, Vi is measured multiple times to obtain temperature information Tj for Vi.

The embodiment in FIG. 49 is a semiconductor testing device according to the second embodiment of the present invention. The transistor 117 in FIG. 49 is provided with a separate diode Ds (diode Dsa, diode Dsb) for temperature measurement. The diode Ds is formed in the same process as the transistor 117.

In the embodiment of FIG. 49, temperature information Tj is measured at the timing of the St2 signal in FIG. 46(d). When the switch circuit Ssa (switch circuit 124a) is in the off state, the St2 signal is set to H and temperature information Tj is measured. During the tn2 period, the signal is set to H level during the tc2 period and temperature information Tj is measured. During the tc1 period, temperature information Tj may be measured during either the ton period or the tn1 period. The temperature information Tj measured during the tc2 period and the temperature information Tj measured during the tc1 period are averaged to obtain the temperature information Tj.

During the period tc2 or tc1, Vi is measured multiple times to obtain temperature information Tj for Vi. The operations of other signals or switch circuits in Fig. 46 are the same as or similar to those in the embodiment described with reference to Fig. 28 and the like.
In the above embodiment, the temperature information Tj is measured by a diode added to or formed in the transistor 117 .
In the embodiment of FIG. 49, a diode Ds that is not connected (is independent) from the transistor 117 is formed.

Diode Dsa is oriented to pass constant current Ic. Diode Dsb is oriented to pass constant current Ic'. Constant current circuit 118 (Pc) generates constant current Ic and constant current Ic'.

Diodes Dsa and Dsb are diodes for measuring temperature. The structure of diodes Dsa and Dsb is similar or identical to that of diode Di in Figure 28, etc.

Diode Di is connected to the terminals (terminals c and e) of transistor 117, while diodes Dsa and Dsb are not connected to the terminals of transistor 117 but are connected to independent terminals, and temperature information Tj of diode Di is measured at timing St1 in Figure 46 (c), while temperature information Tj of diode Dsa and diode Dsb is measured at timing St2 in Figure 46 (d). Other than this, they have the same operation or configuration.

In the embodiment of FIG. 49, the diode Ds is separated from the path through which the constant current Id flows. Even when the current Id flows through the transistor 117, the constant current Ic can be passed through the diode. Therefore, the time for measuring the temperature information Tj can be freely set. The positions of tc1 and tc2 can be set as shown in FIG. 46(d).

However, in tc2, as shown in Fig. 46(d), the gate signal is placed or set in the period of Vt. The temperature information Tj measured in the period tc2 is used as the value before the transistor 117 operates. The period tc1 is preferably immediately before the constant current Id of the transistor 117 is stopped. It may also be immediately after the constant current Id is stopped. It is preferable that "immediately before" and "immediately after" are within 1 ms.
St2 in FIG. 46(d) is a timing signal for causing the current Ic (or current Ic') to flow through the diode Ds (Dsa, Dsb).

When St2 is at H level, a current flows through the diode Ds (Dsa, Dsb) of the transistor 117. The operational amplifier circuit 116 acquires the terminal voltage of the diode Ds, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj.

The temperature information Tj is sent to the control circuit board 111, which performs, stops, or changes the control of the test of the transistor 117 according to the temperature information Tj.

When St2 is at the H level, the constant current circuit 118 passes a constant current Ic, which flows through the diode Dsa. The constant current circuit 118 also passes a constant current Ic', which flows through the diode Dsb.

The constant current Ic and the constant current Ic' are currents of the same magnitude. However, when the threshold voltages of the diodes Dsa and Dsb are different, or when the characteristics of the diodes Dsa and Dsb are different, it is preferable to make the constant current Ic and the constant current Ic' different in magnitude.

The operational amplifier circuit 116 acquires the terminal voltage of the diode Dsa or Dsb, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 tests the transistor 117 based on the temperature information Tj.

The temperature information Tj obtained by passing the constant current Ic and the temperature information Tj obtained by passing the constant current Ic' are averaged or weighted to obtain a single value of temperature information Tj. Using this temperature information Tj, the control circuit board 111 performs or stops the test of the transistor 117, or changes the control.
The other matters are the same as or similar to the matters or contents described in this specification and drawings, and therefore will not be described here.

It goes without saying that the present invention can be modified in various ways without departing from the spirit and scope of the invention. It goes without saying that the matters or contents described in this specification and drawings can be combined with each other.

Figure 50 is an explanatory diagram of a semiconductor testing device in an embodiment of the present invention. The difference from Figure 28 is that a diode-connected transistor 117s is placed in the path of a current Id that flows through a transistor 117m to be tested. Other parts are the same, so the explanation is omitted.

As an example, transistor 117s is a transistor with the same specifications as transistor 117m to be tested. The gate terminal g2 and emitter terminal e2 of transistor 117s are connected, and transistor 117s can be considered equivalent to a diode. The gate terminal g2 and emitter terminal e2 of transistor 117s are connected to the O terminal of connection part 507. The collector terminal c2 of transistor 117s is connected to the P terminal of connection part 507.

As shown in FIG. 43, the terminals of the transistor 117s (gate terminal g2, emitter terminal e2, collector terminal c2) are connected to the connector 202b, which is connected to the sample connection circuit 203 by the signal wiring 222b. The terminals of the transistor 117s (gate terminal g2, emitter terminal e2, collector terminal c2) are connected within the sample connection circuit 203.

When the switch circuit 124b is turned on, a current Im flows, discharging the charge of the current power supply device 121. Alternatively, the current Id output by the current power supply device 121 flows to ground via the switch circuit 124b.

When an inrush current Is flows through the transistor 117m being tested, the transistor 117m is destroyed by the inrush current Is or surge voltage Vs. To prevent the inrush current Is or surge voltage Vs from occurring, the on/off control and on/off sequence of the switch circuits 124a and 124b are controlled.

When testing transistor 117m by shortening the cycle tcycle, it is necessary to turn switch circuits 124a and 124b on and off at high speed. In this case, an inrush current Is or a surge voltage Vs may occur depending on the on/off timing of switch circuit 124.

If the voltage Vm at the collector terminal of transistor 117 is higher than the voltage Vp at the output of the current power supply device, the current flows toward ground as current Im, and no current or only a small amount flows through transistor 117m.

In order to create the relationship Vm > Vp, in the embodiment shown in Figure 50, a diode-connected transistor 117s is placed in the path of current Id. When a current flows through transistor 117s, the voltage Vm is built up by the channel voltage of transistor 117s. Therefore, voltage Vp is lower than voltage Vm, and no inrush current is applied to transistor 117m. Transistor 117m will not be destroyed by inrush current Is or surge voltage Vs.

Figure 60 shows the channel (Vce, Vds) voltage or waveform diagram of a transistor when performing a power cycle test on multiple semiconductor elements (power transistors, etc.). Specific circuit configurations and test methods are shown in Figures 51 and 52.

In the semiconductor device testing apparatus and semiconductor device testing method of the present invention, a method for simultaneously testing a plurality of devices is carried out. In the present invention, as an example of the method for simultaneously testing, a time-share method is carried out.
FIG. 60 shows waveforms when power cycles are performed on four devices using one semiconductor device testing apparatus according to the present invention.
From time 2(s) to 4(s), the first device is on, and the other devices (the second device, the third device, and the fourth device) are off.
From time 4 (s) to 6 (s), the second device is on, and the other devices (the first device, the third device, and the fourth device) are off.
From time 6 (s) to 8 (s), the third device is turned on, and the other devices (the first device, the second device, and the fourth device) are turned off.
From time 8 (s) to 10 (s), the fourth device is turned on, and the other devices (the first device, the second device, and the third device) are turned off.
Next, after 4.5 (s) (13.5 (s)), the first device is turned on again, and thereafter, the second device, the third device, and the fourth device are turned on in sequence.

In FIG. 60, for example, the second device is shown to be turned on at the same time as the first device is turned off, but in reality, the second device is turned on after a predetermined time interval (1 to 100 ms) has elapsed since the first device was turned off. The predetermined time tw is configured to be able to be set to a predetermined value or any time.

The above also applies to the operation intervals with other devices, and the specified time tw between each device can be set arbitrarily. The above also applies to Figure 52, etc.

In the semiconductor element testing apparatus and semiconductor testing method of the present invention, the on-time ton of each device and the off-time toff of each device can be set to a predetermined value. When each semiconductor device is a transistor element, the test cycle tc (tcycle), on-time ton or off-time toff, and predetermined time tw can be easily adjusted or set by the pulse time and cycle applied to the gate terminal of the transistor.
When multiple devices are tested using multiple semiconductor device test equipment, the test results include variations between the equipment, making it impossible to accurately compare the devices.

In the semiconductor element testing apparatus and semiconductor element testing method of the present invention, while one device is powered off (OFF), another device is powered on (ON). Power is repeatedly turned on and off at regular intervals, applying thermal stress to the semiconductor device.

By testing multiple devices simultaneously (sequentially) using the same equipment (power supply, temperature measurement, control, bypass, and other test environments), it is possible to speed up device testing and accurately compare device performance.

Figure 51 is an explanatory diagram of a semiconductor testing device in an embodiment of the present invention. In Figure 51, multiple transistors 117 (transistors 117Q1 to 117Qn) to be tested are connected in parallel to a current power supply device 121.

In the embodiment of FIG. 51, it is necessary to arrange a plurality of transistors 117 on a positioning support plate 519. For this reason, as shown in FIG. 53, positioning holes 512 (positioning holes 512a, 512b, 512c, 512d, and 512e in FIG. 53) corresponding to the number of transistors 117 (SOP117, QFN117) to be tested are formed in the sample arrangement plate 511. The SOP117, QFN117, etc. are arranged in each of the positioning holes.

As shown in FIG. 54, electrode patterns 505 and 506 corresponding to the number of SOP117s and QFN117s are formed on the connection board 514. Anisotropic conductive rubber 504 is arranged on the electrode patterns, and multiple SOP117s and QFN117s are pressed with one pressing head.

In this embodiment, there is one switch circuit board 201a and n switch circuit boards 201b (switch circuit boards 201b1 to 201bn). There are n transistors 117Q (transistors 117Q1 to 117Qn) that are tested simultaneously or sequentially.

The collector terminal of transistor Q1 is connected to fork plug 205e1, and the emitter terminal of transistor Q1 is connected to fork plug 205c1.

The collector terminal of transistor Q2 is connected to fork plug 205e2, and the emitter terminal of transistor Q2 is connected to fork plug 205c2.

The collector terminal of transistor Q3 is connected to fork plug 205e3, and the emitter terminal of transistor Q3 is connected to fork plug 205c3.

Similarly, the collector terminal of transistor Qn is connected to fork plug 205en, and the emitter terminal of transistor Qn is connected to fork plug 205cn.

When the switch circuit Ssa1 is turned on, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Q1. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and is output from the operational amplifier circuit 116 as the Vi1 voltage.

When the switch circuit Ssa2 is turned on, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Q2. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and is output from the operational amplifier circuit 116 as the voltage Vi2.

Similarly, when the switch circuit Ssan is turned on, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Qn. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and is output from the operational amplifier circuit 116 as the voltage Vin.
One voltage is selected from voltage Vi 1 to voltage Vin by selector 127 , and output as Vi, which is then input to temperature measurement circuit 115 .

The temperature measuring circuit 115 obtains temperature information Tj and outputs it to the control circuit board 111. In the embodiment of Fig. 51, one constant current circuit 118 is used, but this is not limited to this. A constant current circuit 118 may be provided for each transistor 117Q. Also, a temperature measuring circuit 115 may be formed or provided for each transistor 117Q.
The voltage data Vi and the temperature information Tj are sent to the control circuit board 111 via the wiring of the mother board 207 .

The connection portion 507 (P terminal) of the transistor 117Q1 is connected to the connection structure 218a1. The connection portion 507 (N terminal) of the transistor 117Q1 is connected to the connection structure 218b1.

The connection portion 507 (P terminal) of the transistor 117Q2 is connected to the connection structure 218a2. The connection portion 507 (N terminal) of the transistor 117Q2 is connected to the connection structure 218b2.

Similarly, the connection portion 507 (P terminal) of the transistor 117Qn is connected to the connection structure 218an. The connection portion 507 (N terminal) of the transistor 117Qn is connected to the connection structure 218bn. Here, n is a positive number equal to or greater than 1.
The connection structure 218 is inserted from an opening 216 provided in the partition wall 217. The connection structure 218 is inserted in the direction from the C2 chamber to the C1 chamber.

The fork plug 205 is inserted into chamber B from the C2 chamber side through an opening 216 formed in the partition wall 214. When the fork plug 205 is inserted, it is connected to the conductor plate 204 of the switch circuit board 201. The switch circuit board 201 can be selected depending on the position of the opening 216 into which the fork plug 205 is inserted.

The switch circuit board 201 to be selected by the fork plug 205 can be selected by changing the position of the switch circuit board 201 connected to the connector 213 of the mother board 207.

Two conductive plates 204 are arranged on the switch circuit board 201. The conductive plates 204 are arranged so that the conductive plate 204 closest to the C2 chamber is connected (contacted) to the fork plug 205.

In the embodiment of the present invention, the fork plug 205 and the conductor plate 204 are electrically connected by contacting each other, but this is not limited to this. Any configuration is acceptable as long as it is possible to change between an electrically connected state and a non-connected state by mechanical operation. In addition, any configuration is acceptable as long as it is possible to stably maintain the connected state.

For example, instead of the fork plug 205, a rotary connector, a rotary joint, a high-current connector, etc. may be used. Instead of the conductor plate 204, a rotary connector, a rotary joint, a high-current connector, a cylindrical conductor rod, a rectangular conductor rod, a comb-shaped conductor plate, etc. may be used.

Figure 52 is an explanatory diagram of a method for testing a semiconductor element in an embodiment of the present invention, explaining the operation of Figure 51. It is possible to perform a semiconductor test by simultaneously turning on transistors 117Q (transistors 117Q1 to 117Qn). In this case, it is necessary to pass a constant current Id through all of transistors 117Q (transistors 117Q1 to 117Qn). Therefore, if there are n transistors 117Q, the current power supply device 121 must be able to output a current of Id x n (n is a positive number equal to or greater than 1). Therefore, a large-capacity current power supply device 121 is required.

If the test is performed by turning on transistors 117Q in sequence and applying a constant current Id to transistor 117Q, the constant current output by current power supply device 121 can be Id. Figure 52 shows an example of a test method for a semiconductor test device that performs a test by turning on transistors 117Q in sequence. The semiconductor element changes depending on the number of times the constant current Id is turned on and off.

Therefore, by performing testing by sequentially turning on the semiconductor elements (transistor 117Q, etc.) as shown in FIG. 52, the testing can be performed efficiently and the maximum output current capacity of the current power supply device 121 can be reduced.

In FIG. 52, the number of transistors 117Q turned on is described as one, but this is not limited to this. For example, multiple transistors 117Q may be turned on simultaneously. In this case, the maximum value of the constant current output by the current power supply device 121 is the number of transistors 117Q turned on x Id.

In the embodiment of the present invention, one current power supply device 121 is illustrated, but the present invention is not limited to this. A current power supply device 121b may be installed separately from the current power supply device 121. Two or more current power supply devices 121 may be installed. By installing multiple current power supply devices 121, the current Id flowing through the transistor 117 can have various waveforms.
The above also applies to the embodiments of the present invention.

As shown in FIG. 52(a), when switch circuit St1 (151s1) to switch circuit Stn (151sn) are turned on, constant currents Id1 to Idn flow through transistor 117. For example, the application time of constant current Id is ton, and constant currents Id1 and Id2 are applied to transistor 117 sequentially at intervals of time tcycle. When transistor 117 is turned on, the channel voltage of transistor 117Q changes sequentially (FIG. 52(c)).

Therefore, for example, there is no overlap in time between the constant current Id1 and the constant current Id2. Therefore, the output capacity of the current power supply device 121 can be the output capacity required to test one transistor 117Q.

The constant currents Id (Id1 to Idn) are controlled so as not to overlap. It is also preferable to leave an interval of 1 μs or more between each of the constant currents Id (Id1 to Idn). The driving and control methods described in FIG. 46 are implemented for each transistor 117Q.

The constant current Ic supplied to each transistor 117Q is supplied to the diode Ds of each transistor 117Q by sequentially turning on the switch circuits Ssa (Ssa1 to Ssan).

A voltage Vi (Vi1 to Vin) corresponding to the terminal voltage of diode Ds is selected by the selector 127 in synchronization with the switch circuit Ssa (Ssa1 to Ssan). For example, when a current Ic is supplied to the transistor 117Q1, the selector 127 selects the terminal voltage of the diode Ds of the transistor 117Q1. When a current Ic is supplied to the transistor 117Q3, the selector 127 selects the terminal voltage of the diode Ds of the transistor 117Q3. The selected voltage Vi is supplied to the temperature measurement circuit 115.
The other configurations and operations are similar to those described in the other embodiments, and therefore the description thereof will be omitted.
In the embodiment of the present invention, the transistor 117 is an IGBT, but the present invention is not limited to this.

For example, it goes without saying that it may be an N-channel JFET (Figure 55(a)), a P-channel JFET (Figure 55(b)), an N-channel MOSFET (Figure 55(c)), a P-channel MOSFET (Figure 55(d)), an N-channel bipolar FET (Figure 55(e)), or a P-channel bipolar FET (Figure 55(f)).

Furthermore, the device is not limited to a three-terminal device, but may be a two-terminal element such as a diode as shown in FIG. 55(g). A two-terminal element does not require the gate signal Vgs. It goes without saying that the semiconductor testing device and semiconductor element testing method of the present invention can be applied by testing by passing a constant current Id from the current power supply device 121.

It goes without saying that the semiconductor testing device and semiconductor element testing method of the present invention can be applied to other semiconductor elements such as thyristors and triacs, varistors, diacs, or modules in which transistors, diodes, resistors, etc. are mixed or integrated, without being limited to transistors and diodes.

In addition, the present invention is not limited to semiconductor elements, but can also be applied to, for example, resistive elements such as concrete resistors and enamel resistors, variable resistive elements, nonlinear resistive elements such as thermistors and posistors, and bias elements such as transformers.

In the above, the present specification has specifically described the present invention based on the embodiment, but it goes without saying that the present invention is not limited thereto and various modifications are possible without departing from the spirit of the present invention.
It goes without saying that the matters or contents described in this specification and the drawings can be mutually combined.

For example, the switch circuit 124a and the switch circuit 124b shown in FIG. 45 can be applied to other embodiments. For example, it goes without saying that the configurations or operations of FIG. 51 and FIG. 52 can be applied to other embodiments such as FIG. 49 and FIG. 50.

For example, it goes without saying that the devices of the present invention shown in Figures 25, 68, and 72, the operations of the devices, and the configurations of the devices can be combined with each other in part or in whole.
For example, it goes without saying that the present inventions described with reference to Figs. 2, 5, 7, 58, etc. can be combined with each other in part or in whole.

For example, it goes without saying that the test methods, inspection methods, and test device driving methods of the present invention described in Figures 46, 47, 48, 49, 50, 51, 53, 60, 61, 62, 63, 64, 65, 66, 67, etc. can be combined in part or in whole with each other.

The present invention provides a semiconductor testing device and a semiconductor testing method that can easily change connections depending on the test content of semiconductor elements such as transistors and the number of semiconductor elements to be tested simultaneously, and can effectively deal with noise generated during testing.

111 Control circuit board (controller)
112 Gate signal control circuit 113 Gate driver circuit 115 Temperature measurement circuit (not shown)
116 Op-amp circuit (buffer amplifier)
117 Power transistor 121 Constant current circuit 122 Switch circuit 123 Switch circuit 124 Switch circuit 125 Variable resistance circuit 126 Variable resistance circuit 127 Changeover switch circuit 128 Current detection circuit 129 Voltage detection circuit 130 Constant current setting circuit 131 Control rack 132 Power supply device 133 Control circuit 134 Heating and cooling plate 135 Circulating water pipe 136 Chiller 137 Short circuit 138 Insulated DC-DC converter circuit 201 Switch circuit board 202 Connector 203 Sample connection circuit 204 Conductive plate 205 Fork plug 206 Connection pin 207 Mother board 208 Connector 209 Device control circuit board 210 Housing 211 Connection wiring 212 Power supply wiring 213 Connector 214 Partition wall 215 Partition wall 216 Opening 217 Partition wall 218 Connection structure 219 Connection bolt 220 Contact portion 221 Fixing screw 222 Signal wiring 223 Heat pipe 224 Fixing screw 225 Contact portion 226 Electrode terminal 227 Signal terminal 228 Heat dissipation fin 229 Cooling fan 230 Conductive wire 231 Heat pipe fitting 232 Connection fitting 233 Connection fitting 234 Recess 235 Signal wiring 239 Placement recess 301 Test circuit module 302 Voltage selection circuit 502 Connection pin 503 Connection wiring 504 Anisotropic conductive rubber 505 Electrode pattern 506 Electrode pattern 507 Connection portion 508 Signal wiring 509 Positioning hole 510 Fixing hole 511 Sample placement plate 512 Sample hole 514 Connection board 515 Pressing plate 516 Pressing tool 517 Rubber (elastic material)
518 Positioning support 519 Positioning support plate 520 Surface plate 521 Sample plate 522 Base 523 Heat-resistant resist 524 Ni-P plating film 525 Heat-resistant substrate 525 Gold plating film 530 Pressing head 531 Pressing post 532 Arm 533 Arm stand 534 Support 601 Semiconductor chip 602 Insulating substrate 604 Copper base 605 Solder 606 Aluminum wire 607 Wiring electrode 608 Pressing member 609 Terminal connection portion 610 Device fixing/connecting device 611 Device stand

Claims (10)

A semiconductor testing apparatus for testing a power module, comprising:
A connection structure;
A support member;
A first heating/cooling plate;
a second heating/cooling plate;
a circulation pipe attached to the first heating/cooling plate and the second heating/cooling plate;
a power supply device that supplies a test current to the power module via the connection structure;
a pressing member attached to the support member and holding the connection structure;
the power module is disposed between the first heating/cooling plate and the second heating/cooling plate;
A power cycle testing device, characterized in that the position of the connection structure can be moved and maintained by changing the mounting positions of the support member and the pressing member. A semiconductor testing apparatus for testing a power module, comprising:
a first switch circuit mounted or disposed on a first switch circuit board;
A connection structure;
A support member;
A first heating/cooling plate;
a second heating/cooling plate;
a circulation pipe attached to the first heating/cooling plate and the second heating/cooling plate;
a power supply device that supplies a test current to the power module via the connection structure and the first switch circuit;
a pressing member attached to the support member and holding the connection structure;
the power module is disposed between the first heating/cooling plate and the second heating/cooling plate;
By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained,
the first switch circuit is disposed between the power supply device and the connection structure;
When the first switch circuit is turned on, the test current is supplied to the power module via the connection structure,
The power module is disposed in a first chamber;
The power cycle testing apparatus according to claim 1, wherein the first switch circuit board is disposed in a second chamber. A semiconductor testing apparatus for testing a power module, comprising:
a first switch circuit mounted or disposed on a first switch circuit board;
a second switch circuit mounted or disposed on a second switch circuit board;
A connection structure;
A support member;
A first heating/cooling plate;
a second heating/cooling plate;
a circulation pipe attached to the first heating/cooling plate and the second heating/cooling plate;
a power supply device that supplies a test current to the power module via the connection structure and the first switch circuit;
a pressing member attached to the support member and holding the connection structure;
the power module is disposed between the first heating/cooling plate and the second heating/cooling plate;
By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained,
the first switch circuit is disposed between the power supply device and the connection structure;
When the first switch circuit is turned on, the test current is supplied to the power module via the connection structure,
the second switch circuit has a function of short-circuiting an output of the power supply device,
The power module is disposed in a first chamber;
The power cycle testing apparatus, wherein the first switch circuit board and the second switch circuit board are disposed in a second chamber. A semiconductor testing apparatus for testing a power module, comprising:
a constant current circuit that applies a constant current between terminals of the power module;
a voltage output circuit that outputs a terminal voltage between terminals of the power module;
A first switch circuit;
A connection structure;
A support member;
A first heating/cooling plate;
a second heating/cooling plate;
a circulation pipe attached to the first heating/cooling plate and the second heating/cooling plate;
a power supply device that supplies a test current to the power module via the connection structure and the first switch circuit;
a pressing member attached to the support member and holding the connection structure;
the power module is disposed between the first heating/cooling plate and the second heating/cooling plate;
By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained,
the first switch circuit is disposed between the power supply device and the connection structure;
When the first switch circuit is turned on, the test current is supplied to the power module via the connection structure,
2. A power cycle testing device comprising: a first switch circuit for applying a constant current between the terminals and a voltage output circuit for outputting a terminal voltage between the terminals during a period in which the first switch circuit is turned off; A semiconductor testing apparatus for testing a power module, comprising:
a gate driver circuit that outputs a gate voltage for turning on or off the power module;
a voltage output circuit that outputs a terminal voltage between terminals of the power module;
A connection structure;
A support member;
A first heating/cooling plate;
a second heating/cooling plate;
a circulation pipe attached to the first heating/cooling plate and the second heating/cooling plate;
a power supply device that supplies a test current to the power module via the connection structure;
a pressing member attached to the support member and holding the connection structure;
the power module is disposed between the first heating/cooling plate and the second heating/cooling plate;
By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained,
The gate driver circuit varies the gate voltage so that the power of the power module calculated from the terminal voltage output by the voltage output circuit and the test current becomes a designated power. The apparatus further includes a cooling or heating device connected to the circulation pipe for adjusting a temperature of the liquid flowing through the circulation pipe,
4. The power cycle testing apparatus according to claim 2, wherein dry air is introduced into said first chamber. a cooling or heating device connected to the circulation pipe and adapted to adjust the temperature of the liquid flowing through the circulation pipe;
Further comprising a water leakage sensor for detecting the leaked liquid,
6. A power cycle testing device according to claim 1, 2, 3, 4 or 5, wherein the operation of the power cycle testing device is stopped or an alarm is issued in response to the operation of the water leakage sensor. Further comprising a gate driver circuit that outputs a gate voltage that turns on or off the power module,
5. The power cycle testing device according to claim 1, 2, 3 or 4, wherein the wiring for outputting the gate voltage is a twisted wiring or a shielded wiring. 6. The power cycle testing device according to claim 4, wherein the test is stopped, the control method is changed, or the test conditions are changed based on the terminal voltage. n (n is a positive number equal to or greater than 2) power modules are disposed between the first heating/cooling plate and the second heating/cooling plate;
6. A power cycle testing device according to claim 1, 2, 3, 4 or 5, further comprising n switch circuit boards arranged corresponding to said n power modules.

Images