JP7574964B1 - Semiconductor Device - Google Patents

Abstract

A plurality of patterns (10, 11, 12) are formed on different levels of a plurality of stacked layers (7, 8, 9) of a semiconductor element (1). The plurality of patterns (10, 11, 12) are divisions of a two-dimensional code of ID information.

Description

The present disclosure relates to a semiconductor element.

To achieve traceability of semiconductor elements, it is necessary to form ID information within the element that can identify the type, lot number, wafer number, chip address, etc. However, with small elements, there is a problem in that it is not possible to secure space to form the ID information. In response to this, it has been proposed to divide the two-dimensional code for the ID information and place it in multiple spare spaces on the surface of the element (see, for example, Patent Document 1).

Japanese Patent Publication No. 2006-351620

However, when the element size is small and there is not enough spare space on the element surface, there is a problem that even if the two-dimensional code is divided, it cannot be completely formed on the element surface.

This disclosure has been made to solve the problems described above, and its purpose is to obtain a semiconductor element that can form a two-dimensional code even when the element size is small.

The semiconductor element according to the present disclosure comprises a plurality of stacked layers and a plurality of patterns formed on different levels of the plurality of layers, the plurality of patterns being divided two-dimensional codes of ID information, the plurality of layers having first and second layers made of materials having different transmission wavelength ranges, the plurality of patterns having a first pattern formed in the first layer and a second pattern formed in the second layer , and the plurality of patterns are arranged in positions where at least a portion of them overlap each other in a planar view .

In this disclosure, multiple patterns obtained by dividing a two-dimensional code are formed not only on the surface of the element but also between layers inside the element. By dividing and arranging the two-dimensional code three-dimensionally, including not only the planar direction but also the height direction, in the surplus space inside the element, it is possible to form a two-dimensional code even if the element size is small.

1 is a plan view showing a semiconductor element according to a first embodiment; 4 is a cross-sectional view showing an excess space of the semiconductor element according to the first embodiment; 1 is a diagram showing an apparatus for reading a two-dimensional code of a semiconductor element according to a first embodiment; 5A to 5C are diagrams illustrating an example of a method for reading a two-dimensional code of a semiconductor element according to the first embodiment. 11A to 11C are diagrams illustrating another example of a method for reading a two-dimensional code of a semiconductor element according to the first embodiment. 11 is a cross-sectional view showing an excess space of a semiconductor element according to a second embodiment. FIG. FIG. 11 is a cross-sectional view showing an excess space of a semiconductor element according to a third embodiment. FIG. 11 is a diagram showing an apparatus for reading a two-dimensional code of a semiconductor element according to a third embodiment.

The semiconductor device according to the embodiment will be described with reference to the drawings. The same or corresponding components will be given the same reference numerals, and repeated explanations may be omitted.

Embodiment 1.
1 is a plan view showing a semiconductor device according to a first embodiment. This semiconductor device 1 is, for example, a chip for optical communications, and has an active region such as a waveguide 2 through which a current flows during operation. Metal electrodes 3, 4, and 5 are formed on the upper surface of the semiconductor device 1. The metal electrodes 3, 4, and 5 are connected to the active region. The semiconductor device 1 has a surplus space 6 where the active region and the metal electrodes 3, 4, and 5 are not formed.

Figure 2 is a cross-sectional view showing the excess space of a semiconductor element according to embodiment 1. The semiconductor element has multiple stacked layers. Specifically, a semiconductor layer 8 is formed on a semiconductor substrate 7, and an insulating film 9 is formed on the semiconductor layer 8. A pattern 10 is formed between the semiconductor substrate 7 and the semiconductor layer 8. A pattern 11 is formed between the semiconductor layer 8 and the insulating film 9. A pattern 12 is formed on the insulating film 9. That is, multiple patterns 10, 11, and 12 are formed on different levels of multiple layers of the semiconductor element. The multiple patterns 10, 11, and 12 are divided two-dimensional codes of ID information indicating the type, lot number, wafer number, or chip address.

Each of the patterns 10, 11, and 12 consists of, for example, 18 x 18 dots. The size of the dots is, for example, 3 μm or more. The patterns 10, 11, and 12 may or may not overlap each other in the vertical direction.

The semiconductor substrate 7 is, for example, an InP substrate, but may be a Si substrate or a SiC substrate, etc. The semiconductor layer 8 is, for example, an InP layer, but may be an insulating resin film such as BCB or polyimide, etc. The insulating film 9 is, for example _{, SiO2} or SiN, but may be an insulating resin film such as BCB or polyimide, etc.

The patterns 10 and 11 are InGaAsP and are made of a different material from the surrounding semiconductor substrate 7, semiconductor layer 8, and insulating film 9. The pattern 12 is a remaining pattern of an insulating film such as _SiO2 or SiN. The patterns 10 and 11 may be changed to an insulating film such as _SiO2 or SiN.

The manufacturing process for a typical semiconductor device includes a step of growing semiconductor crystals such as an InP layer and an InGaAsP layer on an InP substrate, a step of processing and patterning the grown crystals, and a step of forming an insulating film after the semiconductor crystals are grown. Patterns 10 and 11 can be formed simultaneously with the step of patterning the InGaAsP layer of this semiconductor device. Also, pattern 12 can be formed by patterning the insulating film of the semiconductor device.

Figure 3 is a diagram showing an apparatus for reading a two-dimensional code on a semiconductor element according to embodiment 1. This apparatus has a reflective microscope and a transmission microscope. In the reflective microscope, light emitted from a reflected illumination light source 13 is irradiated onto the semiconductor element 1 via an objective lens 14. The light reflected by the semiconductor element 1 is observed by a camera 16 via an imaging lens 15. Meanwhile, in the transmission microscope, light emitted from a transmitted illumination light source 17 is irradiated onto the semiconductor element 1 via a condenser lens 18. The light that has passed through the semiconductor element 1 is observed by a camera 16.

The light emitted by the reflected illumination light source 13 is, for example, visible light, and the light emitted by the transmitted illumination light source 17 is, for example, infrared light. Since neither visible light nor infrared light passes through metal, a two-dimensional code is formed in the excess space 6 where the metal electrodes 3, 4, and 5 are not formed. For example, a high-contrast two-dimensional code image can be obtained by observing the pattern 12 made of an insulating film with a short transmission wavelength with a visible light reflection microscope and observing the patterns 10 and 11, which do not transmit infrared light, with an infrared transmission microscope.

Figure 4 is a diagram showing an example of a method for reading a two-dimensional code of a semiconductor element according to embodiment 1. Even if patterns 10, 11, and 12 are transparent to infrared rays, the transmittance is not 100%, so the patterns can be recognized by focusing on the position of each pattern and observing it. Therefore, using an infrared transmission microscope or the like, patterns 10, 11, and 12 of each layer are read while changing the focal position. The multiple read patterns 10, 11, and 12 are image-processed to restore them to the original two-dimensional code, and the ID information is read.

FIG. 5 is a diagram showing another example of a method for reading a two-dimensional code of a semiconductor element according to the first embodiment. The layers of the semiconductor element are made of materials with different transmission wavelength regions. Here, each material such as the semiconductor layer and the insulating film has its own transmission wavelength region, and transmits light in the transmission wavelength region. Here, the light energy E and the wavelength λ have a relationship of E=hc/λ (h: Planck's constant, c: speed of light). Therefore, E [eV]=1240/λ [nm]. On the other hand, if the band gap energy inherent to the material is Eg, it is considered that light that satisfies E<Eg transmits the material, and light with a wavelength λ that satisfies λ [nm]>1240/Eg [eV] transmits the material. For example, in the case of InP, if Eg=1.35 eV, λ≒919 nm is the lower limit of the transmission wavelength. However, the lower limit of the transmission wavelength varies depending on the uniformity of the crystal and the inclusion of impurities. In addition, in a quaternary mixed crystal such as In1 _{- xGaxAsyP1 -y ,} the lower limit of the transmission wavelength varies within a range of 1.0 to 1.7 μm depending on the composition ratio of the elements.

The wavelength of the emitted light from the infrared transmission microscope is changed to A, B, and C to read the patterns 10, 11, and 12 formed on the multiple layers, respectively. This ensures high contrast during reading, and improves the restoration and reading accuracy of the two-dimensional code. For example, wavelength A is 380 nm to 780 nm in the visible light band when a reflecting microscope is used, and 1000 nm or more when an infrared transmission microscope is used, and wavelengths B and C are 1400 nm or more.

As explained above, in this embodiment, multiple patterns obtained by dividing the two-dimensional code are formed not only on the surface of the element, but also between layers inside the element. In this way, by dividing and arranging the two-dimensional code three-dimensionally, including not only the planar direction but also the height direction, in the surplus space inside the element, it is possible to form a two-dimensional code even if the element size is small. As a result, traceability can be achieved.

In this embodiment, the two-dimensional code is divided into three layers, but the invention is not limited to this and may be divided into two or more layers. The number of divisions and shape of the two-dimensional code are arbitrary.

Furthermore, patterns 10, 11, and 12 are arranged in positions where at least a portion of them overlap each other in a planar view. This allows a two-dimensional code to be formed in a minimum of excess space. However, it is preferable that the materials of patterns 10, 11, and 12 arranged in overlapping positions are not opaque materials but materials with equivalent transmission wavelength ranges.

Embodiment 2.
6 is a cross-sectional view showing an excess space of a semiconductor element according to the second embodiment. Pattern 10 is an uneven pattern obtained by processing the surface of semiconductor substrate 7. Pattern 11 is an uneven pattern obtained by processing the surface of semiconductor layer 8. By making patterns 10 and 11 uneven, it is not necessary to form another material between layers of the semiconductor element, and the process can be simplified. Although pattern 12 is a remaining pattern, it is not limited to this, and may be an uneven pattern obtained by processing the surface of the layer below while leaving the top layer of insulating film 9. The other configurations and effects are the same as those of the first embodiment.

Embodiment 3.
7 is a cross-sectional view showing the surplus space of a semiconductor element according to the third embodiment. The side surfaces of a plurality of patterns 10, 11, and 12 are inclined surfaces. The other configurations are the same as those of the second embodiment. Note that the side surfaces of the remaining patterns of the first embodiment may be inclined surfaces.

Figure 8 is a diagram showing an apparatus for reading a two-dimensional code on a semiconductor element according to embodiment 3. This apparatus is a differential interference microscope. Light emitted from a light source 19 is irradiated onto a semiconductor element 1 via a polarizing plate 20 (polarizer), a DIC prism 21, and a condenser lens 22. The light transmitted through the semiconductor element 1 is observed by a camera 16 via an objective lens 23, a DIC prism 24, and a polarizing plate 25 (analyzer).

In this way, polarizing plates 20, 25 are provided on the light source 19 side or the camera 16 side of the differential interference microscope, and patterns 10, 11, and 12 are read using a principle called differential interference. In differential interference, light from the light source 19 is split into two polarized lights by the polarizing plate 20 and the DIC prism 21, and the two polarized lights pass through two slightly different points on the semiconductor element 1 and are then combined again by the DIC prism 24. If there is an optical path difference between the two polarized lights, interference occurs. At gradient parts such as pattern boundaries, the optical path difference between the two polarized lights becomes large, making interference more likely to occur and resulting in high contrast. Therefore, the side surfaces of the dot patterns of patterns 10, 11, and 12 are made inclined. When such dot patterns are observed with a differential interference microscope, the contrast is emphasized and the reading accuracy of the two-dimensional code is improved.

1 Semiconductor element, 2 Waveguide (active region), 3, 4, 5 Metal electrodes, 7 Semiconductor substrate, 8 Semiconductor layer, 9 Insulating film, 10, 11, 12 Pattern

Claims (6)

A plurality of stacked layers;
A plurality of patterns formed in different levels of the plurality of layers,
The plurality of patterns are obtained by dividing a two-dimensional code of ID information,
the plurality of layers include a first layer and a second layer made of materials having different transmission wavelength ranges;
the plurality of patterns includes a first pattern formed in the first layer and a second pattern formed in the second layer;
The semiconductor element is characterized in that the plurality of patterns are arranged in positions where at least a portion of each pattern overlaps with each other in a plan view . an active region through which current flows during operation;
a metal electrode connected to the active region;
a surplus space in which the active region and the metal electrode are not formed,
The semiconductor device according to claim 1 , wherein the plurality of patterns are formed in the excess space. The semiconductor element according to claim 1 or 2, characterized in that the ID information indicates a product type, a lot number, a wafer number, or a chip address. The semiconductor element according to claim 1 or 2, characterized in that the multiple patterns include a pattern made of a material different from the multiple layers. The semiconductor element according to claim 1 or 2, characterized in that the multiple patterns have a concave-convex pattern formed by processing the surfaces of the multiple layers. The semiconductor element according to claim 1 or 2, characterized in that the side surfaces of the multiple patterns are inclined surfaces.

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