JP7574517B2 - Semiconductor Integrated Circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit including an NMOS transistor formed on a P-type substrate, and equipped with a protection element that protects the NMOS transistor from noise and surge voltages.

For example, in the output circuit of a wired network, the transistors constituting the output circuit are configured with N-type DMOSFETs (Double Diffused MOSFETs) to protect the output circuit from electrostatic noise input from the output terminal. Furthermore, when the voltage of the output terminal becomes negative, the presence of a parasitic diode (body diode) between the drain and source of the DMOSFET makes it impossible to ensure sufficient withstand voltage, so the circuit is configured to include an electrostatic (ESD: Electro-Static Discharge) protection element. For example, the electrostatic protection element can be configured with a bidirectional thyristor (for example, see Patent Document 1).

U.S. Pat. No. 9,659,922

When an NMOS transistor such as an N-type DMOSFET connected between an output terminal and a ground terminal and a bidirectional thyristor (bidirectional electrostatic discharge protection element) serving as the protection element are formed on a P-type substrate, a parasitic diode is formed between the P-type substrate and the N-type region constituting the circuit element. It is known that when ESD of different polarities is applied to the output terminal and ground terminal to which the bidirectional thyristor serving as the protection element is connected, the characteristics of the protection element differ depending on the polarity of the ESD. This is due to the difference in operation between when the parasitic transistor equivalently formed by turning on the parasitic diode due to the polarity of the ESD is turned on and when this parasitic transistor is not formed. Therefore, the present invention aims to provide a semiconductor integrated circuit that can obtain the desired characteristics without being affected by the parasitic transistor when an NMOS transistor serving as the protected element and a bidirectional thyristor serving as the protection element are formed on a P-type substrate.

In order to achieve the above object, the invention according to claim 1 of the present application is a semiconductor integrated circuit including a bidirectional electrostatic discharge protection element consisting of an NMOS transistor having a gate to which a control signal is input and a drain connected to a first terminal, a first bipolar transistor and a second bipolar transistor having a collector commonly connected and an emitter connected to the first terminal or the second terminal, respectively, and a third bipolar transistor having a base connected to the commonly connected collectors of the first bipolar transistor and the second bipolar transistor, one of the bidirectional emitters connected to the base of the first bipolar transistor and the emitter of the first bipolar transistor via a resistor element, and the other of the bidirectional emitters connected to the base of the second bipolar transistor and the emitter of the second bipolar transistor via a resistor element, the semiconductor integrated circuit including a diode having an anode connected to the source of the NMOS transistor and a cathode connected to the second terminal, and a third terminal connected to the connection point between the source of the NMOS transistor and the anode of the diode.

The invention according to claim 2 of the present application is directed to a P-type substrate, which includes an NMOS transistor having a gate to which a control signal is input and a drain connected to a first terminal, a first bipolar transistor and a second bipolar transistor having collectors commonly connected and emitters connected to the first terminal or the second terminal, respectively, and a base connected to the commonly connected collectors of the first bipolar transistor and the second bipolar transistor, one of the bidirectional emitters being connected to the base of the first bipolar transistor and the first bipolar transistor via a resistor element. A bidirectional electrostatic discharge protection element consisting of a third bipolar transistor having an emitter connected to the base of the second bipolar transistor and the other of the bidirectional emitters connected to the base of the second bipolar transistor and the emitter of the second bipolar transistor via a resistor element, the semiconductor integrated circuit is characterized in that it has a diode having an anode connected to the source of the NMOS transistor and a cathode connected to the second terminal, and a third terminal connected to the P-type substrate is connected to the connection point between the source of the NMOS transistor and the anode of the diode.

The invention according to claim 3 of the present application is characterized in that, in the semiconductor integrated circuit according to claim 1 or claim 2, a plurality of the bidirectional electrostatic discharge protection elements are connected in series between the first terminal and the second terminal.

The semiconductor integrated circuit of the present invention is not affected by parasitic transistors (parasitic diodes), so even when ESD of different polarities is applied to the first terminal and the second terminal, the same ESD resistance can be obtained regardless of the polarity. In particular, when forming an NMOS transistor as a protected element and a bidirectional thyristor as a protective element on a P-type substrate used in general semiconductor integrated circuits, it is possible to create a configuration that is not affected by the parasitic diode formed by the P-type substrate and the N-type region, making it a semiconductor integrated circuit with a wide range of applications.

FIG. 2 is an explanatory diagram of a bidirectional thyristor. FIG. 1 is an explanatory diagram of a typical semiconductor integrated circuit in which an NMOS transistor and a bidirectional thyristor are formed on a P-type substrate. This is an equivalent circuit of both thyristors when the parasitic transistor is on. FIG. 1 is an explanatory diagram of a semiconductor integrated circuit according to the present invention; FIG. 1 is an explanatory diagram of a circuit configuration of a semiconductor integrated circuit according to the present invention; 1 is an explanatory diagram of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 11 is an explanatory diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 11 is an explanatory diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

The semiconductor integrated circuit of the present invention includes an NMOS transistor as the protected element and a bidirectional thyristor (corresponding to a bidirectional electrostatic discharge protection element) as the protection element, and is configured to be unaffected by parasitic transistors (parasitic diodes).

First, we will explain the bidirectional thyristor, which is a protective element. A bidirectional thyristor is configured by connecting the collectors of two NPN transistors together and shorting their bases and emitters to form two terminals, forming a pnpn junction between the two terminals.

In a typical semiconductor integrated circuit, such a bidirectional thyristor is formed on a P-type silicon substrate (P-type substrate). Figure 1 is an explanatory diagram of a bidirectional thyristor formed on a P-type substrate. As shown in Figure 1, an N-type epitaxial layer 2 is laminated on a P-type substrate 1, and a bidirectional thyristor is formed in a protection element formation region partitioned by an element isolation region 3 made of a high-concentration P-type region.

As shown in FIG. 1, an N-type buried layer 4 and a high-concentration N-type diffusion region 5 that reaches from the surface of the N-type epitaxial layer 2 to the N-type buried layer 4 are formed between the P-type substrate 1 and the N-type epitaxial layer 2. The two N-type epitaxial layers 2 sandwiching the N-type diffusion region 5 form an NPN transistor formation region. This NPN transistor formation region includes P-type diffusion regions 6a and 6b, and high-concentration P-type diffusion regions 7a and 7b and high-concentration N-type diffusion regions 8a and 8b formed on the surfaces of the P-type diffusion regions 6a and 6b.

When the P-type diffusion region 7a and the N-type diffusion region 8a of one NPN transistor formation region are commonly connected to a first terminal T1, and the P-type diffusion region 7b and the N-type diffusion region 8b of the other NPN transistor formation region are commonly connected to a second terminal T2, a bidirectional thyristor as shown in FIG. 1 is formed.

To explain the bidirectional thyristor shown in FIG. 1 in more detail, a first NPN transistor Q1 with the N-type diffusion region 8a as the emitter, the P-type diffusion region 6a as the base, and the N-type diffusion region 5 as the collector, and a second NPN transistor Q2 with the N-type diffusion region 8b as the emitter, the P-type diffusion region 6b as the base, and the N-type diffusion region 5 as the collector are formed between the first terminal T1 and the second terminal T2. Furthermore, a PNP transistor Q3 with the P-type diffusion regions 6a and 6b as the collector or emitter, the N-type epitaxial layer 2, the N-type buried layer 4, and the N-type diffusion region 5 as the base is formed between the first terminal T1 and the second terminal T2. The resistor elements indicate the resistance components in the P-type diffusion regions 6a and 6b, respectively.

In a bidirectional thyristor with this structure, when ESD is applied between the first terminal T1 and the second terminal T2, it is possible to obtain approximately the same voltage-current characteristics for both positive and negative ESD voltages. In other words, the absolute values of the trigger voltage and snapback holding voltage at which it operates as a protective element are approximately equal.

However, when an NMOS transistor and a protection element are formed on a P-type substrate as the protected element, the bidirectional thyristor may not exhibit the desired voltage-current characteristics. Figure 2 shows an example of an NMOS transistor (DMOSFET in Figure 2) and a bidirectional thyristor formed on a P-type substrate. The NMOS transistor and bidirectional thyristor are connected between the first terminal T1, which is the output terminal, and the second terminal T2, which is the ground terminal. The drain D of the NMOS transistor is connected to the first terminal T1 via a reverse current prevention diode 9, and the source S is connected to the second terminal T2. A control signal that controls the on/off of the NMOS transistor is applied to the gate G of the NMOS transistor. The bidirectional thyristor is connected as described above.

The P-type substrate 1 is generally connected to the second terminal T2, which serves as a ground terminal. As a result, a parasitic diode is formed between the P-type substrate 1 and the N-type buried layer 4. Specifically, a parasitic diode 10 is formed between the P-type substrate 1 and the N-type buried layer 4, which constitutes the bidirectional thyristor, with the P-type substrate 1 as the anode and the N-type buried layer 4 as the cathode.

The formation of this parasitic diode 10 will be explained together with the operation of the protection element. First, a case where a positive ESD is applied to the first terminal T1 with respect to the second terminal T2 as the reference will be explained. When a certain voltage lower than the withstand voltage of the NMOS transistor, which is the protected element, is reached, the bidirectional thyristor, which is the protection element, starts to operate. As a result, the current due to the ESD flows to the second terminal T2 (ground terminal), and the NMOS transistor is protected.

On the other hand, when a negative ESD is applied to the first terminal T1 with the second terminal T2 as the reference, the bidirectional thyristor is set to operate before the reverse current prevention diode 9, so that the current caused by the ESD flows to the first terminal T1 and the NMOS transistor is protected. However, in this case, the parasitic diode 10 is forward biased, and the bidirectional thyristor becomes equivalent to the circuit shown in Figure 3. In other words, a PNP transistor Q4 (parasitic transistor) is generated.

Here, if the thyristor including the PNP transistor Q3 operates predominantly, the same protection characteristics can be obtained as when a positive ESD is applied to the first terminal T1 with the second terminal T2 as the reference. However, there are also cases where the thyristor including the PNP transistor Q4 operates predominantly. That is, there are cases where the PNP transistor Q4 operates before the PNP transistor Q3. As a result, the snapback holding voltage when a negative ESD is applied is lower than when a positive ESD is applied, and the desired characteristics cannot be obtained.

By optimizing the semiconductor diffusion region that constitutes the bidirectional thyristor, it is possible to set the snapback holding voltage at which PNP transistor Q4 operates higher than the snapback voltage at which PNP transistor Q3 operates. However, when forming a semiconductor integrated circuit, the protecting element and the protected element, or the elements that constitute the internal circuit, are formed simultaneously, so the desired characteristics may not be obtained. In addition, forming only the bidirectional thyristor using a dedicated process is not preferable because it increases the manufacturing costs of the semiconductor integrated circuit.

The present invention proposes a semiconductor integrated circuit that is not affected by the parasitic diode 10. The semiconductor integrated circuit of the present invention is similar to the general semiconductor integrated circuit described in FIG. 2 in that it includes an NMOS transistor as the protected element and a bidirectional thyristor as the protective element, but the connection of the reverse current prevention diode and the potential of each terminal are changed. The semiconductor integrated circuit of the present invention will be described in detail below.

Figure 4 is an explanatory diagram of the semiconductor integrated circuit of the present invention. In the example shown in Figure 4, an NMOS transistor as the protected element and a bidirectional thyristor as the protection element are connected between a first terminal T1 as the output terminal and a second terminal T2 as the ground terminal, which is similar to the general semiconductor integrated circuit described in Figure 2. However, it differs from the general semiconductor integrated circuit in the following points.

First, a third terminal T3 is provided. Here, if the first terminal T1 is the high potential terminal of the internal circuit of the semiconductor integrated circuit and the second terminal T2 is the lowest potential terminal, the third terminal is a terminal with a lower potential than the high potential terminal. In addition, since this third terminal T3 is connected to the source of the NMOS transistor, which is the protected element, it is a terminal that provides a potential difference between the third terminal T3 and the first terminal to which the drain is connected that allows the NMOS transistor to operate. The third terminal T3 is also connected to the P-type substrate 1.

Furthermore, the anode of the reverse current prevention diode 11 is connected to the source S of the NMOS transistor, and the cathode is connected to the second terminal T2. Figure 5 shows the circuit configuration of the semiconductor integrated circuit shown in Figure 4.

The operation of the protection element in the semiconductor integrated circuit with the configuration shown in Figure 5 will be described. First, a case where a positive ESD is applied to the first terminal T1 with respect to the second terminal T2 will be described. When a certain voltage lower than the withstand voltage of the NMOS transistor, which is the protected element, is reached, the bidirectional thyristor, which is the protection element, starts to operate. As a result, a current due to the ESD flows to the second terminal T2, and the NMOS transistor is protected.

On the other hand, when a negative ESD is applied to the first terminal T1 with the second terminal T2 as the reference, the negative ESD is applied to the bidirectional thyristor and the reverse current prevention diode 11. Here, by designing the bidirectional thyristor to operate before the reverse current prevention diode 11, the current due to the ESD flows to the first terminal T1. In this way, the reverse current prevention diode 11 prevents the parasitic diode 12 from operating. In other words, the circuit configuration shown in Figure 3 can be configured without the transistor Q4. Therefore, the polarity of the ESD does not cause a difference in the snapback holding voltage.

As described above, according to the present invention, it is possible to form a semiconductor integrated circuit equipped with a protection element with the desired characteristics, regardless of the polarity of the ESD. Next, an example of a semiconductor integrated circuit including a reverse current prevention diode will be described.

The first embodiment is shown in Figure 6. In the example shown in Figure 6, the reverse current prevention diode is configured with an N-type DMOS transistor, the same as the protected element. The structures of the protected element (NMOS transistor) and the protection element (bidirectional thyristor) are as described above.

The reverse current prevention diode of this embodiment is configured by connecting the P-type diffusion region 7c and the P-type diffusion region 6c to the connection point between the source S of the protected element (NMOS transistor) and the third terminal T3, and connecting the N-type diffusion region 13 and the N-type diffusion region 5a to the second terminal T2, thereby making it possible to form a semiconductor integrated circuit equipped with a reverse current prevention diode 11 whose anode is connected to the source S of the NMOS transistor described in FIG. 4 and whose cathode is connected to the second terminal T2.

The second embodiment is shown in Figure 7. In this embodiment, the reverse current prevention diode is composed of an N-type region and a P-type substrate that are formed at the same time as the diffusion region that constitutes the NMOS transistor of the protected element. The structures of the protected element (NMOS transistor) and the protection element (bidirectional thyristor) are as described above.

The reverse current prevention diode of this embodiment is configured by connecting the element isolation region 3 (P-type diffusion region) to the connection point between the source S of the protected element (NMOS transistor) and the third terminal T3, and connecting the N-type diffusion region 13, the N-type diffusion region 5b, and the N-type buried layer 4a to the second terminal T2, thereby making it possible to form a semiconductor integrated circuit equipped with a reverse current prevention diode 11 whose anode is connected to the source S of the NMOS transistor described in FIG. 4 and whose cathode is connected to the second terminal T2.

Next, a third embodiment will be described. In the above description, a case where one bidirectional thyristor is connected as a protection element has been described. Figure 8 shows a semiconductor integrated circuit of the third embodiment, and shows an example where two bidirectional thyristors are connected in series as a protection element. The semiconductor integrated circuit shown in Figure 8 is an example where two bidirectional thyristors are connected in series in the semiconductor integrated circuit described in Figure 4.

With this configuration, the trigger voltage and snapback holding voltage are doubled compared to when one bidirectional thyristor is used as a protection element, and the NMOS transistor can be protected by passing the ESD current through the bidirectional thyristor.

In this embodiment, the reverse current prevention diode 11 can also adopt the structure described in Figures 6 and 7.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments. For example, the reverse current prevention diode is not limited to the structure of the above embodiments. Furthermore, the number of bidirectional thyristors connected in series is not limited to two.

1: P-type substrate, 2: N-type epitaxial layer, 3: element isolation region, 4, 4a: N-type buried layer, 5, 5a, 5b: N-type diffusion region, 6a, 6b, 6c: P-type diffusion region, 7a, 7b, 7c: P-type diffusion region, 8a, 8b: N-type diffusion region, 9: backflow prevention diode, 10: parasitic transistor, 11: backflow prevention diode, 12: parasitic diode, 13: N-type diffusion region

Claims (3)

an NMOS transistor having a gate to which a control signal is input and a drain connected to a first terminal;
a bidirectional electrostatic discharge protection element including a first bipolar transistor and a second bipolar transistor having collectors connected in common and emitters connected to the first terminal or the second terminal, respectively, and a third bipolar transistor having a base connected to the commonly connected collectors of the first bipolar transistor and the second bipolar transistor, one of a bidirectional emitter connected to the base of the first bipolar transistor and the emitter of the first bipolar transistor via a resistor element, and the other of the bidirectional emitter connected to the base of the second bipolar transistor and the emitter of the second bipolar transistor via a resistor element,
a diode having an anode connected to the source of the NMOS transistor and a cathode connected to the second terminal;
a third terminal is connected to the connection point between the source of the NMOS transistor and the anode of the diode. On a P-type substrate,
an NMOS transistor having a gate to which a control signal is input and a drain connected to a first terminal;
a bidirectional electrostatic discharge protection element including a first bipolar transistor and a second bipolar transistor having collectors connected in common and emitters connected to the first terminal or the second terminal, respectively, and a third bipolar transistor having a base connected to the commonly connected collectors of the first bipolar transistor and the second bipolar transistor, one of a bidirectional emitter connected to the base of the first bipolar transistor and the emitter of the first bipolar transistor via a resistor element, and the other of the bidirectional emitter connected to the base of the second bipolar transistor and the emitter of the second bipolar transistor via a resistor element,
a diode having an anode connected to the source of the NMOS transistor and a cathode connected to the second terminal;
a third terminal connected to the P-type substrate is connected to a connection point between the source of the NMOS transistor and the anode of the diode. 3. The semiconductor integrated circuit according to claim 1,
a plurality of bidirectional electrostatic discharge protection elements connected in series between the first terminal and the second terminal of the semiconductor integrated circuit;

Images