JP7568621B2 - Semiconductor device and method for manufacturing the same - Google Patents

Description

The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

The front end of mobile communication terminals such as mobile phones is equipped with a radio frequency switch (RF-SW) that handles radio frequency (RF) electrical signals.

In such high-frequency switches, in order to reduce the loss of electrical signals passing through them, it is desirable to reduce the resistance of the field effect transistor (FET) in the on-state (also called on-resistance) and the capacitance of the FET in the off-state (also called off-capacitance). In other words, in high-frequency switches, it is desirable to reduce the product of the on-resistance and the off-capacitance (Ron*Coff), and various studies are being conducted (see, for example, Patent Document 1).

JP 2015-207640 A

Therefore, it is desirable to reduce the product of on-resistance and off-capacitance in semiconductor devices such as field-effect transistors used in high-frequency switches.

Therefore, it is desirable to provide a semiconductor device and a method for manufacturing a semiconductor device that can further reduce the off-capacitance.

A semiconductor device according to one embodiment of the present disclosure comprises a gate electrode, a semiconductor layer having a source region and a drain region with the gate electrode between them, contact plugs respectively provided on the source region and the drain region, a first metal layered on each of the contact plugs, a first low dielectric constant region provided between each of the first metals in the in-plane direction of the semiconductor layer and in at least any region below the lower surface of the first metal in the stacking direction of the semiconductor layer, and a second low dielectric constant region provided between the contact plug and the gate electrode in the in-plane direction and in at least any region below the first low dielectric constant region in the stacking direction, the second low dielectric constant region being provided in a planar region at least partially different from the planar region in which the first low dielectric constant region is provided.

A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of forming a gate electrode on an upper surface side of a semiconductor layer, forming a source region and a drain region in the semiconductor layer with the gate electrode between them, forming contact plugs on each of the source region and the drain region, stacking a first metal on each of the contact plugs, forming a first low dielectric constant region between each of the first metals in the in-plane direction of the semiconductor layer and in at least any region below the lower surface of the first metal in the stacking direction of the semiconductor layer, and forming a second low dielectric constant region between the contact plug and the gate electrode in the in-plane direction and in at least any region below the first low dielectric constant region in the stacking direction, and the second low dielectric constant region is formed in a planar region at least partially different from the planar region in which the first low dielectric constant region is formed.

According to a semiconductor device and a method for manufacturing a semiconductor device according to one embodiment of the present disclosure, a first low dielectric constant region is provided between each of the first metals in the in-plane direction of the semiconductor layer and in at least any region below the lower surface of the first metal in the stacking direction of the semiconductor layer, and a second low dielectric constant region is provided between the contact plug and the gate electrode in the in-plane direction and in at least any region below the first low dielectric constant region in the stacking direction, thereby reducing the dielectric constant of the space between the contact plug and the gate electrode.

FIG. 1 is a schematic diagram showing the configuration of a high-frequency switch having a 1:10 input/output port number. FIG. 1 is a schematic diagram showing the configuration of a high-frequency switch having a one-to-one input/output port number; 3 is a circuit diagram showing an equivalent circuit of the high-frequency switch shown in FIG. 2 . 3 is a circuit diagram showing an equivalent circuit when the high-frequency switch shown in FIG. 2 is in an on state. 3 is a circuit diagram showing an equivalent circuit when the high-frequency switch shown in FIG. 2 is in an off state. 1 is a plan view showing an overall configuration of a semiconductor device according to a first embodiment of the present disclosure; 7 is a vertical cross-sectional view showing a cross-sectional configuration of the semiconductor device according to the embodiment taken along line VII-VII in FIG. 6. FIG. 1 is a vertical cross-sectional view showing a schematic diagram of the off-capacity of a general field-effect transistor, divided into elements. FIG. 11 is a vertical cross-sectional view showing a layered structure of a semiconductor device according to a comparative example. 10 is a graph showing the results of simulating the magnitude of the external component Cex of the semiconductor device shown in FIG. 7 and the semiconductor device according to the comparative example shown in FIG. 9 . 8 is a schematic diagram showing a positional relationship in the Z stacking direction between a first low dielectric constant region, a second low dielectric constant region, and a multilayer wiring portion in the semiconductor device shown in FIG. 7; 8 is a schematic diagram showing a positional relationship in an XY plane between a first low dielectric constant region, a second low dielectric constant region, and a multilayer wiring portion in the semiconductor device shown in FIG. 7; 13 is a longitudinal sectional view showing a sectional configuration taken along line XV-XV in FIG. 12. 13 is a longitudinal sectional view showing a sectional configuration taken along line XVIA-XVIB in FIG. 12. 13 is a longitudinal cross-sectional view showing a cross-sectional configuration taken along line XVIIB-XVIIC in FIG. 12. 13 is a longitudinal sectional view showing a sectional configuration taken along line XVIIIC-XVIIID in FIG. 12. 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; 4 is a vertical cross-sectional view showing a process for manufacturing the semiconductor device according to the embodiment; FIG. 11 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device according to a second embodiment of the present disclosure. FIG. 11 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device according to a third embodiment of the present disclosure. FIG. 11 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 13 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 13 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device according to a sixth embodiment of the present disclosure. FIG. 13 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device according to a seventh embodiment of the present disclosure. 1 is a schematic diagram showing an example of the configuration of a wireless communication device to which the semiconductor device according to the first to seventh embodiments of the present disclosure is applied;

Below, an embodiment of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology of the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, and dimensional ratios of each component shown in each figure of the present disclosure are not limited to those shown in each figure.

The explanation will be given in the following order.
1. First embodiment 1.1. Configuration of high frequency switch 1.2. Configuration of semiconductor device 1.3. Manufacturing method of semiconductor device 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment 7. Seventh embodiment 8. Application example

1. First embodiment
(1.1. Configuration of High Frequency Switch)
First, the configuration of a high-frequency switch including a semiconductor device according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 5. Figure 1 is a schematic diagram showing the configuration of a high-frequency switch having a 1:10 ratio of input/output ports, and Figure 2 is a schematic diagram showing the configuration of a high-frequency switch having a 1:1 ratio of input/output ports.

A radio frequency switch is an electronic component used primarily for signal processing in the radio frequency (RF) band. Radio frequency switches are used, for example, in the front ends of mobile information terminals such as mobile phones. Depending on the number of input and output ports, radio frequency switches can have a variety of configurations, such as SPST (Single Pole Single Throw), SPDT (Single Pole Double Throw), SP3T, ... SPNT (N is a real number).

For example, the high frequency switch 1 shown in FIG. 1 is an example of an SP10T switch. The high frequency switch 1, which is an SP10T switch, has, for example, one pole connected to an antenna ANT and ten contacts, and can control which of the ten contacts is to be connected. Also, the high frequency switch 1A shown in FIG. 2 is an example of an SPST switch. The high frequency switch 1A, which is an SPST switch, has, for example, one pole connected to an antenna ANT and one contact, and can control the on or off of the one contact.

The high frequency switch can have a configuration other than that shown in Figures 1 and 2. Specifically, the high frequency switch can have a variety of configurations by combining the SPST switch circuits shown in Figure 2.

Next, the equivalent circuit of the high frequency switch 1A shown in Fig. 2 is shown in Fig. 3 to Fig. 5. Fig. 3 is a circuit diagram showing the equivalent circuit of the high frequency switch 1A shown in Fig. 2. Fig. 4 is a circuit diagram showing the equivalent circuit when the high frequency switch 1A shown in Fig. 2 is in the on state, and Fig. 5 is a circuit diagram showing the equivalent circuit when the high frequency switch 1A shown in Fig. 2 is in the off state.

3, the high frequency switch 1A, which is an SPST, includes, for example, a first port Port1 connected to an antenna ANT, a second port Port2 on the output side, a first switching element FET1, and a second switching element FET2. The first switching element FET1 is provided between the first port Port1 and ground, and the second switching element FET2 is provided between the first port Port1 and the second port Port2.

Such a high-frequency switch 1A can control the on/off state of the switch by applying control voltages Vc1 and Vc2 to the gates of the first switching element FET1 and the second switching element FET2 via a resistor.

When the high frequency switch 1A is in the on state, the second switching element FET2 is in a conductive state and the first switching element FET1 is in a non-conductive state, as shown in Fig. 4. When the high frequency switch 1A is in the off state, the first switching element FET1 is in a conductive state and the second switching element FET2 is in a non-conductive state, as shown in Fig. 5.

The first switching element FET1 and the second switching element FET2 are equivalent to a resistor in the conductive state and are equivalent to a capacitor in the non-conductive state. Therefore, the first switching element FET1 and the second switching element FET2 have a resistance called an on-resistance in the conductive state and a capacitance called an off-capacitance in the non-conductive state.

Here, the on-resistance and off-capacitance of the first switching element FET1 and the second switching element FET2 can be expressed as Ron/ _Wg1 , Ron/Wg2, Coff*Wg1, and Coff* _{Wg2 ,} respectively, using Ron [Ωmm] and Coff [fF/mm] per unit length of the field effect transistor and gate widths _Wg1 and _Wg2 [mm] of the field effect transistor. That is, in the field effect transistor, the on-resistance is inversely _proportional to the gate widths _Wg1 and _Wg2 , and the off-capacitance is proportional to the gate widths _Wg1 and _Wg2 .

Therefore, if the gate width Wg of a field effect transistor is increased to reduce losses due to on-resistance, losses due to off-capacitance will increase. Also, while the on-resistance of a field effect transistor does not depend on the signal frequency, the off-capacitance increases as the signal frequency increases. Therefore, in high-frequency switches that handle high-frequency signals, losses due to off-capacitance will be even greater.

Therefore, in order to reduce loss in field effect transistors used in high frequency switches, it is important to reduce both Ron and Coff per unit length, i.e., to reduce the product Ron * Coff.

The technology disclosed herein has been made in consideration of the above circumstances. The technology disclosed herein reduces the on-resistance and off-capacitance of a field-effect transistor or other semiconductor device by reducing the parasitic capacitance of the semiconductor device. The technology disclosed herein can be suitably used in high-frequency switches provided in electronic devices that handle high-frequency signals.

(1.2. Configuration of Semiconductor Device)
Next, the configuration of the semiconductor device according to the first embodiment of the present disclosure will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is a plan view showing the overall configuration of the semiconductor device according to the present embodiment.

As shown in Fig. 6, the semiconductor device 10 according to this embodiment includes, for example, a gate electrode 20, a source electrode 30S, and a drain electrode 30D provided on a semiconductor layer (not shown). Note that the gate electrode 20 is shaded in Fig. 6.

The semiconductor device 10 is, for example, a field effect transistor for a high-frequency device constituting the first switching element FET1 or the second switching element FET2 of the high-frequency switch 1A shown in Figure 3.

The gate electrode 20 has a multi-finger structure having multiple finger portions 21 extending in one direction and connecting portions 22 connecting the multiple finger portions 21 to each other. The gate width Wg of the field effect transistor used in the high frequency switch is larger than that of the field effect transistor used in the logic circuit, for example, hundreds of μm to several mm, in order to reduce loss. The length (finger length) L21 of the finger portion 21 is, for example, several tens of μm. The connecting portions 22 are connected to a gate contact (not shown).

In the following description, the direction in which the finger portion 21 of the gate electrode 20 extends is referred to as the Y direction. The direction perpendicular to the Y direction and in which the connecting portion 22 extends is referred to as the X direction. Furthermore, the direction perpendicular to both the X direction and the Y direction (i.e., the direction perpendicular to the surface of the semiconductor layer, not shown) is referred to as the Z direction.

Similar to the gate electrode 20, the source electrode 30S has finger portions 31S extending in one direction (e.g., the Y direction) and a connecting portion 32S that connects multiple finger portions 31S and is connected to a source contact (not shown).

Similar to the gate electrode 20, the drain electrode 30D has a finger portion 31D extending in one direction (e.g., the Y direction) and a connecting portion 32D that connects multiple finger portions 31D and is connected to a drain contact (not shown).

The finger portion 21 of the gate electrode 20, the finger portion 31S of the source electrode 30S, and the finger portion 31D of the drain electrode 30D are arranged inside an active area AA that is activated by introducing conductive impurities. Specifically, the finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D are arranged alternately between each of the finger portions 21 of the gate electrode 20. On the other hand, the connecting portion 22 of the gate electrode 20, the connecting portion 32S of the source electrode 30S, and the connecting portion 32D of the drain electrode 30D are arranged in an element isolation region (not shown) provided outside the active area AA.

Next, the cross-sectional configuration of the semiconductor device 10 according to this embodiment will be described with reference to Figure 7. Figure 7 is a longitudinal cross-sectional view showing the cross-sectional configuration taken along line VII-VII in Figure 6. Figure 7 shows a cross-sectional configuration including one of the finger portions 21 of the gate electrode 20, finger portions 31S of the source electrode 30S arranged on both sides of the finger portion 21, and finger portions 31D of the drain electrode 30D.

As shown in FIG. 7, the semiconductor device 10 includes, for example, the above-mentioned gate electrode 20, a semiconductor layer 50, contact plugs 60S, 60D, a first metal M1 including the above-mentioned source electrode 30S and drain electrode 30D, a first low dielectric constant region 70, and a second low dielectric constant region 71.

The gate electrode 20 is provided on the semiconductor layer 50 via a gate insulating film 23. The gate electrode 20 may be made of polysilicon having a thickness of 100 nm to 200 nm, for example. The gate insulating film 23 may be made of silicon oxide (SiO _x ) having a thickness of 5 nm to 15 nm, for example.

The semiconductor layer 50 may be made of a semiconductor such as silicon (Si). The semiconductor layer 50 has a source region 50S and a drain region 50D made of first conductivity type (n+) silicon on both sides of the gate electrode 20. Low-resistance regions 51S and 51D made of higher-concentration first conductivity type (n++) silicon or silicide are provided on the surface side of the source region 50S and the drain region 50D for connection with the contact plugs 60S and 60D. Furthermore, extension regions 52S and 52D made of low-concentration first conductivity type (n-) silicon are provided between the source region 50S and the gate electrode 20, and between the drain region 50D and the gate electrode 20.

Here, the semiconductor layer 50 is provided on a support substrate 53 via, for example, a buried oxide film 54. The support substrate 53 may be made of, for example, a high-resistance silicon (Si) substrate, and the buried oxide film 54 may be made of, for example, silicon oxide (SiO _x ). That is, the support substrate 53, the buried oxide film 54, and the semiconductor layer 50 may form a so-called SOI (Silicon On Insulator) substrate 55.

In the above, the case where the support substrate 53 of the SOI substrate 55 is a high-resistance silicon substrate has been described, but the technology according to the present disclosure is not limited to the above example. The support substrate 53 may be a sapphire substrate. In such a case, the SOI substrate 55 can constitute a so-called SOS (Silicon On Sapphire) substrate. Since the sapphire substrate has insulating properties, the field effect transistor formed on the SOS substrate exhibits characteristics closer to those of a compound-based field effect transistor such as GaAs. In addition, the technology according to the present disclosure is not limited to the case where the support substrate 53 is an SOI substrate or an SOS substrate, but can also be applied to the case where the support substrate 53 is a bulk silicon substrate.

The contact plugs 60S, 60D are provided on the low resistance regions 51S, 51D on the surfaces of the source region 50S and the drain region 50D. The contact plugs 60S, 60D can be formed, for example, by stacking a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer in this order from the semiconductor layer 50 side. The titanium layer is provided to reduce the contact resistance between the contact plugs 60S, 60D and the underlying low resistance regions 51S, 51D. The titanium nitride layer is provided as a barrier metal that suppresses the diffusion of silicon, etc. from the semiconductor layer 50 to the tungsten layer.

The first metal M1 includes, for example, a source electrode 30S provided on the contact plug 60S and a drain electrode 30D provided on the contact plug 60D. The first metal M1 may be composed of aluminum (Al) having a thickness of, for example, 500 nm to 1000 nm.

The first low dielectric constant region 70 is provided, for example, in at least one region between the first metals M1 in the XY in-plane direction of the semiconductor layer 50 and below the lower surface of the first metal M1 in the Z stacking direction of the semiconductor layer 50. Specifically, the first low dielectric constant region 70 is provided in a region above the gate electrode 20, between the source electrode 30S and the drain electrode 30D in the XY in-plane direction of the semiconductor layer 50 and below the lower surface of the first metal M1 in the Z stacking direction of the semiconductor layer 50.

The first low dielectric constant region 70 may be provided continuously in the Z stacking direction up to a region further above the above-mentioned region. Specifically, the first low dielectric constant region 70 may be provided in a region between each of the first metals M1 in the XY in-plane direction of the semiconductor layer 50 and between the lower surface and the upper surface of the first metal M1 in the Z stacking direction. The first low dielectric constant region 70 may be provided in a region between each of the first metals M1 in the XY in-plane direction of the semiconductor layer 50 and above the upper surface of the first metal M1 in the Z stacking direction.

The second low dielectric constant region 71 is provided in at least one region between each of the contact plugs 60S, 60D and the gate electrode 20 in the XY in-plane direction of the semiconductor layer 50, and below the first low dielectric constant region 70 in the Z stacking direction of the semiconductor layer 50. Specifically, the second low dielectric constant region 71 is provided laterally on both side surfaces of the gate electrode 20 in the XY in-plane direction of the semiconductor layer 50. The second low dielectric constant region 71 may be provided continuously with the first low dielectric constant region 70, or may be provided separately from the first low dielectric constant region 70.

At least a portion of the second low dielectric constant region 71 is provided in a region different from the region in which the first low dielectric constant region 70 is provided when the semiconductor layer 50 is viewed in a plane from the stacking direction Z. Specifically, at least a portion of the second low dielectric constant region 71 is provided in a region on the periphery of the region in which the first low dielectric constant region 70 is provided in the XY in-plane direction of the semiconductor layer 50. This allows the semiconductor device 10 to be configured with the first low dielectric constant region 70 and the second low dielectric constant region 71 having a more complex shape.

Here, the off capacitance of a field effect transistor will be described with reference to Figure 8. Figure 8 is a vertical cross-sectional view showing the off capacitance of a typical field effect transistor 11, broken down into individual elements. In Figure 8, components corresponding to those of the semiconductor device 10 shown in Figure 7 are given the same reference numerals.

As shown in FIG. 8, the off-capacitance of a field-effect transistor 11 having a typical structure includes an intrinsic component Cin that occurs in the source region 50S, the drain region 50D, and the SOI substrate 55, etc., and an extrinsic component Cex that occurs in the gate electrode 20, the contact plugs 60S, 60D, the first metal M1, etc.

For example, the internal component Cin includes capacitances Cssub, Cdsub occurring between the source region 50S or drain region 50D and the supporting substrate 53, capacitances Csg, Cdg occurring between the source region 50S or drain region 50D and the gate electrode 20, capacitance Cds occurring between the source region 50S and the drain region 50D, and capacitances Csb, Cdb occurring between the source region 50S or drain region 50D and the lower part (body) of the semiconductor layer 50.

For example, the external component Cex may be a capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1, and a capacitance CMM1 generated between the first metal M1.

In order to reduce these off capacitances, it is particularly effective to reduce the external component Cex. The semiconductor device 10 according to the present embodiment can reduce the external component Cex of the off capacitance generated between the gate electrode 20, the contact plugs 60S, 60D, and the first metal M1 by providing the first low dielectric constant region 70 and the second low dielectric constant region 71, which have a lower relative dielectric constant than the surrounding regions, in the above-mentioned region. Therefore, the semiconductor device 10 can reduce the product of the on resistance and the off capacitance (Ron*Coff) by more effectively reducing the external component Cex. As a result, the semiconductor device 10 applied to a high-frequency switch can further reduce the loss of the high-frequency switch.

Here, Figure 10 shows the results of simulating the magnitude of the external component Cex of off-capacitance for the semiconductor device 10 shown in Figure 7 and the semiconductor device 12 of the comparative example shown in Figure 9.

9 is a vertical cross-sectional view showing the cross-sectional configuration of the semiconductor device 12 according to the comparative example. As shown in FIG. 9, the semiconductor device 12 according to the comparative example is different from the semiconductor device 10 according to the present embodiment in that the second low dielectric constant region is not provided between each of the contact plugs 60S, 60D and the gate electrode 20 in the XY in-plane direction of the semiconductor layer 50 and below the first low dielectric constant region 70 in the Z stacking direction of the semiconductor layer 50. That is, the semiconductor device 12 according to the comparative example is different from the semiconductor device 10 according to the present embodiment in that the same first low dielectric constant region 70 is provided, but the second low dielectric constant region 71 is not provided on both sides of the gate electrode 20 in the XY in-plane direction of the semiconductor layer 50.

Figure 10 shows the simulation results of the external component Cex in the semiconductor device 10 according to this embodiment as an example, and shows the simulation results of the external component Cex in the semiconductor device 12 according to the comparative example as a comparative example. As shown in Figure 10, it can be seen that the magnitude of the external component Cex in the example is reduced relative to the magnitude of the external component Cex in the comparative example. Therefore, it can be seen that the semiconductor device 10 according to this embodiment can further reduce the off-capacitance by further providing the second low dielectric constant region 71.

Now, returning to Figure 7, we resume explaining the configuration of the semiconductor device 10 of this embodiment.

The semiconductor device 10 shown in FIG. 7 further includes at least one insulating film 80 provided on the semiconductor layer 50 so as to cover the gate electrode 20, and an opening P provided from the upper surface of the at least one insulating film 80 toward the upper surface of the gate electrode 20.

The opening P is provided in a planar region corresponding to the gate electrode 20 when at least one insulating film 80 is viewed in a plan view from the stacking direction Z. Since the opening P is provided between the source electrode 30S and the drain electrode 30D, the opening width WP of the opening P is, for example, about 100 nm to 1000 nm.

The first low dielectric constant region 70 is preferably provided inside such an opening P. The second low dielectric constant region 71 is preferably provided in spatial continuity with the opening P, and is preferably provided in spatial continuity with the first low dielectric constant region 70 provided inside the opening P. The first low dielectric constant region 70 and the second low dielectric constant region 71 may be provided so that the centers of the regions coincide in either the X direction or the Y direction, or may be provided in regions independent of each other.

It is preferable that the at least one insulating film 80 is composed of a plurality of insulating films each formed of a material having a different etching rate. In this way, the at least one insulating film 80 can control the etching stop position of the opening P with high precision in the manufacturing process described later by using the difference in etching rate of each insulating film.

Specifically, at least one insulating film 80 may be composed of a first insulating film 81, a second insulating film 82, and a third insulating film 83.

The first insulating film 81 is provided to cover the surface of the gate electrode 20 (i.e., the upper surface and side surfaces of the gate electrode 20) and the upper surface of the semiconductor layer 50.

The second insulating film 82 is provided so as to cover the surface of the first insulating film 81. However, the second insulating film 82 is not provided on the surface of the first insulating film 81 provided on the surface of the gate electrode 20 (i.e., the upper surface and side surface of the gate electrode 20), and the first insulating film 81 is exposed to the second low dielectric constant region 71. This is because, as will be explained in the manufacturing process described later, in the semiconductor device 10, the second insulating film 82 is removed to form the second low dielectric constant region 71 between the first insulating film 81 and the third insulating film 83.

The third insulating film 83 is provided between the surface of the second insulating film 82 and the lower surface of the first metal M1. The third insulating film 83 is provided so as to embed the gate electrode 20, and forms a second low dielectric constant region 71 between the third insulating film 83 and the first insulating film 81.

Here, the second insulating film 82 is preferably made of a material having an etching rate different from that of the material constituting the first insulating film 81 and the third insulating film 83. For example, the second insulating film 82 is preferably made of a silicon nitride (SiN) film, and the first insulating film 81 and the third insulating film 83 are preferably made of a silicon oxide (SiO _x ) film having an etching rate different from that of silicon nitride (SiN). According to this, in the semiconductor device 10, the second insulating film 82 is made to function as an etching stopper layer, so that an opening P that penetrates the third insulating film 83 and reaches the upper surface of the second insulating film 82 can be easily formed. In addition, the second low dielectric constant region 71 can be easily formed below the opening P by selectively removing the second insulating film 82 by performing isotropic etching through the opening P.

Furthermore, the at least one insulating film 80 may further include a fourth insulating film 84. Specifically, the fourth insulating film 84 may be provided so as to cover the upper surface of the third insulating film 83 and the surface of the first metal M1 (i.e., the upper surface and side surfaces of the first metal M1). In such a case, the opening P is provided so as to penetrate from the upper surface of the fourth insulating film 84 through the fourth insulating film 84 and the third insulating film 83. The fourth insulating film 84 may be formed of, for example, a silicon oxide (SiO _x ) film.

Furthermore, the at least one insulating film 80 may further include a fifth insulating film 85. Specifically, the fifth insulating film 85 may be provided on the fourth insulating film 84 and close the upper part of the opening P. The fifth insulating film 85 may be composed of, for example, a silicon oxide (SiO _x ) film.

Furthermore, a sixth insulating film 86 made of, for example, a silicon oxide (SiO _x ) film may be provided on the fifth insulating film 85 as necessary.

In the semiconductor device 10 according to this embodiment, an air gap AG (air gap) can be provided as the first low dielectric constant region 70 in at least a portion of the inside of the opening P. For example, the air gap AG of the first low dielectric constant region 70 may be provided below the first low dielectric constant region 70 in spatial continuity with a second low dielectric constant region 71 similarly formed as an air gap AG.

The first low dielectric constant region 70 and the second low dielectric constant region 71 are not particularly limited in terms of their internal configurations, as long as they have a lower dielectric constant than the silicon oxide (SiO _x : dielectric constant 3.9) film constituting the third insulating film 83 and the fourth insulating film 84. For example, the first low dielectric constant region 70 and the second low dielectric constant region 71 may be configured to include air (dielectric constant 1.0) in the gap AG, or may be configured so that the gap AG is a vacuum. The first low dielectric constant region 70 and the second low dielectric constant region 71 may be configured by filling a part or the whole of the gap AG with a low dielectric constant material. The low dielectric constant material refers to, for example, a dielectric material having a dielectric constant of 3 or less.

When the first low dielectric constant region 70 and the second low dielectric constant region 71 are formed by a gap AG, the upper part of the gap AG is closed by the fifth insulating film 85, so that the gap AG is hermetically sealed by the fifth insulating film 85. When the gap AG is closed, a part of the fifth insulating film 85 may get inside the gap AG. In such a case, the fifth insulating film 85 covers a part of the side or bottom surface of the opening P.

In the XY in-plane direction, the width in which the first low dielectric constant region 70 and the second low dielectric constant region 71 are formed is not particularly limited. However, the width in which the first low dielectric constant region 70 is formed may be smaller than the width of the first insulating film 81 provided on the surface of the gate electrode 20, for example, in a cross section cut in the stacking direction Z. Specifically, the width W70 of the first low dielectric constant region 70 may be smaller than the width W81 of the first insulating film 81 covering the upper surface and side surfaces of the gate electrode 20.

When the second insulating film 82 is formed on the surface of the first insulating film 81 on the upper surface and side surface of the gate electrode 20, the width W70 of the first low dielectric constant region 70 may be smaller than the width of the first insulating film 81 and the second insulating film 82 covering the upper surface and side surface of the gate electrode 20. Also, when the first insulating film 81 is not formed on the upper surface and side surface of the gate electrode 20, the width W70 of the first low dielectric constant region 70 may be smaller than the width of the gate electrode 20.

In addition, the width in which the second low dielectric constant region 71 is formed may be larger than the width of the first insulating film 81 provided on the surface of the gate electrode 20 in a cross section cut in the stacking direction Z. Specifically, the width W71 of the second low dielectric constant region 71 may be larger than the width W81 of the first insulating film 81 covering the upper surface and side surfaces of the gate electrode 20 and smaller than the width between the contact plugs 60S and 60D.

When the second insulating film 82 is formed on the surface of the first insulating film 81 on the upper surface and side surface of the gate electrode 20, the width W71 of the second low dielectric constant region 71 may be larger than the width of the first insulating film 81 and the second insulating film 82 covering the upper surface and side surface of the gate electrode 20. Also, when the first insulating film 81 is not formed on the upper surface and side surface of the gate electrode 20, the width W71 of the second low dielectric constant region 71 may be larger than the width of the gate electrode 20.

11 and 12, the positional relationship between the first low dielectric constant region 70 and the second low dielectric constant region 71 in the semiconductor device 10 according to this embodiment and the multi-layer wiring section 90 will be described. The multi-layer wiring section 90 is provided with wiring that transmits signals extracted from each electrode of the semiconductor device 10.

Figure 11 is a schematic diagram showing the positional relationship in the Z stacking direction between the first low dielectric constant region 70 and the second low dielectric constant region 71 in the semiconductor device 10 shown in Figure 7 and the multilayer wiring section 90.

11, the multi-layer wiring section 90 includes, for example, a first wiring layer 91 and a second wiring layer 92. The first wiring layer 91 is provided in the same layer as the first metal M1 including, for example, the source electrode 30S and the drain electrode 30D. The second wiring layer 92 is provided above the first wiring layer 91 and is connected to the first wiring layer 91 via, for example, a contact plug 93.

The first low dielectric constant region 70 and the second low dielectric constant region 71 in the semiconductor device 10 are provided inside the element region AA1 of the active region AA activated by introducing conductive impurities into the semiconductor layer 50. On the other hand, the multilayer wiring section 90 is provided inside the active region AA and inside the wiring region AA2 outside the element region AA1. The element region AA1 and the wiring region AA2 are separated by an element isolation layer 100 formed by, for example, a shallow trench isolation (STI) method.

In addition, the first low dielectric constant region 70 and the second low dielectric constant region 71 do not have to be provided between each of the first wiring layers 91 and each of the second wiring layers 92 of the multilayer wiring section 90. In other words, the first low dielectric constant region 70 and the second low dielectric constant region 71 are provided at least in the semiconductor device 10 within the element region AA1 in the active region AA.

Figure 12 is a schematic diagram showing the positional relationship in the XY plane between the first low dielectric constant region 70 and the second low dielectric constant region 71 in the semiconductor device 10 shown in Figure 7 and the multilayer wiring section 90.

12, inside the active area AA, the semiconductor device 10, the first low dielectric constant area 70, and the second low dielectric constant area 71 are provided. On the other hand, in the element isolation area AB outside the active area AA, instead of the semiconductor layer 50, an element isolation layer 100 formed by the STI method is provided over the entire surface, and a gate contact GC is provided.

More specifically, the active area AA includes finger portions 21 of the gate electrode 20, finger portions 31S of the source electrode 30S, and finger portions 31D of the drain electrode 30D.

The finger portion 21 of the gate electrode 20 is provided extending in one direction (for example, the Y direction). The finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D are provided on both sides of the finger portion 21 of the gate electrode 20, extending in a direction parallel to the extension direction of the finger portion 21 of the gate electrode 20.

The contact plugs 60S, 60D extend in a direction parallel to the extension direction of the finger portion 21 of the gate electrode 20 and are provided below the finger portion 31S of the source electrode 30S and the finger portion 31D of the drain electrode 30D.

The first low dielectric constant region 70 extends in a direction parallel to the extension direction of the finger portion 21 of the gate electrode 20 and is provided on the finger portion 21 of the gate electrode 20. The second low dielectric constant region 71 extends in a direction parallel to the extension direction of the finger portion 21 of the gate electrode 20 and is provided on the side of the finger portion 21 of the gate electrode 20. That is, when the semiconductor layer 50 is viewed in a plan view from the Z stacking direction, the first low dielectric constant region 70 is provided in a region overlapping with the finger portion 21 of the gate electrode 20 in the XY in-plane direction, and the second low dielectric constant region 71 is provided in regions on both sides of the finger portion 21 of the gate electrode 20 in the XY in-plane direction.

In the element isolation region AB, a connection portion 22 of the gate electrode 20, a connection portion 32S of the source electrode 30S, and a connection portion 32D of the drain electrode 30D are provided.

The connection portion 22 of the gate electrode 20 is connected to the gate contact GC. The connection portion 32S of the source electrode 30S is connected to a source contact (not shown), and the connection portion 32D of the drain electrode 30D is connected to a drain contact (not shown).

Now, with reference to Figures 13 to 16, the cross-sectional configurations in the Z stacking direction of each configuration shown in Figure 12 will be described. Figure 13 is a vertical cross-sectional view showing the cross-sectional configuration taken along line XV-XV in Figure 12. Figure 14 is a vertical cross-sectional view showing the cross-sectional configuration taken along line XVIA-XVIB in Figure 12, Figure 15 is a vertical cross-sectional view showing the cross-sectional configuration taken along line XVIIB-XVIIC in Figure 12, and Figure 16 is a vertical cross-sectional view showing the cross-sectional configuration taken along line XVIIIC-XVIID in Figure 12.

12, the gate contact GC can be formed by sequentially providing a connection portion 22 of the gate electrode 20, a gate contact plug 24, and a gate contact layer 25 on an element isolation layer 100 formed by the STI method. The gate contact plug 24 has a similar configuration to the contact plugs 60S, 60D, and is provided in the same layer as the contact plugs 60S, 60D. The gate contact layer 25 has a similar configuration to the source electrode 30S and the drain electrode 30D, and is provided in the same layer as the first metal M1 including the source electrode 30S and the drain electrode 30D.

As shown in FIGS. 12 to 16, the first low dielectric constant region 70 is preferably provided so as to avoid the gate contact GC. This is because, if the first low dielectric constant region 70 is provided on the connection portion 22 of the gate contact GC, it is difficult to provide the gate contact plug 24 on the connection portion 22. If the first low dielectric constant region 70 is not provided on the connection portion 22 of the gate contact GC, the second low dielectric constant region 71 is also not provided. Similarly, the gate contact GC is preferably covered with at least one or more layers of insulating film 80 (i.e., the first insulating film 81 to the sixth insulating film 86) like the gate electrode 20. This makes it possible to protect the gate contact GC with at least one or more layers of insulating film 80 without exposing the gate contact GC, thereby maintaining the reliability of the gate contact GC.

(1.3. Manufacturing method of semiconductor device)
Next, a method for manufacturing the semiconductor device 10 according to this embodiment will be described with reference to Figures 17 to 29. Figures 17 to 29 are vertical cross-sectional views showing each process for manufacturing the semiconductor device 10.

17, an SOI substrate 55 is prepared by stacking a buried oxide film 54 and a semiconductor layer 50 on a support substrate 53. Next, an element isolation layer 100 is formed in the semiconductor layer 50 of the SOI substrate 55 by using the STI method, thereby defining an element area AA1 in the active area AA.

Next, as shown in FIG. 18, a gate electrode 20 is formed on the semiconductor layer 50 via a gate insulating film 23.

Specifically, for example, a thermal oxidation method is used to form an in-through film made of silicon oxide, and then well implantation of a second conductivity type impurity (for example, a p-type impurity such as boron (B) or aluminum (Al)) and channel implantation are performed in the active area AA, and the in-through film is then removed. Then, for example, a gate insulating film 23 made of silicon oxide is formed to a thickness of about 5 nm to 15 nm using a thermal oxidation method.

Next, a gate electrode material film (not shown) made of polysilicon is formed on the semiconductor layer 50 and the gate insulating film 23 to a thickness of about 100 nm to 200 nm using a CVD (Chemical Vapor Deposition) method. Next, the gate electrode material film is processed using photolithography and etching to form the gate electrode 20 on the upper surface of the semiconductor layer 50.

19, the gate electrode 20 and the offset spacer (not shown) are used as a mask to perform S/D IMPL implantation of a first conductivity type impurity (e.g., n-type impurity such as arsenic (As) or phosphorus (P)) to form extension regions 52S, 52D in the semiconductor layer 50 on both sides of the gate electrode 20. Next, sidewalls (not shown) are formed on both sides of the gate electrode 20, and S/D IMPL implantation of the first conductivity type impurity is performed again. This allows the source region 50S and the drain region 50D to be formed in the semiconductor layer 50 on both sides of the gate electrode 20. The sidewalls are removed after the source region 50S and the drain region 50D are formed.

Next, as shown in FIG. 20, a first insulating film 81 made of silicon oxide is formed on the surface of the gate electrode 20 and the upper surface of the semiconductor layer 50 to a thickness of approximately 10 nm to 100 nm using, for example, a CVD method.

21, a second insulating film 82 made of silicon nitride, which has a different etching rate from the silicon oxide that forms the first insulating film 81, is formed on the surface of the first insulating film 81 to a thickness of about 10 nm to 100 nm, for example, by using a CVD method. After that, a third insulating film 83 made of silicon oxide is formed on the second insulating film 82 to a thickness of about 500 nm to 1500 nm, for example, by using a CVD method.

22, the third insulating film 83, the second insulating film 82, and the first insulating film 81 are removed by photolithography and etching at positions corresponding to the source region 50S and the drain region 50D. This forms a contact hole H1 that exposes the source region 50S and the drain region 50D. The contact hole H1 is provided extending in a direction parallel to the extension direction of the finger portion 21 of the gate electrode 20, as shown in FIG.

Next, as shown in FIG. 23, implantation Cnt IMPL of a high concentration of a first conductivity type impurity (e.g., an n-type impurity such as arsenic (As) or phosphorus (P)) is performed into the source region 50S and the drain region 50D through the contact hole H1, thereby forming low resistance regions 51S, 51D in the semiconductor layer 50.

24, a titanium layer, a titanium nitride layer, and a tungsten layer are sequentially stacked in the contact hole H1 to form contact plugs 60S, 60D having a stacked structure. This allows the contact plugs 60S, 60D to be electrically connected to the source region 50S and the drain region 50D via the low resistance regions 51S, 51D. The contact plugs 60S, 60D are provided extending in a direction parallel to the extension direction of the finger portions 21 of the gate electrode 20 as shown in FIG.

25, a source electrode 30S and a drain electrode 30D made of aluminum (Al) are formed as a first metal M1 on the contact plugs 60S and 60D. The finger portions 31S of the source electrode 30S and the finger portions 31D of the drain electrode 30D are provided extending in a direction parallel to the extension direction of the finger portions 21 of the gate electrode 20 as shown in FIG.

Next, as shown in FIG. 26, a fourth insulating film 84 made of silicon oxide is formed on the upper surface of the third insulating film and on the surface of the first metal M1, for example, by using a CVD method.

Next, as shown in FIG. 27, an opening P is formed that penetrates the fourth insulating film 84 and the third insulating film 83 and exposes the second insulating film 82.

Specifically, first, photolithography is used to pattern the low dielectric constant region forming resist 65. Then, the fourth insulating film 84 and a portion of the third insulating film 83 are removed by dry etching using the patterned low dielectric constant region forming resist 65 as a mask to form the opening P. The etching to form the opening P is performed by highly anisotropic dry etching. By using such highly anisotropic etching, it is possible to form an opening P with a high aspect ratio in the desired region with high precision.

Here, the opening P is provided in the region between the first metal M1 in the XY plane direction of the semiconductor layer 50. Specifically, the opening P is provided in the region between the source electrode 30S and the drain electrode 30D (i.e., above the gate electrode 20). The opening width WP of the opening P is, for example, about 100 nm to 1000 nm. In forming the opening P, the second insulating film 82 functions as an etching stopper, so that the etching of the opening P proceeds to the fourth insulating film 84 made of silicon oxide and the third insulating film 83, and stops at the upper surface of the second insulating film 82. The void AG inside the opening P formed in this process becomes the first low dielectric constant region 70.

28, while leaving the low dielectric constant region forming resist 65, a portion of the second insulating film 82 is etched through the opening P to form a gap AG that is continuous with the gap AG provided between the first metals M1 on the side of the gate electrode 20. The etching to remove a portion of the second insulating film 82 is performed using isotropic dry etching or wet etching. By using such isotropic etching, the second insulating film 82 provided on the upper surface and side surfaces of the gate electrode 20 can be efficiently etched, and the gap AG can be formed in a wider area.

In this process, the void AG formed by removing the second insulating film 82 becomes the second low dielectric constant region 71. That is, the void AG that becomes the first low dielectric constant region 70 is formed above the gate electrode 20, and the void AG that becomes the second low dielectric constant region 71 is formed to the side of the gate electrode 20, so that the semiconductor device 10 can further reduce the external component of the off capacitance.

29, after the resist 65 for forming the low dielectric constant region is peeled off, a fifth insulating film 85 made of silicon oxide is formed on the fourth insulating film 84, for example, by using a CVD method under conditions that provide low embedding ability into the void AG. In the CVD method under such conditions, the fifth insulating film 85 is deposited while overhanging the upper part of the opening P. According to this, before the inside of the opening P is filled with the fifth insulating film 85, the upper part of the opening P is blocked by the fifth insulating film 85, so that a hermetically sealed void AG is formed inside the opening P. At this time, the side surface of the opening P and the upper surface of the first insulating film 81 covering the gate electrode 20 may be covered with the fifth insulating film 85 that has entered the inside of the opening P.

The void AG has a lower dielectric constant than the silicon oxide (dielectric constant 3.9) that forms the third insulating film 83, the fourth insulating film 84, and the fifth insulating film 85, and therefore functions as the first low dielectric constant region 70 and the second low dielectric constant region 71. The inside of the void AG may be a vacuum, or air (dielectric constant 1.0) may be present. Alternatively, the inside of the void AG may be filled with a material that has a lower dielectric constant than the silicon oxide (dielectric constant 3.9) that forms the third insulating film 83, the fourth insulating film 84, and the fifth insulating film 85.

Through the above steps, a gap AG is provided in a region corresponding to a first low dielectric constant region 70 that is between the first metal M1 in the XY plane direction and includes at least any region below the lower surface of the first metal M1 in the Z-stacking method, and a second low dielectric constant region 71 that is between the contact plugs 60S, 60D and the gate electrode 20 in the XY plane direction and includes at least any region below the first low dielectric constant region 70 in the Z-stacking method. At this time, the gap AG in the first low dielectric constant region 70 and the gap AG in the second low dielectric constant region 71 are formed spatially continuous.

7 is formed on the fifth insulating film 85 as necessary. Note that, although not shown, it is also possible to form the second metal M2 and then the third metal M3 by sequentially forming a metal layer and an insulating film on the fifth insulating film 85 in the same manner as the first metal M1 and the fourth insulating film 84.

As described above, the semiconductor device 10 can reduce the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D, and the first metal M1, and the capacitance CMM1 between the gate electrode 20 and the contact plugs 60S, 60D, and the first metal M1, by providing the first low dielectric constant region 70 and the second low dielectric constant region 71 in the above-mentioned region. Therefore, the semiconductor device 10 can reduce the external component Cex of the off capacitance. As a result, the semiconductor device 10 can reduce the product of the on resistance and the off capacitance (Ron * Coff), which makes it possible to promote low loss, which is an important characteristic of a high-frequency switch.

In addition, in the semiconductor device 10, the first low dielectric constant region 70 may be further extended in the Z-stack direction into the region between the lower surface and the upper surface of the first metal M1, and into the region above the upper surface of the first metal M1. In such a case, the semiconductor device 10 can further reduce the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D, and the first metal M1, and the capacitance CMM1 generated between the gate electrode 20 and the contact plugs 60S, 60D, and the first metal M1.

Furthermore, the semiconductor device 10 is preferably configured by providing at least one or more insulating films 80, including insulating films each formed of a material with a different etching rate, on the semiconductor layer 50. This makes it possible for the semiconductor device 10 to control with high precision the etching stop positions of the openings P used to form the first low dielectric constant region 70 and the second low dielectric constant region 71, by using the difference in etching rate between the insulating films. Therefore, according to this embodiment, the semiconductor device 10 can be manufactured more stably and with high reliability.

Note that the embedding state of the fifth insulating film 85 in the opening P shown in the vertical cross-sectional view of Figure 7 etc., and the covering state on the side surface of the opening P and the upper surface of the first insulating film 81 covering the gate electrode 20 are merely examples and do not limit the structure of the semiconductor device 10 of this embodiment.

2. Second embodiment
Next, the configuration of a semiconductor device according to a second embodiment of the present disclosure will be described with reference to Fig. 30. Fig. 30 is a vertical cross-sectional view showing the cross-sectional configuration of a semiconductor device 10A according to this embodiment. Fig. 30 shows the cross-sectional configuration taken along line VII-VII in Fig. 6, similar to Fig. 7.

As shown in FIG. 30, the semiconductor device 10A of this embodiment differs from the semiconductor device 10 shown in FIG. 7 in that the range of isotropic etching of the second insulating film 82 performed through the opening P is expanded, thereby expanding the gap AG which becomes the first low dielectric constant region 70 and the second low dielectric constant region 71.

Specifically, in the semiconductor device 10A, the gap AG can be formed over a wider range by removing the first insulating film 81 covering the upper surface of the gate electrode 20 in addition to the second insulating film 82, and further removing the third insulating film 83 and the fourth insulating film 84 on the side surface of the opening P. This makes it possible for the semiconductor device 10A to further reduce the external component Cex of the off capacitance, including the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1, and the capacitance CMM1 generated between the first metal M1.

In the semiconductor device 10A according to this embodiment, since the opening width WP of the opening P is enlarged, a fifth insulating film 85 having a thickness thicker than that of the semiconductor device 10 shown in FIG. 7 may be deposited on the side and bottom surfaces of the opening P (i.e., the upper surface of the gate electrode 20). At this time, the fifth insulating film 85 deposited on the bottom surface of the opening P functions to protect the upper surface of the gate electrode 20 exposed inside the opening P by isotropic etching.

As mentioned in the first embodiment, the state of filling the opening P with the fifth insulating film 85 shown in FIG. 30, as well as the state of covering the side surface of the opening P and the upper surface of the gate electrode 20, are merely examples and do not limit the structure of the semiconductor device 10A according to this embodiment.

3. Third embodiment
Next, the configuration of a semiconductor device according to a third embodiment of the present disclosure will be described with reference to Fig. 31. Fig. 31 is a vertical cross-sectional view showing the cross-sectional configuration of a semiconductor device 10B according to this embodiment. Fig. 31 shows the cross-sectional configuration taken along line VII-VII in Fig. 6, similar to Fig. 7.

As shown in Figure 31, the semiconductor device 10B of this embodiment can maintain the width W70 of the gap AG that becomes the first low dielectric constant region 70 at the same level as that of the semiconductor device 10 shown in Figure 7, while allowing the gap AG that becomes the second low dielectric constant region 71 to be larger than that of the semiconductor device 10A shown in Figure 30.

Specifically, in semiconductor device 10B, the opening width of low dielectric constant region forming resist 65 used in forming opening P is narrowed to form opening P with a narrower opening width WP. In addition, semiconductor device 10B expands the range of isotropic etching of second insulating film 82 performed through opening P, and removes in addition to second insulating film 82, first insulating film 81 covering the upper surface and side surface of gate electrode 20, and further third insulating film 83 and fourth insulating film 84 on the side surface of opening P, thereby forming gap AG over a wider range.

The isotropic etching of the first insulating film 81, the second insulating film 82, the third insulating film 83, and the fourth insulating film 84 through the opening P is performed for a long time in order to expand the void AG, so the opening width WP of the opening P widens before and after the etching. In the semiconductor device 10B according to this embodiment, the opening P is formed with a narrow opening width WP in advance, so that it is possible to prevent the opening width WP of the opening P from widening excessively during the etching that forms the void AG, making it difficult to close the upper part of the opening P with the fifth insulating film 85.

In the semiconductor device 10B, the isotropic etching for forming the void AG is performed by controlling the amount of etching so that the semiconductor layer 50 is not exposed. Specifically, the isotropic etching for forming the void AG is performed by controlling the amount of etching so that the first insulating film 81 provided on the upper surface of the semiconductor layer 50 is not lost. This is because if the semiconductor layer 50 near the gate insulating film 23 is exposed or if the gate insulating film 23 is side-etched, the gate length and threshold voltage may vary significantly.

In the semiconductor device 10B, the gap AG can be formed over a wider range by removing the first insulating film 81 covering the upper surface and side surface of the gate electrode 20 in addition to the second insulating film 82, and further removing the third insulating film 83 and the fourth insulating film 84 on the side surface of the opening P. As a result, the semiconductor device 10B can further reduce the external component Cex of the off capacitance including the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1, and the capacitance CMM1 generated between the first metal M1.

In the semiconductor device 10B according to this embodiment, the opening width WP of the opening P is approximately the same as that of the semiconductor device 10 shown in FIG. 7, so that the thickness of the fifth insulating film 85 deposited on the side and bottom surfaces (i.e., the upper surface of the gate electrode 20) of the opening P can be made thin. As a result, the semiconductor device 10B can prevent the gap AG, which becomes the first low dielectric constant region 70 and the second low dielectric constant region 71, from being excessively filled with the fifth insulating film 85.

As mentioned in the first embodiment, the embedding state of the fifth insulating film 85 in the opening P shown in FIG. 31, as well as the covering state of the side surface of the opening P and the upper surface of the gate electrode 20, are merely examples and do not limit the structure of the semiconductor device 10B of this embodiment.

4. Fourth embodiment
Next, the configuration of a semiconductor device according to a fourth embodiment of the present disclosure will be described with reference to Fig. 32. Fig. 32 is a longitudinal sectional view showing the cross-sectional configuration of a semiconductor device 10C according to this embodiment. Fig. 32 shows the cross-sectional configuration taken along line VII-VII in Fig. 6, similar to Fig. 7.

As shown in FIG. 32, the semiconductor device 10C of this embodiment differs from the semiconductor device 10 shown in FIG. 7 in that a portion of the opening P is filled with a fifth insulating film 85, so that the first low dielectric constant region 70 and the second low dielectric constant region 71 are not spatially continuous but are isolated from each other.

Specifically, in the semiconductor device 10C, when forming the fifth insulating film 85 that closes the upper portion of the opening P, the fifth insulating film 85 is deposited by a CVD method under conditions of high embedding property, so that a large amount of the fifth insulating film 85 is deposited inside the opening P. As a result, the semiconductor device 10C can bond the fifth insulating film 85 deposited on the side and bottom surface (i.e., the upper surface of the first insulating film 81) of the opening P, and separate the first low dielectric constant region 70 and the second low dielectric constant region 71 from each other. As a result, the first low dielectric constant region 70 is provided above the gate electrode 20, and the second low dielectric constant region 71 is provided at a distance from each other so as to surround the side surface of the gate electrode 20.

Therefore, even with a configuration such as that of the semiconductor device 10C of this embodiment, like the semiconductor device 10 shown in FIG. 7, the semiconductor device 10C is capable of reducing the external component Cex of the off capacitance, including the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1, and the capacitance CMM1 generated between the first metal M1.

As mentioned in the first embodiment, the embedding state of the fifth insulating film 85 in the opening P shown in FIG. 32, and the covering state of the side surface of the opening P and the upper surface of the first insulating film 81 are merely examples and do not limit the structure of the semiconductor device 10C according to this embodiment.

<5. Fifth embodiment>
Next, the configuration of a semiconductor device according to a fifth embodiment of the present disclosure will be described with reference to Fig. 33. Fig. 33 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device 10D according to this embodiment. Fig. 33 shows a cross-sectional configuration taken along line VII-VII in Fig. 6, similar to Fig. 7.

As shown in FIG. 33, the semiconductor device 10D of this embodiment differs from the semiconductor device 10 shown in FIG. 7 in that the opening P is filled with a fifth insulating film 85, and thus the region corresponding to the first low dielectric constant region 70 is filled with the fifth insulating film 85.

Specifically, in the semiconductor device 10D, when forming the fifth insulating film 85 that closes the upper portion of the opening P, the fifth insulating film 85 is formed by a CVD method under conditions that provide high filling properties for the opening P, so that the region from the upper surface of the first insulating film 81 to the opening surface of the opening P is filled with the fifth insulating film 85. As a result, the opening P below the lower surface of the first metal M1 and above the upper surface of the first insulating film 81 is filled with the fifth insulating film 85. However, by forming the fifth insulating film 85 from a material having a lower dielectric constant than the third insulating film 83 and the fourth insulating film 84, the above region can function as the first low dielectric constant region 70, as in the semiconductor device 10 shown in FIG. 7. In addition, the second low dielectric constant region 71 is composed of a gap AG that surrounds the side surface of the gate electrode 20.

Therefore, even with a configuration such as that of the semiconductor device 10D of this embodiment, like the semiconductor device 10 shown in FIG. 7, the semiconductor device 10D is capable of reducing the external component Cex of the off capacitance, including the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1, and the capacitance CMM1 generated between the first metal M1.

As mentioned in the first embodiment, the embedded state of the fifth insulating film 85 in the opening P shown in FIG. 33 is merely an example and does not limit the structure of the semiconductor device 10D of this embodiment.

6. Sixth embodiment
Next, the configuration of a semiconductor device according to a sixth embodiment of the present disclosure will be described with reference to Fig. 34. Fig. 34 is a vertical cross-sectional view showing the cross-sectional configuration of a semiconductor device 10E according to this embodiment. Fig. 34 shows the cross-sectional configuration taken along line VII-VII in Fig. 6, similar to Fig. 7.

34, the semiconductor device 10E according to this embodiment is different from the semiconductor device 10D shown in FIG. 33 in that the fifth insulating film 85 is formed by applying a material having fluidity. Specifically, in the semiconductor device 10E, the fifth insulating film 85 is formed by applying SOG (Spin On Glass), which is a low dielectric film, or an organic resin film, or by applying an organic resin film, to close the upper portion of the opening P. Since SOG and organic resin have high fluidity, the region from the opening surface to the upper surface of the first insulating film 81 of the opening P can be filled with the fifth insulating film 85 more easily than by the CVD method.

As a result, the opening P below the lower surface of the first metal M1 and above the upper surface of the first insulating film 81 is filled with the fifth insulating film 85 made of SOG or organic resin, which is a low dielectric film, and can function as the first low dielectric constant region 70, similar to the semiconductor device 10 shown in Figure 7. The second low dielectric constant region 71 is formed of a gap AG surrounding the side surface of the gate electrode 20.

Therefore, even with a configuration such as that of the semiconductor device 10E of this embodiment, like the semiconductor device 10 shown in FIG. 7, the semiconductor device 10E is capable of reducing the external component Cex of the off capacitance, including the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1, and the capacitance CMM1 generated between the first metal M1.

As mentioned in the first embodiment, the embedded state of the fifth insulating film 85 in the opening P shown in FIG. 34 is merely an example and does not limit the structure of the semiconductor device 10E of this embodiment.

7. Seventh embodiment
Next, the configuration of a semiconductor device according to a seventh embodiment of the present disclosure will be described with reference to Fig. 35. Fig. 35 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor device 10F according to this embodiment. Fig. 35 shows the cross-sectional configuration taken along line VII-VII in Fig. 6, similar to Fig. 7.

As shown in FIG. 35, the semiconductor device 10F of this embodiment differs from the semiconductor device 10 shown in FIG. 7 in that it further includes a second metal M2 provided between the fourth insulating film 84 and the fifth insulating film 85, and a seventh insulating film 87 covering the surface of the second metal M2 and the upper surface of the fourth insulating film 84.

Specifically, in the semiconductor device 10F, the fourth insulating film 84 is provided by embedding the first metal M1 and the contact plug 61 provided on the upper surface of the first metal M1. A second metal M2 that connects to the first metal M1 via the contact plug 61 is provided on the fourth insulating film 84, and a seventh insulating film 87 is provided on the surface of the second metal M2 and the upper surface of the fourth insulating film. An opening P is formed from the upper surface of the seventh insulating film 87, and the upper part is closed by a fifth insulating film 85 provided on the seventh insulating film 87.

The materials constituting the second metal M2, the seventh insulating film 87, and the contact plug 61 are substantially the same as those constituting the first metal M1, the fourth insulating film 84, and the contact plugs 60S and 60D, respectively, and therefore will not be described here.

In the semiconductor device 10F according to this embodiment, the first low dielectric constant region 70 consisting of the gap AG can be extended between the second metal M2 provided on the first metal M1. As a result, the semiconductor device 10F can reduce the capacitance Cg between the gate electrode 20 and the second metal M2 and the capacitance CMM2 between the gate electrode 20 and the second metal M2, in addition to the capacitance CgM between the gate electrode 20 and the contact plugs 60S, 60D or the first metal M1 and the capacitance CMM1 between the first metal M1. Therefore, the semiconductor device 10F can reduce the external component Cex of the off capacitance including these capacitances.

As mentioned in the first embodiment, the embedding state of the fifth insulating film 85 in the opening P shown in FIG. 35, and the covering state of the side surface of the opening P and the upper surface of the first insulating film 81 are merely examples and do not limit the structure of the semiconductor device 10F of this embodiment.

8. Application Examples
Furthermore, a configuration of a wireless communication device, which is an application example of the semiconductor device according to the first to seventh embodiments of the present disclosure, will be described with reference to Fig. 36. Fig. 36 is a schematic diagram showing an example of the configuration of the wireless communication device.

As shown in FIG. 36, the wireless communication device 3 includes, for example, an antenna ANT, a high-frequency switch 1, a high-power amplifier HPA, a high-frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I/F (for example, a wireless LAN (Wireless Local Area Network: W-LAN), Bluetooth (registered trademark), etc.). The wireless communication device 3 is, for example, a high-frequency module used in a mobile phone system having multiple functions such as voice, data communication, and LAN (Local Area Network) connection.

The high frequency switch 1 is configured to include any one of the semiconductor devices 10, 10A to 10F according to the first to seventh embodiments.

When a transmission signal is output from the transmission system of the wireless communication device 3 to the antenna ANT (i.e., during transmission), the wireless communication device 3 outputs the transmission signal output from the baseband unit BB to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA, and the radio frequency switch 1.

On the other hand, when the signal received by the antenna ANT is input to the receiving system of the wireless communication device 3 (i.e., during reception), the wireless communication device 3 inputs the received signal to the baseband unit BB via the high frequency switch 1 and the high frequency integrated circuit RFIC. The received signal processed by the baseband unit BB is output from an output unit such as the audio output unit MIC, the data output unit DT, or the interface unit I/F.

The technology related to the present disclosure has been explained above using the first to seventh embodiments, but the technology related to the present disclosure is not limited to the above embodiments and various modifications are possible.

For example, in the above embodiment, the first conductivity type impurity is an n-type impurity such as arsenic (As) or phosphorus (P), and the second conductivity type impurity is a p-type impurity such as boron (B) or aluminum (Al), but these conductivity types may be reversed. That is, the first conductivity type impurity may be a p-type impurity such as boron (B) or aluminum (Al), and the second conductivity type impurity may be an n-type impurity such as arsenic (As) or phosphorus (P).

For example, in the above embodiment, specific configurations of a high-frequency switch 1, a semiconductor device 10 such as a field-effect transistor, and a wireless communication device 3 are given and described as embodiments of the technology disclosed herein, but these are not limited to those having all of the components shown in the figures, and it is possible to replace some of the components with other components.

In addition, in the above embodiment, an example was described in which the semiconductor device 10 is applied to a high-frequency switch 1 of a wireless communication device 3, but the semiconductor device 10 can also be applied to other high-frequency devices such as a high-frequency switch (RF-SW) and a PA (Power Amplifier).

Furthermore, the shapes, materials, thicknesses, and film formation methods of each layer described in the above embodiments are not limited to those described above, and other shapes, materials, and thicknesses, or other film formation methods may be used.

Not all of the configurations and operations described in each embodiment are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in each embodiment, any components that are not described in an independent claim that represents the highest concept of the present disclosure should be understood as optional components.

Terms used throughout this specification and the appended claims should be construed as "open-ended" terms. For example, the terms "including" or "including" should be construed as "not limited to what is described as including." The term "having" should be construed as "not limited to what is described as having." And, it will be apparent to one skilled in the art that modifications can be made to the embodiments of the present disclosure without departing from the scope of the appended claims.

The terms used in this specification include those used merely for convenience of explanation and do not limit the configuration and operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is being made. Furthermore, the terms "inner" and "outer" indicate directions toward and away from the center of the focused element, respectively. The same applies to terms similar to these and terms of a similar meaning.

The technology according to the present disclosure may also have the following configuration. According to the technology according to the present disclosure having the following configuration, it is possible to reduce the off-capacitance of a field-effect transistor. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
(1)
A gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode therebetween;
contact plugs provided on the source region and the drain region, respectively;
a first metal layer deposited on each of the contact plugs;
a first low dielectric constant region provided between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
a second low dielectric constant region provided in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
The second low dielectric constant region is provided in a planar region at least partially different from a planar region in which the first low dielectric constant region is provided.
(2)
The semiconductor device according to (1), wherein the first low dielectric constant region is further extended to at least any region between an upper surface and a lower surface of the first metal in the stacking direction.
(3)
The semiconductor device according to (2), wherein the first low dielectric constant region is further extended to at least any region above an upper surface of the first metal in the stacking direction.
(4)
The semiconductor device according to any one of (1) to (3), wherein the second low dielectric constant region is provided contiguous with the first low dielectric constant region.
(5)
the first low dielectric constant region and the second low dielectric constant region each include a gap;
The semiconductor device according to (4), wherein the void included in the first low dielectric constant region and the void included in the second low dielectric constant region are provided continuously.
(6)
one or more insulating layers provided on the semiconductor layer so as to cover the gate electrode;
an opening provided in a planar region corresponding to the gate electrode from an upper surface of the one or more insulating films;
The semiconductor device according to any one of (1) to (5), wherein the first low dielectric constant region is provided inside the opening.
(7)
The semiconductor device according to (6), wherein the one or more insulating layers include insulating layers each formed of a material having a different etching rate.
(8)
The one or more insulating layers are
a first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer;
a second insulating film covering a surface of the first insulating film;
a third insulating film provided between a surface of the second insulating film and a lower surface of the first metal;
The semiconductor device according to (7), wherein the first insulating film is made of a material having an etching rate different from that of the second insulating film.
(9)
The semiconductor device according to (8), wherein in one cross section in the stacking direction, the width of the first low dielectric constant region is smaller than the width of the first insulating film provided on a surface of the gate electrode.
(10)
The semiconductor device according to (8) or (9), wherein the opening is provided at least penetrating the third insulating film on the gate electrode.
(11)
The semiconductor device according to (10), wherein the opening is provided through the second insulating film above the gate electrode, or through the second insulating film and the first insulating film.
(12)
the one or more insulating layers further include a fourth insulating layer covering an upper surface of the third insulating layer and a surface of the first metal;
The semiconductor device according to (10) or (11), wherein the opening is provided from an upper surface of the fourth insulating film.
(13)
the one or more insulating layers further include a fifth insulating layer provided on the fourth insulating layer;
The semiconductor device according to (12), wherein the fifth insulating film closes an upper portion of the opening.
(14)
a second metal provided between the fourth insulating film and the fifth insulating film;
the one or more insulating layers further include a seventh insulating layer covering an upper surface of the fourth insulating layer and a surface of the second metal;
The semiconductor device according to (13), wherein the opening is provided from an upper surface of the seventh insulating film.
(15)
The semiconductor device according to (13) or (14), wherein the fifth insulating film covers at least a part of a side surface of the opening.
(16)
the fifth insulating film is formed of a material having a lower dielectric constant than materials forming the third insulating film and the fourth insulating film,
The semiconductor device according to any one of (13) to (15), wherein the first low dielectric constant region includes at least a portion of the opening filled with the fifth insulating film.
(17)
The one or more insulating layers are
a first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer;
a second insulating film covering a surface of the first insulating film;
a third insulating film provided between a surface of the second insulating film and a lower surface of the first metal;
a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal;
a fifth insulating film provided on the fourth insulating film and closing the opening;
The semiconductor device according to (6), wherein the second low dielectric constant region includes a void provided in a region in the stacking direction where at least one of the first insulating film, the second insulating film, or the third insulating film is formed.
(18)
The semiconductor device according to (17), wherein the void included in the second low dielectric constant region exposes at least a portion of the first insulating film.
(19)
The semiconductor device according to (18), wherein the void included in the second low dielectric constant region exposes the first insulating film provided on a surface of the semiconductor layer.
(20)
The semiconductor device according to (19), wherein the void included in the second low dielectric constant region further exposes at least a portion of the gate electrode.
(21)
The semiconductor device according to any one of (17) to (20), wherein the void included in the second low dielectric constant region is continuous with the opening provided from an upper surface of the fourth insulating film through at least the third insulating film above the gate electrode.
(22)
The semiconductor device according to (21), wherein the fifth insulating film covers at least a portion of a side surface or a bottom surface of a gap included in the second low dielectric constant region.
(23)
The semiconductor device according to any one of (17) to (22), wherein in a cross section in the stacking direction, a width of a region in which the second low dielectric constant region is provided is larger than a width of the first insulating film provided on a surface of the gate electrode.
(24)
the fifth insulating film is formed of a material having a lower dielectric constant than materials forming the third insulating film and the fourth insulating film,
The semiconductor device according to any one of (17) to (23), wherein the second low dielectric constant region includes a region buried in the fifth insulating film.
(25)
the gate electrode is provided extending in one direction in the in-plane direction,
The semiconductor device according to any one of (1) to (24), wherein the contact plug, the first metal, the first low dielectric constant region, and the second low dielectric constant region are provided extending in the in-plane direction parallel to the extension direction of the gate electrode.
(26)
The semiconductor device according to (25), wherein the first low dielectric constant region and the second low dielectric constant region are provided extending in the in-plane direction in a direction intersecting an extension direction of the gate electrode.
(27)
the gate electrode includes a plurality of finger portions extending in the same direction and a connecting portion connecting the plurality of finger portions,
the first low dielectric constant region is provided above the finger portion or above at least a part of the coupling portion;
The semiconductor device according to any one of (1) to (26), wherein the second low dielectric constant region is provided on a side wall of the finger portion or on at least a part of a side wall of the coupling portion.
(28)
In the in-plane direction,
an element region including the source region and the drain region;
a wiring region having a multi-layer wiring portion and separated from the element region by an element isolation layer;
is established,
28. The semiconductor device according to claim 1, wherein the first low dielectric constant region and the second low dielectric constant region are provided in the element region.
(29)
In the in-plane direction,
an active region including the element region and the wiring region;
an isolation region including the isolation layer and disposed outside the active region;
is established,
a gate contact connected to the gate electrode is provided on the element isolation layer in the element isolation region;
The semiconductor device according to (28), wherein the first low dielectric constant region and the second low dielectric constant region are provided so as to avoid the gate contact.
(30)
The semiconductor device according to any one of (1) to (29) above, which is used as a field effect transistor for a high frequency device.
(31)
forming a gate electrode on an upper surface side of the semiconductor layer;
forming a source region and a drain region in the semiconductor layer with the gate electrode therebetween;
forming a contact plug on each of the source region and the drain region;
depositing a first metal on each of the contact plugs;
forming a first low dielectric constant region between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
forming a second low dielectric constant region in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
A method for manufacturing a semiconductor device, comprising the steps of: forming the second low dielectric constant region in a planar region at least partially different from a planar region in which the first low dielectric constant region is formed.

This application claims priority based on Japanese Patent Application No. 2019-114339, filed on June 20, 2019 in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

It will be understood that those skilled in the art may consider various modifications, combinations, subcombinations, and variations depending on design requirements and other factors, which are intended to fall within the scope of the appended claims and their equivalents.

Claims (34)

A gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode therebetween;
contact plugs provided on the source region and the drain region, respectively;
a first metal layer deposited on each of the contact plugs;
a first low dielectric constant region provided between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
a second low dielectric constant region provided in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
the second low dielectric constant region is provided contiguous with the first low dielectric constant region and is provided in a planar region at least partially different from a planar region in which the first low dielectric constant region is provided. The semiconductor device according to claim 1, wherein the first low dielectric constant region is further extended to at least one region between the upper surface and the lower surface of the first metal in the stacking direction. The semiconductor device according to claim 2, wherein the first low dielectric constant region extends further into at least one region above the top surface of the first metal in the stacking direction. the first low dielectric constant region and the second low dielectric constant region each include a gap;
2 . The semiconductor device according to claim 1 , wherein the void included in said first low dielectric constant region and the void included in said second low dielectric constant region are provided continuously with each other. one or more insulating layers provided on the semiconductor layer so as to cover the gate electrode;
an opening provided in a planar region corresponding to the gate electrode from an upper surface of the one or more insulating films;
The semiconductor device according to claim 1 , wherein said first low dielectric constant region is provided inside said opening. 6. The semiconductor device according to claim 5 , wherein said one or more insulating films include insulating films each formed of a material having a different etching rate. The one or more insulating layers are
a first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer;
a second insulating film covering a surface of the first insulating film;
a third insulating film provided between a surface of the second insulating film and a lower surface of the first metal;
7. The semiconductor device according to claim 6 , wherein said first insulating film is made of a material having an etching rate different from that of said second insulating film. 8. The semiconductor device according to claim 7 , wherein in one cross section in the stacking direction, a width of said first low dielectric constant region is smaller than a width of said first insulating film provided on a surface of said gate electrode. The semiconductor device according to claim 7 , wherein said opening is provided at least penetrating said third insulating film above said gate electrode. 10. The semiconductor device according to claim 9 , wherein the opening is provided by penetrating the second insulating film above the gate electrode, or by penetrating the second insulating film and the first insulating film. the one or more insulating layers further include a fourth insulating layer covering an upper surface of the third insulating layer and a surface of the first metal;
The semiconductor device according to claim 9 , wherein the opening is provided from an upper surface of the fourth insulating film. the one or more insulating layers further include a fifth insulating layer provided on the fourth insulating layer;
The semiconductor device according to claim 11 , wherein the fifth insulating film closes an upper portion of the opening. a second metal provided between the fourth insulating film and the fifth insulating film;
the one or more insulating layers further include a seventh insulating layer covering an upper surface of the fourth insulating layer and a surface of the second metal;
The semiconductor device according to claim 12 , wherein the opening is provided from an upper surface of the seventh insulating film. The semiconductor device according to claim 12 , wherein said fifth insulating film covers at least a part of a side surface of said opening. the fifth insulating film is formed of a material having a lower dielectric constant than materials forming the third insulating film and the fourth insulating film,
13. The semiconductor device according to claim 12 , wherein said first low dielectric constant region includes at least a portion of said opening filled with said fifth insulating film. The one or more insulating layers are
a first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer;
a second insulating film covering a surface of the first insulating film;
a third insulating film provided between a surface of the second insulating film and a lower surface of the first metal;
a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal;
a fifth insulating film provided on the fourth insulating film and closing the opening;
6. The semiconductor device according to claim 5, wherein the second low dielectric constant region includes a void provided in a region in which at least one of the first insulating film, the second insulating film, and the third insulating film is formed in the stacking direction . The semiconductor device according to claim 16 , wherein the void included in the second low dielectric constant region exposes at least a portion of the first insulating film. The semiconductor device according to claim 17 , wherein the void included in the second low dielectric constant region exposes the first insulating film provided on a surface of the semiconductor layer. The semiconductor device according to claim 18 , wherein a void included in the second low dielectric constant region further exposes at least a portion of the gate electrode. 17. The semiconductor device according to claim 16 , wherein the void included in the second low dielectric constant region is provided continuous with the opening provided penetrating at least from an upper surface of the fourth insulating film through the third insulating film above the gate electrode. The semiconductor device according to claim 20 , wherein the fifth insulating film covers at least a part of a side surface or a bottom surface of a gap included in the second low dielectric constant region. 17. The semiconductor device according to claim 16 , wherein in a cross section in the stacking direction, a width of a region in which said second low dielectric constant region is provided is larger than a width of said first insulating film provided on a surface of said gate electrode. the fifth insulating film is formed of a material having a lower dielectric constant than materials forming the third insulating film and the fourth insulating film,
17. The semiconductor device according to claim 16 , wherein said second low dielectric constant region includes a region buried in said fifth insulating film. the gate electrode is provided extending in one direction in the in-plane direction,
2. The semiconductor device according to claim 1, wherein the contact plug, the first metal, the first low dielectric constant region, and the second low dielectric constant region are provided extending in the in-plane direction parallel to an extension direction of the gate electrode. 25. The semiconductor device according to claim 24 , wherein the first low dielectric constant region and the second low dielectric constant region are provided extending in a direction intersecting an extension direction of the gate electrode in the in-plane direction. the gate electrode includes a plurality of finger portions extending in the same direction and a connecting portion connecting the plurality of finger portions,
the first low dielectric constant region is provided above the finger portion or above at least a part of the coupling portion;
The semiconductor device according to claim 1 , wherein the second low dielectric constant region is provided on a sidewall of the finger portion or on at least a part of a sidewall of the coupling portion. In the in-plane direction,
an element region including the source region and the drain region;
a wiring region having a multi-layer wiring portion and separated from the element region by an element isolation layer;
was established,
The semiconductor device according to claim 1 , wherein said first low dielectric constant region and said second low dielectric constant region are provided in said element region. In the in-plane direction,
an active region including the element region and the wiring region;
an isolation region including the isolation layer and disposed outside the active region;
was established,
a gate contact connected to the gate electrode is provided on the element isolation layer in the element isolation region;
28. The semiconductor device according to claim 27 , wherein the first low dielectric constant region and the second low dielectric constant region are provided so as to avoid the gate contact. The semiconductor device according to claim 1, which is used as a field effect transistor for a high frequency device. A gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode therebetween;
contact plugs provided on the source region and the drain region, respectively;
a first metal layer deposited on each of the contact plugs;
a first low dielectric constant region provided between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
a second low dielectric constant region provided in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
one or more insulating layers provided on the semiconductor layer so as to cover the gate electrode;
an opening provided in a planar region corresponding to the gate electrode from the upper surface of the one or more insulating films;
Equipped with
the first low dielectric constant region is provided inside the opening,
the second low dielectric constant region is provided in a planar region at least partially different from a planar region in which the first low dielectric constant region is provided,
The one or more insulating layers are
a first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer;
a second insulating film covering a surface of the first insulating film;
a third insulating film provided between a surface of the second insulating film and a lower surface of the first metal;
Including,
the first insulating film is formed of a material having an etching rate different from that of the second insulating film;
the opening is provided to penetrate at least the third insulating film on the gate electrode and further penetrate the second insulating film or the second insulating film and the first insulating film;
Semiconductor device. A gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode therebetween;
contact plugs provided on the source region and the drain region, respectively;
a first metal layer deposited on each of the contact plugs;
a first low dielectric constant region provided between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
a second low dielectric constant region provided in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
one or more insulating layers provided on the semiconductor layer so as to cover the gate electrode;
an opening provided in a planar region corresponding to the gate electrode from the upper surface of the one or more insulating films;
Equipped with
the first low dielectric constant region is provided inside the opening,
the second low dielectric constant region is provided in a planar region at least partially different from a planar region in which the first low dielectric constant region is provided,
The one or more insulating layers are
a first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer;
a second insulating film covering a surface of the first insulating film;
a third insulating film provided between a surface of the second insulating film and a lower surface of the first metal;
a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal;
a fifth insulating film provided on the fourth insulating film and closing the opening;
Including,
the second low dielectric constant region includes a gap provided in a region in which at least one of the first insulating film, the second insulating film, or the third insulating film is formed in the stacking direction;
the void included in the second low dielectric constant region is provided continuously with the opening provided at least penetrating the third insulating film on the gate electrode from an upper surface of the fourth insulating film;
Semiconductor device. A gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode therebetween;
contact plugs provided on the source region and the drain region, respectively;
a first metal layer deposited on each of the contact plugs;
a first low dielectric constant region provided between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
a second low dielectric constant region provided in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
Equipped with
the second low dielectric constant region is provided in a planar region at least partially different from a planar region in which the first low dielectric constant region is provided,
the gate electrode is provided extending in one direction in the in-plane direction,
the contact plug, the first metal, the first low dielectric constant region, and the second low dielectric constant region are provided extending in the in-plane direction in a direction parallel to an extension direction of the gate electrode,
the first low dielectric constant region and the second low dielectric constant region are provided extending in the in-plane direction in a direction intersecting an extension direction of the gate electrode;
Semiconductor device. A gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode therebetween;
contact plugs provided on the source region and the drain region, respectively;
a first metal layer deposited on each of the contact plugs;
a first low dielectric constant region provided between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
a second low dielectric constant region provided in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
Equipped with
the second low dielectric constant region is provided in a planar region at least partially different from a planar region in which the first low dielectric constant region is provided,
In the in-plane direction,
an element region including the source region and the drain region;
a wiring region having a multi-layer wiring portion and separated from the element region by an element isolation layer;
was established,
the first low dielectric constant region and the second low dielectric constant region are provided in the element region,
an active region including the element region and the wiring region;
an isolation region including the isolation layer and disposed outside the active region;
was established,
a gate contact connected to the gate electrode is provided on the element isolation layer in the element isolation region;
the first low dielectric constant region and the second low dielectric constant region are provided to avoid the gate contact;
Semiconductor device. forming a gate electrode on an upper surface side of the semiconductor layer;
forming a source region and a drain region in the semiconductor layer with the gate electrode therebetween;
forming a contact plug on each of the source region and the drain region;
depositing a first metal on each of the contact plugs;
forming a first low dielectric constant region between the first metals in an in-plane direction of the semiconductor layer and in at least one region below a lower surface of the first metal in a stacking direction of the semiconductor layer;
forming a second low dielectric constant region in at least any region between the contact plug and the gate electrode in the in-plane direction and below the first low dielectric constant region in the stacking direction;
A method for manufacturing a semiconductor device, comprising forming the second low dielectric constant region in a planar region at least partially different from a planar region in which the first low dielectric constant region is formed, so as to be continuous with the first low dielectric constant region .

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