JP7438730B2 - Photoelectric conversion devices, imaging systems, and moving objects - Google Patents

Description

The present invention relates to a photoelectric conversion device, an imaging system, and a moving object.

A single photon avalanche diode (SPAD) is known as a photodetection device capable of detecting weak light at the single photon level by utilizing avalanche (electron avalanche) multiplication. Patent Document 1 discloses a SPAD in which a photocharge caused by a single photon undergoes avalanche multiplication in a strong electric field region of a semiconductor region constituting a photodetector.

In addition, the SPAD of Patent Document 1 has a structure in which a semiconductor region with a high impurity concentration is arranged on a part of the surface of a semiconductor substrate, and a strong electric field is generated in this semiconductor region, and a photoelectric charge generated by incident light is generated in the semiconductor region. The potential is adjusted so that it flows.

Japanese Patent Application Publication No. 2018-64086

In a photoelectric conversion device using an avalanche diode, a noise current may be generated due to the presence of a carrier trapping level near a strong electric field region. This noise current can cause deterioration of signal quality.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a photoelectric conversion device that can reduce deterioration in signal quality caused by noise current.

According to one aspect of the invention, a plurality of pixels each including a plurality of avalanche diodes , and each of the plurality of avalanche diodes of the plurality of pixels are configured to operate in an operating state in which avalanche multiplication can occur or in which avalanche multiplication occurs. a selection unit for controlling the plurality of avalanche diodes to a non -operating state, and the plurality of avalanche diodes of each of the plurality of pixels include a first group of avalanche diodes and a second group of avalanche diodes , and the The selection unit selects each of the plurality of pixels into a first state in which the first group of avalanche diodes are in the operating state and the second group of avalanche diodes are in the inactive state, and a second state in which the avalanche diodes in the second group are in the inactive state. avalanche diodes of the plurality of pixels are in the operating state and the avalanche diodes of the first group are in the non-operating state, and each of the plurality of pixels is controlled to either the first state or the second state . Provided is a photoelectric conversion device that does not include an avalanche diode that is in the operating state when the first state is controlled to the second state .

According to the present invention, it is possible to provide a photoelectric conversion device that can reduce deterioration in signal quality caused by noise current.

FIG. 1 is a schematic cross-sectional view of an avalanche diode according to a first embodiment. FIG. 2 is a schematic plan view of an avalanche diode according to the first embodiment. FIG. 3 is a potential diagram of the avalanche diode according to the first embodiment. FIG. 2 is a block diagram of a photoelectric conversion device according to a second embodiment. FIG. 3 is a block diagram of a pixel according to a second embodiment. 7 is a flowchart illustrating a method for controlling a photoelectric conversion device and signal processing according to a second embodiment. FIG. 2 is a schematic diagram illustrating in more detail the mechanism by which an image signal with less noise current is obtained. It is a graph which shows the cumulative relative frequency of the noise current in 2nd Embodiment. 7 is a flowchart illustrating a method for controlling a photoelectric conversion device and signal processing according to a third embodiment. FIG. 7 is a block diagram of pixels according to a third embodiment. FIG. 7 is a block diagram of an output determination circuit according to a third embodiment. FIG. 7 is a block diagram of a pixel according to a fourth embodiment. FIG. 7 is an equivalent circuit diagram of a variable resistance circuit according to a fourth embodiment. FIG. 3 is a block diagram of an imaging system according to a fifth embodiment. It is a block diagram of an imaging system and a mobile object concerning a 6th embodiment.

[First embodiment]
A photoelectric conversion device according to a first embodiment will be described using FIGS. 1 to 3. The photoelectric conversion device of this embodiment has one or more pixels, and each pixel includes a plurality of avalanche diodes. Among the charge pairs generated in the avalanche diode, the conductivity type of the charge used as the signal charge is called a first conductivity type. Further, a conductivity type opposite to the first conductivity type is referred to as a second conductivity type.

FIG. 1 is a schematic cross-sectional view of an avalanche diode according to this embodiment. The avalanche diode of this embodiment is arranged on the semiconductor substrate 15. Semiconductor substrate 15 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front surface of the semiconductor substrate 15, and the second surface is the back surface of the semiconductor substrate 15. In this specification, the direction from the first surface to the second surface is referred to as the depth direction. On the front side of the semiconductor substrate 15, gate electrodes of transistors, a multilayer wiring structure, etc. are arranged.

As shown in FIG. 1, a well region surrounded by an isolation section 16 functioning as an element isolation region is formed in the semiconductor substrate 15. This well area defines the sensitive area of the pixel. The well region includes first semiconductor regions 71A and 71B of the first conductivity type, a second semiconductor region 76, third semiconductor regions 74A and 74B, a fourth semiconductor region 72 of the second conductivity type, and a fifth semiconductor region 71A and 71B of the first conductivity type. A region 75 is arranged. Further, on the first surface of the semiconductor substrate 15, a contact plug 77A disposed in contact with the first semiconductor region 71A and a contact plug 77B disposed in contact with the first semiconductor region 71B are provided. ing. Contact plug 77A functions as a terminal of the first avalanche diode, and contact plug 77B functions as a terminal of the second avalanche diode.

The first semiconductor regions 71A, 71B and the second semiconductor region 76 are arranged at a first depth X. The first semiconductor region 71A and the second semiconductor region 76 are in contact with each other in a direction perpendicular to the depth direction (lateral direction in FIG. 1). Further, the first semiconductor region 71B and the second semiconductor region 76 are also in contact with each other in a direction perpendicular to the depth direction. The second semiconductor region 76 is arranged between the first semiconductor region 71A and the isolation section 16, between the first semiconductor region 71B and the isolation section 16, and between the first semiconductor region 71A and the first semiconductor region 71B.

Here, when the first semiconductor regions 71A, 71B and the second semiconductor region 76 are arranged at the first depth X, for example, the region (peak) of the highest impurity concentration implanted into the semiconductor substrate 15 is This means that the first depth is X. However, this does not mean that the peak exactly matches the first depth X, and even if the peak deviates from the first depth X due to design errors, manufacturing errors, etc. It is assumed that it is included in the state arranged at the first depth X.

The third semiconductor regions 74A, 74B and the fourth semiconductor region 72 are arranged at a second depth Y, which is deeper than the first depth X, with respect to the first surface. The third semiconductor region 74A and the fourth semiconductor region 72 are in contact with each other in a direction perpendicular to the depth direction. Further, the third semiconductor region 74B and the fourth semiconductor region 72 are also in contact with each other in a direction perpendicular to the depth direction. The fourth semiconductor region 72 is located between the third semiconductor region 74A and the isolation section 16, between the third semiconductor region 74B and the isolation section 16, and between the third semiconductor region 74A and the third semiconductor region 72 at the second depth Y. They are respectively arranged between the area 74B and the area 74B. The fifth semiconductor region 75 is arranged at a third depth Z, which is deeper than the second depth Y, with respect to the first surface.

FIGS. 2A and 2B are schematic plan views of the avalanche diode according to this embodiment. 2(a) is a schematic plan view of the avalanche diode at the first depth X, and FIG. 2(b) is a schematic plan view of the avalanche diode at the second depth Y.

As shown in FIG. 2A, at the first depth X, the first semiconductor regions 71A and 71B are included in the second semiconductor region 76. Further, the first semiconductor region 71A and the first semiconductor region 71B do not overlap with each other. Furthermore, the second semiconductor region 76 is included in the isolation section 16 .

As shown in FIG. 2(b), at the second depth Y, the third semiconductor regions 74A and 74B are included in the fourth semiconductor region 72. Furthermore, the third semiconductor region 74A and the third semiconductor region 74B do not overlap with each other. Furthermore, the fourth semiconductor region 72 is included in the separation section 16 . As shown in FIGS. 1, 2(a), and 2(b), the first semiconductor region 71A overlaps at least a portion of the third semiconductor region 74A in plan view. Furthermore, in plan view, the first semiconductor region 71B overlaps at least a portion of the third semiconductor region 74B. Furthermore, in plan view, the third semiconductor regions 74A, 74B and the fourth semiconductor region 72 overlap with the fifth semiconductor region 75. Furthermore, in plan view, the second semiconductor region 76 overlaps at least a portion of the fourth semiconductor region 72.

FIG. 3 is a graph showing an example of the potential of the avalanche diode according to this embodiment. FIG. 3 shows potential distributions in line segment JK, line segment GH, and line segment LM in the cross-sectional view shown in FIG. The potential within the semiconductor region changes depending on the potential applied to contact plugs 77A and 77B. The potential shown in FIG. 3 is for the case where a potential is supplied so that a reverse bias voltage is applied only to the first avalanche diode corresponding to the contact plug 77A. This potential is supplied from a power supply voltage line provided outside the avalanche diode through a circuit such as a quench circuit. Further, the potential level is set so that avalanche multiplication occurs in the first avalanche diode. On the other hand, the second avalanche diode corresponding to the contact plug 77B is in a floating state or is supplied with a potential having a bias voltage near zero bias.

The broken line 20 shows the potential distribution in the line segment GH, the solid line 21 shows the potential distribution in the line segment JK, and the dashed-dotted line 22 shows the potential distribution in the line segment LM. These potentials indicate potentials for electrons, which are signal charges. Note that when the signal charge is a hole, the relationship between the potential levels is reversed. The depths X, Y, Z, and W correspond to the depths of the correspondingly labeled positions shown in FIG. That is, the depths X, Y, and Z are the first depth X, the second depth Y, and the third depth Z described above, respectively. Moreover, the depth W is the depth between the second depth Y and the third depth Z.

Each potential level in FIG. 3 will be explained. The XH level indicates the potential of the fourth semiconductor region 72. The H level indicates the potential of the third semiconductor region 74A. The M level indicates the potential of the second semiconductor region 76. The L level indicates the potential of the first semiconductor region 71A. Note that although the potential of the second semiconductor region 76 is assumed to be lower than the potential of the third semiconductor region 74A, the reverse may be possible.

The potential of the third semiconductor region 74B is between the XH level and the H level. The potential of the first semiconductor region 71B is between the M level and the L level. Note that although the potential of the third semiconductor region 74B is lower than the potential of the fourth semiconductor region 72, they may be the same. Furthermore, although the potential of the first semiconductor region 71B is lower than the potential of the second semiconductor region 76, they may be the same.

The potential on the line segment GH indicated by the broken line 20 will be explained. At depth Z, the potential is between the XH and H levels. The potential gradually decreases from the depth Z toward the depth W. Then, the potential gradually increases from the depth W toward the depth Y, and reaches the XH level at the depth Y. Further, the potential gradually decreases from depth Y to depth X. In the vicinity of depth X, the potential becomes M level.

The potential on the line segment JK indicated by the solid line 21 passing through the first avalanche diode will be explained. At depth Z, the potential is between the XH and H levels. The potential gradually decreases from depth Z toward depth Y, and the slope of the potential increases near depth Y. The potential is at the H level at depth Y. The potential decreases rapidly from depth Y to depth X. That is, a steep potential gradient is formed between depth Y and depth X. At depth X, the potential is at L level.

The potential of the line segment LM shown by the dashed-dotted line 22 passing through the second avalanche diode will be explained. At depth Z, the potential is between the XH and H levels. The potential gradually decreases from the depth Z toward the depth W. Then, the potential gradually increases from the depth W toward the depth Y, and reaches a level between the XH level and the H level at the depth Y. Further, the potential gradually decreases from depth Y to depth X. At depth X, the potential is at a level between M level and L level. The difference in potential distribution at the positions of these line segments is caused by the difference in potential applied to the two avalanche diodes.

At depth Z, the potentials of line segment GH, line segment JK, and line segment LM are almost the same. Furthermore, in the vicinity of the depth Z, a potential gradient is formed that gradually decreases toward the first surface of the semiconductor substrate 15 at the positions of the line segment GH, line segment JK, and line segment LM. Therefore, charges generated in the semiconductor region within the pixel by the incident light move toward the first surface due to this potential gradient.

In the line segment JK, a potential gradient is formed that gradually decreases toward the first surface of the semiconductor substrate 15 as it approaches the depth Y from the depth W. This causes the charges to move toward the first surface. On the other hand, in the line segment GH and the line segment LM, a potential gradient is formed that gradually increases toward the first surface of the semiconductor substrate 15 as the depth W approaches the depth Y. This potential gradient acts as a potential barrier for charges directed toward the first surface. That is, the fourth semiconductor region 72 and the third semiconductor region 74B function as a potential barrier that suppresses the movement of charges from the fifth semiconductor region 75 to the second semiconductor region 76. On the other hand, since the horizontal potential gradient from the position of line segment GH and line segment LM to line segment JK is small, it exists near line segment GH and line segment LM in the range from depth W to depth Y. During the process of moving toward the first surface, the charges tend to move near line segment JK.

The charges that have moved to the vicinity of the region indicated by the line segment JK are accelerated by a steep potential gradient, that is, a strong electric field, formed in the range from depth Y to depth X. The charges accelerated by the strong electric field reach the first semiconductor region 71A. In this way, avalanche multiplication occurs in the region from depth Y to depth X near line segment JK. On the other hand, in the regions shown by the line segments GH and LM, the potential distribution is such that avalanche multiplication is less likely to occur than in the region from the depth Y to the depth X of the line segment JK. That is, during a period in which one avalanche diode is controlled to cause avalanche multiplication, the other avalanche diode is controlled to prevent avalanche multiplication.

An example of implementing such a structure is as follows. The difference between the potential of the first semiconductor region 71A and the potential of the third semiconductor region 74A is made larger than the difference between the potential of the second semiconductor region 76 and the fourth semiconductor region 72. Then, the difference between the potential of the first semiconductor region 71A and the potential of the third semiconductor region 74A is made larger than the difference between the potential of the first semiconductor region 71B and the third semiconductor region 74B. By adopting such a potential structure, a configuration is realized in which avalanche multiplication occurs in only one of the two avalanche diodes arranged in the pixel. As a result, avalanche multiplication does not occur in the other avalanche diode, but the decrease in sensitivity caused by this is reduced by the following configuration.

In this embodiment, two avalanche diodes are formed in the same well region surrounded by an element isolation region. The potential of the third semiconductor region 74A is lower than the potentials of the fourth semiconductor region 72 and the third semiconductor region 74B. Therefore, the fourth semiconductor region 72 and the third semiconductor region 74B function as a potential barrier against the signal charges existing in the fifth semiconductor region 75. This makes it easier for signal charges existing in the region of the fifth semiconductor region 75 that overlaps with the fourth semiconductor region 72 or the third semiconductor region 74B to move to the first semiconductor region 71A via the third semiconductor region 74A. . Therefore, charges are collected in the avalanche diode on the side where avalanche multiplication occurs, so that the above-mentioned decrease in sensitivity is alleviated.

FIG. 3 shows a potential structure when the third semiconductor regions 74A and 74B are P-type semiconductor regions. However, even if the third semiconductor regions 74A and 74B are N-type semiconductor regions, the magnitude relationship of the potentials at depth Y for each of line segment GH, line segment JK, and line segment LM does not change. That is, at depth Y, the potentials in line segment GH and line segment LM are higher than the potential in line segment JK.

Further, although FIG. 3 shows the potential structure when the second semiconductor region 76 is an N-type semiconductor region, even if it is a P-type semiconductor region, the line segments GH, JK, and LM For each, the magnitude relationship of the potential at depth Y remains unchanged. That is, at depth Y, the potentials in line segment GH and line segment LM are higher than the potential in line segment JK.

Note that, in plan view, it is desirable that all regions of the first semiconductor region 71A overlap with the third semiconductor region 74A. Further, in plan view, it is desirable that all regions of the first semiconductor region 71B overlap the third semiconductor region 74B. In other words, it is desirable that the first semiconductor regions 71A, 71B and the fourth semiconductor region 72 do not overlap in plan view. According to such a configuration, a PN junction is not formed between the first semiconductor regions 71A, 71B and the fourth semiconductor region 72. If a PN junction exists between the first semiconductor regions 71A, 71B and the fourth semiconductor region 72, avalanche multiplication occurs in the PN junction, and noise may be generated due to the tunnel effect. By adopting a structure in which the first semiconductor regions 71A, 71B and the fourth semiconductor region 72 do not overlap, it is possible to suppress noise caused by the above-described mechanism.

In the above description, it is assumed that a potential is supplied so that a reverse bias potential is applied only to the first avalanche diode corresponding to the contact plug 77A. Further, the second avalanche diode corresponding to the contact plug 77B is supplied with a potential near zero bias or is kept in a floating state. However, the relationship between the supplied potentials may be reversed between contact plug 77A and contact plug 77B. That is, a selection unit may be provided that switches the supply potential so that an avalanche diode that causes avalanche multiplication can be selected.

In this case, in FIG. 3, a broken line 20 shows the potential distribution in the line segment GH, a solid line 21 shows the potential distribution in the line segment LM, and a dashed-dotted line 22 shows the potential distribution in the line segment JK. That is, the potential distribution of line segment LM and the potential distribution of line segment JK are swapped. Therefore, by changing the potentials applied to the contact plugs 77A and 77B, the region where avalanche multiplication occurs can be switched from the first semiconductor region 71A to the first semiconductor region 71B.

Next, a description will be given of noise current that may occur in a strong electric field region. Noise current due to carrier trapping levels caused by heavy metals, etc. becomes large when both nearby electron carrier density n and hole carrier density p are smaller than the intrinsic carrier density ni (i.e., n<ni and p<ni). It is known that This state where both the electron carrier density n and the hole carrier density p are small is a state found in a depletion layer where carriers are excluded by a strong electric field or the like. It is also known that in a strong electric field region, the potential displacement in the vicinity is large, so the apparent band gap becomes small and the noise current due to the tunnel effect becomes large.

For the above-mentioned reasons, if a carrier trapping level due to heavy metal or the like exists near the strong electric field region of the first semiconductor region 71A or 71B, a relatively large noise current may occur. This carrier trapping level due to heavy metals or the like may occur randomly with a certain probability during manufacturing of a photoelectric conversion device.

The photoelectric conversion device of this embodiment can reduce the probability of occurrence of noise current caused by the above-mentioned factors. First, after manufacturing the photoelectric conversion device of this embodiment, one of the first avalanche diode and the second avalanche diode, which has a smaller noise current, is confirmed. Thereafter, the potential to be supplied to the contact plug 77A or the contact plug 77B is set and a reverse bias voltage is supplied so that avalanche multiplication occurs in the avalanche diode on the side with less noise current in the pixel. Further, the potential of the avalanche diode on the side where the noise current is large is controlled so that it is floating or has zero bias so that avalanche multiplication does not occur. Thereby, performance deterioration caused by noise current can be reduced.

As described above, the photoelectric conversion device of this embodiment includes a plurality of avalanche diodes, and it is possible to select an avalanche diode with less noise current. Thereby, it is possible to provide a photoelectric conversion device that can reduce deterioration in signal quality caused by noise current.

Note that when the photoelectric conversion device further includes a microlens array having a plurality of microlenses, one microlens is arranged for one pixel. From another perspective, it can be said that the area corresponding to one microlens is the area of one pixel. The light transmitted through this microlens enters a plurality of avalanche diodes provided in one pixel. Note that the photoelectric conversion device of this embodiment has a so-called front-illuminated configuration in which the microlens is provided on the first surface side of the semiconductor substrate 15 in FIG. Any so-called back-illuminated configuration may be used.

Furthermore, it has been described that an element isolation region is provided between pixels to electrically isolate the pixels from each other. Such an element isolation region can be an insulation isolation region using LOCOS (Local Oxidation Of Silicon), STI (Shallow Trench Isolation), DTI (Deep Trench Isolation), or the like. Further, the element isolation region may be a PN isolation region formed by a PN junction between a P-type semiconductor region and an N-type semiconductor region.

[Second embodiment]
A photoelectric conversion device according to a second embodiment will be described using FIGS. 4 to 8. Portions having the same functions as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. FIG. 4 is a block diagram of the photoelectric conversion device 1010 according to this embodiment. The photoelectric conversion device 1010 includes a pixel section 106, a control pulse generation section 109, a horizontal scanning circuit 104, a column circuit 105, a signal line 107, an output circuit 108, and a vertical scanning circuit 103.

The pixel section 106 includes a plurality of pixels 100 arranged in a plurality of rows and a plurality of columns. Each pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing section 102. The photoelectric conversion element 101 converts light incident on the photoelectric conversion device 1010 into an electrical signal. The pixel signal processing unit 102 outputs the converted electrical signal to the column circuit 105 via the signal line 107.

The vertical scanning circuit 103 supplies control pulses for driving each pixel 100 for each pixel row based on the control pulse supplied from the control pulse generation unit 109. For the vertical scanning circuit 103, a logic circuit such as a shift register or an address decoder may be used. The signal line 107 is arranged for each column of the pixel section 106. The signal line 107 transmits the signal output from the pixel 100 selected by the vertical scanning circuit 103 to the column circuit 105.

Signals from each pixel 100 are input to the column circuit 105 for each column of the pixel section 106 via the signal line 107, and predetermined processing is performed. The predetermined processing may include processing such as noise removal and amplification of the input signal, and processing of converting the processed signal into a form that can be outputted to the outside. To realize this function, for example, the column circuit 105 includes a parallel-to-serial conversion circuit.

The horizontal scanning circuit 104 supplies the column circuit 105 with a control pulse for sequentially outputting the signal processed by the column circuit 105 to the output circuit 108 column by column.

The output circuit 108 is composed of a buffer amplifier, a differential amplifier, and the like. The output circuit 108 outputs the signal output from the column circuit 105 to a storage unit or a signal processing unit of a device external to the photoelectric conversion device 1010.

In FIG. 4, the pixels 100 in the pixel section 106 are arranged in a two-dimensional matrix, but the arrangement is not limited to this. For example, the pixel section 106 may include a plurality of pixels 100 arranged one-dimensionally. Further, the pixel 100 included in the pixel section 106 may be a single pixel. Further, the vertical scanning circuit 103, the horizontal scanning circuit 104, and the column circuit 105 may be divided into a plurality of blocks. Further, the plurality of pixels 100 of the pixel section 106 may also be divided into a plurality of blocks, such that the blocks of the pixel section 106 correspond to the blocks of the above-mentioned vertical scanning circuit 103, horizontal scanning circuit 104, and column circuit 105. may be placed. Further, the horizontal scanning circuit 104 and the column circuit 105 may be divided into blocks corresponding to each pixel column.

It is not essential that the function of the pixel signal processing unit 102 is provided for each pixel 100 in the pixel unit 106, and for example, one pixel signal processing unit 102 may be shared by a plurality of pixels 100. . In this case, the pixel signal processing unit 102 sequentially processes signals output from the plurality of pixels 100.

Further, the pixel signal processing section 102 may be provided on a semiconductor substrate different from the semiconductor substrate 15 on which the photoelectric conversion element 101 is formed. Thereby, the ratio of the area of the photoelectric conversion element 101 to the chip area can be increased, and the sensitivity of the photoelectric conversion element 101 is improved. In this case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are electrically connected to each other via a connection wiring provided for each pixel 100. The vertical scanning circuit 103, the horizontal scanning circuit 104, the signal line 107, and the column circuit 105 may also be provided on a different semiconductor substrate from the photoelectric conversion element 101, and the same effect can be obtained.

FIG. 5 is an example of a block diagram of the pixel 100 in this embodiment. In FIG. 5, one pixel 100 has a photoelectric conversion element 101 and a pixel signal processing section 102. The photoelectric conversion element 101 includes two photoelectric conversion sections 201A and 201B, a control section 202, and a selection circuit 210.

The photoelectric conversion units 201A and 201B generate charge pairs according to incident light by photoelectric conversion. The photoelectric conversion units 201A and 201B correspond to the first avalanche diode and the second avalanche diode described in the first embodiment, respectively. The anodes of the photoelectric conversion units 201A and 201B are connected to a potential line that supplies the potential VL. The cathodes of the photoelectric conversion units 201A and 201B are connected to the selection circuit 210.

A control pulse pSW is input to the selection circuit 210 from the vertical scanning circuit 103 via the drive line 209. The selection circuit 210 selects one of the photoelectric conversion units 201A and 201B based on the control pulse pSW and connects it to the control unit 202. The selection circuit 210 may be a switch circuit whose connection state changes depending on the signal level of the control pulse pSW, for example. As an example, the control pulse pSW is a high level or low level signal corresponding to a value of 0 or 1, respectively, where 0 is a signal that selects the photoelectric conversion unit 201A, and 1 is a signal that selects the photoelectric conversion unit 201B. Assume that there is. When the control pulse pSW is 0, the selection circuit 210 connects the cathode of the photoelectric conversion unit 201A to the control unit 202, and does not connect the cathode of the photoelectric conversion unit 201B to the control unit 202. On the other hand, when the control pulse pSW is 1, the selection circuit 210 connects the photoelectric conversion section 201B and the control section 202, and does not connect the photoelectric conversion section 201A and the control section 202.

A potential based on the potential VH higher than the potential VL is supplied to the cathode of the photoelectric conversion unit (the photoelectric conversion unit 201A or the photoelectric conversion unit 201B) selected by the selection circuit 210. A reverse bias is applied to the anode and cathode of the photoelectric conversion unit selected by the selection circuit 210 so that avalanche multiplication can occur. When photoelectric conversion is performed using incident light while such a reverse bias potential is applied, the generated charges undergo avalanche multiplication and an avalanche current is generated.

Note that when a reverse bias potential is supplied to the photoelectric conversion section and the potential difference between the anode and the cathode is larger than the breakdown voltage, the avalanche diode operates in Geiger mode. A SPAD is a photodiode that uses Geiger mode operation to detect weak signals at the single photon level at high speed.

Furthermore, if the potential difference between the anode and cathode of the photoelectric conversion section is greater than the potential difference that causes the charge generated in the photoelectric conversion section to cause avalanche multiplication, and less than the breakdown voltage, the avalanche diode is in linear mode. Operate. An avalanche diode that performs photodetection in a linear mode is called an avalanche photodiode (APD). In this embodiment, the photoelectric conversion section may operate as either avalanche diode. Note that the potential difference that causes avalanche multiplication is about 6 V or more.

No potential is supplied to the cathodes of photoelectric conversion units not selected by the selection circuit 210. The potential difference between the anode and cathode of the unselected photoelectric conversion units becomes sufficiently small, and the charges generated by the incident light do not flow into the photoelectric conversion units, so avalanche multiplication does not occur.

The control unit 202 is connected to a power supply voltage line that supplies a potential VH higher than the potential VL and to one of the photoelectric conversion units 201A and 201B. The control unit 202 has a function of replacing a change in avalanche current generated in the photoelectric conversion unit with a voltage signal. Further, the control unit 202 functions as a load circuit (quench circuit) during signal amplification by avalanche multiplication. This load circuit suppresses avalanche multiplication by changing the voltage supplied to the photoelectric conversion section. This operation is called a quench operation. Control unit 202 may include, for example, a resistive element or an active quench circuit. The active quench circuit is a circuit that actively suppresses avalanche multiplication by detecting an increase in avalanche current and performing feedback control. As described above, the control unit 202 and the selection circuit 210 function as a selection unit that controls so that avalanche multiplication occurs in either one of the two avalanche diodes.

The pixel signal processing section 102 includes a waveform shaping section 203, a counter circuit 204, and a selection circuit 206. The waveform shaping section 203 shapes the voltage change caused by the single photon level signal and outputs a pulse signal. This pulse signal indicates the incidence of photons. For example, an inverter circuit as shown in FIG. 5 may be used for the waveform shaping section 203. The waveform shaping section 203 may be a circuit in which a plurality of inverters are connected in series, or any other circuit may be used as long as it is effective in shaping the waveform.

The pulse signal output from the waveform shaping section 203 is counted by a counter circuit 204. The counter circuit 204 is equipped with, for example, an N-bit counter (N: a positive integer), and the N-bit counter counts input pulse signals up to approximately 2 to the N power. It is possible to hold the value. The signal obtained by counting is held in the counter circuit 204 as a signal indicating the detection result of the incident light. Further, a control pulse pRES is supplied to the counter circuit 204 from the vertical scanning circuit 103 via a drive line 207. The counter circuit 204 resets the held signal when the control pulse pRES is input.

A control pulse pSEL is supplied to the selection circuit 206 from the vertical scanning circuit 103 via a drive line 208. The selection circuit 206 switches electrical connection or disconnection between the counter circuit 204 and the signal line 107 based on the control pulse pSEL. For the selection circuit 206, for example, a transistor, a buffer circuit for outputting a signal outside the pixel, or the like can be used.

When the pixel unit 106 has a configuration in which a plurality of pixels 100 are arranged in a matrix, the imaging operation may be either a rolling shutter operation or a global electronic shutter operation. For example, the rolling shutter operation is realized by sequentially resetting the count by the counter circuit 204 for each row and sequentially outputting the signal held in the counter circuit 204 for each row.

In addition, a global electronic shutter operation is realized by simultaneously resetting the counts by the counter circuits 204 of all pixel rows and sequentially outputting the signals held in the counter circuits 204 for each row. Note that when applying the global electronic shutter operation, it is desirable to provide a switching means such as a switch so that it is possible to switch whether or not the counter circuit 204 performs counting.

FIG. 6 is a flowchart showing a control method and a signal processing method for the photoelectric conversion device 1010 according to this embodiment. All or part of the processing in FIG. 6 may be based on control by a control device provided in an external device such as an imaging system equipped with the photoelectric conversion device 1010, or may be based on control by a control device provided inside the photoelectric conversion device 1010. It may also be based on control by a control device. A control method and a signal processing method for the photoelectric conversion device 1010 will be explained along FIG. 6.

In step S101, the selection circuit 210 connects the cathode of the photoelectric conversion unit 201A and the control unit 202, and disconnects the cathode of the photoelectric conversion unit 201B and the control unit 202. Thereby, the photoelectric conversion unit 201A enters a state where avalanche multiplication occurs.

In step S102, the photoelectric conversion device 1010 performs imaging based on the light incident on the pixel section 106. By this photographing, each pixel 100 of the pixel unit 106 outputs a count value according to the incident light. Here, it is assumed that the photographing conditions in step S102 are photographing conditions for normal photographing such that light from the outside is incident on the pixel portion 106. The photographing conditions for normal photographing are, for example, when the photoelectric conversion device 1010 is installed in a digital still camera, such that the shutter is opened and incident light is taken into the pixel section 106. That is, the photographing conditions for normal photographing are not the photographing conditions under which no incident light is captured, such as when photographing is performed with the shutter closed.

Thereafter, the count value of each pixel is held in the first frame memory of the plurality of frame memories. Here, a plurality of frame memories are memories that can store a plurality of image data, and may be a storage device provided within the photoelectric conversion device 1010, an imaging system external to the photoelectric conversion device 1010, etc. It may also be a storage device provided in the. This storage device is controlled by a processor provided in a photoelectric conversion device 1010, an imaging system, etc. in which the storage device is provided.

In step S103, the selection circuit 210 connects the cathode of the photoelectric conversion unit 201B and the control unit 202, and disconnects the cathode of the photoelectric conversion unit 201A and the control unit 202. As a result, the photoelectric conversion unit 201B enters a state where avalanche multiplication occurs.

In step S104, the photoelectric conversion device 1010 captures an image of the light incident on the pixel unit 106. The photographing conditions at this time are the photographing conditions for normal photographing, as in step S102. Thereafter, the count value of each pixel is held in a second frame memory of the plurality of frame memories.

The loop process from step S105 to step S109 is a process that is sequentially performed by reading data corresponding to each pixel 100 of the pixel unit 106. That is, when the number of pixels 100 is N, processing is executed a total of N times from the first pixel 100 to the Nth pixel 100. These processes are executed by a processor that controls storage devices that constitute a plurality of frame memories. This processor may be provided in an imaging system or the like inside the photoelectric conversion device 1010 or outside the photoelectric conversion device 1010. Note that if parallel processing is possible in the processor, part or all of these N times of processing may be executed simultaneously.

In step S106, the processor compares the value held in the first frame memory and the value held in the second frame memory. If the value held in the first frame memory is less than or equal to the value held in the second frame memory (YES in step S106), the process moves to step S107. If the value held in the first frame memory is larger than the value held in the second frame memory (NO in step S106), the process moves to step S108.

In step S107, the processor stores the value held in the first frame memory in a third frame memory of the plurality of frame memories. In step S108, the value held in the second frame memory is stored in the third frame memory of the plurality of frame memories. In this way, the processing from step S106 to step S108 transfers the smaller of the value held in the first frame memory and the value held in the second frame memory to the third frame memory for external output. This is a memorizing process.

In step S110, the processor outputs the value of the third frame memory to the outside as an image signal obtained by imaging. Note that this process is not essential if the plurality of frame memories are storage devices external to the photoelectric conversion device 1010.

As described above, it is possible to obtain an image signal based on the smaller value of the signal obtained by the photoelectric conversion unit 201A and the signal obtained by the photoelectric conversion unit 201B. As a result, it is possible to obtain an image signal in which a signal that is less affected by noise current is selected, and an image with good image quality can be obtained.

Note that in the processing from step S106 to step S108, when the value held in the first frame memory is larger than the value held in the second frame memory, the value held in the second frame memory is changed to the first frame memory. The frame memory may be overwritten. In this case, the third frame memory becomes unnecessary.

7(a) to 7(d) are schematic diagrams illustrating in more detail the mechanism by which an image signal less affected by noise current is obtained by the processing shown in FIG. 6. FIGS. 7A to 7D are schematic plan views of an avalanche diode at the first depth X when 16 pixels 100 are arranged in 4 rows and 4 columns.

Similarly to FIG. 2A, each pixel 100 includes first semiconductor regions 71A and 71B of the first conductivity type and a second semiconductor region 76. The hatching applied to the first semiconductor regions 71A and 71B indicates that these regions contain heavy metals and are avalanche diodes with large noise currents. FIG. 7A shows the first semiconductor region 71A of the pixel 100 containing heavy metal in the vicinity of the first semiconductor region 71A with hatching. FIG. 7B shows the first semiconductor region 71B of the pixel 100 containing heavy metal in the vicinity of the first semiconductor region 71B with hatching. FIG. 7C shows the first semiconductor regions 71A and 71B of the pixel 100 containing heavy metal near at least one of the first semiconductor regions 71A and 71B with hatching. FIG. 7D shows only the pixel 100 containing heavy metal near both the first semiconductor regions 71A and 71B, with the first semiconductor regions 71A and 71B hatched. Note that the number and arrangement of the pixels 100 containing heavy metals shown in FIGS. 7(a) to 7(d) are illustrative to explain the effects of this embodiment in an easy-to-understand manner, and may differ in the actual manufacturing process. It does not explain the contamination distribution of heavy metals that occur.

Referring to FIG. 7C, among the 16 pixels 100, seven pixels 100 include at least one avalanche diode that contains heavy metals in the vicinity. That is, seven pixels 100 among the 16 pixels can be a factor that degrades the quality of the image signal.

The value held in the first frame memory is based on the signal output from the first avalanche diode corresponding to the first semiconductor region 71A. Therefore, as shown in FIG. 7A, for the values held in the first frame memory, 4 pixels out of 16 pixels can be a factor that degrades the quality of the image signal.

Further, the value held in the second frame memory is based on the signal output from the second avalanche diode corresponding to the first semiconductor region 71B. Therefore, as shown in FIG. 7B, for the values held in the second frame memory, 4 pixels out of 16 pixels can be a factor that degrades the quality of the image signal.

Since the arrangement and layout of the first semiconductor region 71A and the first semiconductor region 71B are the same, if the distribution of heavy metals in the semiconductor substrate 15 is uniform, the two avalanche diodes will generate a large noise current. The probability that .

Through the process shown in FIG. 6, the smaller count value of the first frame memory and the second frame memory is selected for the third frame memory. Therefore, with respect to the values held in the third frame memory, only one pixel out of 16 pixels can be a factor that degrades the quality of the image signal, as shown in FIG. 7(d). That is, by selecting the smaller count value of the first frame memory and the second frame memory as the value held in the third frame memory, the occurrence of quality deterioration of pixel signals due to heavy metals is avoided. The frequency has been reduced.

FIG. 8 is a graph showing the cumulative relative frequency of noise current values for signals output from a large number of pixels 100 including avalanche diodes according to this embodiment. The cumulative relative frequency in this graph is normalized by accumulating the frequencies of a plurality of acquired signals in order of increasing noise current value and dividing by the total number of signals. In FIG. 8, graphs of values held in the first, second, and third frame memories are displayed in an overlapping manner. Further, in FIG. 8, the noise current having a value equal to or lower than the level P is caused by a diffusion current. Further, the noise current near level Q is caused by noise current caused by heavy metals and the like.

As described with reference to FIG. 7, the value held in the third frame memory is the smaller count value selected from the first frame memory and the second frame memory. The probability that a value affected by the noise current due to heavy metals is held in both the first frame memory and the second frame memory is the product of the probabilities in each frame memory. Therefore, the cumulative relative frequency of the third frame memory at level Q is the product of the cumulative relative frequencies of the first and second frame memories. Therefore, if the probability of occurrence of noise current due to heavy metals in the two avalanche diodes is the same, the cumulative relative frequency of the third frame memory is the square of the cumulative relative frequency of the first frame memory. Therefore, according to this embodiment, the probability that an image signal includes a signal affected by a noise current can be significantly reduced.

Note that the number of avalanche diodes included in one pixel 100 may be three or more. If the number is n, the probability of occurrence of a noise current is the nth power of one, and the influence of the noise current can be further reduced.

As described above, according to the present embodiment, it is possible to provide a photoelectric conversion device that can reduce deterioration in signal quality caused by noise current, similar to the first embodiment.

[Third embodiment]
A photoelectric conversion device according to a third embodiment will be described using FIGS. 9 to 11. Portions having the same functions as those in the first or second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 9 is a flowchart showing a control method and a signal processing method for the photoelectric conversion device 1010 according to this embodiment. All or part of the processing in FIG. 9 may be realized by a circuit provided within the photoelectric conversion device 1010. Further, all or a part of the processing in FIG. 9 may be based on control by a control device provided in an external device such as an imaging system in which the photoelectric conversion device 1010 is mounted, and the processing shown in FIG. It may be based on control by a control device provided. A method of controlling the photoelectric conversion device 1010 and a method of signal processing will be explained along FIG. 9.

In step S201, the photoelectric conversion device 1010 sets imaging conditions for pre-setting. Here, it is assumed that the photographing conditions for pre-setting are photographing conditions such that no light from the outside enters the pixel portion 106. This pre-setting is a setting for acquiring a signal corresponding to a noise current. As a specific example, if the photoelectric conversion device 1010 is installed in a digital still camera, the shooting conditions for pre-setting can be achieved by closing the shutter and preventing incident light from entering the pixel section 106. Ru.

In step S202, the selection circuit 210 connects the cathode of the photoelectric conversion unit 201A and the control unit 202, and disconnects the cathode of the photoelectric conversion unit 201B and the control unit 202. Thereby, the photoelectric conversion unit 201A enters a state where avalanche multiplication occurs.

In step S203, the photoelectric conversion device 1010 performs imaging based on the light incident on the pixel unit 106. By this photographing, a count value corresponding to the incident light from each pixel 100 of the pixel section 106 is outputted from the counter circuit 204. In this process, the accumulation time of the incident light is set to a longer time than during normal photography. This is because photography for pre-setting is for acquiring a signal corresponding to a noise current, and it is desirable to acquire it over a sufficiently long time in order to prevent erroneous determination due to disturbance. This accumulation time can be, for example, about 1 second.

The loop processing from step S204 to step S208 is processing performed for each pixel 100 of the pixel unit 106. Part or all of the processes from step S204 to step S208 may be executed simultaneously, or may be executed sequentially for each pixel 100. For example, in the process using the SR latch circuit described below, the processes from step S204 to step S208 can be performed in parallel for each pixel 100.

In step S205, the photoelectric conversion device 1010 compares the count value output from the counter circuit 204 and the set value. If the count value is less than or equal to the set value (YES in step S205), the process moves to step S206. If the count value is larger than the set value (NO in step S205), the process moves to step S207.

In step S206, the memory device in the photoelectric conversion device 1010 sets the setting value of the corresponding pixel 100 to 0. In step S207, the memory device in the photoelectric conversion device 1010 sets the setting value of the corresponding pixel 100 to 1. Here, the memory device may be any device that can store 1 bit of information for each pixel 100. It is desirable for this memory device to stably hold a logical value regardless of the holding period, and an example of this is the SR latch circuit described below. Further, the memory device may be a non-volatile memory so that information is not lost even when the power is cut off.

In step S209, the selection circuit 210 connects the cathode of the photoelectric conversion unit 201A and the control unit 202 for the pixel 100 whose setting value is 0, and disconnects the cathode of the photoelectric conversion unit 201B and the control unit 202. state. Thereby, the photoelectric conversion unit 201A enters a state where avalanche multiplication occurs.

In step S210, the selection circuit 210 connects the cathode of the photoelectric conversion unit 201B and the control unit 202 for the pixel 100 whose setting value is 1, and disconnects the cathode of the photoelectric conversion unit 201A and the control unit 202. state. As a result, the photoelectric conversion unit 201B enters a state where avalanche multiplication occurs.

In step S211, the photoelectric conversion device 1010 sets photographing conditions for normal photographing. The shooting conditions for normal shooting are the same as those described in the second embodiment. In step S212, the photoelectric conversion device 1010 performs photography with the accumulation time set to the normal value under the photography conditions for normal photography, and acquires a count value used as an image signal. Note that the normal value shooting time is shorter than the long shooting time for pre-setting.

As described above, similarly to the second embodiment, it is possible to obtain an image signal in which a signal that is less affected by noise current is selected, and an image with good image quality can be obtained.

Note that in step S202 of this process, the photoelectric conversion unit 201B may be placed in a state where avalanche multiplication occurs instead of the photoelectric conversion unit 201A. In this case, the correspondence between the set values and the photoelectric conversion units in steps S209 and S210 is reversed.

Next, an example of a circuit that can realize the process of FIG. 9 will be described with reference to FIGS. 10 and 11. Note that the circuits shown in FIGS. 10 and 11 are only examples of means that can realize the processing of this embodiment, and other embodiments may be used as long as the processing of FIG. 9 can be realized. FIG. 10 is a block diagram of the pixel 100 according to this embodiment. The pixel signal processing unit 102 of the pixel 100 further includes an output determination circuit 212 in addition to the elements described in the second embodiment.

The output determination circuit 212 is a circuit that functions as a determination unit that stores the determination result of whether the count value exceeds a predetermined value at the time of pre-setting as a set value and outputs it to the selection circuit 210. The output determination circuit 212 receives the output signal from the counter circuit 204 and the control pulses pRES and pENB output from the vertical scanning circuit 103. The control pulse pRES is input to the output determination circuit 212 via the drive line 207, and the control pulse pENB is input to the output determination circuit 212 via the drive line 209. A control pulse pSW, which is an output signal of the output determination circuit 212, is input to the selection circuit 210. Note that the output signal from the counter circuit 204 that is input to the output determination circuit 212 may be the value of some bits of the digital value that constitutes the count value.

Control pulse pENB is an enable signal for enabling output determination circuit 212. The output determination circuit 212 effectively accepts the signal input from the counter circuit 204 only when the value of the control pulse pENB is 1. When the value of the control pulse pENB is 0, the output determination circuit 212 continues to hold the previous state regardless of the signal from the counter circuit 204. For example, in the example shown in FIG. 9, during pre-setting, the value of the control pulse pENB is set to 1 so that the settings can be changed, and during normal shooting, the value of the control pulse pENB is set to 0 and the settings cannot be changed. Thus, the state of the output determination circuit 212 can be appropriately controlled.

The control pulse pRES is a signal that resets the output determination circuit 212. The reset of the output determination circuit 212 is desirably performed before pre-setting, and can be performed, for example, before the process of step S202. In the example shown in FIG. 10, the control pulse pRES used to reset the counter circuit 204 is also used in common by the output determination circuit 212, so that the reset timing can be made to match. However, this is not essential, and the counter circuit 204 and the output determination circuit 212 may be reset by mutually different control pulses.

FIG. 11 is a block diagram of the output determination circuit 212 according to this embodiment. The output determination circuit 212 includes AND circuits 212A, 212B and an SR latch circuit 212C. The control pulse pENB and the output signal from the counter circuit 204 are input to the AND circuit 212A. The AND circuit 212A outputs the logical product of the control pulse pENB and the output signal from the counter circuit 204. The output signal of the AND circuit 212A is input to the set terminal S of the SR latch circuit 212C. A control pulse pENB and a control pulse pRES are input to the AND circuit 212B. AND circuit 212B outputs the logical product of control pulse pENB and control pulse pRES. The output signal of the AND circuit 212B is input to the reset terminal R of the SR latch circuit 212C. A control pulse pSW is output from the output terminal Q of the SR latch circuit 212C.

The signal output from the counter circuit 204 to the output determination circuit 212 may be, for example, the value of the intermediate bit of the counter circuit 204. The value of the intermediate bit functions as a set value in step S205. If the counter circuit 204 is a 16-bit counter, the value of the 8th bit of the counter circuit 204 may be the value of the intermediate bit. In this case, a value corresponding to 128LSB (Least Significant Bit) (10000000 in binary) can be set as the setting value in step S205.

In the pre-setting process (when the value of the control pulse pENB is 1), when 128 pulses based on photocharges are counted by the counter circuit 204, the output value of the counter circuit 204 becomes 1, and the output value of the SR latch circuit 212C becomes 1. 1 is input to the set terminal S. As a result, the output signal of the SR latch circuit 212C changes from 0 to 1. The output signal of the SR latch circuit 212C is a control pulse pSW, which is used by the selection circuit 210 to select the avalanche diode connected. As described above, the process of switching the connected avalanche diode when a noise current larger than the set value is detected under the pre-setting imaging conditions is realized.

As described above, according to the present embodiment, it is possible to provide a photoelectric conversion device that can reduce deterioration in signal quality caused by noise current, similar to the first embodiment and the second embodiment.

[Fourth embodiment]
A photoelectric conversion device according to a fourth embodiment will be described using FIGS. 12 and 13. Portions having the same functions as those in the first to third embodiments are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 12 is a block diagram of the pixel 100 according to this embodiment. The photoelectric conversion element 101 of this embodiment includes a variable resistance circuit 211 in place of the control section 202 and selection circuit 210 in FIG. Furthermore, the pixel signal processing unit 102 of this embodiment includes a waveform shaping unit 213 configured with a NOR circuit in place of the waveform shaping unit 203 configured with an inverter in FIG.

The variable resistance circuit 211 is provided between the power supply voltage line that supplies the potential VH and the cathodes of the photoelectric conversion units 201A and 201B. A control pulse pSW is input to the variable resistance circuit 211 from the vertical scanning circuit 103 via the drive line 209. The variable resistance circuit 211 changes the resistance value between the power supply voltage line and the photoelectric conversion unit 201A and the resistance value between the power supply voltage line and the photoelectric conversion unit 201B depending on the signal level of the control pulse pSW.

One of the two resistance values is set to a large resistance value (first resistance value) so that the potential difference between the anode and the cathode is close to zero. This makes it possible to prevent avalanche multiplication from occurring in the avalanche diode. The other of the two resistance values is a resistance value adjusted so that avalanche multiplication occurs in the avalanche diode and a potential change due to the current generated by the avalanche multiplication causes logic inversion in the waveform shaping section 213 ( second resistance value).

By setting the resistance value between the power supply voltage line and the photoelectric conversion unit 201A to the second resistance value, and setting the resistance value between the power supply voltage line and the photoelectric conversion unit 201B to the first resistance value, photoelectric conversion is performed. The photoelectric conversion element 101 can be controlled so that avalanche multiplication occurs only in the portion 201A. Furthermore, by setting the resistance value between the power supply voltage line and the photoelectric conversion unit 201A to the first resistance value, and setting the resistance value between the power supply voltage line and the photoelectric conversion unit 201B to the second resistance value, The photoelectric conversion element 101 can be controlled so that avalanche multiplication occurs only in the photoelectric conversion unit 201B. As described above, the variable resistance circuit 211 functions as a selection unit that controls so that avalanche multiplication occurs in either one of the two avalanche diodes.

Specifically, the variable resistance circuit 211 may be constructed of NMOS or PMOS. The NMOS or PMOS can be switched between an ON state in which an inversion layer (channel) is formed between the source and drain and an OFF state in which an inversion layer is not formed, depending on the gate potential. Further, in NMOS or PMOS, the size of the inversion layer, that is, the resistance value can be changed depending on the gate potential. Therefore, NMOS or PMOS can function as a variable resistance element that can switch between the two resistance values described above.

FIG. 13 is an example of an equivalent circuit diagram of the variable resistance circuit 211 according to this embodiment. The variable resistance circuit 211 includes an inverter 211A, input level conversion circuits 211B and 211C, and variable resistance elements 211D and 211E. The variable resistance elements 211D and 211E are, for example, NMOS, but may be PMOS. The input level conversion circuits 211B and 211C are circuits that convert the potential level of the input control pulse pSW to a level suitable for controlling the resistance value of the NMOS. Specifically, when the control pulse pSW is at a high level, the input level conversion circuits 211B and 211C have the variable resistance element 211D in the on state and the second resistance value, and the variable resistance element 211E in the off state and the second resistance value. , converts the potential level so that it has the first resistance value.

The control pulse pSW is input as is to the input level conversion circuit 211B. The signal output from the input level conversion circuit 211B is input to the gate of the variable resistance element 211D. The control pulse pSW inverted by the inverter 211A is input to the input level conversion circuit 211C. The signal output from the input level conversion circuit 211C is input to the gate of the variable resistance element 211E.

The drains of variable resistance elements 211D and 211E are connected to a power supply voltage line that supplies potential VH. The source of the variable resistance element 211D is connected to the cathode of the photoelectric conversion unit 201A, and the source of the variable resistance element 211E is connected to the cathode of the photoelectric conversion unit 201B. With the above configuration, the variable resistance circuit 211 can change the resistance so that avalanche multiplication occurs in either one of the two avalanche diodes.

As described above, according to the present embodiment, it is possible to provide a photoelectric conversion device that can reduce signal quality deterioration caused by noise current, similar to the first to third embodiments.

[Fifth embodiment]
An imaging system according to a fifth embodiment will be described using FIG. 14. The imaging system of this embodiment includes the photoelectric conversion devices of the first to fourth embodiments. The imaging system is a device used to take still images or moving images, such as a digital still camera, a digital video camera, or a digital camera for a mobile phone.

FIG. 14 is a block diagram of an imaging system according to a fifth embodiment. The imaging system includes a lens unit 1401, a lens driving device 1402, a shutter 1403, a shutter driving device 1404, a photoelectric conversion device 1405, an imaging signal processing circuit 1406, and a timing generation unit 1407. The imaging system further includes a memory section 1408, an overall control/calculation section 1409, a recording medium control I/F (Interface) section 1410, a recording medium 1411, an external I/F section 1412, and a photometry device 1413.

The lens portion 1401 is a portion that forms an optical image of a subject on a photoelectric conversion device 1405. A lens driving device 1402 is a device that drives the lens portion 1401. A lens driving device 1402 performs zoom control, focus control, aperture control, etc. by driving the lens unit 1401. The shutter 1403 is an optical member that blocks incident light, and for example, a mechanical shutter may be used. Furthermore, the shutter 1403 may also have the function of an aperture. A shutter drive device 1404 controls opening and closing of the shutter 1403, etc.

The photoelectric conversion device 1405 is the photoelectric conversion device of the first to fourth embodiments, and converts an optical image of a subject formed by the lens unit 1401 into an image signal and acquires the image signal. The image signal processing circuit 1406 is a circuit that performs various corrections, data compression, etc. on the image signal output from the photoelectric conversion device 1405. The timing generator 1407 is a circuit that outputs various timing signals to the photoelectric conversion device 1405 and the imaging signal processing circuit 1406.

The overall control/calculation unit 1409 is a control circuit that performs various calculations and controls the entire imaging system. The memory unit 1408 is a recording device for temporarily recording image data output from the imaging signal processing circuit 1406. The recording medium control I/F unit 1410 is an interface for recording on or reading from the recording medium 1411. The recording medium 1411 is a removable recording medium such as a semiconductor memory, and is used for recording or reading image data. The external I/F unit 1412 is an interface for providing various information, photographed images, etc. to the outside, and may be a communication interface with other information processing devices such as a computer, or a user interface such as a display device. There may be.

Next, a description will be given of the operation during photographing when the imaging system is a digital still camera equipped with a distance measurement function. When the main power source of the imaging system is turned on, a power source for controlling the imaging system and a power source for imaging that supplies power to the imaging signal processing circuit 1406 and the like are sequentially turned on.

When the user presses a release button (not shown), the photoelectric conversion device 1405 acquires an image signal, the overall control/calculation unit 1409 performs distance measurement calculation based on the data of the image signal, and based on the result. Calculate the distance to the subject. Thereafter, the lens driving device 1402 drives the lens unit 1401 based on the calculated distance to determine whether or not it is in focus, and if it is not in focus, it drives the lens unit 1401 again. Focus adjustment is performed through processing. In addition to using the image signal acquired by the photoelectric conversion device 1405, the distance measurement calculation may be performed by a dedicated distance measurement device (not shown).

When focus is confirmed, the imaging system starts a shooting operation. After the photographing operation is completed, the image signal output from the photoelectric conversion device 1405 is processed in the image signal processing circuit 1406 and written into the memory section 1408 under the control of the overall control/calculation section 1409. The imaging signal processing circuit 1406 performs data rearrangement, addition, and the like. The data recorded in the memory section 1408 is recorded on the recording medium 1411 via the recording medium control I/F section 1410 under the control of the overall control/calculation section 1409. Further, this data may be input to a computer or the like via the external I/F section 1412. The computer can perform processing such as image processing on data output from the imaging system.

The imaging system of this embodiment includes the photoelectric conversion devices of the first to fourth embodiments. The photoelectric conversion devices of the first to fourth embodiments are configured to reduce deterioration in signal quality caused by noise current. Therefore, according to this embodiment, an imaging system capable of acquiring images with less noise is provided.

[Sixth embodiment]
An imaging system and a moving body according to a sixth embodiment of the present invention will be described using FIGS. 15(a) and 15(b). FIGS. 15A and 15B are diagrams showing the configurations of an imaging system 300 and a moving body according to this embodiment.

FIG. 15(a) shows an example of an imaging system 300 related to a vehicle-mounted camera. The imaging system 300 includes a photoelectric conversion device 310. The photoelectric conversion device 310 of this embodiment is the photoelectric conversion device described in any one of the above-described first to fourth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 310, and an image processing unit 312 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 310. ) is provided. The imaging system 300 also includes a distance measurement unit 316 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 318 that determines whether there is a possibility of a collision based on the calculated distance. and has. Here, the parallax calculation unit 314 and the distance measurement unit 316 are an example of distance information acquisition means that acquires distance information to the target object. That is, distance information is information regarding parallax, defocus amount, distance to a target object, and the like. The collision determination unit 318 may use any of these distance information to determine the possibility of collision. The distance information acquisition means may be realized by specially designed hardware or may be realized by a software module. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Further, the imaging system 300 is connected to a control ECU 330 that is a control device that outputs a control signal for generating a braking force on the vehicle based on the determination result of the collision determination section 318. The imaging system 300 is also connected to a warning device 340 that issues a warning to the driver based on the determination result of the collision determination unit 318. For example, if the collision determination unit 318 determines that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and reduce damage by applying the brakes, releasing the accelerator, or suppressing engine output. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, or applying vibration to the seat belt or steering wheel.

In this embodiment, the imaging system 300 images the surroundings of the vehicle, for example, the front or rear. FIG. 15(b) shows an example of the arrangement of the imaging system 300 when imaging the front of the vehicle (imaging range 350). Vehicle information acquisition device 320 sends instructions to imaging system 300 or photoelectric conversion device 310. With such a configuration, the accuracy of distance measurement can be further improved.

Although an example of control to avoid collisions with other vehicles has been described, it can also be applied to control to automatically drive by following other vehicles, control to automatically drive to avoid running out of the lane, etc. Furthermore, the imaging system 300 can be applied not only to vehicles such as own vehicle, but also to mobile objects (mobile devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to mobile objects but also to a wide range of devices that use object recognition, such as intelligent transportation systems (ITS).

[Modified embodiment]
The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or an example in which a part of the configuration in another embodiment is replaced is also an embodiment of the present invention.

Further, the devices or systems shown in the fifth and sixth embodiments are configuration examples of devices or systems to which the photoelectric conversion device of the present invention can be applied. The device or system is not limited to the configuration shown in FIG. 14 or 15.

In some embodiments described above, the pixel 100 including two photoelectric conversion units 201A and 201B is illustrated, but the number of photoelectric conversion units may be greater than two. That is, in some of the embodiments described above, the plurality of photoelectric conversion units can be said to consist of only the first group including the first avalanche diode and the second group including the second avalanche diode. The number of avalanche diodes included in each of the first group and the second group may be one, or two or more. At this time, the selection unit performs control such that the operating state/non-operating state of the first group of photoelectric conversion units and the second group of photoelectric conversion units are exclusive. That is, in the first case where the first group is controlled to be in the active state, the selection unit controls the second group to be in the non-active state, and in the second case where the second group is controlled to be in the active state, the selection unit is configured to control the first group to be in the non-active state. Control the group to a non-operating state. In both the first case and the second case, control is performed so that no photoelectric conversion unit (avalanche diode) is in an operating state. Furthermore, control can be performed so that the number of photoelectric conversion units in the operating state is equal in both the first case and the second case. Furthermore, in the example shown in FIG. 9 in which the operating state/non-operating state is controlled depending on whether or not the noise exceeds a predetermined value, the selection section determines whether the noise included in the signal output from the first group is If the predetermined value is exceeded, the first group is controlled to be inactive, and the second group is controlled to be in active state.

The present invention provides a system or device with a program that implements one or more functions of the embodiments described above via a network or a storage medium, and one or more processors in a computer of the system or device reads and executes the program. This can also be achieved by processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

Note that the above-described embodiments are merely examples of implementation of the present invention, and the technical scope of the present invention should not be interpreted to be limited by these embodiments. That is, the present invention can be implemented in various forms without departing from its technical idea or main features.

100 Pixel 101 Photoelectric conversion element 102 Pixel signal processing section 201A, 201B Photoelectric conversion section (avalanche diode)
202 Control unit 210 Selection circuit

Claims (18)

a plurality of pixels each including a plurality of avalanche diodes ;
a selection unit that controls each of the plurality of avalanche diodes of the plurality of pixels to an operating state in which avalanche multiplication can occur or a non-operating state in which avalanche multiplication does not occur ;
has
The plurality of avalanche diodes of each of the plurality of pixels include a first group of avalanche diodes and a second group of avalanche diodes ,
The selection unit selects each of the plurality of pixels into a first state in which the first group of avalanche diodes are in the operating state and the second group of avalanche diodes are in the inactive state; a second state in which the avalanche diodes of the group are in the operative state and the avalanche diodes of the first group are in the non-operative state;
A photoelectric conversion device characterized in that each of the plurality of pixels does not have an avalanche diode that is in the operating state when controlled to the first state and the second state . The photoelectric conversion device according to claim 1 , wherein in each of the plurality of pixels, the number of avalanche diodes in the first group and the number of avalanche diodes in the second group are the same . The selection unit selects at least one of the first group of avalanche diodes and the second group of avalanche diodes so that avalanche multiplication occurs in either one of the first group of avalanche diodes and the second group of avalanche diodes. The photoelectric conversion device according to claim 1 or 2, wherein a bias voltage supplied to one side is controlled. The photovoltaic device according to claim 3, wherein the selection unit controls the bias voltage so that a reverse bias voltage is supplied to one of the first group of avalanche diodes and the second group of avalanche diodes. conversion device. The photoelectric conversion according to claim 4, wherein the selection unit controls the bias voltage so that the other of the first group of avalanche diodes and the second group of avalanche diodes is set to floating or zero bias. Device. The pixel includes a well region surrounded by an element isolation region,
The photoelectric conversion device according to any one of claims 1 to 5, wherein the first group of avalanche diodes and the second group of avalanche diodes are formed in the well region. The selection section includes a selection circuit and a quench circuit,
7. The selection circuit is arranged between the quench circuit and at least one of the first group of avalanche diodes and the second group of avalanche diodes. The photoelectric conversion device described in . The selection section includes a variable resistance element,
The variable resistance element is arranged between at least one of the first group of avalanche diodes and the second group of avalanche diodes and a potential line that provides a predetermined potential. 6. The photoelectric conversion device according to any one of 6. a first frame memory that stores an output value when avalanche multiplication occurs in the first group of avalanche diodes;
a second frame memory that stores an output value when avalanche multiplication occurs in the second group of avalanche diodes;
It further has
Claims 1 to 8, wherein the smaller of the value stored in the first frame memory and the value stored in the second frame memory is output as the output value of the pixel. The photoelectric conversion device according to any one of the items. a first frame memory that stores an output value when avalanche multiplication occurs in the first group of avalanche diodes;
a second frame memory that stores an output value when avalanche multiplication occurs in the second group of avalanche diodes;
a third frame memory that stores the smaller of the value stored in the first frame memory and the value stored in the second frame memory;
The photoelectric conversion device according to any one of claims 1 to 8, further comprising: further comprising a determination unit that outputs a control signal indicating whether an output value of one of the first group of avalanche diodes and the second group of avalanche diodes exceeds a predetermined value;
The photoelectric conversion device according to any one of claims 1 to 8, wherein the selection unit performs control to select an avalanche diode in which avalanche multiplication occurs based on the output of the determination unit. The determination unit generates the control signal based on an output value of the first group of avalanche diodes or the second group of avalanche diodes obtained under a condition that no light is incident on the pixel. The photoelectric conversion device according to claim 11. The photoelectric conversion device has a plurality of microlenses ,
13. The plurality of microlenses are arranged with respect to the plurality of pixels such that one microlens corresponds to one pixel. Photoelectric conversion device. a plurality of pixels each including a plurality of avalanche diodes ;
a selection unit that controls each of the plurality of avalanche diodes of the plurality of pixels to an operating state in which avalanche multiplication can occur or a non-operating state in which avalanche multiplication does not occur ;
has
The plurality of avalanche diodes of each of the plurality of pixels include a first group of avalanche diodes and a second group of avalanche diodes ,
For each of the plurality of pixels, if noise included in the signal output from the first group of avalanche diodes exceeds a predetermined value, the selection unit selects the first group of avalanche diodes from the non-avalanche diodes. control the avalanche diodes of the second group to the operating state , and if noise included in the signal output from the second group of avalanche diodes exceeds a predetermined value, the avalanche diodes of the second group are controlled to the operating state; controlling the second group of avalanche diodes to the non-operating state, and controlling the first group of avalanche diodes to the operating state ;
A photoelectric conversion device characterized by: a plurality of pixels each including a plurality of avalanche diodes ;
a selection unit that controls each of the plurality of avalanche diodes of the plurality of pixels to an operating state in which avalanche multiplication can occur or a non-operating state in which avalanche multiplication does not occur ;
has
The plurality of avalanche diodes of each of the plurality of pixels include a first group of avalanche diodes and a second group of avalanche diodes ,
The selection unit selects each of the plurality of pixels into a first state in which the first group of avalanche diodes are in the operating state and the second group of avalanche diodes are in the inactive state; a second state in which the avalanche diodes of the group are in the operative state and the avalanche diodes of the first group are in the non-operative state;
A photoelectric conversion device, wherein each of the plurality of pixels has an equal number of avalanche diodes in the operating state when controlled to the first state and the second state . The selection section includes a quench circuit shared by the plurality of avalanche diodes, and a selection circuit arranged between the plurality of avalanche diodes and the quench circuit.
The photoelectric conversion device according to any one of claims 1 to 15. A photoelectric conversion device according to any one of claims 1 to 16 ,
An imaging system comprising: a signal processing unit that processes a signal output from the photoelectric conversion device. A mobile object,
A photoelectric conversion device according to any one of claims 1 to 16 ,
distance information acquisition means for acquiring distance information to a target object from a parallax image based on a signal from the photoelectric conversion device;
A moving object, comprising: control means for controlling the moving object based on the distance information.

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