JP7456113B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7456113B2 JP7456113B2 JP2019187825A JP2019187825A JP7456113B2 JP 7456113 B2 JP7456113 B2 JP 7456113B2 JP 2019187825 A JP2019187825 A JP 2019187825A JP 2019187825 A JP2019187825 A JP 2019187825A JP 7456113 B2 JP7456113 B2 JP 7456113B2
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Description
特許文献1 特開2015-185742号公報
図3は、実施例1に係る半導体装置100の一部の断面及びその電気的接続を示す図である。一例として、図3に示す断面は、図2におけるa-a'断面に対応する。a-a'断面は、エミッタ領域12、ベース領域14、並びにゲートトレンチ部40及びダミートレンチ部30を通るXZ面である。本例の半導体装置100は、a-a'断面において、半導体基板10、層間絶縁膜38、エミッタ電極52及びコレクタ電極24を有する。
実施例2は、半導体装置100が1つのゲートパッドと2つのゲートランナーを備え、オフのタイミングを合わせる構成例である。図4は、実施例2に係る半導体装置100の一部の断面及びその電気的接続を示す図である。一例として、図4に示す断面は、図2におけるa-a'断面に対応する。
実施例3は、係る半導体装置100が1つのゲートパッドを備え、オフのタイミングを合わせる構成例である。図6は、実施例3に係る半導体装置100の一部の断面及びその電気的接続を示す図である。一例として図6に示す断面は、図2におけるa-a'断面に対応する。
実施例4は、ゲートランナーが後述する外周ゲートランナー及び内側ゲートランナーを有する構成例である。図7は、実施例4に係る半導体装置100の上面を示す図である。一例として、図7に示す半導体装置100は、1つのゲートパッドGを有する。
実施例4-1は実施例4の一例であり、オフのタイミングを合わせる構成例である。図8は、実施例4-1に係る半導体装置100の一部の断面を示す図である。一例として、図8に示す断面は、図2におけるa-a'断面に対応する。図8は、図7の内側ゲートランナー134によりオフのタイミングを合わせる場合の電気的接続の一例を併せて示す。
実施例4-2は実施例4の一例であり、オフのタイミングを合わせる他の構成例である。図9は、実施例4-2に係る半導体装置100の一部の断面を示す図である。図9は、図8と同様に、内側ゲートランナー134が第2ゲートトレンチ部46の直上を第2ゲートトレンチ部46の延伸方向に延伸し、オフのタイミングを合わせる場合の電気的接続の他の一例を示す。以下、図8との相違点を中心に説明する。
実施例5は実施例4の変形例である。図10Aは、実施例5に係る半導体装置100の上面を示す図である。図10Aに示す半導体装置100は、図7と同様に、外周ゲートランナー133と内側ゲートランナー134とを備える。以下、図7との相違点を中心に説明する。
実施例5-1は実施例5の一例である。図10Bは、実施例5-1に係る半導体装置100の一部の上面を示す図である。一例として、図10Bは、図10Aにおける領域Aの拡大図に対応する。本例の内側ゲートランナー134は表面保護層53により覆われ、表面保護層53はエミッタ電極52から露出しているが、説明の便宜上、エミッタ電極52及び表面保護層53は省略している。内側ゲートランナー134は、コンタクトホール55を通って、第1ゲートトレンチ部45又は第2ゲートトレンチ部46の何れか一方のゲート導電部44と接続される。
実施例5-2は実施例5の他の一例である。図11Aは、実施例5-2に係る半導体装置100の一部の上面を示す図である。一例として、図11Aは、図10Aにおける領域Aの拡大図に対応する。本例の内側ゲートランナー134は、コンタクトホール55を通って、第1ゲートトレンチ部45又は第2ゲートトレンチ部46の何れか一方のゲート導電部44と接続される。本例の内側ゲートランナー134はエミッタ電極52の内部に配置されているが、説明の便宜上、エミッタ電極52は省略している。
実施例5-3は実施例5の他の一例である。図12Aは、実施例5-3に係る半導体装置100の一部の上面を示す図である。一例として、図12Aは、図10Aにおける領域Aの拡大図に対応する。本例の内側ゲートランナー134は、コンタクトホール55を通って、第1ゲートトレンチ部45又は第2ゲートトレンチ部46の何れか一方のゲート導電部44と接続される。また本例では、内側ゲートランナー134の下方において、ダミートレンチ部30のダミー導電部34及びメサ部60も、コンタクトホール54、56を通ってエミッタ電極52と接続される。本例の内側ゲートランナー134はエミッタ電極52の内部に配置されているが、説明の便宜上、エミッタ電極52は省略している。
実施例5-4は実施例5の他の一例である。図13A~図13Dは、実施例5-4に係る半導体装置100の一部の断面を示す図である。具体的には、図13Aは、図12Aにおけるn-n'断面に対応し、図13Bは、図12Aにおけるo-o'断面に対応し、図13Cは、図12Aにおけるt-t'断面に対応し、図13Dは、図12Aにおけるu-u'断面に対応する。本例の半導体装置100の上面図は、図12Aと共通するため省略する。ただし本例の内側ゲートランナー134は、図12A~図12Eを参照して説明した例と異なり、エミッタ電極52の上方に配置されている。なお、説明の便宜上、エミッタ電極52は省略している。
実施例6は、図7と同様に、ゲートランナーが外周ゲートランナー及び内側ゲートランナーを有する構成例である。図14Aは、実施例6に係る半導体装置100の一部の上面を示す図である。一例として、図14Aは、図7における領域Aの拡大図に対応する。本例の内側ゲートランナー134はエミッタ電極52の内部に配置されているが、説明の便宜上、エミッタ電極52は省略している。本例の内側ゲートランナー134は、図7と同様に、第1ゲートトレンチ部45又は第2ゲートトレンチ部46の何れか一方のゲートトレンチ部の直上を当該ゲートトレンチ部の延伸方向に延伸する。
実施例6-1は実施例6の一例である。図14Bは、実施例6-1に係る半導体装置100の一部の断面を示す図である。具体的には、図14Bは、図14Aにおけるk-k'断面に対応する。本例のエミッタ電極52は、第1層52-1、第2層52-2、第3層52-3、第4層52-4、第5層52-5及び第6層52-6を有する。第1層52-1、第2層52-2、第3層52-3、第4層52-4、第5層52-5及び第6層52-6は、半導体基板10の上面21から+Z軸方向に順に積層されており、一例として、第1層52-1、第3層52-3及び第5層52-5がビア層、第2層52-2、第4層52-4及び第6層52-6が金属層である。
実施例6-2は実施例6の他の一例である。図15は、実施例6-2に係る半導体装置100の一部の断面を示す図である。具体的には、図15は、図14Aにおけるk-k'断面に対応する。本例のエミッタ電極52は、第1層52-1及び第2層52-2を有する。第1層52-1及び第2層52-2は、半導体基板10の上面21から+Z軸方向に順に積層されており、一例として、第1層52-1がビア層、第2層52-2が金属層である。
実施例7は、半導体装置100が1つのゲートパッドと2つのゲートランナーを備え、オンのタイミングを合わせる構成例である。図16は、実施例7に係る半導体装置100の一部の断面及びその電気的接続を示す図である。図16に示す断面は、図2におけるa-a'断面に対応する。
実施例8は、オン及びオフの両方のタイミングを合わせる構成例である。図17は、実施例8に係る半導体装置100の一部の断面及びその電気的接続を示す図である。図17に示す断面は、図2におけるa-a'断面に対応する。
Claims (16)
- トランジスタ部とダイオード部とを有する半導体基板を備え、
前記トランジスタ部及び前記ダイオード部の双方が、
前記半導体基板の内部に設けられた第1導電型のドリフト領域と、
前記半導体基板の内部において、前記ドリフト領域の上方に設けられた第2導電型のベース領域と、
を有し、
前記半導体基板の内部において、前記ベース領域の下方に、前記トランジスタ部の少なくとも一部から前記ダイオード部にわたって、ライフタイムキラーを含むライフタイム制御領域が設けられ、
前記トランジスタ部は、
前記半導体基板の上面視で、前記ダイオード部から離間する主領域と、
前記半導体基板の上面視で、前記主領域と前記ダイオード部との間に位置し、前記ライフタイム制御領域と重なる境界領域と、
前記半導体基板の上面から前記ベース領域を貫通して前記ドリフト領域まで設けられた複数のゲートトレンチ部と
を有し、
前記複数のゲートトレンチ部は、
前記主領域に設けられた第1ゲートトレンチ部と、
前記境界領域に設けられた第2ゲートトレンチ部と
を含み、
前記第1ゲートトレンチ部とゲートパッドとの間のゲート信号の伝送経路における全ての抵抗成分を合算したゲート抵抗成分は、前記第2ゲートトレンチ部とゲートパッドとの間のゲート信号の伝送経路における全ての抵抗成分を合算したゲート抵抗成分と異なる
半導体装置。 - 前記半導体基板の上面視で、前記半導体装置の動作時に主電流が流れる活性領域を囲むように配置され、前記第1ゲートトレンチ部と電気的に接続する第1ゲートランナー及び前記第2ゲートトレンチ部と電気的に接続する第2ゲートランナーをさらに備える
請求項1に記載の半導体装置。 - 前記第1ゲートランナー及び前記第2ゲートランナーの何れか一方は、他方と前記活性領域の外周との間に配置される
請求項2に記載の半導体装置。 - 前記第1ゲートランナーは、前記第2ゲートランナーと異なる断面積を有する
請求項2又は3に記載の半導体装置。 - 前記第1ゲートランナーは、前記第2ゲートランナーと異なる材料で形成される
請求項2から4の何れか一項に記載の半導体装置。 - 前記第1ゲートランナーと前記第2ゲートランナーとは、同じゲートパッドと電気的に接続する
請求項2から5の何れか一項に記載の半導体装置。 - 逆並列に設けられたダイオードをそれぞれ有し、前記第1ゲートランナーとゲートパッドとを電気的に接続する配線対と、
逆並列に設けられたダイオードをそれぞれ有し、前記第2ゲートランナーと前記ゲートパッドとを電気的に接続する配線対と
をさらに備える
請求項6に記載の半導体装置。 - 前記第1ゲートランナー及び前記第2ゲートランナーは、それぞれ異なるゲートパッドと電気的に接続する
請求項2から5の何れか一項に記載の半導体装置。 - 前記半導体基板の上面視で、前記半導体装置の動作時に主電流が流れる活性領域を囲むように配置され、前記第1ゲートトレンチ部及び前記第2ゲートトレンチ部と電気的に接続する外周ゲートランナーと、
前記半導体基板の上面視で、前記外周ゲートランナーの内側を延伸し、前記外周ゲートランナーと電気的に接続する内側ゲートランナーと
をさらに備え、
前記内側ゲートランナーは、前記第1ゲートトレンチ部及び前記第2ゲートトレンチ部のうち下方に位置するゲートトレンチ部と、コンタクトホールを介して電気的に接続する
請求項1に記載の半導体装置。 - 前記半導体基板の上面視で、前記内側ゲートランナーは、前記下方に位置するゲートトレンチ部の直上を、前記下方に位置するゲートトレンチ部の延伸方向に延伸する
請求項9に記載の半導体装置。 - 前記半導体基板の上面視で、前記内側ゲートランナーの延伸方向は、前記複数のゲートトレンチ部の延伸方向と交差する
請求項9に記載の半導体装置。 - 前記活性領域において、前記半導体基板の上方に設けられたエミッタ電極をさらに備え、
前記複数のゲートトレンチ部は、前記エミッタ電極と電気的に接続するダミートレンチ部をさらに含み、
前記エミッタ電極は、前記ダミートレンチ部との電気的接続を形成する第1層と、前記第1層の上方に配置される第2層とを有し、
前記内側ゲートランナーは、前記第2層に配置される
請求項9から11の何れか一項に記載の半導体装置。 - 前記ダイオード部は、前記半導体基板の上面から前記ベース領域を貫通して前記ドリフト領域まで設けられ、前記エミッタ電極と電気的に接続する複数のゲートトレンチ部をさらに有する
請求項12に記載の半導体装置。 - 前記半導体基板の上面視で、前記内側ゲートランナーの上方に配置された表面保護層をさらに備える
請求項9から13の何れか一項に記載の半導体装置。 - 前記第1ゲートトレンチ部は、前記第2ゲートトレンチ部と異なる断面積を有する
請求項1から14の何れか一項に記載の半導体装置。 - 前記第1ゲートトレンチ部内のゲート導電体は、前記第2ゲートトレンチ部内のゲート導電部と異なる材料で形成される
請求項1から15の何れか一項に記載の半導体装置。
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