JP7452040B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 1
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1に示すように、パワー半導体モジュール50は、パワー半導体チップ1と、絶縁基板2と、接合材3a、3b、3cと、電極パターン4と、金属基板5と、リードフレーム配線6と、樹脂ケース7と、封止樹脂8と、金属端子9と、金属ワイヤ10と、を備える。
次に、実施の形態にかかる半導体装置の製造方法について、説明する。図6~図8は、実施の形態にかかるパワー半導体モジュールの電極部の製造途中の状態を示す断面図である。まず、従来技術による半導体装置の製造方法と同様に、半導体基板上に半導体素子20を形成する。例えば、半導体装置がIGBTである場合、半導体基板上にエピタキシャル成長によりドリフト層、ベース層を形成し、イオン中でイオンを注入することにより、おもて面にエミッタ領域を形成し、裏面にコレクタ領域を形成する。次に、おもて面に熱酸化等でゲート絶縁膜を選択的に形成する。
2 絶縁基板
3a、3b、3c 接合材
4 電極パターン
5 金属基板
6、106 リードフレーム配線(外部接続用端子)
7 樹脂ケース
8、108 封止樹脂
9 金属端子
10 金属ワイヤ
12 積層基板
20、120 半導体基板上の半導体素子
21、121 Al電極
22、122 第1保護膜
23、123 第2保護膜
24、124 めっき膜
25、125 はんだ
26 第1フィラー
27 第2フィラー
50 パワー半導体モジュール
Claims (7)
- 半導体基板上に設けられた半導体素子と、
前記半導体素子のおもて面に設けられた、前記半導体素子に電気的に接続された電極層と、
前記電極層上に、選択的に設けられた第1保護膜と、
前記電極層上の前記第1保護膜以外の部分に、前記第1保護膜と接して設けられた金属膜と、
前記金属膜と前記第1保護膜とが接する部分を覆う第2保護膜と、
前記金属膜に接合され、前記電極層の電位を外部に取り出す外部接続用端子と、
前記第1保護膜、前記第2保護膜および前記外部接続用端子を覆う封止樹脂と、
を備え、前記第1保護膜は無機物の第1フィラーが添加され、
前記第1保護膜の線膨張係数α1、前記第2保護膜の線膨張係数α2および前記封止樹脂の線膨張係数α3は、α2>α1>α3の関係を満たすことを特徴とする半導体装置。 - 前記第2保護膜は無機物の第2フィラーが添加され、
前記第1保護膜に添加された第1フィラーの濃度は、前記第2保護膜に添加された第2フィラーの濃度より大きいことを特徴とする請求項1に記載の半導体装置。 - 前記第1保護膜に添加された第1フィラーの平均粒径は、前記第2保護膜に添加された第2フィラーの平均粒径より小さいことを特徴とする請求項2に記載の半導体装置。
- 前記第1フィラーおよび前記第2フィラーの平均粒径は、10nm以上250nm以下であることを特徴とする請求項2または3に記載の半導体装置。
- 前記第1フィラーおよび前記第2フィラーは、SiO2またはSiCであることを特徴とする請求項2~4のいずれか一つに記載の半導体装置。
- 前記第1保護膜および前記第2保護膜は、ポリイミド膜であることを特徴とする請求項1~5のいずれか一つに記載の半導体装置。
- 半導体基板上に半導体素子を形成する第1工程と、
前記半導体素子のおもて面に、前記半導体素子に電気的に接続された電極層を形成する第2工程と、
前記電極層上に、無機物の第1フィラーが添加された第1保護膜を選択的に形成する第3工程と、
前記電極層上の前記第1保護膜以外の部分に、金属膜を形成する第4工程と、
前記金属膜と前記第1保護膜とが接する部分を覆う第2保護膜を形成する第5工程と、
前記金属膜に接合され、前記電極層の電位を外部に取り出す外部接続用端子を形成する第6工程と、
前記第1保護膜、前記第2保護膜および前記外部接続用端子を覆う封止樹脂を形成する第7工程と、
を含み、
前記第1保護膜の線膨張係数α1、前記第2保護膜の線膨張係数α2および前記封止樹脂の線膨張係数α3は、α2>α1>α3の関係を満たすことを特徴とする半導体装置の製造方法。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000022052A (ja) | 1998-06-30 | 2000-01-21 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
US20090296364A1 (en) | 2008-05-28 | 2009-12-03 | Shinko Electric Industries Co., Ltd. | Wiring substrate and semiconductor package |
JP2011192774A (ja) | 2010-03-15 | 2011-09-29 | Fuji Electric Co Ltd | 半導体素子及び半導体素子の製造方法 |
JP2015023183A (ja) | 2013-07-19 | 2015-02-02 | 三菱電機株式会社 | パワーモジュール |
JP2018012748A (ja) | 2016-07-19 | 2018-01-25 | 日立化成株式会社 | 半導体再配線層形成用樹脂フィルム、半導体再配線層形成用複合フィルム、それらを用いた半導体装置及び半導体装置の製造方法 |
JP2018067592A (ja) | 2016-10-18 | 2018-04-26 | 富士電機株式会社 | 半導体装置およびモジュール型半導体装置 |
US20180197729A1 (en) | 2017-01-06 | 2018-07-12 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
JP2018113428A (ja) | 2017-01-06 | 2018-07-19 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000022052A (ja) | 1998-06-30 | 2000-01-21 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
US20090296364A1 (en) | 2008-05-28 | 2009-12-03 | Shinko Electric Industries Co., Ltd. | Wiring substrate and semiconductor package |
JP2009289849A (ja) | 2008-05-28 | 2009-12-10 | Shinko Electric Ind Co Ltd | 配線基板及び半導体パッケージ |
JP2011192774A (ja) | 2010-03-15 | 2011-09-29 | Fuji Electric Co Ltd | 半導体素子及び半導体素子の製造方法 |
JP2015023183A (ja) | 2013-07-19 | 2015-02-02 | 三菱電機株式会社 | パワーモジュール |
JP2018012748A (ja) | 2016-07-19 | 2018-01-25 | 日立化成株式会社 | 半導体再配線層形成用樹脂フィルム、半導体再配線層形成用複合フィルム、それらを用いた半導体装置及び半導体装置の製造方法 |
JP2018067592A (ja) | 2016-10-18 | 2018-04-26 | 富士電機株式会社 | 半導体装置およびモジュール型半導体装置 |
US20180197729A1 (en) | 2017-01-06 | 2018-07-12 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
JP2018113428A (ja) | 2017-01-06 | 2018-07-19 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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