JP7387558B2 - switching power supply - Google Patents

Description

The present invention relates to a switching power supply device including a switching element.

BACKGROUND ART A switching power supply device including an inverter circuit and a converter circuit has been known (for example, see Patent Document 1). In the above switching power supply device, the switching elements of the inverter circuit and the switching elements of the converter circuit are simultaneously driven by PWM control (pulse width modulation control).

However, the switching elements of the inverter circuit and the switching elements of the converter circuit have different switching frequencies. Therefore, the timing at which switching noise occurs is also different, and there is a possibility that switching noise may occur randomly.

If switching noise occurs randomly, it becomes difficult to remove the switching noise.For example, switching noise generated in the inverter circuit may have a negative effect on the converter circuit, or switching noise generated in the converter circuit may cause damage to the inverter circuit. may have a negative impact on.

Japanese Patent Application Publication No. 2007-82318

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a switching power supply device that can suppress random generation of switching noise.

In order to solve the above problems, a switching power supply device according to the present invention includes:
a first power conversion circuit including at least one first switching element;
a second power conversion circuit including at least one second switching element;
A switching power supply device comprising: a PLD that outputs a first gate pulse for turning on/off the first switching element and a second gate pulse for turning the second switching element on/off. hand,
The PLD is
a first carrier generation unit that generates a first carrier signal synchronized with a predetermined synchronization signal;
a first PWM control unit that generates the first gate pulse by comparing a first detection signal regarding the input/output current or input/output voltage of the first power inverter circuit with the first carrier signal;
a second carrier generation unit that generates the second carrier signal that is synchronized with the synchronization signal and has a different frequency from the first carrier signal;
a second PWM control unit that generates the second gate pulse by comparing a second detection signal regarding the input/output current or input/output voltage of the second power inverter circuit with the second carrier signal;
It is characterized by including.

In this configuration, since the first carrier generation section and the second carrier generation section generate the first carrier signal and the second carrier signal using a common synchronization signal, the first carrier signal and the second carrier signal are synchronized. The first gate pulse and the second gate pulse can be synchronized. Therefore, according to this configuration, it is possible to suppress random occurrence of switching noise.

In the above switching power supply device,
The first carrier generation section includes:
a first count operation unit that performs a count operation of adding or subtracting a first set value to a count value at a predetermined period, and generates a first triangular wave as the first carrier signal;
a first count storage unit that stores a first ideal count value as the count value when the triangular wave is synchronized with the synchronization signal;
a first synchronization processing unit that performs a first synchronization process when the synchronization signal is input,
The first synchronization processing unit includes, as the first synchronization processing,
a first determination process of determining whether a difference between the count value and the first ideal count value exceeds a predetermined threshold;
If the difference exceeds the threshold, a first calculation process of adding or subtracting a numerical value of 1 or more to the first set value in order to bring the count value closer to the first ideal count value;
When the counting operation is performed after the first calculation process, a first return process returns the first setting value to the value before the first calculation process;
can be configured to do this.

As a method of synchronizing a triangular wave with a synchronization signal, there is a known method of resetting the count value of a counting unit for generating the triangular wave (suddenly setting it to zero). However, with this method, one cycle of gate pulses generated based on the triangular wave cannot be generated, which adversely affects the output of the first power conversion circuit.

On the other hand, in the above configuration of the present invention, when synchronizing the triangular wave with the synchronization signal, the count value is not reset, but a value of 1 or more is added to or subtracted from the first set value that is added to or subtracted from the count value. . Therefore, according to the above configuration, it is possible to prevent the count value from rapidly increasing or decreasing, and it is possible to suppress the first synchronization process from having an adverse effect on the output of the first power inverter circuit.

In the above switching power supply device,
It is preferable that the first synchronization processing unit performs the first synchronization processing once every time the synchronization signal is input N times (N is an integer of 2 or more).

According to this configuration, since the count value can be gradually brought closer to the first ideal count value, it is possible to further suppress the first synchronization process from having an adverse effect on the output of the first power conversion circuit.

In the above switching power supply device,
The second carrier generation section includes:
a second counting operation unit that performs a counting operation of adding or subtracting a second set value to the count value at a predetermined period and generating a second triangular wave as the second carrier signal;
a second count storage unit that stores a second ideal count value as the count value in a state where the triangular wave is synchronized with the synchronization signal;
a second synchronization processing unit that performs a second synchronization process when the synchronization signal is input,
The second synchronization processing unit includes, as the second synchronization processing,
a second determination process for determining whether a difference between the count value and the second ideal count value exceeds a predetermined threshold;
If the difference exceeds the threshold, a second calculation process of adding or subtracting a numerical value of 1 or more to the second set value in order to bring the count value closer to the second ideal count value;
When the counting operation is performed after the second calculation process, a second return process returns the second setting value to the value before the second calculation process;
can be configured to do this.

According to this configuration, it is possible to prevent the count value from rapidly increasing or decreasing, and it is possible to suppress the second synchronization process from having an adverse effect on the output of the second power inverter circuit.

In the above switching power supply device,
Preferably, the second synchronization processing section performs the second synchronization processing once every time the synchronization signal is input M times (M is an integer of 2 or more).

According to this configuration, it is possible to further suppress the second synchronization process from having an adverse effect on the output of the second power inverter circuit.

In the above switching power supply device,
The first PWM control section includes:
a first comparison unit that compares the first detection signal and the first carrier signal to generate a first comparison signal having a predetermined pulse width;
a first pulse generation unit that generates the first gate pulse based on the first comparison signal,
The first pulse generation section includes:
The pulse width adjustment process may be performed to increase or decrease the pulse width of the first comparison signal, and the first gate pulse may be generated based on the first comparison signal after the pulse width adjustment process.

When connecting multiple first power conversion circuits (for example, inverter circuits) in parallel, the length of the cable connected to the first power conversion circuit, the stray capacitance of the first power conversion circuit, and the amount included in the first power conversion circuit The timing of the rise and fall of the first gate pulse may be shifted due to variations in the first switching element. If the timing of the rise and fall of the first gate pulse deviates, the balance (shunt balance) of the output current or output voltage of the first power inverter circuit will collapse. As a method of adjusting the balance (shunt balance) of this output current or output voltage, a method of providing a resistor on the output side of the first power conversion circuit is known. However, with this method, the size of the resistor increases depending on the output current, resulting in an increase in the size of the power supply device.

On the other hand, in the above configuration of the present invention, instead of providing a resistor for adjusting the shunt balance, the first pulse generation section of the PLD performs pulse width adjustment processing to increase or decrease the pulse width of the first gate pulse. The processed first gate pulse is output to the first power conversion circuit. Therefore, according to the above configuration, the shunt balance of the first power conversion circuit can be adjusted without increasing the size of the power supply device.

In the above switching power supply device,
The first pulse generation section includes:
A first parameter for increasing or decreasing the pulse width according to a time change in the input/output current of the first power conversion circuit, which can be set to a negative value, zero, or a positive value; The pulse width adjustment process can be configured to be performed based on a second parameter that is a parameter for increasing or decreasing the pulse width and can be set to a negative value, zero, or a positive value.

According to the present invention, it is possible to provide a switching power supply device that can suppress random generation of switching noise.

FIG. 1 is a circuit diagram of a switching power supply device according to a first embodiment. FIG. 2 is a block diagram of a PLD according to the first embodiment. (A) is a diagram for explaining the counting operation of the first counting operation unit, and (B) is an enlarged diagram of area B in (A). (A) is a diagram for explaining the first determination process, and (B) is a diagram for explaining the first calculation process and the first return process. (A) is a diagram showing the first deviation signal and the first comparison signal when there is no first rate limit section, and (B) is a diagram showing the first deviation signal and the first comparison signal when there is the first rate limit section. It is a diagram. (A) is a diagram showing the first deviation signal and the first triangular wave, (B) is a diagram showing the first comparison signal, (C) is a diagram showing the first gate pulse, (D) is the operation mode of the inverter circuit. FIG. (A) is a diagram showing the dead time of the first gate pulse, and (B) is a diagram showing the minimum pulse width of the first gate pulse. FIG. 2 is a circuit diagram of a switching power supply device according to a second embodiment. FIG. 2 is a block diagram of an inverter control section of a PLD according to a second embodiment. (A) is a diagram showing the first deviation signal and the first triangular wave, (B) is a diagram showing the first comparison signal, (C) is a diagram showing the first gate pulse, (D) is the operation mode of the inverter circuit. FIG.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a switching power supply device according to the present invention will be described with reference to the accompanying drawings.

[First embodiment]
FIG. 1 shows a switching power supply device 100 according to a first embodiment of the present invention. The switching power supply device 100 includes a power converter 110 and a PLD (programmable logic device) 120 that controls the power converter 110.

The power conversion unit 110 includes an inverter circuit 111 corresponding to the "first power conversion circuit" of the present invention, a converter circuit 112 corresponding to the "second power conversion circuit" of the present invention, a capacitor 113, and a first input/output circuit. It includes an end T11 and a second input/output end T12. Note that the capacitor 113 may be included in the inverter circuit 111 or the converter circuit 112.

Under the control of the PLD 120, the inverter circuit 111 performs a DC/AC conversion operation that converts an input DC voltage to an AC voltage and outputs the same, and an AC/DC conversion operation that converts the input AC voltage to a DC voltage and outputs the DC voltage. Perform the action. The inverter circuit 111 includes four full-bridge connected switching elements Q1 to Q4 (corresponding to the "first switching elements" of the present invention) and a gate drive circuit (not shown) that turns on/off the first switching elements Q1 to Q4. ). As the first switching elements Q1 to Q4, power transistors such as bipolar transistors, MOSFETs (metal oxide semiconductor field effect transistors), or IGBTs (insulated gate transistors) are used, for example.

Converter circuit 112 is composed of an AC/DC converter, and performs AC/DC conversion operation and DC/AC conversion operation under the control of PLD 120. Converter circuit 112 includes at least one switching element (corresponding to the "second switching element" of the present invention) and a gate drive circuit that turns on/off the second switching element. As the second switching element, for example, a power transistor such as a bipolar transistor, MOSFET, or IGBT is used. Note that the converter circuit 112 may be configured with a DC/DC converter including at least one second switching element.

The power converter 110 converts AC power or DC power input to the second input/output terminal T12 into predetermined DC power with a converter circuit 112, and converts the DC power into predetermined AC power with an inverter circuit 111. It is output from the first input/output terminal T11. In addition, the power conversion unit 110 converts the AC power input to the first input/output terminal T11 into predetermined DC power with the inverter circuit 111, and converts the DC power into predetermined AC power or DC power with the converter circuit 112. and output from the second input/output terminal T12.

The PLD 120 is a circuit configured with at least one of an FPGA, a CPLD, a DSP, and a microcomputer, and the functions (programs) of the circuit can be designed and changed using software. The PLD 120 outputs first gate pulses q1 to q4 for turning on/off the first switching elements Q1 to Q4 of the inverter circuit 111, and outputs a second gate pulse for turning on/off the second switching elements of the converter circuit 112. Outputs gate pulse.

The PLD 120 includes a first carrier generation section 130 and a first PWM control section 140 as an inverter control section for controlling the inverter circuit 111, and a second carrier generation section 150 as a converter control section for controlling the converter circuit 112. and a second PWM control section 160.

The first carrier generation section 130 generates a first carrier signal (in this embodiment, a first triangular wave) synchronized with a predetermined synchronization signal S, and the second carrier generation section 150 generates a first carrier signal synchronized with the synchronization signal S. A second carrier signal (in this embodiment, a second triangular wave) is generated. The first PWM control unit 140 generates first gate pulses q1 to q4 based on the first triangular wave and the first deviation signal, and the second PWM control unit 160 generates the first gate pulses q1 to q4 based on the second triangular wave and the second deviation signal. Generate 2 gate pulses.

The first deviation signal corresponds to a first detection signal regarding the input/output current (input current or output current) or input/output voltage (input voltage or output voltage) of the inverter circuit 111. The first deviation signal of the present embodiment includes a digital signal obtained by AD converting an analog signal regarding the difference between the detected value of the output voltage of the power converter 110 (inverter circuit 111) and a predetermined reference value, and a polarity of the digital signal. and an inverted digital signal. Hereinafter, the digital signal will be referred to as a first deviation signal d1, and the inverted digital signal will be referred to as a first deviation signal d2. Note that the first deviation signal d2 may be generated inside the PLD 120.

The second deviation signal corresponds to a second detection signal regarding the input/output current (input current or output current) or input/output voltage (input voltage or output voltage) of the converter circuit 112. The second deviation signal of the present embodiment includes a digital signal obtained by AD converting an analog signal regarding the difference between the detected value of the input voltage of the power converter 110 (converter circuit 112) and a predetermined reference value, and a polarity of the digital signal. and an inverted digital signal. In the following, the digital signal will be referred to as the second deviation signal d3, and the inverted digital signal will be referred to as the second deviation signal d4. Note that the second deviation signal d4 may be generated inside the PLD 120.

FIG. 2 shows a block diagram of the PLD 120. The first carrier generation section 130 includes a first oscillation section 131, a first count operation section 132, a first count storage section 133, and a first synchronization processing section 134.

The first oscillator 131 oscillates a clock signal consisting of clock pulses with a predetermined period. The first counting operation unit 132 performs a counting operation of adding or subtracting the first set value _X1 to the count value every time the clock pulse is counted a predetermined number of times.

As shown in FIG. 3B, the first count operation unit 132 performs a count operation and sets the count value to the first value until the count value reaches the maximum value _Lmax from the minimum value (in this embodiment, 0). While adding the value X ₁ (X ₁ = 1 in this embodiment), after reaching the maximum value L _max , the first set value X ₁ (X ₁ = 1). This counting operation allows the first counting operation section 132 to generate a first triangular wave (see FIG. 3(A)). The frequency of the first triangular wave is preferably set within the range of 15 [kHz] to 20 [kHz], and is set to 15 [kHz] in this embodiment.

The first count storage unit 133 stores a first ideal count value. The first ideal count value is a count value in a first triangular wave (ideal triangular wave) synchronized with the synchronization signal S. It is preferable to synchronize the first triangular wave with the synchronization signal S each time the PLD 120 is activated.

The first synchronization processing unit 134 converts the first triangular wave into the synchronization signal S every time the pulse of the synchronization signal S is input N times (N is an integer of 2 or more. In this embodiment, N=3). A first synchronization process for synchronization is performed. By performing the first synchronization process only once every three times the synchronization signal S is input, it is possible to prevent the count value from rapidly increasing or decreasing, and the first synchronization process can prevent the output of the inverter circuit 111 from being adversely affected. You can prevent it from happening.

The first synchronization process includes a first determination process, a first calculation process, and a first return process. As shown in FIG. 4A, the first synchronization processing unit 134 performs the first determination process when the third pulse of the synchronization signal S is input after the PLD 120 is activated (see time _t1 ). . In the first determination process, the first synchronization processing unit 134 calculates the difference D (=L _max ) between the current count value (L 1 at time t ₁ ) and the first ideal count value (L _max at time t ₁ ) _. -L ₁ ), and it is determined whether the difference D exceeds a predetermined threshold. The first count storage unit 133 stores, for example, a first ideal count value corresponding to the number of input pulses of the synchronization signal S.

If the difference D exceeds the predetermined threshold, the first synchronization processing unit 134 performs the first calculation process. In the first calculation process, the first synchronization processing unit 134 adds a value of 1 or more (in this embodiment, 1) to the first set value X ₁ in order to bring the current count value closer to the first ideal count value. Or subtract. As shown in FIG. 4B, when the first synchronization processing unit 134 adds 1 to the first setting value _X1 , the first count operation unit 132 adds the count value to The first set value X ₁ (=2) after addition is added (see time t ₁ ').

The first synchronization processing section 134 performs the first return processing when the first counting operation section 132 performs the counting operation after the first arithmetic processing. In the first return process, the first synchronization processing unit 134 returns the numerical value of the first set value X ₁ (X ₁ =2) to the numerical value (X ₁ =1) before the first calculation process. The first count operation section 132 adds the first set value X ₁ (=1) to the count value as a count operation after the first return process by the first synchronization processing section 134 .

The first synchronization process according to the present embodiment does not reset the count value when synchronizing the first triangular wave with the synchronization signal S, but adds 1 to the first set value X ₁ that is added to or subtracted from the count value. Add or subtract. Therefore, it is possible to prevent the count value from rapidly increasing or decreasing, and it is possible to suppress the first synchronization process from having an adverse effect on the output of the inverter circuit 111.

Referring to FIG. 2, the first PWM control section 140 includes a first rate limit section 141, a first comparison section 142, a first pulse generation section 143, and a first pulse protection section 144.

When the amount of change in the first deviation signals d1, d2 is larger than the amount of change in the first triangular wave, the first rate limiter 141 controls the amount of change in the first deviation signals d1, d2 to be the amount of change in the first triangular wave. The amount of change in the first deviation signals d1 and d2 is limited so that the amount of change is as follows.

In the present embodiment, the first rate limiter 141 controls the amount of change in the first deviation signals d1 and d2 to match the amount of change in the first triangular wave based on the first set value X ₁ (X ₁ =1). Thus, the amount of change in the first deviation signals d1 and d2 is limited. Specifically, the first rate limiter 141 changes the signal values of the first deviation signals d1 and d2 to the first set value X ₁ (X ₁ =1) at the same timing as the count operation of the first count operation section 132. Increase or decrease by increments.

FIG. 5(A) shows the first deviation signal d1 and the first comparison signal c1 (signals generated by the first comparing section 142) when the first rate limiter 141 is not present, and FIG. 5(B) shows the first The first deviation signal d1 and the first comparison signal c1 when the rate limiter 141 is present are shown. The first comparison signal c1 is a signal for generating first gate pulses q1 and q2, as will be described later.

In the switching power supply device 100, the output power of the inverter circuit 111 is changed from the output in the positive direction (the direction in which current flows from the upper terminal to the lower terminal of the first input/output terminal T11 shown in FIG. 1) to the negative direction (as shown in FIG. 1). When switching to the output in the direction in which the current flows from the lower terminal to the upper terminal of the first input/output terminal T11 shown in FIG. Change the polarity (see Z1 and Z2 in FIG. 6).

As shown in FIG. 5A, without the first rate limiter 141, the signal value of the first deviation signal d1 suddenly changes from Vc- to Vc+ (or from Vc+ to Vc-) (at time _t12 , t ₁₇ ). As a result, the magnitude relationship between the first deviation signal d1 and the first triangular wave changes multiple times in a short period of time, so that unnecessary pulses are generated in the first comparison signal c1 (see times t ₁₂ to t ₁₃ ), pulses Cracks may occur (see times t ₁₇ to t ₁₈ ). Further, even when the polarity of the first deviation signal d1 is not changed, if chattering occurs in the first deviation signal d1 (see time t ₁₅ to t ₁₆ ), unnecessary continuous pulses are generated in the first comparison signal c1.

On the other hand, when the first rate limit section 141 is provided, as shown in FIG. 5(B), the first rate limit section 141 changes the signal value of the first deviation signal d1 from Vc- to Vc+ (or from Vc+ to Vc-). Instead of suddenly changing the first set value X 1 (X 1 =1), the first set value X ₁ (X ₁ =1) is changed so that the amount of change in the first deviation signal d1 matches the amount of change in the first triangular wave. As a result, unnecessary pulses are not generated in the first comparison signal c1 (see times t ₁₂ to t ₁₃ ), and pulse breaks do not occur (see times t ₁₇ to t ₁₈ ). Furthermore, even if chattering occurs (see time t ₁₅ to t ₁₆ ), unnecessary continuous pulses will not occur in the first comparison signal c1.

The first comparison unit 142 functions as a comparator. As shown in FIG. 6, the first comparing unit 142 compares the first deviation signal d1 and the first triangular wave to generate first comparison signals c1, c1' having a predetermined pulse width. The first comparison signal c1' is a signal obtained by inverting the polarity of the first comparison signal c1. Further, the first comparison unit 142 compares the first deviation signal d2 and the first triangular wave to generate first comparison signals c2 and c2' having a predetermined pulse width. The first comparison signal c2' is a signal obtained by inverting the polarity of the first comparison signal c2.

The first pulse generator 143 generates first gate pulses q1 to q4. As shown in FIG. 6, the first pulse generation unit 143 generates first gate pulses q1, q2 based on first comparison signals c1, c2, and generates first gate pulses q1, q2 based on first comparison signals c1', c2'. 1 gate pulses q3 and q4 are generated. The first pulse generator 143 outputs the first gate pulse q1 to the gate drive circuit of the first switching element Q1, outputs the first gate pulse q2 to the gate drive circuit of the first switching element Q2, and generates the first gate pulse q1. q3 is output to the gate drive circuit of the first switching element Q3, and the first gate pulse q4 is output to the gate drive circuit of the first switching element Q4.

FIG. 6(D) shows the operation mode of the inverter circuit 111. The inverter circuit 111 whose operating mode is power running is supplied with current from the capacitor 113, while the inverter circuit 111 whose operating mode is regeneration is supplied with current to the capacitor 113. Further, in the section Z1 to Z2 in FIG. 6, the output power of the inverter circuit 111 becomes an output in a negative direction, while in the sections other than the above, the output power of the inverter circuit 111 becomes an output in a positive direction.

The first pulse protection unit 144 sets the dead time and minimum pulse width for the first gate pulses q1 to q4, as shown in FIG. 7 (first gate pulses q3 and q4 are omitted in the figure). The first pulse generation section 143 causes the first gate pulses q1 to q4 to have a dead time of the time set by the first pulse protection section 144, and also has a dead time of the time set by the first pulse protection section 144. First gate pulses q1 to q4 having a width are generated. Note that the dead time is omitted in FIG. 6.

Referring to FIG. 2, second carrier generation section 150 includes a second oscillation section 151, a second count operation section 152, a second count storage section 153, and a second synchronization processing section 154.

The second oscillator 151 oscillates a clock signal consisting of clock pulses with a predetermined period. Note that the second oscillation section 151 may be omitted and the clock signal of the first oscillation section 131 may be inputted to the second count operation section 152.

The second counting operation unit 152 performs a counting operation of adding or subtracting a second set value X ₂ (X ₂ =1 in this embodiment) to the count value every time the clock pulse is counted a predetermined number of times. The counting operation performed by the second counting operation section 152 is common to the counting operation performed by the first counting operation section 132. The second count operation section 152 can generate a second triangular wave by a count operation, similarly to the first count operation section 132. The frequency of the second triangular wave is set to 1.9 [kHz] in this embodiment.

The second count storage unit 153 stores a second ideal count value. The second ideal count value is a count value in a second triangular wave (ideal triangular wave) synchronized with the synchronization signal S. It is preferable to synchronize the second triangular wave with the synchronization signal S each time the PLD 120 is activated.

The second synchronization processing unit 154 converts the second triangular wave into the synchronization signal S every time the pulse of the synchronization signal S is inputted M times (M is an integer of 2 or more. In this embodiment, M=3). A second synchronization process is performed for synchronization. By performing the second synchronization process only once every three times the synchronization signal S is input, it is possible to prevent the count value from rapidly increasing or decreasing, and the second synchronization process can prevent the output of the converter circuit 112 from being adversely affected. You can prevent it from happening. The second synchronization process includes a second determination process, a second calculation process, and a second return process. The second synchronization process is common to the first synchronization process.

In this embodiment, when the frequency of the second triangular wave is set to 1.9 [kHz], the second triangular wave is synchronized with the synchronization signal S in about 20 [s] after starting the PLD 120 (current count value to match the second ideal count value).

The second PWM control section 160 includes a second rate limit section 161, a second comparison section 162, a second pulse generation section 163, and a second pulse protection section 164.

When the amount of change in the second deviation signals d3, d4 is larger than the amount of change in the second triangular wave, the second rate limiter 161 controls the second rate limiter 161 to adjust the amount of change in the second deviation signals d3, d4 to the amount of change in the second triangular wave. The amount of change in the second deviation signals d3 and d4 is limited so that the amount of change is as follows. In this embodiment, the second rate limiter 161 operates at the same timing as the counting operation of the second counting operation section 152 so that the amount of change in the second deviation signals d3 and d4 matches the amount of change in the second triangular wave. , the signal values of the second deviation signals d3 and d4 are increased or decreased by the second set value X ₂ (X ₂ =1).

The second comparison section 162 functions as a comparator similarly to the first comparison section 142. That is, the second comparing section 162 compares the second deviation signals d3 and d4 with the second triangular wave to generate a second comparison signal having a predetermined pulse width.

The second pulse generator 163 generates a second gate pulse based on the second comparison signal, similar to the first pulse generator 143. The second pulse generator 163 outputs the generated second gate pulse to the gate drive circuit of the second switching element.

The second pulse protector 164, like the first pulse protector 144, sets the dead time and minimum pulse width for the second gate pulse. The second pulse generator 163 causes the second gate pulse to have a dead time of the time set by the second pulse protector 164, and has a width equal to or greater than the minimum pulse width set by the second pulse protector 164. Generate a second gate pulse.

In the switching power supply device 100, the first carrier generation section 130 and the second carrier generation section 150 use a common synchronization signal S to generate a first carrier signal (first triangular wave) and a second carrier signal (second triangular wave). , the first triangular wave and the second triangular wave can be synchronized with a predetermined phase difference, and the first gate pulses q1 to q4 and the second gate pulse can be synchronized with a predetermined phase difference. can. Therefore, according to the switching power supply device 100, random generation of switching noise can be suppressed.

[Second embodiment]
FIG. 8 shows a switching power supply device 200 according to a second embodiment of the present invention. The switching power supply device 200 includes a power conversion section 210 and a PLD (programmable logic device) 220 that controls the power conversion section 210.

The power conversion unit 210 includes inverter circuits 211A, 211B corresponding to the "first power conversion circuit" of the present invention, converter circuits 212A, 212B corresponding to the "second power conversion circuit" of the present invention, and capacitors 213A, 213B. , a first input/output end T21, and a second input/output end T22. Inverter circuits 211A, 211B, converter circuits 212A, 212B, and capacitors 213A, 213B have the same configuration as inverter circuit 111, converter circuit 112, and capacitor 113 of the first embodiment.

PLD 220 includes a first carrier generation section 230 and first PWM control sections 240A and 240B as an inverter control section, and includes a second carrier generation section 250 and second PWM control sections 260A and 260B as converter control sections. The synchronization signal S, first deviation signals d1, d2, and second deviation signals d3, d4 input to the PLD 220 are the same as in the first embodiment.

The first carrier generation section 230 and the second carrier generation section 250 have the same configuration as the first carrier generation section 130 and the second carrier generation section 150 of the first embodiment. The first PWM control units 240A and 240B have the same configuration as the first PWM control unit 140 of the first embodiment, except that first pulse generation units 243A and 243B, which will be described later, perform pulse width adjustment processing. The second PWM control sections 260A and 260B have the same configuration as the second PWM control section 160 of the first embodiment.

The first PWM control section 240A outputs first gate pulses q1 to q4 for turning on/off the first switching elements Q1 to Q4 of the inverter circuit 211A, and the first PWM control section 240B outputs first gate pulses q1 to q4 for turning on/off the first switching elements Q1 to Q4 of the inverter circuit 211A. First gate pulses q11 to q14 are output for turning on/off the elements Q11 to Q14. The second PWM control section 260A outputs a second gate pulse for turning on/off the second switching element of the converter circuit 212A, and the second PWM control section 260B turns on/off the second switching element of the converter circuit 212B. A second gate pulse is output for this purpose.

As shown in FIG. 9, the first PWM control section 240A includes a first rate limit section 241A, a first comparison section 242A, a first pulse generation section 243A, and a first pulse protection section 244A. Similarly, the first PWM control section 240B includes a first rate limit section 241B, a first comparison section 242B, a first pulse generation section 243B, and a first pulse protection section 244B.

The first pulse generation units 243A, 243B perform pulse width adjustment processing to increase or decrease the pulse width on the first comparison signals c1, c2, c1', c2', and the first comparison signals c1, c2 after the pulse width adjustment processing, First gate pulses q1 to q4 and q11 to q14 are generated based on c2, c1', and c2'. More specifically, the first pulse generation units 243A and 243B perform pulse width adjustment processing of the first comparison signals c1, c2, c1', and c2' based on a calculation formula regarding the pulse width Y to be increased or decreased.

The calculation formula for the pulse width Y can be expressed as the sum of the first parameter A×di/dt and the second parameter B. That is, Y=A×di/dt+B. The first parameter A×di/dt is a parameter for increasing or decreasing the pulse width according to the time change of the output current of the inverter circuits 211A, 211B, and A is set to a negative value, zero, or a positive value. It is possible. The second parameter B is a parameter for constantly increasing or decreasing the pulse width, and can be set to a negative value, zero, or a positive value.

For example, the current value of the output current of the inverter circuit 211A detected by the first current detection means (for example, a current transformer) provided between the inverter circuit 211A and the first input/output terminal T21, and the current value of the output current of the inverter circuit 211B and the The first pulse generator 243A and the first The first parameter A×di/dt and the second parameter B can be set independently with the pulse generation unit 243B.

FIG. 10(B) shows the first comparison signals c1, c2, c1', c2', and FIG. 10(C) shows the first comparison signals c1, c2, c1', c2' after pulse width adjustment processing. The generated first gate pulses q1 to q4 are shown. In FIG. 10, it is assumed that the first parameter A is set to a negative value and the second parameter B is set to zero.

As shown in FIGS. 10(B) and 10(C), the first pulse generator 243A adjusts the pulse widths of the first comparison signals c1, c2, c1', c2' by performing pulse width adjustment processing. After decreasing by Y, first gate pulses q1 to q4 are generated. As a result, the pulse width of the first gate pulses q1 to q4 can be reduced by Y.

For example, when the output current or output voltage balance (shunt balance) is disrupted between the inverter circuits 211A and 211B, at least one of the first pulse generation units 243A and 243B performs pulse width adjustment processing, so that the inverter circuit 211A , 211B can be adjusted.

In the switching power supply device 200, similarly to the first embodiment, the first carrier generation section 230 and the second carrier generation section 250 use a common synchronization signal S to generate the first carrier signal (first triangular wave) and the second carrier signal. Since the carrier signal (second triangular wave) is generated, the first triangular wave and the second triangular wave can be synchronized with a predetermined phase difference, and the first gate pulses q1-q4, q11-q14 and the second gate pulse The pulses can be synchronized with a predetermined phase difference.

Furthermore, in the switching power supply device 200, the first gate pulses q1 to q4 and the first gate pulses q11 to q14 can be synchronized, and the second gate pulse outputted by the second PWM control section 260A and the second PWM control section 260B can be synchronized. The second gate pulse to be output can be synchronized. Therefore, according to the switching power supply device 200, random generation of switching noise can be suppressed.

[Modified example]
Although the embodiments of the switching power supply device according to the present invention have been described above, the present invention is not limited to the above embodiments.

A switching power supply device according to the present invention includes a first power conversion circuit including a first switching element, a second power conversion circuit including a second switching element, and a first gate pulse for turning on/off the first switching element. and a PLD that outputs a second gate pulse for turning on/off the second switching element, and the PLD generates a first carrier signal synchronized with a predetermined synchronization signal; a first PWM control section that generates a first gate pulse based on a first carrier signal; and a second PWM control section that generates a second carrier signal that is synchronized with the synchronization signal and has a different frequency from the first carrier signal. The configuration can be changed as appropriate as long as it includes a 2-carrier generation section and a second PWM control section that generates a second gate pulse based on the second carrier signal.

In the above embodiment, the first triangular wave is generated as the first carrier signal, and the second triangular wave is generated as the second carrier signal, but a carrier signal other than the triangular wave may be generated. For example, a first sawtooth wave may be generated as the first carrier signal, and a second sawtooth wave may be generated as the second carrier signal.

In the embodiments described above, the synchronization signal S is input from outside the PLD 120, 220, but the synchronization signal S may be generated inside the PLD 120, 220. Further, the PLDs 120 and 220 may include a switching unit that selects and outputs either the synchronization signal S input from the outside or the synchronization signal S generated internally.

The PLDs 120 and 220 may include an output stop section that receives a stop command from the outside and stops outputting the first gate pulse and the second gate pulse.

If the period of the synchronization signal S is long, the first synchronization processing section 134 may perform the first synchronization processing every time the synchronization signal S is input. Similarly, the second synchronization processing section 154 may perform the second synchronization processing every time the synchronization signal S is input.

100, 200 Switching power supply device 110, 210 Power converter section 111, 211A, 211B Inverter circuit 112, 212A, 212B Converter circuit 113, 213A, 213B Capacitor 120, 220 PLD
130, 230 First carrier generation section 131 First oscillation section 132 First count operation section 133 First count storage section 134 First synchronization processing section 140, 240A, 240B First PWM control section 141, 241A, 241B First rate limit section 142, 242A, 242B First comparison section 143, 243A, 243B First pulse generation section 144, 244A, 244B First pulse protection section 150, 250 Second carrier generation section 151 Second oscillation section 152 Second count operation section 153 2-count storage section 154 Second synchronization processing section 160, 260A, 260B Second PWM control section 161 Second rate limit section 162 Second comparison section 163 Second pulse generation section 164 Second pulse protection section

Claims (3)

a first power conversion circuit including at least one first switching element;
a second power conversion circuit including at least one second switching element;
A switching power supply device comprising: a PLD that outputs a first gate pulse for turning on/off the first switching element and a second gate pulse for turning the second switching element on/off. hand,
The PLD is
a first carrier generation unit that generates a first carrier signal synchronized with a predetermined synchronization signal;
a first PWM control unit that generates the first gate pulse by comparing a first detection signal regarding the input/output current or input/output voltage of the first power inverter circuit with the first carrier signal;
a second carrier generation unit that generates the second carrier signal that is synchronized with the synchronization signal and has a different frequency from the first carrier signal;
a second PWM control unit that generates the second gate pulse by comparing a second detection signal regarding the input/output current or input/output voltage of the second power inverter circuit with the second carrier signal;
including;
The first carrier generation section includes:
a first counting operation unit that performs a first counting operation of adding or subtracting a first set value to a count value at a predetermined period, and generating a first triangular wave as the first carrier signal;
a first count storage unit that stores a first ideal count value as the count value of the first count operation unit in a state where the first triangular wave is synchronized with the synchronization signal;
a first synchronization processing unit that performs a first synchronization process when the synchronization signal is input,
The first synchronization processing unit includes, as the first synchronization processing,
a first determination process of determining whether a difference between the count value of the first count operation unit and the first ideal count value exceeds a predetermined threshold;
If the difference exceeds the threshold in the first determination process, a value of 1 or more is set to the first set value in order to bring the count value of the first count operation unit closer to the first ideal count value. a first calculation process of adding or subtracting;
When the first counting operation is performed after the first calculation process, a first return process returns the first setting value to the value before the first calculation process;
and
The second carrier generation section includes:
a second counting operation section that performs a second counting operation of adding or subtracting a second set value to the count value at a predetermined period and generating a second triangular wave as the second carrier signal;
a second count storage unit that stores a second ideal count value as the count value of the second count operation unit in a state in which the second triangular wave is synchronized with the synchronization signal;
a second synchronization processing unit that performs a second synchronization process when the synchronization signal is input,
The second synchronization processing unit includes, as the second synchronization processing,
a second determination process of determining whether a difference between the count value of the second count operation unit and the second ideal count value exceeds a predetermined threshold;
If the difference exceeds the threshold in the second determination process, a value of 1 or more is set to the second set value in order to bring the count value of the second counting operation unit closer to the second ideal count value. a second operation process of adding or subtracting;
When the second counting operation is performed after the second calculation process, a second return process returns the second setting value to the value before the second calculation process;
A switching power supply device characterized by performing the following . The switching according to claim 1 , wherein the first synchronization processing section performs the first synchronization processing once every time the synchronization signal is input N times (N is an integer of 2 or more). power supply. 3. The second synchronization processing unit performs the second synchronization processing once every time the synchronization signal is input M times (where M is an integer of 2 or more). switching power supply.

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