JP7384318B1 - power amplifier - Google Patents

Abstract

A stacked circuit (19) having n FETs (n is an integer of 2 or more), where the FET numbers are 1 to n and i is an integer of 2 or more and (n-1) or less, 1 The input signal is input to the gate terminal of the th FET (12), the drain terminal is connected to the source terminal of the second FET, and the source terminal is a terminal connected to GND. A stack type circuit (19) whose terminal is connected to the source terminal of the (i+1)th FET, an output signal is output from the drain terminal of the nth FET (18), and the drain terminal is a terminal connected to the power supply. , a resistor connected to the gate terminals of the second to nth FETs of the stacked circuit (19), a capacitor connected to the electrode opposite to the gate terminal of the resistor, and a resistor connected in parallel with the resistor. and first switches connected to each other.

Description

The present disclosure relates to a stacked power amplifier.

Currently, power amplifiers mainly using GaAs HBTs (Heterojunction Bipolar Transistors) are used as power amplifiers for mobile terminals. The reason for this is that it is normally off, capable of single power supply operation, can be operated with a Li-ion battery voltage of 3.7V, and has a lower power density than a GaAs FET (Field Effect Transistor) in the output power range of several watts. Because of its high resistance, the chip area is small when integrated into an integrated circuit, and it is possible to achieve a much higher yield than GaAs-based FETs.

However, in recent years, power amplifiers, band switching switches, and antenna switches have been equipped with CMOS (Complementary Metal-Oxide-Semiconductor) control circuits that enable digital control in addition to GaAs HBTs in order to simplify control within terminals. Equipped with amplifier and switch. In addition, GaAs HBT chips, which are not Si-based, cannot be integrated with control circuits and are more expensive to mass produce than CMOS chips, so there has been a strong desire to use CMOS power amplifiers.

The standard voltage of a CMOS FET is 1.2V for a 65nm process and 1.8V for a 0.18μm process, which is considerably lower than the battery voltage (3.7V). It cannot be used.

Against this background, stacked power amplifiers that are effective in operating CMOS as a power amplifier at as high a power supply voltage as possible are attracting attention (for example, see Non-Patent Document 1).

S. Pornpromlikit, et al. , A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS, IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 1, pp. 57-64, Jan. 2010.

Next, the problem will be explained using as an example a four-stage stack type power amplifier using a 65 nm CMOS process in which the standard voltage of the FET is 1.2V. In this example, assuming that each amplification FET operates equally, it is possible to operate up to a power supply voltage of 4.8V. The standard voltage of a Li-ion battery is 3.7V, but for high output power operation, assume that it is boosted to 4.8V with a DC-DC converter and operates with an output power of 1W.

In mobile communications, the output power of a terminal is often reduced depending on the distance between the base station and the terminal. In other words, if the distance is long, the output power is switched to the maximum output power, and if the distance is short, the output power is switched to the low output power frequently. For example, in urban areas, the distance between the base station and the terminal is relatively short, so the output power of the terminal is often low, on the order of several to several tens of mW. This output power control is achieved by lowering the power supply voltage of the power amplifier. This is because if the output power is lowered by reducing the input power while keeping the power supply voltage high, the efficiency of the power amplifier will drop significantly.

However, if the power supply voltage of the stacked power amplifier is lowered from 4.8V to, for example, 2.4V, the power supply voltage will drop while the FET load line remains the same, so the FET load line of each stage will be in the best condition. This is very different from the conventional method, and the problem arises that not only the output power decreases, but also the efficiency significantly decreases.

The present disclosure has been made to solve the above problems, and aims to provide a power amplifier that can suppress a decrease in efficiency even when the power supply voltage is lowered.

The power amplifier according to the present disclosure is a stacked circuit having n FETs, where n is an integer of 2 or more, and the FET numbers are 1 to n, and i is 2 or more and (n-1) or less. If it is an integer, the input signal is input to the gate terminal of the first FET, the drain terminal is connected to the source terminal of the second FET, the source terminal is the terminal connected to GND, and the i-th FET is the terminal that is connected to GND. , the drain terminal is connected to the source terminal of the (i+1)th FET, the output signal is output from the drain terminal of the nth FET, and the drain terminal is a terminal connected to the power supply. A resistor connected to the gate terminal of the second to nth FET in the circuit, a capacitor connected to the electrode opposite to the gate terminal of the resistor, and a first capacitor connected in parallel with the resistor, respectively. and a switch.

According to the present disclosure, it is possible to obtain a power amplifier that can suppress a decrease in efficiency even when the power supply voltage decreases.

1 is a diagram showing a circuit configuration of a power amplifier according to a first embodiment; FIG. FIG. 3 is a diagram showing load lines of FETs of the power amplifier according to the first embodiment. FIG. 3 is a diagram showing load lines of FETs of the power amplifier according to the first embodiment. FIG. 3 is a diagram showing a circuit configuration of a power amplifier according to a second embodiment. FIG. 7 is a diagram showing a circuit configuration of a power amplifier according to a third embodiment.

Embodiment 1.
FIG. 1 shows a circuit configuration of a power amplifier 10 according to the first embodiment. It is assumed that a 65 nm CMOS process is used to manufacture the power amplifier 10, and that the maximum standard voltage of the FET is 1.2V. Here, the maximum standard voltage is the maximum DC voltage that can be applied between the drain and source terminals of an FET with the smallest gate length used in the CMOS process and that provides long-term reliability of the FET.

The FET 12 is a terminal into which an input signal is input from the input terminal 22 to a gate terminal, a drain terminal is connected to a source terminal of the FET 14, and the source terminal is connected to GND. The drain terminal of the FET 14 is connected to the source terminal of the FET 16. The drain terminal of the FET 16 is connected to the source terminal of the FET 18. An output signal is outputted from the drain terminal of the FET 18, and the drain terminal is connected to the power supply (Vdd). A circuit made up of these four FETs is called a stack type circuit 19. FET12, FET14, FET16 and FET18 are n-type FETs. Although not shown, an input matching circuit is connected to the input terminal 22. An output matching circuit 20 is connected between the output terminal 24 and the drain terminal of the third FET 18.

Bias terminal 50, bias terminal 52, and bias terminal 54 are gate bias terminals of FET14, FET16, and FET18, respectively, and are connected to the gate terminals of FET14, FET16, and FET18 via resistor 38, resistor 40, and resistor 42 of about kΩ. ing. FET switch 32, FET switch 34, and FET switch 36 are connected in parallel with resistor 38, resistor 40, and resistor 42, respectively. These FET switches function as resistor bypass switches. FET switch 32, FET switch 34, and FET switch 36 are turned on/off by switch terminal 56, switch terminal 58, and switch terminal 60, respectively.

Bias terminal 50, bias terminal 52, and bias terminal 54 are terminals on the opposite side from the gate terminals of resistor 38, resistor 40, and resistor 42, and capacitor 44, capacitor 46, and capacitor 48 are connected between them and GND, respectively. ing. Capacitor 44, capacitor 46, and capacitor 48 are variable capacitors.

Note that the number of FETs included in the stacked circuit is not limited to four. Here, the number of FETs included in the stacked circuit will be explained as n (n is a number of 2 or more). The numbers of these FETs are 1 to n, and i is an integer greater than or equal to 2 and less than or equal to (n-1). The first FET corresponds to the FET 12 in FIG. 1, has a gate terminal to which an input signal is input, a drain terminal connected to the source terminal of the second FET, and the source terminal connected to GND. The i-th FET corresponds to FET14 and FET16 in FIG. 1, and its drain terminal is connected to the source terminal of the (i+1)-th FET. The n-th FET corresponds to the FET 18 in FIG. 1, an output signal is output from the drain terminal, and the drain terminal is a terminal connected to the power supply (Vdd).

Returning to the case where the stack type circuit has four FETs, the explanation will be continued. Since the maximum standard voltage of the FET is 1.2V, the power supply voltage of the power amplifier 10 can be increased to 4.8V in DC voltage. The well of each FET is isolated, with the back gate connected to the source. If the FET is a fully depleted SOI (Silicon On Insulator), the back gate may be floating. Since the control FETs such as the FET switch 32, the FET switch 34, and the FET switch 36 also need to have a maximum withstand voltage of 4.8V, a high withstand voltage FET with a thick gate oxide film is used as the control FET.

When the power supply voltage is the maximum 4.8V, a voltage of 4.8V is applied to the drain terminal of the FET 18 if there is no voltage drop. If there is a voltage drop, the applied voltage will be reduced by that amount, but here the explanation will be made assuming that there is no voltage drop. When the power supply voltage is 4.8V, FET switch 32, FET switch 34, and FET switch 36 are all closed, and resistor 38, resistor 40, and resistor 42 are bypassed. By doing so, a voltage of 1.2V is applied between the drain and source terminals of each of FET12, FET14, FET16, and FET18, and these FETs all perform an amplifying operation.

Next, consider the case where the power supply voltage is lowered to 3.6V. In this case, FET switch 32 and FET switch 34 are closed, and FET switch 36 is opened. Resistor 42 is therefore enabled and FET 18 operates in switch mode. Here, the switch mode is an operating state in which the gate terminal of the FET is made floating by a resistor, so that the input to the source terminal is output from the drain terminal with almost no loss. The remaining FET12, FET14, and FET16 perform an amplification operation. By doing this, the voltage drop between the drain and source terminals of FET18 is minimized, and a voltage of approximately 1.2V is applied between the drain and source terminals of FET12, FET14, and FET16, which perform amplification operations. Therefore, the optimum state for power amplification operation can be achieved. That is, the FET operates in the saturation region so that the voltage amplitude and current amplitude during amplification can be made sufficiently large.

Next, consider the case where the power supply voltage is lowered to 2.4V. In this case, the FET switch 32 is closed, and the FET switches 34 and 36 are opened. Therefore, the resistors 40 and 42 at the gate terminals of the FETs 16 and 18 become effective, and the FETs 16 and 18 operate in the switch mode. The remaining FET12 and FET14 perform an amplification operation. By doing this, the voltage drop between the drain and source terminals of FET16 and FET18 is minimized, and a voltage of approximately 1.2V is applied between the drain and source terminals of FET12 and FET14, which perform amplification operations. Therefore, sufficient amplification operation is possible.

Next, consider the case where the power supply voltage is lowered to 1.2V. In this case, FET switch 32, FET switch 34, and FET switch 36 are all opened. Therefore, the resistors 38, 40, and 42 at the gate terminals of FET14, FET16, and FET18 become effective, and FET14, FET16, and FET18 operate in the switch mode. The remaining FET 12 performs an amplification operation. By doing this, the voltage drop between the drain and source terminals of FET14, FET16, and FET18 is minimized, and a voltage of approximately 1.2V is applied between the drain and source terminals of FET12, which performs amplification operation. , can perform sufficient amplification operation.

Note that when the power supply voltage is lowered, the order in which the FET switches are opened does not have to be from the upper FET switch 36 as described above.

Let us generalize the previous explanation. Assume that the number of FETs included in the stacked circuit is n (n is an integer of 2 or more), and the FETs are numbered as described above. Assuming that the maximum standard voltage of all these FETs is Vm, and the voltage applied to the drain terminal of the n-th FET is Vd, and j is an integer greater than or equal to 1 and less than or equal to n, then (j-1) x Vm If <Vdd≦j×Vm, (j-1) of the FET switches are closed and the rest are opened.

Even if the power supply voltage is lowered in this way, by appropriately opening the FET switch 32, FET switch 34, and FET switch 36 according to the level of the power supply voltage drop, the FET can be connected between the drain and source terminals of the FET that performs amplification operation. A voltage sufficient to operate in the saturation region can be applied.

The capacitance values of the capacitors may be set so that the load lines of each of FET12, FET14, FET16, and FET18 are equal. FIG. 2 schematically shows a load line when all FETs perform an amplifying operation. To make the load lines of each FET equal, let the input impedance of FET14, FET16, and FET18 be Zi (i=1, 2, 3), and let Ropt be the optimal load resistance of the first stage FET, then Z1=Ropt, It is preferable that Z2=2×Ropt and Z3=3×Ropt. 4×Ropt is made equal to the load impedance seen from the drain terminal of the FET 18. For example, if the impedance of the output matching circuit 20 is 50Ω, Ropt is 12.5Ω. This makes the load lines of FET12, FET14, FET16, and FET18 equal.

In order to set Zi (i=1, 2, 3) to the above values, the capacitance values of capacitance 44, capacitance 46, and capacitance 48 can be set to predetermined values using equation 1 (non-patent (See Reference 1).

Here, Cgs is the gate-source capacitance of FET14, FET16, and FET18, Ci (i=1, 2, 3) is the capacitance value of capacitor 44, capacitor 46, and capacitor 48, and gm is the mutual conductance of FET14, FET16, and FET18. be. Here, it is assumed that the mutual conductance and gate-source capacitance of FET14, FET16, and FET18 are equal, and the operating frequency is sufficiently lower than the cutoff frequency of these FETs.

If the power supply voltage is lowered, the load line of each FET will change. For example, assume that the power supply voltage is lowered to 3.6V, the FET switch 36 is opened, and the FET 18 is operated in switch mode. In this case, the input impedance Z3 of the FET 18 is 4×Ropt. Then, the load line of the FET 18 deviates from the optimal load line drawn with a broken line, as shown in FIG.

In order to reduce changes in the load line, it is preferable to change the capacitance values of the variable capacitors 44 and 46. Specifically, the capacitance value C1 of the capacitor 44 is set so that Z1=1/3×4×Ropt, and the capacitance value C2 of the capacitor 46 is set so that Z2=2/3×4×Ropt. Set. By doing so, changes in the load lines of FET12, FET14, and FET16 can be suppressed.

Similarly, when the power supply voltage is lowered to 2.4V, FET switch 34 and FET switch 36 are opened and FET16 and FET18 are operated in switch mode, the capacitance value C1 of capacitor 44 is Z1=1/2×4 Set so that ×Ropt.

Let us generalize the previous explanation. Assume that the number of FETs included in the stacked circuit is n (n is an integer of 2 or more), and the FETs are numbered as described above. Let Z0 be the load impedance seen from the drain terminal of the n-th FET. The number of FETs performing an amplification operation among the second to n-th FETs is assumed to be m, and the numbers of the FETs performing an amplification operation are 1 to m in order from the smallest number of FETs in the stacked circuit. If k is an integer greater than or equal to 1 and less than or equal to m, the input impedance seen from the source terminal of the k-th FET that performs amplifying operation is calculated from (k-0.5)/(m+1)×Z0 to (k+0.5)/( It is sufficient to set it within the range of m+1)×Z0. Ideally, the input impedance is set to k/(m+1)×Z0, but it may have a width of the above range.

Even if the power supply voltage is lowered in this way, by appropriately setting the input impedance of the FET, it is possible to equalize the load lines of the FET that performs the amplification operation.

As described above, according to this embodiment, even when the power supply voltage is lowered, a voltage sufficient for the FET to operate in the saturation region is applied between the drain and source terminals of the FET that performs the amplifying operation. be able to. Therefore, a decrease in efficiency of the power amplifier can be suppressed.

Furthermore, even when the power supply voltage is lowered, the load lines of the FETs that perform amplifying operation can be made equal. Therefore, a decrease in efficiency of the power amplifier can be suppressed.

Furthermore, since switching is performed using an FET switch, there is no need for an additional path such as a high-frequency bypass circuit at a location where high-frequency signals are transmitted. Therefore, the circuit area can be reduced.

Embodiment 2.
In the power amplifier according to the second embodiment, in addition to the capacitors 44, 46, and 48 of the power amplifier 10 according to the first embodiment, an additional capacitor whose connection can be turned on/off by an FET switch is added.

Here, explanation will be made using FIG. 4, which shows only the vicinity of the gate terminal of the FET 14. As shown in FIG. 4, in addition to the capacitor 44, an FET switch 64 and an additional capacitor 62, and an FET switch 70 and an additional capacitor 68 are added. The additional capacitor 62 can be turned on/off with a FET switch 64. The additional capacitor 68 can be turned on/off with a FET switch 70.

Like the power amplifier 10 according to the first embodiment, the power amplifier according to this embodiment also has four FETs involved in amplification, so as can be seen from the explanation in the first embodiment, the gate terminal of the FET 14 is It is preferable that the capacitance value of the connected capacitor can be set to one of three values. In this embodiment, three capacitance values can be switched by turning on/off the FET switch 64 and the FET switch 70.

Note that the above is applicable not only to the FET 14 but also to the FET 16 and FET 18.

As described above, in this embodiment, the capacitance value can be changed digitally using a normal FET. Therefore, compared to analog variable capacitors, control is easier and the circuit area can be reduced.

Embodiment 3.
As shown in FIG. 5, power amplifier 110 according to the third embodiment has a differential circuit configuration of power amplifier 10 according to the first embodiment. Accordingly, the input signal also becomes a differential signal, and this differential signal is input to the input terminal 122 and the input terminal 123. Differentialization can significantly suppress the influence of gain reduction due to GND inductance, which is often a problem with single-phase amplifiers mounted on Si-based LSIs. Furthermore, the power amplifier according to the second embodiment may be made differential.

Note that in the power amplifiers according to all embodiments, GaAs FETs, InP FETs, etc. can also be used instead of CMOS. When using GaAs or InP, the back gate is usually floating.

12, 14, 16, 18 FET, 38, 40, 42 resistor, 44, 46, 48 capacitor, 32, 34, 36, 64, 70 FET switch, 20 output matching circuit, 62, 68 additional capacitor, 19 stack type circuit

Claims (6)

A stacked circuit having n FETs, where n is an integer of 2 or more ,
If the numbers of the FETs are 1 to n, and i is an integer of 2 or more and (n-1) or less,
The first FET has a gate terminal to which an input signal is input, a drain terminal connected to a source terminal of the second FET, and a source terminal connected to GND.
The i-th FET has its drain terminal connected to the source terminal of the (i+1)-th FET,
The n-th FET has a stacked circuit in which an output signal is output from the drain terminal, and the drain terminal is a terminal connected to a power supply.
Resistors connected to the gate terminals of the second to nth FETs of the stacked circuit, respectively;
a capacitor each connected to an electrode on the opposite side of the gate terminal of the resistor;
a first switch each connected in parallel with the resistor;
Power amplifier with. The power amplifier according to claim 1, wherein the first switch is a FET switch. It is assumed that the maximum standard voltage of the FETs in the stacked circuit is Vm,
Let Vd be the voltage applied to the drain terminal of the n-th FET of the stacked circuit,
If j is an integer greater than or equal to 1 and less than or equal to n,
The power amplifier according to claim 1 or 2, wherein (j-1) of the switches are closed and the remaining switches are opened when (j-1)×Vm<Vd≦j×Vm. Let Z0 be the load impedance seen from the drain terminal of the n-th FET of the stacked circuit,
m is an integer greater than or equal to 1, and the number of FETs that perform an amplification operation among the second to nth FETs of the stacked circuit is m ;
The numbers of the FETs that perform the amplification operation are set from 1 to m in order from the smallest number of the FETs of the stacked circuit,
If k is an integer greater than or equal to 1 and less than or equal to m,
The input impedance seen from the source terminal of the k-th FET that performs the amplification operation is set within the range of (k-0.5)/(m+1)×Z0 to (k+0.5)/(m+1)×Z0. The power amplifier according to item 1. an additional capacitor that can be turned on/off by a second switch in parallel with the capacitor;
The power amplifier according to claim 4, wherein the input impedance is set by turning on/off the second switch. The power amplifier according to claim 5, wherein the second switch is comprised of a FET switch.

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