JP7236078B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device.

In recent years, crystal growth methods for nitride-based semiconductors have progressed rapidly, and blue and green light-emitting devices with high brightness using this material have been put to practical use. By combining conventional red light-emitting elements with these blue light-emitting elements and green light-emitting elements, all the three primary colors of light are obtained, and a full-color display device can be realized. That is, by mixing all the three primary colors of light, it becomes possible to obtain white light, which can be applied to illumination devices.

A semiconductor light-emitting device used as a light source for lighting is desirably capable of achieving high energy conversion efficiency and high light output in a high current density region, and is desirably stable in light distribution characteristics of emitted light. In order to solve these problems, Patent Document 1 proposes a semiconductor light-emitting device in which an n-type nanowire core, an intermediate active layer, and a p-type shell are grown on a semiconductor substrate, and a transparent conductive film such as ITO is formed on the shell. It is

However, in the prior art of Patent Document 1, it is necessary to form an ITO film on the shell for current injection, and a part of the light emitted from the intermediate active layer is absorbed by the ITO film, which reduces the external quantum efficiency. occurs. In particular, edge-emitting lasers and vertical-cavity semiconductor lasers have a structure in which light travels back and forth within the cavity, so there is a problem that light absorption by ITO adversely affects laser oscillation.

Further, in Patent Document 2, in order to prevent light absorption in the transparent conductive film, a p-type semiconductor layer and a tunnel junction layer are formed on the outer periphery of the active layer, and the embedded semiconductor layer is used as a contact layer from the side of the nanowire core. Techniques for injecting current are disclosed.

Japanese Patent Publication No. 2016-518703 JP 2019-012744 A

In the prior art of Patent Document 2, in order to activate the p-type semiconductor layer included in the columnar semiconductor layer, after forming the tunnel junction layer, part of the tunnel junction layer is removed to expose the p-type semiconductor layer. By performing heat treatment, the hydrogen taken into the p-type semiconductor layer is released and the p-type semiconductor layer is activated.

However, in Patent Document 2, since the embedded semiconductor layer is regrown after the p-type semiconductor layer is activated, the hydrogen contained in the ammonia of the nitrogen source gas used for growing the embedded semiconductor layer is absorbed into the p-type semiconductor layer. and part of the p-type semiconductor layer may be inactivated. If a part of the p-type semiconductor layer is inactivated in a semiconductor light-emitting device, it is not preferable because it causes a decrease in luminous efficiency and an increase in forward voltage.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the conventional problems described above, and provides a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device capable of improving the activation rate of a p-type semiconductor layer in a columnar semiconductor layer. for the purpose.

In order to solve the above problems, a semiconductor light emitting device of the present invention is a semiconductor light emitting device comprising a growth substrate, a columnar semiconductor layer formed on the growth substrate, and a buried semiconductor layer covering the columnar semiconductor layer. wherein the columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed outside the n-type nanowire layer, and a p-type semiconductor layer formed around the active layer, A tunnel junction layer is formed outside the p-type semiconductor layer, and at least a portion of the columnar semiconductor layer is provided with a removed region obtained by removing a portion of the tunnel junction layer from the buried semiconductor layer. It is characterized by

In such a semiconductor light emitting device of the present invention, since part of the buried semiconductor layer and the tunnel junction layer are removed in the removed region, the p-type semiconductor layer is activated after growing all the semiconductor layers. It is possible to prevent hydrogen from being taken in by re-growth after the activation treatment and improve the activation rate of the p-type semiconductor layer in the columnar semiconductor layer.

Further, in one aspect of the present invention, a plurality of the columnar semiconductor layers are provided, and the removal region is provided over the plurality of the columnar semiconductor layers.

Further, in one aspect of the present invention, the removal region is removed up to part of the p-type semiconductor layer.

Further, in one aspect of the present invention, the removal region is removed up to a part of the active layer.

Moreover, in one aspect of the present invention, the removal region is removed up to a part of the n-type nanowire layer.

Further, in one aspect of the present invention, an insulating film is formed on the removed region, and a transparent electrode is formed covering at least part of the embedded semiconductor layer and the removed region.

In one aspect of the present invention, a high resistance layer is formed on top of the n-type nanowire layer.

In order to solve the above problems, the method for manufacturing a semiconductor light emitting device of the present invention includes a mask step of forming a mask layer having an opening on a growth substrate, and forming a columnar semiconductor layer in the opening using selective growth. and a embedding step of growing a buried semiconductor layer on the growth substrate so as to cover the columnar semiconductor layer, wherein the growing step includes forming an n-type nanowire layer, and forming the n-type nanowire layer. forming an active layer outside the nanowire layer; forming a p-type semiconductor layer outside the active layer; and forming a tunnel junction layer outside the p-type semiconductor layer. a removal step of forming a removed region by removing from the embedded semiconductor layer to a portion of the tunnel junction layer in at least a portion of the columnar semiconductor layer after the embedding step; It is characterized by having an activation step of annealing the semiconductor layer.

INDUSTRIAL APPLICABILITY The present invention can provide a semiconductor light emitting device capable of improving the activation rate of the p-type semiconductor layer in the columnar semiconductor layer and a method for manufacturing the semiconductor light emitting device.

1 is a schematic diagram showing a semiconductor light emitting device 10 according to a first embodiment; FIG. 2(a) is a mask formation process, FIG. 2(b) is a nanowire growth process, FIG. 2(c) is a growth process, and FIG. 2(d) is a removal process. FIG. 2(e) shows the electrode formation process. FIG. 5 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 30 according to a second embodiment; FIG. 11 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 40 according to a third embodiment; 5(a) is a mask formation process, FIG. 5(b) is a nanowire growth process, FIG. 5(c) is a growth process, and FIG. 5(d) is a removal process. FIG. 5(e) shows the electrode forming process. FIG. 11 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 50 according to a fourth embodiment; FIG. 11 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 60 according to a fifth embodiment;

(First embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. FIG. 1 is a schematic diagram showing a semiconductor light emitting device 10 according to the first embodiment.

As shown in FIG. 1, a semiconductor light emitting device 10 includes a growth substrate 11, an underlying layer 12, a mask 13, an n-type nanowire layer 14, an active layer 15, a p-type semiconductor layer 16, and a tunnel junction layer 17. and a buried semiconductor layer 18 . Here, the n-type nanowire layer 14, the active layer 15, the p-type semiconductor layer 16, and the tunnel junction layer 17 are selectively grown in a direction perpendicular to the growth substrate 11 to form a columnar shape. make up the layers. In a portion of the plurality of columnar semiconductor layers, a removed region 19 is formed by removing the embedded semiconductor layer 18 to a portion of the tunnel junction layer 17 and the p-type semiconductor layer 16 .

As shown in FIG. 1, the underlying layer 12 is partially exposed in the semiconductor light emitting device 10, and cathode electrodes 20 and 21 are formed on the underlying layer 12. As shown in FIG. Moreover, the embedded semiconductor layer 18 is left in a partial region above the columnar semiconductor layer, and the anode electrodes 22 and 23 are formed on the embedded semiconductor layer 18 in this region. As described above, in regions where anode electrodes 22 and 23 are not formed, buried semiconductor layer 18 and tunnel junction layer 17 are removed until p-type semiconductor layer 16 is partially exposed to form removed region 19 . ing. Here, the exposure of the p-type semiconductor layer 16 means that the p-type semiconductor layer 16 is exposed after all the semiconductor layers constituting the semiconductor light emitting device 10 are formed. , an insulating film or the like may be formed.

The growth substrate 11 is a substantially flat member made of a material capable of crystal growth of a semiconductor material, and has a mask 13 formed on its main surface. The growth substrate 11 may be composed of a single material, or may be a single crystal substrate on which a plurality of semiconductor layers such as a buffer layer are grown. The growth substrate 11 may be a single-crystal substrate made of a material for growing a semiconductor single-crystal layer through a buffer layer. A sapphire substrate is preferred, but other heterogeneous substrates such as Si may be used. Also, for laser oscillation, a c-plane GaN substrate, on which cavity planes are easily formed by cleavage, may be used. The buffer layer is a layer formed between the single crystal substrate and the underlying layer 12 to alleviate the lattice mismatch between the two. When a c-plane sapphire substrate is used as the single crystal substrate, AlN is preferably used as the material, but GaN, AlGaN, or the like may also be used.

The underlying layer 12 is a single-crystal semiconductor layer formed on the growth substrate 11 and the buffer layer, and is preferably formed of non-doped GaN with a thickness of several μm. The underlying layer 12 may be composed of a single layer, or may be composed of multiple layers including an n-type semiconductor layer such as an n-type contact layer. The n-type contact layer is a semiconductor layer doped with an n-type impurity, such as Si-doped n-type Al _0.05 Ga _0.95 N. As shown in FIG. 1, a portion of the underlying layer 12 is exposed to form cathode electrodes 20 and 21 .

Mask 13 is a layer made of a dielectric material formed on the surface of underlying layer 12 . As a material for forming the mask 13, a material that makes crystal growth of a semiconductor difficult is selected from the mask 13. For example, _SiO.sub.2 and _SiN.sub.x are suitable. A plurality of openings, which will be described later, are formed in the mask 13, and a semiconductor layer can be grown from the underlying layer 12 partially exposed through the openings.

The columnar semiconductor layer is a semiconductor layer crystal-grown in the opening provided in the mask 13 , and the substantially columnar semiconductor layer is formed vertically with respect to the main surface of the growth substrate 11 . Such a columnar semiconductor layer can be obtained by setting appropriate growth conditions according to the semiconductor material to be formed, and performing selective growth in which a specific crystal plane orientation is grown. In the example shown in FIG. 1, since a plurality of openings are formed in the mask 13 two-dimensionally and periodically, the columnar semiconductor layers are also formed two-dimensionally and periodically on the growth substrate 11 . Although an example in which the columnar semiconductor layers are arranged two-dimensionally and periodically is shown here, the number of columnar semiconductor layers may be one, and a plurality of columnar semiconductor layers may be formed aperiodically.

The n-type nanowire layer 14 is a columnar semiconductor layer selectively grown on the underlying layer 12 exposed through the opening of the mask 13, and is made of GaN doped with n-type impurities, for example. When GaN is used as the n-type nanowire layer 14, the n-type nanowire layer 14 selectively grown on the c-plane of the underlayer 12 has a substantially hexagonal prism shape with six m-planes formed as facets. In FIG. 1, it seems that the n-type nanowire layer 14 is grown only in the region where the opening is formed. An enlarged hexagonal prism is formed. For example, when the opening is formed as a circle with a diameter of about 150 nm, the n-type nanowire layer 14 having a hexagonal prism shape with a height of about 1 to 2 mm and a hexagonal bottom surface inscribed in a circle with a diameter of about 240 nm is formed. can be done.

The active layer 15 is a semiconductor layer grown on the outer circumference of the n-type nanowire layer 14. For example, a _{Ga0.85In0.15N} quantum well layer with a thickness of 5 nm and a GaN barrier layer with a _thickness of 10 nm are arranged in five cycles. Stacked multiple quantum well active layers are included. Although a multiple quantum well active layer is mentioned here, a single quantum well structure or a bulk active layer may be used. Since the active layer 15 is formed on the side and top surfaces of the n-type nanowire layer 14, the area of the active layer 15 can be secured.

The p-type semiconductor layer 16 is a semiconductor layer grown outside the active layer 15, and is made of GaN doped with p-type impurities, for example. Since the p-type semiconductor layer 16 is formed on the side surface and the upper surface of the active layer 15, the n-type nanowire layer 14, the active layer 15 and the p-type semiconductor layer 16 form a double hetero structure, and the carriers are well transferred to the active layer 15. can be confined to improve the probability of radiative recombination. In the semiconductor light emitting device 10 of the present embodiment, the p-type semiconductor layer 16 is removed halfway by etching when forming the removal region 19 . Therefore, it is preferable to increase the thickness of the p-type semiconductor layer 16 grown on the upper surface of the active layer 15 so that the etching does not reach the active layer 15. For example, the thickness of the p-type semiconductor layer 16 is increased to 200 nm or more.

The tunnel junction layer 17 is a semiconductor layer grown outside the p-type semiconductor layer 16. For example, the tunnel junction layer 17 includes a p+ layer heavily doped with p-type impurities on the inside and a heavily doped n-type impurity on the outside. It has a two-layer structure in which the n+ layer and the n+ layer are grown in order. The p+ layer is a semiconductor layer heavily doped with p-type impurities, and can be made of GaN with a thickness of 5 nm and an Mg concentration of 2×10 ²⁰ cm ⁻³ , for example. For the n+ layer, for example, GaN with a thickness of 10 nm and a Si concentration of 2×10 ²⁰ cm ⁻³ can be used. Since a tunnel junction is formed by the p+ layer and the n+ layer, the two layers of the p+ layer and the n+ layer constitute the tunnel junction layer 17 in the present invention.

The buried semiconductor layer 18 is a semiconductor layer formed so as to cover the top surface and side surfaces of the columnar semiconductor layer and the mask 13 . As shown in FIG. 1, the buried semiconductor layer 18 also covers the tunnel junction layer 17 above the columnar semiconductor layers in the regions where the anode electrodes 22 and 23 are formed. Above the columnar semiconductor layer in the removed region 19 where the anode electrodes 22 and 23 are not formed, the embedded semiconductor layer 18 and the tunnel junction layer 17 are removed to expose the upper portion of the p-type semiconductor layer 16, and the tunnel junction layer 17 is removed. is in contact with the buried semiconductor layer 18 as shown in FIG.

The removed region 19 is a region in which at least part of the columnar semiconductor layer is removed from the buried semiconductor layer 18 to part of the tunnel junction layer 17 . Although the example shown in FIG. 1 shows an example in which not only the tunnel junction layer 17 but also the upper portion of the p-type semiconductor layer 16 are removed, at least part of the p-type semiconductor layer 16 may be exposed. In addition, although FIG. 1 shows an example in which the removal regions 19 are collectively formed over a plurality of columnar semiconductor layers, the removal regions 19 may be provided individually for the plurality of columnar semiconductor layers.

The cathode electrodes 20 and 21 are electrodes formed in the regions where the base layer 12 is exposed, and are composed of a layered structure of a metal material and a pad electrode that are in ohmic contact with the outermost surface of the base layer 12 . The anode electrodes 22 and 23 are electrodes formed on part of the embedded semiconductor layer 18, and are composed of a layered structure of a metal material and a pad electrode that are in ohmic contact with the outermost surface of the embedded semiconductor layer 18. FIG. Also, although not shown in FIG. 1, a known structure such as covering the surface of the semiconductor light emitting device 10 with a passivation film may be applied as necessary. Alternatively, a transparent electrode may be formed by extending the anode electrode 22 over the entire removal area 19 .

In order to lengthen the emission wavelength of the semiconductor light emitting device 10, the InN mole fraction of the active layer 15 must be increased. For example, when the diameter of the circumscribed circle of the n-type nanowire layer 14 is 300 nm, it is necessary to use a red active layer composition of Ga _0.6 In _0.4 N. may occur. In order to avoid this, it is possible to reduce the film thickness of the Ga _0.6 In _0.4 N well layer or to use GaInN as the material forming the n-type nanowire layer 14 . Similarly, when the wavelength of the semiconductor light emitting device 10 is shortened, AlGaN may be used as the n-type nanowire layer 14, or the well layer and barrier layer of the active layer 15 may be changed to AlGaN having different compositions. It is possible.

2A and 2B are schematic diagrams showing a method for manufacturing the semiconductor light emitting device 10. FIG. 2A is a mask forming step, FIG. 2B is a nanowire growing step, FIG. d) shows the removing step, and FIG. 2(e) shows the electrode forming step.

First, in the mask step shown in FIG. 2A, a buffer layer made of AlN, GaN and An underlayer 12 of Al _0.05 Ga _0.95 N is grown. Next, a mask 13 made of SiO ₂ is deposited on the underlying layer 12 by a sputtering method to a thickness of about 30 nm, and an opening having a diameter of about 150 nm is formed using a fine pattern forming method such as nanoimprinting lithography. The growth conditions for the buffer layer are, for example, TMA (TriMethylAluminium), TMG (TriMethylGallium) and ammonia are used as material gases, the growth temperature is 1100° C., the V/III ratio is 100, hydrogen is used as carrier gas and the pressure is 10 hPa. The growth conditions for the underlying layer 12 and the n-type semiconductor layer are, for example, a growth temperature of 1050° C., a V/III ratio of 1000, and a pressure of 500 hPa using hydrogen as a carrier gas.

Next, in the nanowire growth step shown in FIG. 2B, an n-type nanowire layer 14 made of GaN is grown on the underlying layer 12 exposed from the opening by selective growth by MOCVD. The growth conditions for the n-type nanowire layer 14 are, for example, TMG and ammonia as material gases, a growth temperature of 1050° C., a V/III ratio of 10, and hydrogen as a carrier gas at a pressure of 100 hPa.

Next, in the growth step shown in FIG. 2C, a 5 nm-thick Ga _0.85 In _0.15 N quantum well layer and a 10 nm-thick An active layer 15 in which five GaN barrier layers are stacked, a p-type semiconductor layer 16 made of GaN doped with a p-type impurity, a p+ layer made of GaN with a thickness of 5 nm and an Mg concentration of 2×10 ²⁰ cm ⁻³ , a thickness of A tunnel junction layer 17 including an n+ layer having a thickness of 10 nm and a Si concentration of 2×10 ²⁰ cm ⁻³ is grown sequentially. Next, a buried semiconductor layer 18 made of n-type GaN is grown to fill the outer periphery and upper surface of the tunnel junction layer 17 with the buried semiconductor layer 18 .

The growth conditions for the active layer 15 are, for example, a growth temperature of 800° C., a V/III ratio of 3000, a pressure of 1000 hPa with nitrogen as a carrier gas, and TMG, TMI (Trimethylindium) and ammonia as source gases. The growth conditions for the p-type semiconductor layer 16 are, for example, a growth temperature of 950° C., a V/III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, Cp2Mg (biscyclopentadienylmagnesium) and ammonia as source gases. As described above, in order to stop the etching at the p-type semiconductor layer 16 when forming the removal region 19, it is preferable to increase the thickness of the p-type semiconductor layer 16. Conditions that promote c-plane growth, which is the growth of The growth conditions for the tunnel junction layer 17 are, for example, a growth temperature of 800° C., a V/III ratio of 3000, and a pressure of 500 hPa using nitrogen as a carrier gas.

As described above, the buried semiconductor layer 18 needs to be grown on the mask 13 provided between the columnar semiconductor layers, and when the buried semiconductor layer 18 is grown, voids may occur under the columnar semiconductor layers. have a nature. Therefore, in the growth of the buried semiconductor layer 18, it is preferable to use TMG, silane and ammonia as raw material gases and to grow at a low temperature and a low V/III ratio that promote growth of the m-plane, which is lateral growth, in the initial stage. . An example of a low temperature and low V/III ratio is a V/III ratio of 100 or less at 800° C. or less and hydrogen as a carrier gas and a pressure of 200 hPa.

After the top of the mask 13 is completely buried under the columnar semiconductor layer by the lateral growth of the buried semiconductor layer 18, it grows at a high temperature and a high V/III ratio that promotes the growth of the c-plane, which is the vertical growth. is preferred. An example of a high temperature and high V/III ratio is a V/III ratio of 2000 or more at 1000° C. or more and hydrogen as a carrier gas and a pressure of 500 hPa.

Next, in the removal step shown in FIG. 2D, the embedded semiconductor layer 18, the tunnel junction layer 17 and part of the p-type semiconductor layer 16 are selectively removed by dry etching, and the upper surface of the p-type semiconductor layer 16 is removed. A removal region 19 is formed by exposing. In the regions where the cathode electrodes 20 and 21 are to be formed, the mask 13 is also removed to expose the upper surface of the underlying layer 12 .

Next, after the removing step, the p-type semiconductor layer 16 is exposed and annealed at 600.degree. Then, an activation step of activating the p-type semiconductor layer 16 and the tunnel junction layer 17 is performed. Annealing in an air atmosphere is shown here, but an atmosphere in which atomic hydrogen that can activate the p-type semiconductor layer 16 and the tunnel junction layer 17 does not exist may be used.

Finally, in the electrode forming step shown in FIG. 2E, cathode electrodes 20 and 21 are formed on the surface of the base layer 12, and anode electrodes 22 and 23 are formed on the embedded semiconductor layer 18. As shown in FIG. Further, if necessary, annealing after electrode formation, formation of a passivation film, and element division are performed to obtain the semiconductor light emitting element 10 .

As described above, in the semiconductor light emitting device 10, after all the semiconductor layers constituting the semiconductor light emitting device 10 have been grown, the removal region 19 is formed to expose the p-type semiconductor layer 16, and activation treatment can be performed. Therefore, it is not necessary to regrow the semiconductor layer after the activation process, and the hydrogen contained in the ammonia of the nitrogen source gas used for regrowth is prevented from being taken into the p-type semiconductor layer. It is possible to improve the activation rate of the p-type semiconductor layer.

In addition, in the columnar semiconductor layer located under the regions where the anode electrodes 22 and 23 are formed, the activation treatment is performed while the upper portion of the p-type semiconductor layer 16 is covered with the tunnel junction layer 17 and the embedded semiconductor layer 18 . Since it is carried out, it is difficult for the hydrogen taken in to be released. Therefore, the p-type semiconductor layer 16 in the columnar semiconductor layer below the anode electrodes 22 and 23 remains at a high resistance, no current is injected into the active layer 15, and no light is emitted.

In the semiconductor light emitting device 10 of this embodiment, when a voltage is applied between the cathode electrodes 20 and 21 and the anode electrodes 22 and 23, the buried semiconductor layer 18, the tunnel junction layer 17, the p-type semiconductor layer 16, the active layer 15, A current flows through the n-type nanowire layer 14 and the n-type semiconductor layer in that order, and light is generated by radiative recombination in the active layer 15 . Light emitted from the active layer 15 is extracted to the outside of the semiconductor light emitting device 10 .

In addition, in the semiconductor light emitting device 10 of this embodiment, the active layer 15 is formed on the outer periphery of the n-type nanowire layer 14, and the tunnel junction layer 17 is formed on the outer periphery thereof, and is embedded with the buried semiconductor layer 18. . Therefore, the current injected from the anode electrodes 22 and 23 is injected from the sidewall of the p-type semiconductor layer 16 into the active layer 15 as a tunnel current from the buried semiconductor layer 18 via the tunnel junction layer 17 . In addition, in the upper part of the columnar semiconductor layer, the upper surface of the p-type semiconductor layer 16 in contact with the n-type buried semiconductor layer 18 is reverse biased, and the buried semiconductor layer 18 is removed in the removal region 19 . Therefore, no current is injected into the upper surface of the p-type semiconductor layer 16 . The current injection by the tunnel current through the tunnel junction layer 17 has a small resistance and can be carried out satisfactorily. In addition, since the buried semiconductor layer 18, which is an n-type semiconductor layer, diffuses current more easily than a p-type semiconductor layer, the current is favorably diffused from the side surface of the columnar semiconductor layer to the vicinity of the bottom surface, and the tunnel junction layer 17 is formed. Current injection can be done from the whole.

As a result, the current injected from the anode electrodes 22 and 23 is well injected into the p-type semiconductor layer 16 not from the upper surface of the columnar semiconductor layer but from the entire side surface of the columnar semiconductor layer, and the current is well injected into the active layer 15, resulting in a high It is possible to realize current density and improve external quantum efficiency.

In addition, since the side surfaces of the n-type nanowire layer 14 are m-planes formed by selective growth, the active layer 15 and the p-type semiconductor layer 16 formed on the outer periphery are also in contact with each other on the m-planes. Since the m-plane is a nonpolar plane and does not cause polarization, the luminous efficiency in the active layer 15 is high, and since all the side surfaces of the hexagonal prism are m-planes, the luminous efficiency of the semiconductor light-emitting device 10 can be improved. Furthermore, when the height of the columnar semiconductor layer is increased to 500 nm or more, the volume of the active layer 15 can be increased to about 3 to 10 times that of the conventional semiconductor light emitting device, and the density of injected carriers is reduced, resulting in an efficient droop. can be greatly reduced.

Furthermore, since the embedded semiconductor layer 18 is made of a material having a bandgap larger than that of the active layer 15, the embedded semiconductor layer 18 is less likely to inject current into the columnar semiconductor layer using ITO or the like. can significantly reduce the light absorption of As a result, the absorption of light generated in the active layer 15 inside the semiconductor light emitting device 10 can be suppressed, and the external quantum efficiency for extracting light to the outside of the semiconductor light emitting device 10 can be improved.

As described above, in the semiconductor light emitting device 10 and the manufacturing method thereof according to the present embodiment, the embedded semiconductor layer 18 and the tunnel junction layer 17 are partly removed in the removed region 19, so that all the semiconductor layers are removed. The p-type semiconductor layer 16 can be activated after it has been grown, preventing hydrogen from being taken in by re-growth after the activation process, and improving the activation rate of the p-type semiconductor layer 16 in the columnar semiconductor layer. Is possible.

(Second embodiment)
Next, a second embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 3 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 30 according to the second embodiment. This embodiment differs from the first embodiment in that the active layer 15 is partially removed in the removal region 19 .

As shown in FIG. 3, in the semiconductor light emitting device 30 of this embodiment as well, the growth substrate 11, the underlying layer 12, the mask 13, the n-type nanowire layer 14, the active layer 15, the p-type semiconductor layer 16, A tunnel junction layer 17 and a buried semiconductor layer 18 are provided, and a removed region 19 is formed by removing a portion of the columnar semiconductor layer.

In the semiconductor light emitting device 30 of the present embodiment, the embedded semiconductor layer 18, the tunnel junction layer 17, the p-type semiconductor layer 16 and the active layer 15 are removed in the removed region 19, and at least a part of the p-type semiconductor layer 16 is removed. exposed. Although FIG. 3 shows an example in which the upper surface of the active layer 15 is removed, a part of the lower n-type nanowire layer 14 may also be removed.

Also in the present embodiment, since the buried semiconductor layer 18 and the tunnel junction layer 17 are partly removed in the removal region 19, the p-type semiconductor layer 16 can be activated after all the semiconductor layers are grown. It is possible to prevent hydrogen from being taken in by re-growth after the activation treatment and improve the activation rate of the p-type semiconductor layer 16 in the columnar semiconductor layer.

In addition, since the active layer 15 formed on the upper surface of the columnar semiconductor layer is also removed, the active layer 15 contributing to light emission is only the portion provided on the side surface of the columnar semiconductor layer, and the m-plane efficiency is high. Luminescence can be enhanced.

(Third Embodiment)
Next, a third embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 4 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 40 according to the third embodiment. This embodiment differs from the first embodiment in that no columnar semiconductor layer is formed in the regions where the anode electrodes 22 and 23 are to be formed.

As shown in FIG. 4, in the semiconductor light emitting device 40 of this embodiment as well, the growth substrate 11, the underlying layer 12, the mask 13, the n-type nanowire layer 14, the active layer 15, the p-type semiconductor layer 16, A tunnel junction layer 17 and a buried semiconductor layer 18 are provided, and a removed region 19 is formed by removing a portion of the columnar semiconductor layer. In this embodiment, the anode electrodes 22 and 23 are formed on the mask 13 , and a part of the anode electrode 22 extends to the side surface and upper surface of the buried semiconductor layer 18 to form the extended portion 24 .

The extending portion 24 is a portion formed by extending a part of the anode electrode 22 from the side surface to the upper surface of the embedded semiconductor layer 18 , and is made of a metal material that makes ohmic contact with the embedded semiconductor layer 18 . Since the extending portion 24 is in ohmic contact with the embedded semiconductor layer 18 , current can be injected from the side surface and upper surface of the embedded semiconductor layer 18 . Although FIG. 4 shows an example in which the extending portion 24 is formed only in the regions adjacent to the anode electrodes 22 and 23 , the extending portion 24 may be formed over the entire upper surface of the embedded semiconductor layer 18 . Alternatively, the extending portion 24 may be formed only on the side surface of the embedded semiconductor layer 18 .

5A and 5B are schematic diagrams showing a method for manufacturing the semiconductor light-emitting device 40. FIG. 5A is a mask forming step, FIG. 5B is a nanowire growing step, FIG. 5d) shows the removing step, and FIG. 5(e) shows the electrode forming step.

In the mask process shown in FIG. 5A, a buffer layer and an underlying layer 12 are grown on a growth substrate 11, a mask 13 made of SiO ₂ is deposited on the underlying layer 12 by sputtering, and a nanoimprinting lithography is performed. A fine pattern forming method is used to form the openings. At this time, the regions where the cathode electrodes 20 and 21 and the anode electrodes 22 and 23 are to be formed are left covered with the mask 13 without forming openings.

Next, in the nanowire growth step shown in FIG. 5B, the n-type nanowire layer 14 is grown on the underlying layer 12 exposed from the opening. Next, in the growth step shown in FIG. 5C, an active layer 15, a p-type semiconductor layer 16, and a tunnel junction layer 17 are sequentially grown on the side and top surfaces of the n-type nanowire layer . Next, the buried semiconductor layer 18 is grown to fill the outer periphery and top surface of the tunnel junction layer 17 with the buried semiconductor layer 18 .

Next, in the removing step shown in FIG. 5D, the embedded semiconductor layer 18, the tunnel junction layer 17 and a part of the p-type semiconductor layer 16 are selectively removed by dry etching, and the upper surface of the p-type semiconductor layer 16 is removed. A removal region 19 is formed by exposing. Also, in the regions where the cathode electrodes 20 and 21 are to be formed, the mask 13 is removed to expose the upper surface of the underlying layer 12 . After the removing step, annealing is performed in a state where the p-type semiconductor layer 16 is exposed, hydrogen taken into the p-type semiconductor layer 16 and the tunnel junction layer 17 is released, and the p-type semiconductor layer 16 and the tunnel junction layer 17 are activated. An activation step is performed.

Finally, in the electrode forming step shown in FIG. 5E, cathode electrodes 20 and 21 are formed on the surface of the base layer 12, and anode electrodes 22 and 23 are formed on the mask 13. Next, as shown in FIG. At this time, the extended portion 24 is formed by patterning so that a portion of the anode electrode 22 covers a portion of the side surface and the upper surface of the embedded semiconductor layer 18 .

Also in the present embodiment, since the buried semiconductor layer 18 and the tunnel junction layer 17 are partly removed in the removal region 19, the p-type semiconductor layer 16 can be activated after all the semiconductor layers are grown. It is possible to prevent hydrogen from being taken in by re-growth after the activation treatment and improve the activation rate of the p-type semiconductor layer 16 in the columnar semiconductor layer.

In addition, since no columnar semiconductor layer is provided under the anode electrodes 22 and 23, light emission does not occur in the region where the light is blocked by the anode electrodes 22 and 23, and light emission due to the injected current can be efficiently emitted to the outside. can be taken out. In addition, since the anode electrodes 22 and 23 are formed below the active layer 15, it is possible to prevent the light emitted from the columnar semiconductor layers from being blocked by the anode electrodes 22 and 23, thereby improving the external quantum efficiency. can.

(Fourth embodiment)
Next, a fourth embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 6 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 50 according to the fourth embodiment. In this embodiment, the insulating film 26 is formed on the upper portion of the columnar semiconductor layer in the removal region 19, and the transparent electrode 25 is formed covering the insulating film 26 and the embedded semiconductor layer 18, which is the difference from the first embodiment. is different from

As shown in FIG. 6, the semiconductor light emitting device 50 of this embodiment includes a growth substrate 11, an underlying layer 12, a mask 13, an n-type nanowire layer 14, an active layer 15, a p-type semiconductor layer 16, A tunnel junction layer 17 and a buried semiconductor layer 18 are provided, and a removed region 19 is formed by removing a portion of the columnar semiconductor layer. In addition, an insulating film 26 is formed on the n-type nanowire layer 14, the active layer 15, the p-type semiconductor layer 16 and the tunnel junction layer 17, which constitute the columnar semiconductor layers in the removed region 19. A transparent electrode 25 is formed to cover 26 and the embedded semiconductor layer 18 .

The transparent electrode 25 is an electrode that is in ohmic contact with the embedded semiconductor layer 18 and that transmits light emitted from the active layer 15. For example, ITO or a metal multilayer film can be used. The transparent electrode 25 is formed by extending a part of the anode electrode 22, and is removed from the embedded semiconductor layer 18 in the region where the anode electrodes 22 and 23 are formed through the side surface of the embedded semiconductor layer 18. It is formed to cover the entire region 19 . A known sputtering method or EB vapor deposition method can be used to form the transparent electrode 25 .

The insulating film 26 is a layer made of an insulating material provided on the columnar semiconductor layer in the removal region 19, and can be made of AlN, SiO ₂ , SiN, or the like, for example. A transparent electrode 25 is formed on the insulating film 26, but since the insulating film 26 is inserted between the transparent electrode 25 and the columnar semiconductor layer, current is not injected from the upper surface of the columnar semiconductor layer.

In the semiconductor light emitting device 50 of the present embodiment, the current supplied from the anode electrodes 22 and 23 is not only from the buried semiconductor layer 18 located directly below the anode electrodes 22 and 23, but also passes through the transparent electrode 25 to the removed area. It is also implanted from the buried semiconductor layer 18 in 19 . Therefore, the current can be diffused satisfactorily to the side surfaces of the columnar semiconductor layers, and the current can be injected into the active layers 15 included in the plurality of columnar semiconductor layers. In addition, since the insulating film 26 is provided, it is possible to suppress the current injection from the upper surface of the columnar semiconductor layer to the active layer 15 and promote the current injection from the side surface, thereby improving the luminous efficiency.

Also in this embodiment, since the embedded semiconductor layer 18 and the tunnel junction layer 17 are partly removed in the removal region 19, the activation of the p-type semiconductor layer 16 is performed after all the semiconductor layers are grown. It is possible to prevent hydrogen from being taken in by re-growth after the activation treatment and improve the activation rate of the p-type semiconductor layer 16 in the columnar semiconductor layer.

(Fifth embodiment)
Next, a fifth embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 7 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 60 according to the fifth embodiment. This embodiment differs from the first embodiment in that a high resistance layer 27 is formed on the top of the n-type nanowire layer 14 .

As shown in FIG. 7, a semiconductor light emitting device 60 of this embodiment includes a growth substrate 11, an underlying layer 12, a mask 13, an n-type nanowire layer 14, a high resistance layer 27, an active layer 15, and a p It comprises a semiconductor layer 16, a tunnel junction layer 17, and a buried semiconductor layer 18, and a removed region 19 is formed by removing part of the columnar semiconductor layer. A transparent electrode 25 is formed so as to cover the upper surface of the removal region 19 .

The high resistance layer 27 is a layer provided on the top of the n-type nanowire layer 14 and is made of a semiconductor material having a higher resistance than the n-type nanowire layer 14 . The semiconductor material forming the high resistance layer 27 may have the same composition as the n-type nanowire layer 14 or may have a different composition. Also, the high resistance layer 27 may be formed as a non-doped layer or as a layer doped with a p-type impurity.

When a semiconductor material having the same composition as that of the n-type nanowire layer 14 is used as the high-resistance layer 27, at the end of the growth process of the n-type nanowire layer 14, the raw material supply of Si, which is an n-type impurity material, is stopped, The high-resistance layer 27 can be grown by supplying a raw material of Mg, which is a p-type impurity material.

In the semiconductor light emitting device 60 of the present embodiment, the current supplied from the anode electrodes 22 and 23 is not only from the embedded semiconductor layer 18 located directly below the anode electrodes 22 and 23, but also passes through the transparent electrode 25 to the removed region. It is also implanted from the buried semiconductor layer 18 in 19 . Therefore, the current can be diffused satisfactorily to the side surfaces of the columnar semiconductor layers, and the current can be injected into the active layers 15 included in the plurality of columnar semiconductor layers. In addition, by providing the high resistance layer 27 on the top of the n-type nanowire layer 14, the current injection from the top surface of the columnar semiconductor layer to the active layer 15 is suppressed, and the current injection from the side surface is promoted to increase the luminous efficiency. can be improved.

Also in this embodiment, since the embedded semiconductor layer 18 and the tunnel junction layer 17 are partly removed in the removal region 19, the activation of the p-type semiconductor layer 16 is performed after all the semiconductor layers are grown. It is possible to prevent hydrogen from being taken in by re-growth after the activation treatment and improve the activation rate of the p-type semiconductor layer 16 in the columnar semiconductor layer.

The present invention is not limited to the above-described embodiments, but can be modified in various ways within the scope of the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. is also included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 10, 30, 40, 50, 60... Semiconductor light emitting element 11... Growth substrate 12... Base layer 13... Mask 14... N-type nanowire layer 15... Active layer 16... P-type semiconductor layer 17... Tunnel junction layer 18... Buried semiconductor Layer 19 Removal area 20 Cathode electrode 22 Anode electrode 24 Extension part 25 Transparent electrode 26 Insulating film 27 High resistance layer

Claims (8)

A semiconductor light emitting device comprising a growth substrate, a columnar semiconductor layer formed on the growth substrate, and a buried semiconductor layer covering the columnar semiconductor layer,
The columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed around the n-type nanowire layer, a p-type semiconductor layer formed around the active layer, and the p-type semiconductor layer. A tunnel junction layer is formed on the outer periphery of the layer,
A semiconductor light-emitting device, wherein at least part of the columnar semiconductor layer is provided with a removed region obtained by removing part of the tunnel junction layer from the embedded semiconductor layer. The semiconductor light emitting device according to claim 1,
A semiconductor light-emitting device comprising a plurality of the columnar semiconductor layers, wherein the removal region is provided over the plurality of the columnar semiconductor layers. The semiconductor light emitting device according to claim 1 or 2,
A semiconductor light-emitting device, wherein the removed region includes a portion of the p-type semiconductor layer removed. The semiconductor light emitting device according to claim 1 or 2,
A semiconductor light-emitting device, wherein the removed region includes a part of the active layer. The semiconductor light emitting device according to claim 1 or 2,
The semiconductor light-emitting device, wherein the removed region is partially removed from the n-type nanowire layer. The semiconductor light emitting device according to any one of claims 1 to 5,
A semiconductor light emitting device, wherein an insulating film is formed on the removed region, and a transparent electrode is formed covering at least part of the embedded semiconductor layer and the removed region. The semiconductor light emitting device according to any one of claims 1 to 6,
A semiconductor light emitting device, wherein a high resistance layer is formed on top of the n-type nanowire layer. a masking step of forming a mask layer having an opening on a growth substrate; a growth step of forming a columnar semiconductor layer in the opening using selective growth; an embedding step of growing an embedded semiconductor layer;
The growth step includes forming an n-type nanowire layer, forming an active layer outside the n-type nanowire layer, forming a p-type semiconductor layer outside the active layer, and Forming a tunnel junction layer outside the p-type semiconductor layer,
a removal step of removing from the embedded semiconductor layer to a portion of the tunnel junction layer in at least a portion of the columnar semiconductor layer to form a removal region after the embedding step;
A method for growing a semiconductor light emitting device, comprising an activation step of annealing the p-type semiconductor layer after the removing step.

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