JP7213846B2 - Display device, data driver and display controller - Google Patents

Description

The present invention relates to a display device that displays an image according to a video signal, and a data driver and a display controller included in the display device.

2. Description of the Related Art At present, many large-screen display devices employ an active-matrix-driven liquid crystal panel as a display device.

In the liquid crystal panel, a plurality of data lines extending in the vertical direction of the two-dimensional screen and a plurality of gate lines extending in the horizontal direction of the two-dimensional screen are arranged so as to cross each other. Furthermore, at each intersection of the plurality of data lines and the plurality of gate lines, a pixel section including pixel switches connected to the data lines and the gate lines is formed. The pixel section consists of a transparent electrode arranged independently for each pixel, a counter substrate on which one transparent electrode that covers the entire two-dimensional screen of the liquid crystal panel is formed, and a transparent electrode of each pixel and the counter substrate. and a backlight.

The liquid crystal display device, together with such a liquid crystal panel, turns on a data driver for supplying a grayscale data signal having an analog voltage value corresponding to the luminance level of each pixel to a data line in units of one horizontal scanning period, and a pixel switch. - Includes a gate driver that applies a gate selection signal for off-control to each of the gate lines.

In a liquid crystal display device, when a pixel switch is turned on according to a gate selection signal sent from a gate driver, a gradation data signal sent from a data driver is applied to a transparent electrode of a pixel portion. Such an operation is hereinafter referred to as voltage supply to the pixel portion or charging (including discharging) to the pixel portion. At this time, the transmittance of the liquid crystal changes according to the potential difference between the voltage value of the gradation data signal applied to the transparent electrode of each pixel portion and the fixed voltage applied to the counter substrate (referred to as the counter substrate voltage). A display corresponding to the grayscale data signal is performed.

Furthermore, in the liquid crystal display device, in order to prevent deterioration of the liquid crystal of itself, a polarity reversal is performed to alternately supply a positive grayscale data signal and a negative grayscale data signal with respect to the counter substrate voltage every predetermined frame period. drive.

In addition, as the screen size and resolution of liquid crystal display devices have increased in recent years, the period length of one horizontal scanning period of a video signal has become shorter. The period during which the gradation data signal is supplied (also referred to as one data period) is also shortened. As a result, the charging period for the pixels is shortened, and in particular, the pixels to which the positive grayscale data signals are supplied (charged) are insufficiently charged as compared to the pixels to which the negative grayscale data signals are supplied (charged). was likely to occur.

That is, the pixel switch included in each pixel is actually a thin film transistor, and the current driving capability is determined according to the potential difference between the gate selection signal applied to its control terminal and the gradation data signal applied to its first terminal. , a gradation data signal is supplied to the pixel (transparent electrode) connected to the second terminal. Therefore, the smaller the potential difference between the gate selection signal and the gradation data signal, the smaller the current driving capability of the pixel switch, and the slower the charging speed of the gradation data signal to the pixel.

At this time, the voltage of the positive grayscale data signal is generally higher than the voltage of the negative grayscale data signal. Therefore, the potential difference between the positive grayscale data signal and the gate selection signal is smaller than the potential difference between the negative grayscale data signal and the gate selection signal. As a result, even if the pixels supplied (charged) with the gradation data signal of the negative polarity are properly charged within one data period, the pixels supplied (charged) with the gradation data signal of the positive polarity are charged. In some cases, it may become insufficient, and there is a possibility that flicker or image quality deterioration may occur in the displayed image.

Therefore, driving is adopted in which the polarity of the grayscale data signal is inverted for each horizontal scanning line, and the period length of one horizontal scanning period for writing with the grayscale data signal of positive polarity is changed to that of the grayscale data signal of negative polarity. There has been proposed a liquid crystal driving method that solves the above problem by making the period length longer than one horizontal scanning period in which writing is performed in (see, for example, Patent Document 1).

JP-A-2002-108288

By the way, as the screen size and resolution of liquid crystal display devices are increased, one data period is shortened and the wiring resistance and wiring capacitance of gate lines and data lines are increased. As a result, in pixels arranged at positions where the wiring length from the output terminal of the gate driver is long, the edges of the pulses of the gate selection signals reaching the pixels are duller than pixels arranged in closer positions. becomes larger. In addition, if the data line with a large potential difference due to polarity reversal is frequently charged and discharged, the power consumption (heat generation) of the data driver increases.

Therefore, in a large-screen and high-resolution liquid crystal panel, the polarities of the gradation data signals supplied to the data lines are set to be the same within a frame period, and the polarities of adjacent data lines are set to be different. So-called column inversion driving (also referred to as column-line inversion driving) is performed to invert the polarity of grayscale data signals supplied to lines.

However, even when column inversion driving is performed, as described above, even if the pixels supplied with the grayscale data signal of the negative polarity are properly charged, the pixels supplied with the grayscale data signal of the positive polarity are not charged. Insufficient charging may occur.

FIG. 1 shows a positive gradation data signal Vdx and a negative gradation data signal Vdx applied to adjacent Xth and (X+1)th data lines of a display panel during a certain frame period by column inversion driving. 4 is a time chart showing an example of an adjustment data signal Vd(x+1) and a gate selection signal Vgk applied to a gate line; In FIG. 1, similarly to the display panel 150 shown in FIG. 2 which will be described later, the first gate line closest to the data driver is GL1, the furthest r-th gate line is GLr, and the gate line GLr is connected to the gate line GL1. A drive example in which gate selection signals are sequentially output from the gate driver is shown. In addition, the positive grayscale data signal Vdx and the negative grayscale data signal Vd(x+1) output from the data driver also correspond to the selection order of the gate selection signals, and are supplied to the pixels in the r-th row. The gradation data pulses Dpr and Dnr are sequentially output, and finally the gradation data pulses Dp1 and Dn1 supplied to the pixels of the first row are output.

Here, the grayscale data signal has an analog voltage value (grayscale voltage) supplied to each pixel in the data line direction, and is composed of a plurality of grayscale data pulses in units of one data period. Each grayscale data pulse of the positive grayscale data signal Vdx has a grayscale voltage within a voltage range from a predetermined lower limit value Lpy to a higher upper limit value Lpz on the higher potential side than the opposing substrate voltage VCOM. In addition, the negative grayscale data signal Vd(x+1) has a grayscale voltage within a voltage range from a predetermined upper limit value Lny to a lower lower limit value Lnz on the lower potential side than the opposing substrate voltage VCOM. The opposing substrate voltage is generally set between the lower limit value Lpy of the positive grayscale data signal and the upper limit value Lny of the negative grayscale data signal. In the drawing, for convenience of explanation, the grayscale data pulses of the grayscale data signals Vdx and Vd(x+1) alternately output the grayscale voltages of the upper limit value and the lower limit value within each voltage range every one data period. A drive pattern is shown.

The gate selection signal Vgk is a pulse signal applied to the k-th (k is an integer equal to or greater than 2) gate line to be selected and transitions from a predetermined low potential VGL to a high potential VGH. The gate selection signal has a blunted waveform due to impedance (wiring resistance and wiring capacitance) corresponding to the wiring length of the gate line from the output terminal of the gate driver. In FIG. 1, the waveform of the gate selection signal Vgk observed at the position of the gate line crossing the X-th and (X+1)-th data lines where the wiring length from the output terminal of the gate driver is relatively long is Here is an example. Further, in the example shown in FIG. 1, in order to increase the pixel charging efficiency, the gate selection signal Vgk is such that the positive grayscale data pulse Dpk and the negative grayscale data pulse Dnk supplied to the k-th pixel are the first. The state of the high potential VGH is maintained from the data period before the one data period output to the X, (X+1)th data line. As a result, as shown in FIG. 1, the pixels in the k-th row to be selected are precharged by the gradation data pulses Dp(k+1) and Dn(k+1) immediately before Dpk and Dnk. Gate precharge is done.

Here, the positive data pulse Dpk and the negative data pulse Dnk (k are both 1, 2, . . . , r) are timing-controlled by the same clock CLK, and their phases are the same. The phase timings of the gate selection signal Vgk and the gradation data pulses Dpk and Dnk are such that the next gradation data pulses Dp(k-1) and Dn(k-1) do not charge the selected pixels in the k-th row. , it is determined by the relationship between the lower limit value Lnz of the amplitude of the negative grayscale data signal Vd(x+1) and the potential of the gate selection signal Vgk. In FIG. 1, at the end of one data period T1H for supplying the grayscale data pulse Dnk having the lower limit value Lnz of the negative grayscale data signal Vd(x+1), the phase timing is set so that the gate signal Vgk falls below the potential Lnz. adjusted.

As a result, the effective pixel charging period Tn1 of the negative grayscale data pulse Dnk is equivalent to one data period T1H.

On the other hand, the effective pixel charging period Tp1 of the positive grayscale data pulse Dpk is determined by the grayscale data pulse Dpk of the lower limit value Lpy of the dynamic range of the positive grayscale data signal Vdx and the potential of the gate selection signal Vgk. .

At this time, the effective pixel charging period Tp1 by the positive grayscale data pulse Dpk is shortened by the period Ts1 from the one data period T1H due to the dullness of the rear edge portion of the gate selection signal Vgk as shown in FIG. The pixel charging rate is reduced accordingly.

Furthermore, as described above, the potential difference between the gate selection signal Vgk and the gradation data signal also affects the pixel charging rate. The pixel charging rate of the grayscale data signal Vdx is low.

Therefore, when the pixel charging rate of the positive grayscale data signal is lower than that of the negative grayscale data signal, the positive and negative transmittances of the pixels become uneven, and the displayed image becomes uneven. Problems such as flicker and image quality deterioration occur.

When column inversion driving is performed, pixels supplied with a positive grayscale data signal and pixels supplied with a negative grayscale data signal are mixed along one horizontal scanning line. The problem cannot be solved by adopting the method described in Patent Document 1 described above.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a display device, a data driver, and a display controller that employ column inversion driving and are capable of displaying images on a large screen while suppressing deterioration in image quality.

A display device according to the present invention includes a plurality of data lines composed of first and second data line groups, and a plurality of gate lines arranged to cross the plurality of data lines, wherein the data lines and the a display panel in which display cells serving as pixels are arranged at intersections with gate lines; a gate driver for supplying a gate selection signal to each of the plurality of gate lines; Each receives a video signal, and a signal in which a data pulse having a positive analog voltage value with respect to a predetermined reference voltage corresponding to the luminance level of each pixel based on the video signal appears at a predetermined cycle. A signal generated as a gradation data signal and in which a data pulse having a negative analog voltage value with respect to the reference voltage appears in each predetermined cycle with a phase different from that of the positive gradation data signal is a negative gradation signal. and outputs the positive grayscale data signal to one of the first and second data line groups, and outputs the negative grayscale data signal to the other data line group. and a plurality of data drivers for outputting grayscale data signals, wherein the data drivers provide a first output delay representing a delay time with respect to the reference timing for each predetermined cycle when outputting the positive grayscale data signals. receiving setting information indicating time and a second output delay time representing a delay time with respect to the reference timing when the negative grayscale data signal is output in each of the predetermined cycles, and receiving the positive grayscale data; A signal is delayed from the reference timing by the first output delay time indicated by the setting information every predetermined period, and the negative grayscale data signal is output every predetermined period. Output is delayed by the second output delay time indicated by the setting information from the reference timing .

A data driver according to the present invention receives a video signal indicating a luminance level of each pixel, and drives a display panel having a plurality of data lines to which a plurality of display cells are connected respectively according to the video signal. A driver having a plurality of output terminals consisting of first and second output terminal groups to which the plurality of data lines are connected, receives a video signal, and adjusts the luminance level of each pixel based on the video signal. A signal in which data pulses each having a positive analog voltage value with respect to a corresponding predetermined reference voltage appear at a predetermined cycle is generated as a positive grayscale data signal, and corresponds to the luminance level of each pixel based on the video signal. A signal in which data pulses each having a negative analog voltage value with respect to the predetermined reference voltage appears in each predetermined cycle with a phase different from that of the positive grayscale data signal is generated as a negative grayscale data signal. , a first output delay time representing a delay time with respect to the reference timing for each predetermined cycle when outputting the positive grayscale data signal, and outputting the negative grayscale data signal at each predetermined cycle; receiving setting information indicating a second output delay time representing a delay time with respect to the reference timing, and outputting the positive gradation data to one of the first and second output terminal groups; A signal is delayed from the reference timing by the first output delay time indicated by the setting information at each predetermined cycle, and the negative gradation data signal is output to the other output terminal group. , the output is delayed by the second output delay time indicated by the setting information from the reference timing at every predetermined period .

A display controller according to the present invention has i output channels for outputting i (i is an integer equal to or greater than 2) gradation data signals each having a positive polarity or a negative polarity to data lines of a display panel. A display controller that supplies a video signal, a control signal, and setting information to each of a plurality of data drivers, wherein the positive gradation data of a plurality of stages is provided for each unit of a predetermined number of output channels among the i output channels. Information indicating the output delay time of the signal and the negative grayscale data signal with respect to the reference timing is individually set, and the setting information including the respective information is supplied to each of the plurality of data drivers.

In the present invention, when performing column inversion driving in which a positive grayscale data signal and a negative grayscale data signal are supplied to each data line of the display panel within one frame period, the positive grayscale data signal and the negative grayscale data signal The phases of the gradation data signals are different from each other. As a result, in a state where the rear edge portion of the gate selection signal is dulled, it is possible to reduce the pixel charging rate by the negative grayscale data signal and increase the pixel charging rate by the positive grayscale data signal. . Therefore, the difference between the pixel charge rate by the negative grayscale data signal and the pixel charge rate by the positive grayscale data signal can be reduced. It is possible to suppress the flicker due to the difference between the pixel charge rate and the pixel charge rate due to the gradation data signal.

5 is a time chart showing conventional application timings of positive and negative gradation data signals applied to adjacent data lines and gate selection signals applied to gate lines; 1 is a block diagram showing a schematic configuration of a liquid crystal display device as a display device according to the present invention; FIG. FIG. 4 is a diagram schematically representing the structure of a display cell; 4 is a time chart showing clock signals and delayed clock signals; 3 is a block diagram showing an example of the internal configuration of a data driver; FIG. FIG. 4 is a diagram showing a form of column inversion driving by a liquid crystal display device; 5 is a time chart showing an example of application timings of positive and negative grayscale data signals applied to adjacent data lines and gate selection signals applied to gate lines in the display device according to the present invention; . A time chart showing another example of application timings of positive and negative grayscale data signals applied to adjacent data lines and gate selection signals applied to gate lines in the display device according to the present invention. is. FIG. 4 is a block diagram showing another configuration of a liquid crystal display device as a display device according to the present invention; 3 is a block diagram showing another example of the internal configuration of a data driver; FIG. FIG. 4 is a diagram showing an example of output delay characteristics of a data driver; FIG. 4 is a diagram showing first output delay characteristics; FIG. 10 is a diagram showing a second output delay characteristic; FIG. 11 is a diagram showing a third output delay characteristic; FIG. 4 is a diagram showing an example of the form of output delay characteristics; FIG. 10 is a diagram showing another example of output delay characteristics of a data driver; It is a figure which shows an example of the time chart of each timing signal in a liquid crystal display device. FIG. 10 is a diagram showing another example of the form of column inversion driving by the liquid crystal display device;

FIG. 2 is a block diagram showing a schematic configuration of an active matrix liquid crystal display device 10 as a display device according to the present invention.

As shown in FIG. 2, the liquid crystal display device 10 has a display controller 100, data drivers 120-1 to 120-S, a gate driver 110, and a display panel 150. FIG.

As shown in FIG. 2, the display panel 150 includes gate lines GL1 to GLr (r is an integer equal to or greater than 2) extending in the horizontal direction of the two-dimensional screen, and data lines DL1 to DLm extending in the vertical direction of the two-dimensional screen. (m is an integer of 2 or more) are intersected. The data drivers 120-1 to 120-S are provided for each predetermined number of data lines, respectively, and the data lines DL1 to DLm of the display panel 150 are driven by all of the S data drivers (S is an integer greater than 1). do. The gate driver 110 for driving the gate lines GL1 to GLr is mainly composed of a thin film transistor circuit integrally formed with the display panel 150 due to the demand for a narrower frame. Although the gate driver 110 is shown arranged on one side of the display panel 150 in FIG. 2, it may be arranged on both sides.

A display cell 154 serving as a unit pixel is formed at each intersection of each of the gate lines GL1 to GLr and each of the data lines DL1 to DLm.

FIG. 3 is a diagram schematically showing the structure of the display cell 154. As shown in FIG.

As shown in FIG. 3, the display cell 154 includes a pixel electrode C1, a liquid crystal layer C2, a counter substrate electrode C3, and a thin film transistor TR as a pixel switch, which are stacked together. FIG. 3 shows an example of an n-channel thin film transistor. The pixel electrode C1 is a transparent electrode provided independently for each display cell 154, and the counter substrate electrode C3 is a single transparent electrode covering the entire surface of the display panel 150. FIG. A control terminal of the transistor TR is connected to the gate line GL, and a first terminal thereof is connected to the data line DL. Furthermore, the second terminal of the transistor TR is connected to the pixel electrode C1. A voltage VCOM as a reference potential is applied to the opposing substrate electrode C3.

The display controller 100 receives the video signal VD, and based on the video signal VD, supplies the gate driver 110 with a gate timing signal indicating the timing of applying the gate selection signal to each of the gate lines GL1 to GLr.

Further, the display controller 100 includes a control signal including a start pulse signal ST and a clock signal CLK indicating the data acquisition start timing based on the video signal VD, and a series of video data PD indicating the luminance level of each pixel. A digital video signal DVS is generated.

The clock signal CLK is a binary (logical level 0 or 1) clock signal having a period of one data period T1H as shown in FIG. Also, the series of video data PD is a group of digital data pieces representing the luminance level of each pixel, for example, in 8 bits.

The display controller 100 supplies the video signal DVS described above to each of the data drivers 120-1 to 120-S. In order to reduce the number of transmission lines between the display controller 100 and each data driver, the display controller 100 normally sends out high-speed serial signals. In that case, each data driver has a deserialization function that receives the high-speed serial signal and returns it to the original frequency.

The gate driver 110 sequentially generates gate selection signals Vg(r) to Vg1, each of which includes at least one pulse for selecting a gate line, according to a gate timing signal supplied from the display controller 100. outputs from each of the output terminals. The gate driver 110 supplies the gate selection signals Vg(r) to Vg1 output from the r output terminals to the gate lines GLr to GL1 of the display panel 150, respectively.

The data drivers 120-1 to 120-S each generate video for one horizontal scanning line (for each predetermined number of data lines) included in the video signal DVS in response to the start pulse signal ST and the clock signal CLK included in the video signal DVS. Take in each of the data PDs.

The data drivers 120-1 to 120-S have output channels corresponding to a predetermined number of data lines, and convert the received video data PD into gradation data signals having analog voltage values corresponding to respective luminance levels. output. The gradation data signals Vd1 to Vd(m) are generated by the data drivers 120-1 to 120-S as a whole, and the gradation data signals Vd1 to Vd(m) output from the data drivers 120-1 to 120-S are , are supplied to the data lines DL1 to DLm of the display panel 150, respectively.

Note that the data drivers 120-1 to 120-S apply a positive grayscale data signal to one of the adjacent paired data lines during a certain frame period among the grayscale data signals Vd1 to Vd(m). column inversion driving is performed to supply a grayscale data signal of negative polarity to the other data line. The polarity state of each gradation data signal is inverted on a frame-by-frame basis. As the simplest method, each of the gradation data signals Vd1, Vd3, Vd5, . The polarity of each of the gradation data signals Vd2, Vd4, Vd6, .

Further, when the data drivers 120-1 to 120-S output the gradation data signals Vd1 to Vd(m), as shown in FIGS. gradation data signal group at a timing synchronized with the phase of the clock signal CLK. In addition, the data drivers 120-1 to 120-S generate the negative grayscale data signal group among the grayscale data signals Vd1 to Vd(m) as a delayed clock that is delayed by a predetermined period from the phase of the clock signal CLK. It is output at a timing synchronized with the phase of signal CLKd.

FIG. 5 is a block diagram showing the internal configuration of each of data drivers 120-1 to 120-S. Any one data driver is hereinafter referred to as data driver 120 .

As shown in FIG. 5, the data driver 120 includes a control circuit 51, a delay circuit 52, a gradation voltage generation section 54, a shift register 60, a data latch section 70, a level shifter 80, a decoder section 90, and an output amplifier section 95. . The data driver 120 is formed by a semiconductor IC.

The control circuit 51 receives and deserializes the video signal DVS serialized and sent from the display controller 100, and extracts the control signal, the start pulse signal ST, the clock signal CLK, the polarity inversion signal, and the video data PD from the video signal DVS. are extracted respectively. The control circuit 51 has a timing generation function and controls the timing of each signal.

The control circuit 51 supplies the extracted start pulse signal ST to the shift register 60 , and supplies the extracted clock signal CLK to the delay circuit 52 , the shift register 60 and the data latch section 70 . Furthermore, the control circuit 51 supplies the series of the extracted video data PD to the data latch section 70 .

The control circuit 51 also outputs a binary (logical level 0 or 1) polarity inversion signal POL for inverting the polarity of each grayscale data signal output by the data driver 120 in frame period units according to the video signal DVS. and supplies it to the data latch section 70 .

As shown in FIG. 4, the delay circuit 52 supplies the data latch section 70 with a delayed clock signal CLKd obtained by delaying the clock signal CLK by a time Ts21. As the delay circuit 52, a variable delay circuit capable of adjusting the time Ts21 for delaying the clock signal CLK to an arbitrary length may be employed. At this time, the delay circuit 52 functions as means for adjusting the amount of phase shift when the phase of the negative grayscale data signal is shifted in the direction of delaying the phase of the positive grayscale data signal, which will be described later.

The gradation voltage generator 54 generates L reference voltage groups X1 to XL of positive polarity and L reference voltage groups Y1 to YL of negative polarity, and supplies them to the decoder section 90 . For example, the gradation voltage generation unit 54 outputs a reference voltage group obtained by dividing a predetermined high potential VGH and a predetermined low potential VGL lower than the high potential VGH into a plurality of voltages using a ladder resistor. .

The shift register 60 generates a plurality of latch timing signals indicating different latch timings in synchronization with the clock signal CLK according to the start pulse signal ST, and supplies the signals to the data latch section 70 .

The data latch unit 70 has a positive data latch 71 and a negative data latch 72 that take in video data PD corresponding to the number of outputs from the series of video data PD described above in response to a plurality of latch timing signals supplied from the shift register 60. including.

The positive data latch 71 receives a clock signal CLK and a polarity inversion signal POL along with the series of video data PD described above. Negative data latch 72 receives delayed clock signal CLKd and polarity inversion signal POL along with the series of video data PD.

When the number of outputs of the data driver 120 is q (q is an integer equal to or greater than 1), and one of the odd-numbered and even-numbered data lines of the display panel 150 is driven with positive polarity and the other is driven with negative polarity, the polarity inversion signal POL indicates the logic level 1, the positive data latch 71 fetches each of the odd-numbered video data PD in the series of q video data PD corresponding to the number of outputs as positive data. Further, at this time, the negative data latch 71 takes in each of the even-numbered video data PD in the series of the q pieces of video data PD as negative data.

Then, the positive data latch 71 supplies the plurality of video data PD as the positive data it has taken in to the level shifter 80 as odd-numbered video data P1, P3, P5, . . . at the timing of the clock signal CLK. The negative data latch 72 supplies a plurality of video data PD as negative data that it has taken in to the level shifter 80 as even-numbered video data P2, P4, P6, . . . at the timing of the delayed clock signal CLKd.

On the other hand, when the polarity inversion signal POL indicates logic level 0, the positive data latch 71 takes in each of the even-numbered video data PD in the series of the q pieces of video data PD as positive data. takes in each of the odd-numbered video data PD in the sequence of the q video data PD as the negative data.

Then, the positive data latch 71 supplies a plurality of video data PD as positive data that it has taken in to the level shifter 80 as even-numbered video data P2, P4, P6, . . . at the timing of the clock signal CLK. The negative data latch 72 supplies the plurality of video data PD as the negative data it has taken in to the level shifter 80 as odd-numbered video data P1, P3, P5, . . . at the timing of the delayed clock signal CLKd.

The level shifter 80 performs a level shift process for increasing the signal level (voltage amplitude) of each of the q pieces of video data P1 to Pq supplied from the data latch unit 70 to obtain video data J1. ˜Jq to the decoder unit 90 .

The decoder unit 90 has q decoders DEC that individually convert each of the video data J1 to Jq into a gradation data signal having an analog voltage value.

Each of the q decoders DEC receives a positive reference voltage group X1 to XL and a negative reference voltage group Y1 to YL from the gradation voltage generator . Further, each of the q decoders DEC individually receives one of the video data J1-Jq.

When the video data J received by itself is positive data, each decoder DEC selects one or a plurality of reference voltages designated by the video data J from among the positive reference voltage group X1 to XL. select. On the other hand, when the video data J received by itself is negative data, the decoder DEC selects one or a plurality of reference voltages designated by the video data J from among the negative reference voltage group Y1 to YL. to select.

The decoder section 90 outputs one or a plurality of reference voltages selected by the q decoders DEC to the output amplifier section 95 .

The output amplifier unit 95 includes q operational amplifiers corresponding to the q decoders DEC, and one or more reference voltages supplied from each decoder DEC are input to each operational amplifier. Each of these q operational amplifiers consists of a voltage follower with its output terminal and inverting input terminal (-) connected together, and one or more references received at its non-inverting input terminal (+). An analog voltage value obtained by operationally amplifying the voltage is supplied to the output terminal. The analog voltage value obtained at this time is a gradation voltage corresponding to the luminance level. The output amplifier unit 95 externally outputs the analog voltage values operationally amplified by the q operational amplifiers as grayscale data pulses of the grayscale data signal via the q output terminals T1 to Tq of the semiconductor IC. The gradation data pulses are continuously output within one frame period in units of one data period. In this specification, a continuous signal of grayscale data pulses output from each output terminal is referred to as a grayscale data signal. Here, the q output terminals T1 to Tq are connected to q of the data lines DL1 to DLm of the display panel 150. FIG. For example, when the data driver 120 is the data driver 120-1 responsible for DL1 to DLq of the data lines DL1 to DLm, the output terminals T1 to Tq of the data driver 120 output the gradation data signals Vd1 to Vd(q), respectively. be done.

With the configuration shown in FIG. 5, the data driver 120 outputs the positive grayscale data signal group among the grayscale data signals Vd1 to Vd(q) to the data lines DL1 to DLm of the display panel 150, for example. It is supplied to one of the odd-numbered data line group and the even-numbered data line group of the q data lines handled by the driver. In addition, the data driver 120 outputs the negative grayscale data signal group among the grayscale data signals Vd1 to Vd(q) to the odd-numbered data line group and the even-numbered data line group of the q data lines of the display panel 150. data lines. The phase of the negative grayscale data signal group is phase-shifted by the time Ts21 shown in FIG. 4 with respect to the positive grayscale data signal group.

Column inversion driving by operations of the data latch section 70 and the decoder section 90 shown in FIG. 5 will be described in detail below.

FIG. 6 is a time chart showing an example of the state (positive polarity or negative polarity) of each of the gradation data signals Vd1 to Vd(q) output from the data driver 120-1 by the column inversion driving.

As shown in FIG. 6, during one frame period in which the polarity inversion signal POL is at logic level 1, the positive data latch 71 of the data latch unit 70 outputs the odd-numbered video data PD in the series of q video data PD for one horizontal scanning line. , is taken in as positive data. During this time, the negative data latch 72 of the data latch unit 70 takes in each of the even-numbered video data PD in the series of q video data PD for one horizontal scanning line as negative data.

In one frame period in which the polarity inversion signal POL is at logic level 1, the positive data latch 71 converts each of the odd-numbered video data PD as positive data into the odd-numbered video data P1, P3, P5, P7, Output as . Also, during this time, the negative data latch 72 outputs each of the even-numbered video data PD as negative data as the even-numbered video data P2, P4, P6, P8, .

As a result, as shown in FIG. 6, during one frame period when the polarity inversion signal POL is at logic level 1, the grayscale data signals Vd1 to Vd(q) applied to the data lines DL1 to DLq of the display panel 150 are Each of the odd-numbered gradation data signals Vd1, Vd3, Vd5, Vd7, . . . has a positive polarity. Further, during one frame period in which the polarity inversion signal POL is at logic level 1, each of the even-numbered gradation data signals Vd2, Vd4, Vd6, Vd8, . . . becomes negative as shown in FIG.

As shown in FIG. 6, during one frame period in which the polarity inversion signal POL is at logic level 0, the positive data latch 71 latches the even-numbered video in the series of q video data PD for one horizontal scanning line. Each of the data PD is taken in as positive data. During this time, the negative data latch 72 takes in each of the odd-numbered video data PD in the series of q video data PD for one horizontal scanning line as negative data.

In one frame period in which the polarity inversion signal POL is at logic level 0, the positive data latch 71 converts each of the even-numbered video data PD as positive data to the even-numbered video data P2, P4, P6, P8, Output as . Also, during this time, the negative data latch 72 outputs each of the odd-numbered video data PD as negative data as the odd-numbered video data P1, P3, P5, P7, .

As a result, as shown in FIG. 6, during one frame period in which the polarity inversion signal POL is at logic level 0, the grayscale data signals Vd1 to Vd(q) applied to the data lines DL1 to DLm of the display panel 150 are Each of the odd-numbered gradation data signals Vd1, Vd3, Vd5, Vd7, . . . has a negative polarity. Further, during one frame period in which the polarity inversion signal POL is at logic level 0, each of the even-numbered gradation data signals Vd2, Vd4, Vd6, Vd8, . . . becomes positive as shown in FIG.

Note that each of the grayscale data signals Vd1 to Vd(q) is composed of r grayscale data pulses corresponding to the r display cells 154 arranged along each of the data lines DL1 to DLq. It consists of a series of continuous pulses for each cycle of the period T1H.

At this time, the display cell 154 receives the pulse-shaped gate selection signal Vg sent from the gate driver 110 via the gate line GL and receives the grayscale data signal Vd sent from the data driver 120, and the grayscale data A pulse is supplied (charged) to the pixel electrode through the pixel switch. That is, the grayscale data pulse is supplied to the display cell 154 with a current driving capability corresponding to the potential difference between the potential of the grayscale data pulse and the potential of the gate selection signal Vg, and the display cell 154 receives the grayscale data pulse. It is held at the voltage value.
As the data driver 120, the data driver 120-1 serving the data lines DL1 to DLq among the data lines DL1 to DLm of the display panel 150 has been described as a representative. The data drivers 120-2 to 120-S other than the data driver 120-1 differ only in the locations of the data lines they are in charge of, and the configuration of the data drivers shown in FIG. and the explanation is omitted.

In FIG. 7, data lines DLx (x is an integer from 1 to m) and DL(x+1) adjacent to each other are formed at intersections with gate lines GLk (k is an integer from 1 to r). 4 is a time chart showing application timings of various signals when grayscale data pulses Dpk and Dnk are supplied (charged) to two display cells 154. FIG. Similar to FIG. 1, it shows a driving example in which gate selection signals are sequentially output from the gate driver from the gate line GLr farthest from the data driver toward the gate line GL1 closest to the data driver. Here, the data lines DLx and DL(x+1) are data lines crossing the gate line GLk at positions where the wiring length from the output terminal (not shown) of the gate driver 110 on the gate line GLk is relatively long. . Also, the pulse waveform of the gate selection signal Vgk indicated by the dashed line in FIG. 7 is the waveform observed at the position of the intersection between the gate line GLk and the data lines DLx and DL(x+1). The gate selection signal Vgk observed at the position of intersection with the data lines DLx and DL(x+1) has a large impedance corresponding to the wiring length of the gate line from the output terminal of the gate driver, and has a relatively large waveform blunting. occur.

In the example shown in FIG. 7, the positive grayscale data signal Vdx including the grayscale data pulse Dpk is applied to the data line DLx, and the negative grayscale data signal Vd(x+1) including the grayscale data pulse Dnk is applied to the data line DLx. is applied to the data line DL(x+1). The grayscale data signal has an analog voltage value (grayscale voltage) to be supplied to each pixel in the data line direction, and is composed of a plurality of grayscale data pulses in units of one data period. Each grayscale data pulse of the positive grayscale data signal Vdx has a grayscale voltage within a voltage range from the lower limit value Lpy to the upper limit value Lpz. Similarly, each grayscale data pulse of the negative grayscale data signal Vd(x+1) has a grayscale voltage within the voltage range from the upper limit value Lny to the lower limit value Lnz. The opposing substrate voltage VCOM is set between the lower limit value Lpy of the positive grayscale data signal and the upper limit value Lny of the negative grayscale data signal. Also in FIG. 7, for convenience of explanation, the gradation data pulses of the gradation data signals Vdx and Vd(x+1) alternately output the gradation voltages of the upper limit value and the lower limit value within each voltage range every one data period. shows the drive pattern used.

The gate selection signal Vgk shown in FIG. 7 is precharged to increase the pixel charging rate, as in FIG. That is, the grayscale data pulses Dp(k+1) and Dn(k+1) one data period earlier corresponding to the pixels in the (k+1)th row are applied together with the grayscale data pulses Dpk and Dnk corresponding to the pixels in the kth row. The state of the high potential VGH is maintained including the period.

A feature of the time chart shown in FIG. 7 is that the positive grayscale data pulse Dpk and the negative grayscale data pulse Dnk are controlled at different timings. In comparison with FIG. 1, in FIG. 1, the positive data pulse Dpk and the negative data pulse Dnk are timing-controlled by the same clock signal CLK, and have the same phase. On the other hand, in FIG. 7, the timing of the positive grayscale data pulse Dpk is controlled by the clock signal CLK, and the timing of the negative data pulse Dnk is controlled by the delayed clock signal CLKd, which is shifted from the clock signal CLK by a predetermined phase. Therefore, the negative grayscale data pulse Dnk is controlled at a timing delayed by a predetermined phase shift with respect to the positive grayscale data pulse Dpk.

In FIG. 7, timing control of the positive grayscale data signal Vdx and the gate selection signal Vgk will be described below. Regarding the output timing of the positive grayscale data signal Vdx, the data driver 120 supplies the grayscale data pulse Dp(k−1) in the data period next to the grayscale data pulse Dpk to the display cell 154 according to the gate selection signal Vgk. It is set as follows so that it is not (charged).

That is, as shown in FIG. 7, the data driver 120 sets the potential of the rear edge portion of the gate selection signal Vgk to the lower limit value Lpy or less of the grayscale data pulse Dpk at the time of the rear edge portion of the positive grayscale data pulse Dpk. The positive grayscale data signal Vdx is output at such timings. For example, the control circuit 51 may adjust the phase of the clock signal CLK that determines the phase of the positive grayscale data signal Vdx so as to obtain such an output form.

As a result, the effective pixel charging period of the positive grayscale data pulse Dpk can be set to the pixel charging period Tp2, which is equivalent to one data period T1H, as shown in FIG.

7, the data driver 120 phase-shifts the phase of the negative grayscale data signal Vd(x+1) with respect to the phase of the positive grayscale data signal Vdx by time Ts21. ing.

That is, in the configuration shown in FIG. 5, the positive data latch 71 outputs the video data piece group determined as the positive data at the timing of the clock signal CLK. On the other hand, the video data piece group determined as negative data by the negative data latch 72 is output at the timing of the delayed clock signal CLKd, which is delayed in phase by time Ts21 with respect to the clock signal CLK.

As a result, as shown in FIG. 7, the data driver 120 outputs negative grayscale data shifted in the direction of delaying the phase by time Ts21 with respect to the positive grayscale data signal Vdx synchronized with the clock signal CLK. It outputs the signal Vd(x+1). As a result, as shown in FIG. 7, before the rear edge of the grayscale data pulse Dnk included in the negative grayscale data signal Vd(x+1), the potential of the rear edge portion of the gate signal Vgk changes to the grayscale level. It becomes equal to or less than the lower limit value Lpy of the data pulse Dnk.

Therefore, the effective pixel charging period of the negative grayscale data pulse Dnk is, as shown in FIG. 7, a pixel charging period Tn2 that is shorter than one data period T1H by a period Ts22 (≧0). The action of this period Ts22 is as follows.

Since the potential difference between the gate selection signal Vgk and the gradation data signal is larger in the negative polarity than in the positive polarity, the pixel charging rate of the negative polarity is higher even during the same pixel charging period. A period Ts22 is provided to adjust the difference between the positive and negative pixel charge rates associated with the potential difference between the gate selection signal Vgk and the gradation data signal.

That is, by the above-described driving, a period equivalent to one data period T1H is secured as an effective pixel charging period Tp2 of the positive grayscale data pulse Dpk, and an effective pixel charging period Tp2 of the negative grayscale data pulse Dnk is secured. It is possible to set the charging period Tn2 to one data period T1H or less.

Therefore, the pixel charging period Tp2 of the positive grayscale data pulse Dpk is made longer than the pixel charging period Tp1 shown in FIG. 1, and the pixel charging period Tn2 of the negative grayscale data pulse Dnk is set to It is possible to make the period Tn1 or shorter.

In this manner, the pixel charging rate by the negative grayscale data signal is adjusted to be lower, while the pixel charging rate by the positive grayscale data signal is increased. , the difference from the pixel charging rate due to the positive grayscale data signal is reduced.

Therefore, according to the present invention, even if the pulse edge portion of the gate selection signal is blunted, the difference between the pixel charging rate due to the negative grayscale data signal and the pixel charging rate due to the positive grayscale data signal is It is possible to suppress flicker and image quality deterioration that accompany this.

In the above embodiment, the data driver 120 shifts the phase of the negative grayscale data signal by time Ts21 with respect to the phase of the positive grayscale data signal. The length of time Ts21 may be varied for each grayscale data signal.

For example, the degree of blunting of the rear edge portion of the pulse of the gate selection signal Vg, that is, the rate of voltage change over time depends on the wiring length of the gate line GL between the output terminal of the gate driver 110 and the display cell 154 (hereinafter referred to as the wiring length WL). ) becomes smaller.

Therefore, the time length (Ts21) of the phase shift of the negative grayscale data signal output to each of the data lines DL1 to DLm with respect to the positive grayscale data signal is changed from the output terminal of the gate driver 110 to the negative grayscale data signal. The shorter the wiring length WL of the gate line up to the position where the data line DL for receiving the gradation data signal and the gate line GL intersects, the shorter the wiring length WL is. In FIG. 2, the data lines DL1 to DLm of the display panel 150 are driven by S data drivers 120-1 to 120-S, and each data driver handles a predetermined number (q lines) of data lines. Since the wiring length of the gate line GL from the output terminal of the gate driver 110 to the data line handled by each data driver is different, the phase shift time of the negative grayscale data signal with respect to the positive grayscale data signal. The length (Ts21) may be set for each data driver. That is, the length of the phase shift (Ts21) of the gradation data signal between the positive polarity and the negative polarity output from the data driver with the short wiring length of the gate line GL to the data line to be served is short, and the gate line to the data line to be served is short. The time length (Ts21) of the phase shift output from the data driver with the long wiring length of the line GL is lengthened.

FIG. 8 supplies gradation data pulses Dpk and Dnk to two display cells 154 formed at intersections of data lines DLx and DL(x+1) and gate lines GLk, respectively, as in FIG. 4 is a time chart showing application timings of various signals during (charging).

However, the data line DLx to which the grayscale data pulse Dpk is applied in FIG. The wiring length WL is short. As a result, the rate of voltage change over time at the rear edge portion of the pulse of the gate selection signal Vgk observed at the position of the crossing portion of the gate line GLk with the data line DLx is obtained from the gate selection signal Vgk shown in FIG. is large, that is, steep (waveform blunting is small).

Therefore, as shown in FIG. 8, the phase shift amount of the negative grayscale data signal Vdx with respect to the positive grayscale data signal Vdx is set to a time Ts31 shorter than the time Ts21 shown in FIG.

As a result, as shown in FIG. 8, the pixel charging period Tp3 by the positive grayscale data pulse Dpk can be extended to be equivalent to one data period T1H. On the other hand, the pixel charging period Tn3 of the negative grayscale data pulse Dnk can be adjusted to be shortened by the time Ts32 shown in FIG. 8 from the one data period T1H. At this time, the effective pixel charging period Tp3 by the positive grayscale data pulse Dpk is longer than the effective pixel charging period Tp1 shown in FIG. 1, and the effective pixel charging period by the negative grayscale data pulse Dnk. Tn3 is shorter than the effective pixel charging period Tn1 shown in FIG.

Therefore, the pixel charging rate by the negative grayscale data signal can be adjusted to be lower, while the pixel charging rate by the positive grayscale data signal can be increased. , the difference from the pixel charging rate due to the positive grayscale data signal is reduced.

Furthermore, according to such driving, even if the degree of blunting of the rear edge portion of the gate selection signal reaching each display cell differs due to the difference in the wiring length of the gate line from the output terminal of the gate driver, the rear edge portion of the gate selection signal reaching each display cell is made to follow the degree of blunting, and the negative polarity It is possible to equalize the difference between the pixel charging rate by the gradation data signal and the pixel charging rate by the positive gradation data signal within the screen. As a result, it is possible to provide a flicker-free, high-quality image over the entire screen without being affected by waveform blunting of the gate selection signal.

In FIG. 5, an embodiment in which the data latch section 70 includes the positive data latch 71 and the negative data latch 72 has been described. You may divide and comprise. For example, the shift register 60 that generates the latch timing signal may be divided into a circuit section that generates a positive latch timing signal and a circuit section that generates a negative latch timing signal.

In the above embodiment, as shown in FIG. 7, the clock signal CLK and the delayed clock signal are used to shift the phase of the negative grayscale data signal Vd(x+1) with respect to the positive grayscale data signal Vdx. CLKd, the positive data latch 71 and the negative data latch 72 are used, but the configuration is not limited to this.

In short, display cells (154 ) on which the display panel (150) is arranged, the display device (10) may include the following gate drivers and data drivers.

A gate driver (110) supplies a gate selection signal (Vg) to each of a plurality of gate lines.

A data driver (120) receives a video signal (DVS) and generates a positive grayscale data signal and a negative grayscale data signal based on the video signal. A positive gradation data signal is output to one of the first data line group and the second data line group, and a negative gradation data signal is output to the other. The first data line group and the second data line group are composed of approximately the same number of data lines, and one data line paired adjacently belongs to the first data line group, and the other data line group A data line belongs to the second data line group. For example, the odd-numbered data line group may be the first data line group, and the even-numbered data line group may be the second data line group.

At this time, the data driver (120) generates data pulses (Dp) each having a positive analog voltage value (gradation voltage) corresponding to the brightness level of each pixel based on the video signal (DVS) at a predetermined cycle (T1H). ) is generated as a positive grayscale data signal. Further, the data driver (120) generates data pulses (Dn) each having a negative analog voltage value (grayscale voltage) corresponding to the luminance level of each pixel based on the video signal. A signal that appears every predetermined period (T1H) at a phase (Ts21) different from that is generated as a negative gradation data signal.

Next, another embodiment of the display device according to the present invention will be described.

FIG. 9 is a block diagram showing a schematic configuration of a liquid crystal display device 10_1 as another embodiment of the display device according to the invention. The liquid crystal display device 10_1 includes a display controller 100A, gate drivers 110A and 110B, data driver ICs 120-1 to 120-p (p is an integer of 2 or more), and a display panel 150_1.

The display panel 150_1 has the same structure as the display panel 150 shown in FIG. 2 except that the screen size is larger than that of the display panel 150 shown in FIG.

The gate drivers 110A and 110B are composed of thin film transistor circuits integrally formed with the display panel 150_1, and are arranged at both the left and right ends of the display panel 150_1. The gate driver 110A is connected to one end of each of the gate lines GL1 to GLr formed on the display panel 150_1, and the gate driver 110B is connected to the other end of each of the gate lines GL1 to GLr formed on the display panel 150_1. It is connected. The gate drivers 110A and 110B, like the gate driver 110 shown in FIG. 2, apply the gate selection signals Vg(r) to Vg1 to the gate lines of the display panel 150_1 according to the gate timing signal supplied from the display controller 100A. It is supplied to each of GLr to GL1.

The display controller 100A supplies the gate timing signals described above to the gate drivers 110A and 110B based on the video signal VD.

Furthermore, based on the video signal VD, the display controller 100A generates a video signal DVS representing a control signal group CS, a sequence of video data PD indicating the luminance level of each pixel, and digital setting information in a serial digital signal format.

The control signal group CS includes a vertical blanking signal Vsync that is a reference signal for a frame period, a horizontal blanking signal Hsync that is a reference signal for a data period, a clock signal CLK, and the like.

The digital setting information includes output delay direction information CF, output delay shift amount information SA1 and SA2, and output start timing information TA1 and TA2.

The output delay direction information CF is defined for each of the data driver ICs 120-1 to 120-p, for i output channels that output i (i is an integer equal to or greater than 2) gradation data signals Vd. The increasing direction of the output delay time from each of the output start channels of the negative polarity and the negative polarity is increased in either ascending order or descending order of the output channel numbers, or from both ends of the i output channels to the center. This is information that specifies whether to increase the output delay time toward. The output delay direction information CF for the positive and negative electrodes is common. Specifically, for example, gate drivers are arranged at both left and right ends of the two-dimensional screen of the display panel, and data driver ICs 120-1 to 120-p are arranged along the horizontal direction at the lower end (or upper end) of the two-dimensional screen. When arranged side by side, the output delay direction information CF of each of the data driver ICs on the left half of the two-dimensional screen indicates the direction in which the gate selection signal delay increases from the left end gate driver toward the center of the screen for i output channels. , the direction of increasing the output delay time from the first output channel to the i-th output channel can be specified. The output delay direction information CF of each data driver IC on the right half of the two-dimensional screen corresponds to the direction in which the gate selection signal delay increases from the right end gate driver toward the center of the screen for i output channels. Then, a direction can be specified to increase the output delay time from the i-th output channel to the first output channel. Alternatively, the output delay direction information CF is an output delay time from both ends of the i output channels toward the center in order to correct the data line fan-out wiring length at the end of the display panel where the data driver IC is mounted. You can also specify the direction to increase .

The output delay shift amount information SA1 is information specifying the delay shift amount to be set to the output channel group responsible for outputting the positive grayscale data signal Vd for each of the data driver ICs 120-1 to 120-p. The output delay shift amount information SA2 is information specifying the delay shift amount to be set to the output channel group that outputs the negative grayscale data signal Vd for each of the data driver ICs 120-1 to 120-p. The amount of delay shift is the change in delay time per predetermined output channel number unit xr (ascending order of output channel numbers) or xl (descending order of output channel numbers) (where xr<i, xl<i). It is a quantity, which is expressed stepwise, for example, by integral multiples of the pulse width of the clock signal CLK.

The output start timing information TA1 is information specifying the output timing of the output start channel for each of the data driver ICs 120-1 to 120-p for the output channel group responsible for outputting the positive grayscale data signal Vd. . The output start timing information TA2 is information that designates the output timing of the output start channel for each of the data driver ICs 120-1 to 120-p for the output channel group responsible for the output of the negative gradation data signal Vd group. be.

The output start timing information TA1 and TA2 may include information specifying the output start channels of positive and negative polarities, respectively. Alternatively, the output channel may be specified in correspondence with the output delay direction information CF.

The display controller 100A supplies the video signal DVS generated as described above to each of the data driver ICs 120-1 to 120-p.

The data driver ICs 120-1 to 120-p are composed of p ICs, and are provided for each i (i is an integer equal to or greater than 2) data lines DL1 to DLm of the display panel 150_1.

FIG. 10 is a block diagram showing the internal configuration of one data driver IC 120 extracted from the data drivers 120-1 to 120-p.

5, the data driver IC 120 delays the timing of the negative data latch with respect to the positive data latch, and outputs the phases of the positive and negative gradation data signals to the data lines. control. However, the data driver IC 120 shown in FIG. 10 is configured so that the phases of the positive and negative gradation data signals, that is, the output timing, can be adjusted in various forms based on the setting information supplied from the display controller 100A. .

As shown in FIG. 10, the data driver IC 120 includes a gradation voltage generation section 54, a level shifter 80, a decoder section 90, an output amplifier section 95, a control core section 510, a setting storage section 600, a timing control section 650, and a latch section 700. including. Note that the gradation voltage generating section 54, the level shifter 80, the decoder section 90, and the output amplifier section 95 are the same as those shown in FIG.

The control core unit 510 deserializes the video signal DVS in serial form, that is, performs serial-parallel conversion processing, thereby separating and extracting the series of video data PD, the above-described various signal groups, and setting information, and extracting each of them as follows: Feed the corresponding block.

That is, the control core unit 510 extracts the sequence of the video data PD, the digital setting information (CF, SA1, SA2, TA1, TA2) and the clock signal CLK from the video signal DVS. The control core unit 510 supplies digital setting information (CF, SA1, SA2, TA1, TA2) to the setting storage unit 600, supplies the reference timing signal STD to the timing control unit 650, and stores the series of video data PD in the latch unit. 700.

Note that the control core unit 510 internally generates a reference timing signal STD of one horizontal period cycle (1H cycle) according to the video signal DVS. As this reference timing signal STD, for example, a signal synchronized with the gate-off timing of the gate selection signal may be used.

Further, the control core unit 510 outputs the positive latch output timing signal LOAD1 for taking in the above-described polarity inversion signal POL and the positive and negative video data signals into the latch unit 700 according to the video signal DVS. and a negative latch output timing signal LOAD2. The control core section 510 supplies the polarity inversion signal POL to the latch section 700 and supplies the latch output timing signals LOAD1 and LOAD2 to the timing control section 650 and the latch section 700 . Note that the latch output timing signals LOAD1 and LOAD2 are generated as signals having a predetermined delay amount with respect to the reference timing signal STD based on the control signal group CS and digital setting information. The negative latch output timing signal LOAD2 is generated as a signal obtained by delaying the positive latch output timing signal LOAD1.

The setting storage unit 600 takes in and stores the digital setting information (CF, SA1, SA2, TA1, TA2) supplied from the control core unit 510 . The setting storage section 600 supplies the stored digital setting information, that is, the output delay direction information CF, the output delay shift amount information SA1 and SA2, and the output start timing information TA1 and TA2 to the timing control section 650. FIG. The digital setting information stored in the setting storage unit 600 is refreshed every predetermined period.

The timing control unit 650 includes functional blocks for positive and negative electrodes, and generates a timing signal for outputting video data signals corresponding to the positive and negative electrodes captured by the latch unit 700 .

That is, the functional block for the positive electrode of the timing control unit 650 outputs the video data for the positive electrode based on the output delay direction information CF, the output delay shift amount information SA1, the output start timing information TA1, the reference timing signal STD, and the latch output timing signal LOAD1. A latch output timing signal group LOAD1-Grs of signals is generated.

The negative block of the timing control unit 650 latches and outputs the negative video data signal based on the output delay direction information CF, the output delay shift amount information SA2, the output start timing information TA2, the reference timing signal STD, and the latch output timing signal LOAD2. A timing signal group LOAD2-Grs is generated.

The timing control section 650 supplies the latch output timing signal groups LOAD1-Grs and LOAD2-Grs to the latch section 700 .

Latch unit 700 includes a positive data latch 710 and a negative data latch 720 . The latch unit 700 distributes each video data PD in the series of video data PD to the positive polarity and the negative polarity according to the polarity switching signal POL.

The positive data latch 710 takes in each of the video data PD assigned to the positive polarity according to the latch output timing signal LOAD1.

The positive data latch 710 uses each of the received positive video data PD as video data P, and is set for each predetermined output number unit based on the output timing signal group LOAD1-Grs corresponding to the corresponding output channel. output at the specified output timing.

The negative data latch 720 takes in each of the video data PD allocated to the negative in accordance with the latch output timing signal LOAD2.

Negative data latch 720 sets each of the received negative video data PD as video data P for each predetermined output number unit based on the output timing signal group LOAD2-Grs corresponding to the corresponding output channel. output at the specified output timing.

The latch unit 700 supplies i (i is an integer equal to or greater than 2) video data P output from the positive data latch 710 and the negative data latch 720 to the level shifter 80 as video data P1 to Pi.

The level shifter 80, the decoder section 90 and the output amplifier section 95 generate grayscale data signals Vd1 to Vdi based on the video data P1 to Pi and supply them to the corresponding data lines DL.

Therefore, the output timing of the phase of the gradation data signal (gradation data pulse) to each data line corresponds to the output timing of each piece of video data output from the latch unit 700 based on the predetermined number of output units and the polarity. Yes.

FIG. 11 shows phases of grayscale data signals Vd1 to Vdm applied to the data lines DL1 to DL(m) of the display panel 150_1 by the data driver ICs 120-1 to 120-p each having the configuration shown in FIG. FIG. 10 is a diagram showing an example of output delay characteristics of a data pulse); In FIG. 11, the output delay characteristics of the positive gradation data signals Vd1 to Vdm are represented by POS, and the output delay characteristics of the negative gradation data signals Vd1 to Vdm are represented by NEG.

Here, the horizontal axis shown in FIG. 11 represents the data lines DL1 to DL(m) of the display panel 150_1, and the data driver ICs 120-1 to 120- each responsible for driving i (eg, 960) data lines DL. p are associated with each other. In FIG. 11, the data driver IC 120-1 responsible for driving the data lines DL1 to DLi is IC1, the data driver IC 120-1 responsible for driving the data lines DL(i+1) to DL(2i) is IC2, . The data driver IC 120-p responsible for driving the data lines DL(m−i+1)1 to DL(m) is denoted as ICp. Furthermore, in FIG. 11, among the data lines DL1 to DLm, the data driver IC 120 responsible for driving the data line group included in the central region in the horizontal direction of the screen is denoted as ICs.

The vertical axis shown in FIG. 11 indicates the output delay time of the grayscale data signals Vd1 to Vdm by the data driver ICs 120-1 to 120-p with respect to the phase of the reference timing of one horizontal period (one data period) cycle. Note that the reference timing is the timing of the reference timing signal STD having a phase for each data period. This is the falling start timing.

That is, in the output delay characteristics shown in FIG. 11, the output delay time is the smallest in the data line DL1 (IC1 side) at the left end of the display panel 150_1 and the data line DLm (ICp side) at the right end of the display panel 150_1. , the data line DL(c) has the maximum output delay time. Furthermore, in the output delay characteristics shown in FIG. 11, as shown by the output delay characteristics POS and NEG, the output delay time of the negative grayscale data signals Vd1 to Vdm is longer than that of the positive grayscale data signals Vd1 to Vdm. becomes larger.

By setting the output delay time of the gradation data signal for each data driver IC 120 as shown in FIG. 11, it is possible to improve the deterioration of the pixel charging rate due to the blunting of the pulse waveform of the gate selection signal.

A specific example will be described with reference to FIGS. 7 and 8. FIG.

As described above, FIG. 8 shows the gate selection signal Vgk observed at the position where the wiring length of the gate line from the output terminal of the gate driver is short at the intersection of the gate line and the data line, and the positive and negative polarity levels. FIG. 4 shows a phase timing diagram of the modulation data signals Vdx, Vd(x+1).

In the example shown in FIG. 8, the gate selection signal Vgk and the gradation data signals Vdx and Vd(x+1) are arranged so as to suppress a decrease in the pixel charging rate according to the degree of blunting of the rear edge portion (falling waveform) of the gate selection signal Vgk. ) are optimized for each phase timing.

In FIG. 8, the gate-off timing (at the start of falling) Tgof of the gate selection signal Vgk is used as the reference timing (phase of the reference timing signal STD), and the time difference from the data switching timing Tpt (phase) of the positive gradation data signal Vdx. be Ts30. Further, let Ts31 be the time difference between the data switching timing Tpt of the positive grayscale data signal Vdx and the data switching timing Tnt of the negative grayscale data signal Vd(x+1). At this time, the time difference between Ts30 and Ts31 corresponds to the output delay time of the data line DL driven by the data driver IC (eg, IC1 in FIG. 11) near the output terminal of the gate driver 110A (or 110B).

Similarly, FIG. 7 shows the gate selection signal Vgk and the positive and negative gradation data signals observed at the intersection of the gate line and the data line where the wiring length of the gate line from the output terminal of the gate driver is long. Fig. 3 shows a phase timing diagram for Vdx, Vd(x+1);

In the example shown in FIG. 7, the gate selection signal Vgk and the gradation data signals Vdx and Vd(x+1) are arranged so as to suppress a decrease in the pixel charging rate according to the degree of blunting of the rear edge portion (falling waveform) of the gate selection signal Vgk. ) are optimized for each phase timing.

In FIG. 7, the gate-off timing (falling start time) Tgof of the gate selection signal Vgk is used as the reference timing (phase of the reference timing signal STD), and the time difference from the data switching timing Tpt (phase) of the positive gradation data signal Vdx. be Ts20. Further, let Ts21 be the time difference between the data switching timing Tpt of the positive grayscale data signal Vdx and the data switching timing Tnt of the negative grayscale data signal Vd(x+1). At this time, the time difference between Ts20 and Ts21 corresponds to the output delay time of the data line DL driven by the data driver IC (eg, ICs in FIG. 11) far from the output terminal of the gate driver 110A (or 110B).

In FIG. 7, each phase of the timings Tgof, Tpt, and Tnt is, for example, the reference timing signal STD of ICs in FIG. are set by the output timing signals LOAD1-Grg and LOAD2-Grg.

That is, in FIGS. 7 and 8, based on the wiring length of the gate line from the output terminal of the gate driver, that is, the position of the data line DL of the display panel 150_1, each of the positive and negative gradation data signals is determined as follows. Adjust the output delay time. In other words, the timing difference between the phases of the positive and negative gradation data signals with respect to the gate selection signal is adjusted to be small at both ends in the horizontal direction of the display panel 150_1 where the rear edge portion of the gate selection signal is relatively less dull. On the other hand, in the central portion in the horizontal direction of the display panel, where the rear edge portion of the gate selection signal is largely blunted, the timing difference between the phases of the positive and negative gradation data signals with respect to the gate selection signal is adjusted to be large. By adjusting the output delay time in this way, a decrease in the pixel charging rate is suppressed.

Therefore, by setting the output delay time of the gradation data signal for each data driver IC based on the arrangement position of each data line of the display panel as shown in FIG. It becomes possible to improve the decrease.

Next, a method for setting the output delay characteristics for each polarity shown in FIG. 11 will be described.

12A to 12C show examples of positive output delay characteristics set for each data driver IC 120. FIG. 12A shows the first output delay characteristics Shift-1, and FIG. 12B shows the second output delay characteristics. Characteristic Shift-2, FIG. 12C shows the third output delay characteristic Shift-3. The same applies to the output delay characteristics of the negative polarity.

The horizontal axis shown in each of FIGS. 12A to 12C represents i output channels of the data driver IC 120 that output i gradation data signals, respectively, and data lines of the display panel connected to the i output channels, respectively. DL group (i number). That is, each of FIGS. 12A to 12c shows a state in which the first output channel is connected to the data line DLx of the display panel and the i-th output channel is connected to the data line DL(x+i). “x” shown in FIGS. 12A to 12C represents the number of the data line DL of the display panel to which the first output channel of each data driver IC 120 is connected.

In the output delay characteristic Shift-1 shown in FIG. 12A, the output delay time increases at a constant rate from the first output channel of the data driver IC 120 to the i-th output channel as the output channel number increases.

In the output delay characteristic Shift-2 shown in FIG. 12B, the increase and decrease in the output delay time with respect to the change in the output channel are opposite to those in the output delay characteristic Shift-1, and the output from the i-th output channel of the data driver IC 120 to the first output is reversed. The output delay time increases at a constant rate towards the channel.

The output delay characteristic Shift-3 shown in FIG. 12C is set such that the output delay time increases at a constant ratio from each of the first output channel and the i-th output channel of the data driver IC 120 toward the center output channel. be. In any of the examples of FIGS. 12A to 12C, the output delay time difference between adjacent outputs within the same polarity is a relatively small time difference that does not affect the display.

Here, the output delay characteristic as shown in FIG. 11 is determined by each data driver IC 120 ( IC1 side) is set to the output delay characteristic Shift-1 in FIG. 12A. Further, each data driver IC 120 (on the ICp side) responsible for displaying the image area on the right half of the display panel is set to the output delay characteristic Shift-2 in FIG. 12B.

To realize the output delay characteristic Shift-1 shown in FIG. 12A, the output delay direction information CF designates that the output delay time is increased in ascending order of the output channel numbers. Further, according to the output delay shift amount information SA1, the change rate (tr1/xr1) of the output delay time tr1 per group of (xr1) output channels from the first output channel to the i-th output channel is It is specified as the delay shift amount of the positive grayscale data signal. Furthermore, the rate of change (tr2/xr2) of the output delay time tr2 per group of (xr2) output channels from the first output channel to the i-th output channel is calculated from the output delay shift amount information SA2, It is specified as the delay shift amount of the negative grayscale data signal.

To realize the output delay characteristic Shift-2 shown in FIG. 12B, the output delay direction information CF designates that the output delay time is increased in descending order of the output channel number. Further, according to the output delay shift amount information SA1, the change rate (tl1/xl1) of the output delay time tl1 per group of (xl1) output channels from the i-th output channel to the first output channel is It is specified as the delay shift amount of the positive grayscale data signal. Further, according to the output delay shift amount information SA2, the change rate (tl2/xl2) of the output delay time tl2 per group of (xl2) output channels from the i-th output channel to the first output channel is expressed as It is specified as the delay shift amount of the negative grayscale data signal.

To realize the output delay characteristic Shift-3 shown in FIG. 12C, the output delay direction information CF is used to increase the output delay time from the first output channel toward the central output channel of the data driver IC 120 in ascending order of numbers. , and increasing in descending order from the i-th output channel toward the central output channel. The rate of change of each output delay time may be the same as the amount of delay shift designated by each of the output delay characteristics Shift-1 and Shift-2.

Furthermore, in order to realize the output delay characteristics shown in FIG. 11, the output start timing information TA1 and TA2 are used to set the output start channel for each data driver IC 120 on the IC1 side responsible for driving the image area on the left half of the display panel 150_1. It designates the first output channel side, and designates the output start timing of each of the positive and negative output start channels. The output start timing is designated by an output delay time from the reference timing.

For example, in the output start timing information TA1 of IC1, "tsp1" shown in FIG. 11 is designated as the output start timing of the output start channel on the positive side (for example, the positive side of the data line DL(i+1) or DL(i+2)). Furthermore, in the output start timing information TA1 of IC3, "tsp3" shown in FIG. In the output start timing information TA1, "tsp4" shown in FIG. 11 is specified as the output start timing of the output start channel on the positive side (for example, the positive side of the data line DL(3i+1) or DL(3i+2)). Also, for example, in the output start timing information TA2 of IC1, "tsn1" shown in FIG. , "tsn2" shown in FIG. 11 is designated as the output start timing of the output start channel on the negative side (for example, the negative side of the data line DL(i+1) or DL(i+2)). Furthermore, in the output start timing information TA2 of IC3, "tsn3" shown in FIG. The output start timing information TA2 designates "tsn4" shown in FIG. 11 as the output start timing of the negative output start channel (for example, the negative side of the data line DL(3i+1) or DL(3i+2)).

In each data driver IC 120 on the ICp side responsible for driving the image area on the right half surface of the display panel 150_1, the output start timing information TA1 and TA2 specify the output start channel on the i-th output channel side, Specifies the output start timing from the i-th output channel. The output start timing of each data driver IC 120 is symmetrical with respect to the center of the display panel with respect to the output start timing of each data driver IC 120 on the IC1 side responsible for driving the left half image area.

Therefore, for example, in the output start timing information TA1 of ICp, "tsp1" shown in FIG. 11 is specified as the output start timing of the output start channel on the positive side (for example, the positive side of the data line DL(m−1) or DL(m)). , in the output start timing information TA1 of IC(p-1), "tsp2" shown in FIG. ) as the output start timing. Further, in the output start timing information TA2 of ICp, "tsn1" shown in FIG. 11 is designated as the output start timing of the output start channel on the negative electrode side (for example, the negative electrode side of the data line DL(m−1) or DL(m)), In the output start timing information TA2 of IC(p-1), "tsn2" shown in FIG. specified as the output start timing of

Note that since the polarity of each output is switched in frame cycle units, for example, when the first output channel of IC1 is positive and the second output channel is negative, the output delay time of the first output channel is determined by the output start timing information TA1. It is set to "tsp1" as shown. Also, the output delay time of the second output channel is set to "tsn1" indicated by the output start timing information TA2. On the other hand, when the first output channel of IC1 is switched to the negative polarity and the second output channel is switched to the positive polarity, the output delay time of the first output channel is set to "tsn1" indicated by TA2, and the output delay time of the second output channel is set to "tsn1" indicated by TA2. is set to "tsp1" indicated by TA1. Between adjacent data lines DL on the boundary between the data driver ICs 120, the difference between the respective output delay times is set to a relatively small value that does not affect the display.

By the way, in the example described above, TA1 and TA2 are used to set the start timings of the positive and negative electrodes of the first output channel side of each data driver IC 120 on the IC1 side, which drives the image area on the left half of the display panel 150_1. explained with an example. At this time, the output start timing information TA1 and TA2 may include information specifying the output start timing of the positive and negative electrodes of the i-th output channel side of each data driver IC 120 .

Here, each data driver IC 120 on the IC1 side responsible for driving the image area on the left half of the display panel 150_1 and each data driver IC 120 on the ICp side responsible for driving the image area on the right half of the display panel 150_1 determine the output start timing with respect to the output delay time. is specified is different from the first output channel side (usually each data driver IC 120 for the left half image area) or the ith output channel side (usually each data driver IC 120 for the right half image area). , the designation of the output start channel can be automatically switched based on the output delay direction information CF.

12A to 12C are representative examples, and output delay characteristics other than those shown in FIGS. 12A to 12C may be set for each output channel.

Further, in the above-described embodiment, an application example of the output delay characteristic Shift-3 shown in FIG. can be applied to correct the fan-out wiring length of the data lines arranged on the end side in the horizontal direction of the screen. In setting the output delay characteristic Shift-3, the output start timing information TA1 and TA2 specify both the first output channel side and the i-th output channel side of the output start channel of the data driver IC 120 to be applied, and Specifies the output start timing for each of the positive and negative output start channels. Further, the output delay characteristic Shift-3 shown in FIG. 12C may be set not only by applying it alone but also in combination with the output delay characteristics Shift-1 and Shift-2.

In the above-described embodiment, the digital setting information includes the output delay direction information CF, the output delay shift amount information SA1 and SA2, and the output start timing information TA1 and TA2, but the present invention is not limited to this. In other words, the digital setting information may include arbitrary digital setting parameters for realizing output timings based on CF, SA1, SA2, TA1 and TA2. For example, instead of SA1 and SA2, TA1 and TA2 for setting the start or end timing of the phase of the gradation data signal Vd on the first output channel side for each data driver IC 120 for each polarity, and i-th for each data driver IC 120 Based on TB1 and TB2 for setting the start or end timing of the phase of the gradation data signal Vd on the output channel side for each polarity, the delay shift amount for each polarity can be internally set by the timing control unit.

By the way, the output delay times shown in FIGS. 11 and 12A-12C appear to change continuously with respect to the data line for convenience. However, for example, if the output delay time is designed to be shifted for each output channel, the circuit scale of the data driver IC 120 becomes enormous, which is not practical.

Therefore, in reality, as shown in FIG. 13, it is desirable to adopt a step type that changes the output delay time by (tr1) every (xr1) output channels. When the output delay time is set to change stepwise for each unit of the predetermined number of output channels, the delay time tr1 per step is a value small enough that the output delay time difference between adjacent output channels does not affect the display. is set to be A plurality of positive and negative output timing signal groups set for each predetermined number of output channels correspond to LOAD1-Grs and LOAD2-Grs in FIG. 10, respectively.

FIG. 14 is a diagram showing another example of output delay characteristics by the data drivers 120-1 to 120-p.

In FIG. 14 , the positive and negative delay shift amounts are changed for each data driver IC 120 based on the output delay shift amount information SA1 and SA2 for each data driver IC 120 .

Specifically, the positive and negative delay shift amounts are set so as to gradually decrease from both ends toward the center in the horizontal direction of the screen of the display panel 150_1. With this setting, the rear edge portion (for example, the falling waveform portion) of the gate selection signal is blunted (slope of the falling waveform) at both ends in the horizontal direction of the screen of the display panel 150_1, and the amount of change is large at the center portion in the horizontal direction of the screen. is a setting corresponding to a small amount of change in blunting (slope of falling waveform). Output start timing information TA1 and TA2 for setting the start timing of the phase of the gradation data signal for each data driver IC 120 is also provided corresponding to the output delay shift amount information SA1 and SA2 indicating the delay shift amount for each data driver IC 120. Optimized.

As described above, by optimally setting the digital setting information (CF, SA1, SA2, TA1, TA2) for each data driver IC 120 according to changes in dullness of the rear edge portion of the gate selection signal, A decrease in the pixel charging rate of the display panel due to dulling of the rear edge portion can be suppressed, and high-quality display can be realized.

Further, by setting the digital setting information (CF, SA1, SA2, TA1, TA2) to optimum values on the display controller 100A side according to the screen size and panel design of the display panel 150_1 of the liquid crystal display device 10_1, high quality A liquid crystal display device can be realized. At this time, since the amount of the digital setting information described above is not large, it is possible to perform optimum adjustment according to the display panel by storing the information in a rewritable memory or the like from the outside.

FIG. 15 is a diagram showing an example of a time chart of each timing signal in the liquid crystal display device shown in FIG. 2 or 9 in which the data driver IC 120 shown in FIG. 10 is mounted.

In the time chart shown in FIG. 15, IC1 and ICs in FIG. Signal STD and gate line selection sequence are shown. Also, in FIG. 15, as an example of the latch output timing signal groups LOAD1-Grs and LOAD2-Grs generated by the timing control unit 650, Corresponding LOAD2-Gr1, LOAD1-Grf (f is an integer equal to or greater than 2) corresponding to positive polarity on the i-th output channel side in IC1, and LOAD2-Grf corresponding to negative polarity are shown. Furthermore, FIG. 15 shows LOAD1-Grg corresponding to positive polarity and LOAD2-Grg corresponding to negative polarity on the i-th output channel side of ICs. Note that the gate line selection sequence represents only a simple gate selection order for a plurality of latch output timing signal groups.

Here, LOAD1-Gr1 and LOAD1-Grf belong to different groups in the positive latch output timing signal group LOAD1-Grs of IC1. Similarly, LOAD2-Gr1 and LOAD2-Grf belong to groups different from each other in the negative latch output timing signal group LOAD2-Grs of IC1.

Timing of each output timing signal from the latch section is individually set for each predetermined number of output channels according to the digital setting information (CF, TA1, TA2, SA1, SA2).

IC1 as the data driver IC 120 is installed closest to the gate driver 110A among the data driver ICs 120-1 to 120-p (IC1 to ICp) that drive the display panel 150_1 shown in FIG.

The ICs as the data driver 120 are installed at the farthest position (central part of the display panel) from each of the gate drivers 110A and 110B. In FIG. 15, the rising edge of each timing signal is shown as the timing reference. In addition, in the time chart shown in FIG. 15, the order of selection of the gate line GL for the grayscale data signal Vd applied to each data line DL of the display panel 150_1 is the gate line formed at the position farthest from the data driver IC 120. A case of sequentially selecting from GLr toward the gate line GL1 formed closest to the data driver IC 120 is shown.

In FIG. 15, LOAD1-Gr1 and LOAD2-Gr1 are the positive and negative latch output timing signals, respectively, on the first output channel side of IC1. At this time, based on the digital setting information described above, LOAD1-Gr1 corresponding to the positive polarity is set to a signal delayed by time Ts30 with respect to the reference timing signal STD, and LOAD2-Gr1 corresponding to the negative polarity is set to LOAD1-Gr1. is set to a signal delayed by time Ts31.

The times Ts30 and Ts31 as delay shift amounts are set in advance according to the delay of the gate selection signal. Here, the first output channel side of IC1 is a data line close to the gate driver 110A, and the signal delay of the gate signal is small. Therefore, the times Ts30 and Ts31 as delay shift amounts are set to relatively small values. Note that the times Ts30 and Ts31 are the phase difference between the gate-off timing Tgof shown in FIG. 8 and the positive grayscale data signal Vdx, and the positive grayscale data signal Vdx and the negative grayscale data signal Vd( x+1).

In FIG. 15, LOAD1-Grf and LOAD2-Grf are positive and negative latch output timing signals on the i-th output channel side of IC1.

The latch output timing signal LOAD1-Grf corresponding to the positive polarity is delayed by time Ts30a with respect to the reference timing signal STD as shown in FIG. signal. On the other hand, the negative latch output timing signal LOAD2-Grf is set to a signal delayed by time Ts31a with respect to LOAD1-Grf as shown in FIG. The times Ts30a and Ts31a as delay shift amounts are set in advance according to the delay of the gate signal.

Here, the data line on the i-th output channel side of IC1 is a data line arranged at a position farther from the gate driver 110A than the data line on the first output channel side, and the delay of the gate signal increases. Therefore, times Ts30a and Ts31a as delay shift amounts are set to values greater than times Ts30 and Ts31 as delay shift amounts on the first output channel side.

Further, in FIG. 15, LOAD1-Grg and LOAD2-Grg are the positive and negative latch output timing signals on the i-th output channel side of the ICs.

The latch output timing signal LOAD1-Grg corresponding to the positive polarity is set to a signal delayed by time Ts20 as shown in FIG. 15 with respect to the reference timing signal STD. On the other hand, the latch output timing signal LOAD2-Grg corresponding to the negative polarity is set to a signal delayed by time Ts21 as shown in FIG. 15 with respect to LOAD1-Grg. The times Ts20 and Ts21 as delay shift amounts are set in advance according to the delay of the gate signal.

Here, the data line DL on the i-th output channel side of the ICs is a data line arranged at a position separated from the gate driver, and the signal delay of the gate signal is large. Therefore, the times Ts20 and Ts21 as delay shift amounts are set to large values. Note that the times Ts20 and Ts21 correspond to the phase difference between the gate-off timing Tgof shown in FIG. 7 and the positive grayscale data signal Vdx, and the positive grayscale data signal Vdx and the negative grayscale data signal Vd( x+1).

As described in detail above, the data drivers 120-1 to 120-p shown in FIGS. 9 and 10 provide the output delay time when delaying and outputting the positive grayscale data signal and the negative grayscale data signal. Setting information that individually designates an output delay time for delaying and outputting the tone data signal is received, and driving is performed based on the setting information. The setting information includes the following output delay direction information, output delay shift amount information, and output start timing information. That is, the output delay direction information (CF) is the output delay time to be set to i (i is an integer equal to or greater than 2) output channels for each of the plurality of data drivers (120-1 to 120-p). This is information specifying the direction of increase. As representative output delay direction information (CF), for i output channels, the output delay time from the output start channel is increased in ascending order or descending order of the output channel number, or There is information specifying whether to increase the output delay time from both ends toward the center of the i output channels. The output delay shift amount information (SA1, SA2) is the rate of change in the output delay time (tr1/xr1, tr1/xr1, tl1/xl1) is designated as the first delay shift amount (SA1), and the change rate (tr2/xr2, tl2/xl2) of the output delay time for the negative grayscale data signal in i output channels is designated as This is information designated as the second delay shift amount (SA2). The output start timing information (TA1, TA2) designates the output timing (for example, tsp1) of the output start channel for the positive grayscale data signal as the first output start timing (TA1) for each of the plurality of data drivers, This is information specifying the output timing (for example, tsn1) of the output start channel for the negative grayscale data signal as the second output start timing (TA2). The output start timing information (TA1, TA2) may include information specifying an output start channel (first channel side or i-th channel side) for setting the output start timing of each data driver. Alternatively, the output start channel of the output start timing setting may be designated in correspondence with the output delay direction information.

By adopting the configuration shown in FIGS. 9 and 10, it is possible to adapt to the size of the display panel of the display device, the number and arrangement of data drivers and gate drivers, and the display panel due to the bluntness of the rear edge portion of the gate selection signal. Therefore, it is possible to suppress the decrease in the pixel charging rate.

FIG. 16 is a time chart showing another example of the state (positive polarity or negative polarity) of each of the gradation data signals Vd1 to Vd(q) output from, for example, the data driver 120-1 by column inversion driving. 6 shows a modified example of the time chart shown in FIG.

That is, FIG. 6 shows an example in which the polarity of the grayscale data signal is switched between even-numbered data lines and odd-numbered data lines.

On the other hand, in another example shown in FIG. 16, the data lines DL1 to DLm of the display panel are divided into groups of a predetermined number (j lines), and in each group, grayscale levels having different polarities are applied to the adjacent data lines DL. Driving is performed so as to apply a data signal, and driving is performed so that a gradation data signal of the same polarity is applied to adjacent data lines DL sandwiching the boundary between adjacent groups.

That is, particularly in a high-resolution display panel having an extremely large number of data lines DL, there are cases where the polarities of gradation data signals are set in a plurality of patterns in order to improve display quality. Therefore, in performing the column inversion driving, the driving shown in FIG. 16 is also introduced to cope with such various polarity patterns.

70 data latch unit 71 positive data latch 72 negative data latch 100 amplifier circuit 110 gate driver 120 data driver 150 display panel

Claims (7)

a plurality of data lines consisting of first and second data line groups; and a plurality of gate lines arranged to cross the plurality of data lines; a display panel on which display cells serving as pixels are arranged;
a gate driver that supplies a gate selection signal to each of the plurality of gate lines;
Each data line is provided for a predetermined number of data lines, each receives a video signal, and a data pulse having a positive analog voltage value with respect to a predetermined reference voltage corresponding to the luminance level of each pixel based on the video signal is predetermined. A signal that appears in a cycle is generated as a positive polarity gradation data signal, and a data pulse having a negative analog voltage value with respect to the reference voltage is generated every the predetermined period in a phase different from that of the positive polarity gradation data signal. is generated as a negative gradation data signal, and the positive gradation data signal is output to one of the first and second data line groups, and the other data a plurality of data drivers that output the negative grayscale data signals to the line group;
The data driver is
A first value representing a delay time with respect to a reference timing corresponding to the gate-off timing of the gate selection signal output from each of the plurality of gate lines when the positive grayscale data signal is output every predetermined period . An output delay time, and a second output delay time different from the first output delay time representing the delay time with respect to the reference timing when the negative grayscale data signal is output in each of the predetermined cycles, respectively. receive configuration information,
The positive grayscale data signal is delayed from the reference timing by the first output delay time indicated by the setting information, and the negative grayscale data signal is output every predetermined period. delaying from the reference timing by the second output delay time indicated by the setting information every predetermined period and outputting ;
The negative grayscale data signal is a signal that is phase-shifted in a direction lagging with respect to the positive grayscale data signal,
The time length of the phase shift of the negative grayscale data signal with respect to the positive grayscale data signal is determined by the crossing of the data line receiving the grayscale data signal from the output terminal of the gate driver and the gate line. A display device, wherein the shorter the wiring length of the gate line to the position, the shorter the wiring length is set . The display cell is
a liquid crystal layer;
a pixel electrode and a counter substrate electrode sandwiching the liquid crystal layer;
a pixel switch that turns on when the gate selection signal is supplied to the gate line and supplies the grayscale data signal supplied to the data line to the pixel electrode;
A counter-substrate voltage forming the predetermined reference voltage is applied to the counter-substrate electrode,
The pixel switch is a thin film transistor having a control end connected to the gate line, a first terminal connected to the data line, and a second terminal connected to the pixel electrode. 2. The display device according to claim 1 , wherein: Each of the plurality of data drivers includes:
i output channels for outputting i (i is an integer equal to or greater than 2) gradation data signals each having a positive polarity or a negative polarity;
3. A display according to claim 1 , wherein a plurality of stages of output delay times are set for each polarity and for each unit of a predetermined number of output channels for said i output channels based on said setting information. Device. The setting information is
For each of the plurality of data drivers, the output delay times from the output start channels of the positive and negative polarities for the i output channels are arranged in either ascending order or descending order of the output channel numbers. or output delay direction information specifying whether to increase the output delay time from both ends toward the center of the i output channels;
For each of the plurality of data drivers, a rate of change in output delay time for the positive grayscale data signal in the i output channels is designated as a first delay shift amount, and the i outputs are generated. output delay shift amount information specifying a change rate of the output delay time for the negative grayscale data signal in the channel as a second delay shift amount;
for each of the plurality of data drivers, specifying the output start timing of the positive output start channel for the positive grayscale data signal in the i output channels as a first output start timing; 4. The output start timing information specifying the output start timing of the negative output start channel for the negative grayscale data signal in the output channel of the second output start timing as a second output start timing . display device. The setting information, instead of the output delay shift amount information,
a third output start timing designating an output start timing of the positive output final channel for the positive grayscale data signal in the i output channels; and the negative grayscale data in the i output channels. a fourth output start timing designating the output start timing of the final output channel of negative polarity for the signal is added to the output start timing information;
The rate of change of the output delay time with respect to the positive grayscale data signal is calculated and set by the first delay shift amount based on the specification of the first and third output start timings, and the negative grayscale data 5. The display device according to claim 4 , wherein the change rate of the output delay time with respect to the signal is set by calculating the second delay shift amount based on the specification of the second and fourth output start timings. . 6. The display device according to claim 5 , wherein said plurality of data drivers include storage circuits for storing said setting information supplied from said display controller . the plurality of data line groups constituting the display panel are grouped by a predetermined number of data lines adjacent to each other;
The data lines adjacent to each other within the group output grayscale data signals of different polarities, and the data lines adjacent across the boundary of the adjacent groups output grayscale data signals of the same polarity. The display device according to any one of claims 1 to 6 .

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