JP7128809B2 - semiconductor equipment - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optic devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices. .

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter.

A technique for constructing a transistor using a semiconductor thin film is attracting attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a display device using a transistor having a channel formation region containing zinc oxide or In--Ga--Zn oxide as an oxide semiconductor has been disclosed (see Patent Documents 1 and 2). ).

Furthermore, in recent years, a technique for manufacturing an integrated circuit of a memory device using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3). In addition to memory devices, arithmetic devices and the like are manufactured using transistors including oxide semiconductors.

Japanese Patent Application Laid-Open No. 2007-123861 JP 2007-96055 A JP 2011-119674 A

By the way, as electronic devices have become more sophisticated, smaller, and lighter, integrated circuits have become more highly integrated, and transistors have become finer in size. Accordingly, the process rule for transistor fabrication is also becoming smaller year by year to 45 nm, 32 nm, and 22 nm. Along with this, a transistor including an oxide semiconductor is also required to have favorable electrical characteristics as designed in a fine structure.

An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with small variations in electrical characteristics across the substrate surface. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high productivity. Alternatively, an object of one embodiment of the present invention is to provide a novel semiconductor device.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the descriptions of the specification, drawings, claims, etc. is.

One embodiment of the present invention includes a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, the first conductor, the first insulator, and the first conductor. and an oxide having a region in contact with a side surface of the second conductor; a second insulator over the oxide; and a third conductor over the second insulator; The second insulator has regions facing side surfaces of the first conductor, the first insulator, and the second conductor with oxide interposed therebetween, and the third conductor includes oxide and The semiconductor device includes a first conductor, the first insulator, and a region facing side surfaces of the second conductor with the second insulator interposed therebetween.

Further, in the above aspect, the first conductor, the first insulator, and the second conductor are covered with a third insulator, the third insulator has an opening, the oxide is The two insulators and the third conductor may be formed to fill the opening.

Further, in the above aspect, the oxide has a region in contact with the top surface of the second conductor, and the second insulator has a region overlapping with the top surface of the second conductor with the oxide interposed therebetween. , the third conductor may have a region overlapping the upper surface of the second conductor with the oxide and the second insulator interposed therebetween.

Further, in the above aspect, the film thickness of the first insulator may be 1 nm or more and 100 nm or less.

Moreover, in the above aspect, the oxide may contain a metal oxide.

According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with small variations in electrical characteristics over the substrate surface can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a high degree of freedom in design can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided. Alternatively, one embodiment of the present invention can provide a novel semiconductor device.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Effects other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract effects other than these from the descriptions of the specification, drawings, claims, etc. is.

1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a configuration example of a memory device according to one embodiment of the present invention; 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention; FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention; FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention; FIG. 1A and 1B are block diagrams and circuit diagrams each illustrating a configuration example of a memory device according to one embodiment of the present invention; 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention; FIG. 1A and 1B are block diagrams and circuit diagrams each illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and timing charts each illustrating an operation example of the semiconductor device; 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention; FIG. 4A and 4B are circuit diagrams each illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and timing charts each illustrating an operation example of the semiconductor device; 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention; FIG. 1A and 1B are circuit diagrams each illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are top views of a semiconductor wafer according to one embodiment of the present invention; 4A and 4B are a flowchart and a schematic perspective view for explaining an example of a manufacturing process of an electronic component; 1A and 1B illustrate electronic devices according to one embodiment of the present invention;

Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily appreciate that the embodiments can be embodied in many different forms and that various changes in form and detail can be made without departing from the spirit and scope thereof. be. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

Also, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but are sometimes omitted for ease of understanding. In addition, in the drawings, the same reference numerals may be used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof may be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In particular, in top views (also referred to as “plan views”) and perspective views, description of some components may be omitted in order to facilitate understanding of the invention. Also, description of some hidden lines may be omitted.

In this specification and the like, ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third". Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

In this specification and the like, terms such as “above” and “below” are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. In addition, the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately rephrased according to the situation.

In this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of −5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode). current can flow through the Note that in this specification and the like, a channel formation region means a region where current mainly flows.

Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" can be used interchangeably in some cases.

Note that the channel length of a transistor refers to, for example, a region where a semiconductor (or a portion through which current flows in a semiconductor when the transistor is on) overlaps with a gate electrode, or a region where a channel is formed. source region or source electrode) and the drain (drain region or drain electrode). Note that the channel length does not always have the same value in all regions of one transistor. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the region where the channel is formed.

In this specification and the like, a silicon oxynitride film refers to a film that contains more oxygen than nitrogen in its composition, and a silicon nitride oxide film means a film that contains more nitrogen than oxygen in its composition. Membrane with a lot of

Moreover, in this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for a channel formation region of a transistor, the metal oxide is sometimes called an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide can be called a metal oxide semiconductor, abbreviated as an OS. In addition, the description of an OS FET or an OS transistor can also be referred to as a transistor including a metal oxide or an oxide semiconductor.

In addition, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

In this specification and the like, it may be referred to as CAAC (C-Axis Aligned Crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

In this specification and the like, CAC-OS or CAC-metal oxide means that part of the material has a conductive function, part of the material has an insulating function, and the entire material is a semiconductor. It has a function as Note that when CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, the function of conductivity is to flow electrons (or holes) that serve as carriers, and the function of insulation is to flow carriers. It is a function that does not flow any electrons (or holes). A switching function (on/off function) can be imparted to the CAC-OS or CAC-metal oxide by making the conductive function and the insulating function act complementarily. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

In this specification and the like, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive regions have the above-described conductive function, and the insulating regions have the above-described insulating function. In some materials, the conductive region and the insulating region are separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected like a cloud with its periphery blurred.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. There is

Also, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from an insulating region and a component having a narrow gap resulting from a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having a narrow gap acts complementarily on the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current drivability, that is, large on-current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

In this specification and the like, the terms “film” and “layer” can be used interchangeably. For example, it may be possible to change the term "conductive layer" to the term "conductive film." Or, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Also, the term “conductor” can be replaced with a conductive film or a conductive layer. Also, the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

In addition, transistors described in this specification and the like are field-effect transistors unless otherwise specified. In addition, transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, its threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

(Embodiment 1)
<Structure Example 1 of Semiconductor Device>
Structure examples of a semiconductor device including the transistor 10 according to one embodiment of the present invention are described below with reference to FIGS.

FIG. 1A is a top view of a semiconductor device having a transistor 10. FIG. FIG. 1(B) is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1(A). FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 1(A). Here, the portion A1-A2 indicated by the dashed-dotted line and the portion indicated by the dashed-dotted line A3-A4 are orthogonal to each other. In the top view of FIG. 1A, some elements are omitted for clarity of illustration.

A semiconductor device of one embodiment of the present invention includes the transistor 10, the insulators 100, 102, 105, 110, 175, and 175, which function as interlayer films, over a substrate (not shown). 176 , an insulator 178 and an insulator 180 . In addition, it is electrically connected to the transistor 10 and has conductors 185 and 200 functioning as wirings and conductors 190 and 195 functioning as plugs.

Conductor 185 is formed in an opening provided in insulator 105 . Here, the height of the top surface of the conductor 185 and the height of the top surface of the insulator 105 are preferably approximately the same. Note that although the conductor 185 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, the conductor 185 may have a laminated structure of two or more layers.

Conductor 190 is formed in an opening provided in insulator 110 . The bottom surface of the conductor 190 is provided so as to have a region in contact with the top surface of the conductor 185 . Here, it is preferable that the height of the upper surface of the conductor 190 and the height of the upper surface of the insulator 110 be approximately the same. Note that although the conductor 190 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, as the conductor 190, a conductor is formed in contact with the inner wall of the opening provided in the insulator 110 and is made of a material that suppresses permeation of impurities such as hydrogen and water, and oxygen. A laminated structure of two or more layers in which a conductor made of a material having a higher conductivity than the conductor may be used.

Conductor 195 is formed in openings provided in insulator 175 , insulator 176 , insulator 178 , and insulator 180 reaching the upper surface of conductor 140 . Here, it is preferable that the height of the upper surface of the conductor 195 and the height of the upper surface of the insulator 180 be approximately the same. Note that although the conductor 195 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. A conductor made of a material that suppresses permeation of impurities such as hydrogen and water and oxygen is formed in contact with the inner walls of the openings provided in the insulator 178 and the insulator 180, and the conductor is formed over the conductor. It may be a laminated structure of two or more layers in which conductors made of a material having a higher electrical conductivity are formed.

Conductor 200 is formed over insulator 180 so as to have a region in contact with the top surface of conductor 195 . Note that although the conductor 200 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, the conductor 200 may have a laminated structure of two or more layers.

[Transistor 10]
As illustrated in FIG. 1B, the transistor 10 includes a conductor 120 and an oxide 150 over the insulator 110, an insulator 130 over the conductor 120, and the insulator 130. It has a conductor 140 overlying it, an insulator 160 overlying the oxide 150 , and a conductor 170 overlying the insulator 160 . Here, the oxide 150 is provided so as to have regions in contact with side surfaces of the conductor 120 , the insulator 130 , and the conductor 140 . The insulator 160 is provided so as to have regions facing side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 interposed therebetween. In addition, the conductor 170 is provided so as to have regions facing side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 and the insulator 160 interposed therebetween.

As shown in FIGS. 1B and 1C, an insulator 175 is provided over the conductor 120, the insulator 130, and the conductor 140 so as to cover them. The insulator 175 is provided with openings in which the side surfaces of the conductor 120, the insulator 130, and the conductor 140 partially overlap with the inner walls, and the oxide 150 is provided along the inner walls of the openings. An insulator 160 is provided above, and a conductor 170 is provided over the insulator 160 so as to fill the opening. Here, as shown in FIG. 1B, the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175. FIG. Note that although the oxide 150 has a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited thereto. For example, oxide 150 may have a stacked structure of two or more layers.

In transistor 10 , conductor 120 functions as one of the source and drain electrodes, conductor 140 functions as the other of the source and drain electrodes, and insulator 130 of oxide 150 . The overlapping region functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode.

As described above, the transistor 10 according to one embodiment of the present invention includes a conductive layer (the conductor 120) functioning as one of a source electrode and a drain electrode, and an insulating layer (the An insulator 130) and a conductive layer (conductor 140) functioning as the other of a source electrode and a drain electrode are stacked in this order from the bottom. That is, in the transistor 10, the direction in which carriers (electrons or holes) flow (channel length direction) is substantially perpendicular to the substrate surface. Since the transistor 10 has this structure, the channel length of the transistor 10 is defined by the thickness of the insulator 130 sandwiched between the source electrode and the drain electrode. Therefore, the channel length of the transistor 10 can be controlled by the film thickness of the insulator 130 when it is formed. For example, the channel length of the transistor 10 can be arbitrarily controlled within the range of 1 nm or more and 100 nm or less. Therefore, a plurality of fine transistors can be manufactured with higher precision within the substrate plane than when the channel length is formed by a lithography method or the like.

Note that in the transistor 10, the oxide 150 functioning as a channel formation region is preferably a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). A transistor using a metal oxide for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state; thus, a semiconductor device with low power consumption can be provided. In addition, since a metal oxide can be deposited by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.

On the other hand, in a transistor using a metal oxide for a channel formation region, electrical characteristics are likely to vary due to impurities or oxygen vacancies in the metal oxide, and reliability may be degraded. In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, are generated in some cases. Therefore, a transistor in which a metal oxide containing oxygen vacancies is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiency in the metal oxide is reduced as much as possible.

In particular, when oxygen vacancies are present at the interface between the channel formation region of the oxide 150 and the insulator 160 functioning as a gate insulator, the electrical characteristics of the transistor 10 are likely to fluctuate and the reliability may be degraded. There is

Therefore, the insulator 160 in contact with the oxide 150 preferably contains more oxygen (also referred to as excess oxygen) than the oxygen that satisfies the stoichiometric composition. That is, excess oxygen in the insulator 160 diffuses into the channel formation region of the oxide 150, whereby oxygen vacancies in the channel formation region can be reduced.

Furthermore, the transistor 10 is preferably covered with an insulator having a barrier property to prevent entry of impurities such as water or hydrogen. An insulator with a barrier property has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ , etc.), and copper atoms. It is an insulator using an insulating material having (the impurities are difficult to permeate). In addition, it is preferable to use an insulating material that has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate).

For example, the transistor 10 is provided over an insulator 102 having barrier properties. An insulator 178 having a barrier property is provided over the transistor 10 . With the structure in which the insulator 102 and the insulator 178 are arranged above and below the transistor 10, the transistor 10 can be sandwiched between insulators having a barrier property. With this structure, impurities such as hydrogen and water can be prevented from entering the transistor 10 from the lower layer of the insulator 102 and from the upper layer of the insulator 178 . Alternatively, diffusion of oxygen contained in the insulators 130 and 160 to the lower layer of the insulator 102 and the upper layer of the insulator 178 can be suppressed. Accordingly, oxygen contained in the insulators 130 and 160 can be efficiently supplied to the channel formation region of the oxide 150 .

A detailed structure of the semiconductor device including the transistor 10 according to one embodiment of the present invention is described below.

The insulator 102 and the insulator 178 preferably function as barrier films that prevent impurities such as water or hydrogen from entering the transistor 10 from outside the insulator. Therefore, insulator 102 and insulator 178 suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N ₂ O, NO, NO ₂ ), and copper atoms. It is preferable to use an insulating material that has a function to prevent the impurities from penetrating therethrough. Alternatively, it is preferable to use an insulating material that has a function of suppressing at least one diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate).

For example, the insulator 102 and the insulator 178 are preferably made of aluminum oxide, silicon nitride, or the like. Accordingly, impurities such as hydrogen and water can be prevented from diffusing inward (on the transistor 10 side) from the insulator. Alternatively, diffusion of oxygen contained in the insulator 130 or the like to the outside of the insulator 102 and the insulator 178 can be suppressed.

Further, for example, as the insulator 102 and the insulator 178, an insulator such as aluminum oxide, hafnium oxide, or silicon nitride can be used as a single layer or a stacked layer.

The insulators 100 , 105 , 110 , 175 , 176 , and 180 that function as interlayer films preferably have lower dielectric constants than the insulators 102 and 178 . By using a material with a relatively low dielectric constant for the insulator, for example, parasitic capacitance generated between wirings can be reduced.

For example, the insulator 100, the insulator 105, the insulator 110, the insulator 175, the insulator 176, and the insulator 180 include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide. , lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba,Sr)TiO ₃ (BST) can be used in single layers or stacks. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator. Note that it is preferable that the concentrations of impurities such as hydrogen and water in the films of the various insulators described above be as low as possible.

In the transistor 10, the insulator 130 physically and electrically separates the conductor 120 functioning as one of the source electrode and the drain electrode from the conductor 140 functioning as the other of the source electrode and the drain electrode. have a function. The thickness of the insulator 130 is preferably 1 nm or more and 100 nm or less. As described above, the sides of insulator 130 are in contact with the channel forming region of transistor 10 of oxide 150 . Therefore, as the insulator 130, an oxide insulator containing more oxygen than the stoichiometric composition is preferably used. In other words, the insulator 130 preferably has an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 150, oxygen vacancies in the channel formation region of the oxide 150 can be reduced and the reliability of the transistor 10 can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having the excess oxygen region. The oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms is 1.0×10 ¹⁴ atoms/cm ² or more, preferably 3, in TDS (Thermal Desorption Spectroscopy) analysis. It is an oxide film having a density of 0×10 ¹⁵ atoms/cm ² or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower.

Note that while the insulator 130 preferably contains oxygen as much as possible, it preferably does not contain hydrogen, water, or the like as much as possible. This is because hydrogen, water, and the like can cause changes in electrical characteristics of the transistor 10 . Therefore, the concentration of hydrogen, water, and the like, which can be impurities in the transistor 10, is reduced as much as possible not only in the oxide 150 functioning as a channel formation region but also in the insulator 130 in contact with the oxide 150. preferable.

For the oxide 150 functioning as a channel formation region of the transistor 10, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, it is preferable to use a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, as a metal oxide used for the channel formation region. By using a metal oxide with a large bandgap in this manner, off-state current of a transistor can be reduced.

The oxide 150 may have a laminated structure of two or more layers using oxides with different atomic ratios of metal atoms. For example, when the oxide 150 has a two-layer structure consisting of an oxide 150a (first layer) and an oxide 150b (second layer), in the metal oxide used for the oxide 150b, It is preferable that the atomic number ratio of the element M is larger than the atomic number ratio of the element M among the constituent elements in the metal oxide used for the oxide 150a. Moreover, in the metal oxide used for the oxide 150b, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 150a. In addition, the atomic ratio of In to the element M in the metal oxide used for the oxide 150a is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 150b.

In the case where the oxide 150 has the above structure, the oxide 150a mainly functions as a channel formation region of the transistor . Here, defect levels are more likely to be formed at the interface between the insulator 160 and the oxide 150b made of different materials than at the interface between the oxide 150a and the oxide 150b made of materials with similar compositions. The defect level can become a trap level that causes variations in electrical characteristics of the transistor 10 and deterioration in reliability. can be separated from This allows transistor 10 to provide good electrical characteristics and reliability.

In addition, by providing the oxide 150b over the oxide 150a, diffusion of impurities from above the oxide 150b into the channel formation region of the oxide 150a can be suppressed.

As described above, a transistor in which a metal oxide is used for a channel formation region has extremely low leakage current in a non-conducting state; therefore, a semiconductor device with low power consumption can be provided. In addition, since a metal oxide can be deposited by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.

For example, as the oxide 150, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or the like) may be used. Alternatively, as the oxide 150, an In--Ga oxide or an In--Zn oxide may be used.

The conductors 120 and 140 function as source and drain electrodes of the transistor 10 . As shown in FIGS. 1B and 1C, the conductor 120 and the conductor 140 are vertically provided with the insulator 130 interposed therebetween. A conductor such as tantalum nitride, tungsten, or titanium nitride can be used for the conductor 120 and the conductor 140, for example. Note that although the conductors 120 and 140 each have a single-layer structure in FIG. 1, they may have a laminated structure of two or more layers.

For example, when the conductor 120 and the conductor 140 have a two-layer structure, a metal such as tungsten is used for the first layer (second layer) of the conductor 120 (the conductor 140) and the conductor 120 (the conductor 140). 140), a conductor having a function of suppressing permeation of oxygen, such as titanium nitride or tantalum nitride, may be used for the second layer (first layer). With this structure, as described above, when the insulator 130 sandwiched between the conductor 120 and the conductor 140 contains excess oxygen, the first layer of the conductor 120 (the conductor 140) from the insulator 130 Mixing of oxygen into (the second layer) is reduced, and an increase in the electrical resistance value of the first layer (the second layer) of the conductor 120 (the conductor 140) can be suppressed.

Although not shown in FIG. 1, an insulator having a function of suppressing permeation of oxygen, such as aluminum oxide, may be formed over the conductor 120 (under the conductor 140). For example, a structure in which a conductor such as tantalum nitride, tungsten, or titanium nitride is used as the conductors 120 and 140 and an insulator such as aluminum oxide is stacked over the conductor 120 (under the conductor 140) may be employed. With such a structure, entry of oxygen from the insulator 130 into the conductors 120 and 140 can be reduced, and an increase in electrical resistance of the conductors 120 and 140 can be suppressed. In addition, a large amount of oxygen can be supplied to the oxide 150 by reducing the amount of oxygen mixed into the conductors 120 and 140 . Note that aluminum oxide containing excess oxygen can be deposited over the conductor 120 (under the conductor 140) by a sputtering method. The excess oxygen may be supplied to insulator 130 . Furthermore, oxygen supplied to insulator 130 may be supplied to oxide 150 .

Also, conductor 120 or conductor 140 may react with oxide 150 . As a result, although not shown in FIG. 1, an n-type region with increased carriers may be formed at the interface between the oxide 150 and the conductor 120 or the conductor 140 . Such regions may contribute to increasing the drain current of transistor 10 .

Insulator 160 functions as a gate insulator for transistor 10 . Insulator 160 is preferably placed in contact with the top surface of oxide 150 . The insulator 160 is preferably formed using an insulator from which oxygen is released by heating. For example, the insulator 160 has an oxygen desorption amount of 1.0×10 ¹⁴ atoms/cm ² or more, preferably 3 atoms/cm 2 or more in terms of oxygen atoms in thermal desorption spectroscopy (TDS analysis). An oxide film having a density of 0.0×10 ¹⁵ atoms/cm ² or more is preferable. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower.

By providing an insulator from which oxygen is released by heating as the insulator 160 in contact with the top surface of the oxide 150 , oxygen can be efficiently supplied to a channel formation region of the oxide 150 . Further, similarly to the insulator 130, the concentration of impurities such as water or hydrogen in the insulator 160 is preferably reduced. The thickness of the insulator 160 is preferably 1 nm or more and 20 nm or less. Note that although the insulator 160 has a single-layer structure in FIG. 1, it may have a laminated structure of two or more layers.

Conductor 170 functions as a gate electrode of transistor 10 . A metal such as tungsten can be used for the conductor 170, for example. Note that although the conductor 170 has a single-layer structure in FIG. 1, it may have a laminated structure of two or more layers.

For example, when the conductor 170 has a three-layer structure, a conductive oxide is used for the first layer of the conductor 170 , titanium nitride is used for the second layer of the conductor 170 , and titanium nitride is used for the third layer of the conductor 170 . It is preferable to use a metal such as tungsten for . Note that in the case where the conductor 170 has a three-layer structure as described above, the first layer of the conductor 170 is arranged along the top surface of the insulator 160, and the second layer of the conductor 170 is arranged along the top surface of the conductor 170. It is preferable that the third layer of the conductor 170, which is arranged along the top surface of the first layer, fills the remaining space in which the conductor 170 is provided. Further, the heights of the top surface of the first layer of the conductor 170, the second layer of the conductor 170, and the top surface of the third layer of the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175.

As a conductive oxide that can be used for the first layer of the conductor 170, a metal oxide that can be used as the oxide 150 is given, for example. In particular, among In--Ga--Zn oxides, the atomic ratio of metals with high conductivity [In]:[Ga]:[Zn]=4:2:3 to 4.1 and values in the vicinity thereof It is preferred to use metal oxides. By using such a metal oxide for the first layer of the conductor 170, the mixture of oxygen from the lower side of the first layer of the conductor 170 to the second and third layers of the conductor 170 is reduced, and oxidation is prevented. can suppress an increase in the electrical resistance values of the second and third layers of the conductor 170 .

In addition, oxygen is added to the insulator 160 and oxygen is supplied to the oxide 150 by forming the above conductive oxide that can be used as the first layer of the conductor 170 by a sputtering method. becomes possible. Accordingly, oxygen vacancies in the channel formation region of the oxide 150 can be reduced.

For the second layer of the conductor 170, for example, metal nitride such as titanium nitride can be used as described above. By using a metal nitride for the second layer of the conductor 170 , an impurity such as nitrogen may be added to the first layer of the conductor 170 to improve the conductivity of the first layer of the conductor 170 . A metal such as tungsten can be used for the third layer of the conductor 170, for example. By using a low-resistivity material such as tungsten, the electrical resistance of the conductor 170 can be lowered.

Further, for example, when the conductor 170 has a two-layer structure, it may have a structure in which a metal nitride such as titanium nitride is stacked as the first layer and a metal such as tungsten is stacked as the second layer.

Although not shown in FIG. 1, an insulator having a function of suppressing permeation of oxygen may be formed between the insulator 175 and the insulator 176 . For example, as the insulator, an insulator such as aluminum oxide may be deposited. With such a structure, entry of oxygen into the conductor 170 from an insulator such as aluminum oxide is reduced, and oxidation of the conductor 170 can be suppressed.

In addition, the conductor 170 functioning as a gate electrode has openings provided in the insulator 175 so as to have regions that partially overlap side surfaces of the conductor 120, the insulator 130, and the conductor 140. 150 and the insulator 160 are embedded (see FIGS. 1A and 1B). When a mask is used for forming the gate electrode, the smaller the size of the gate electrode is, the higher the alignment accuracy of the mask is required. alignment is not required. Therefore, compared with the case of using a mask for gate electrode formation, a fine gate electrode can be formed with high accuracy, and productivity is excellent.

As described above, in the transistor 10, the conductor 120 functions as one of the source electrode and the drain electrode, the conductor 140 functions as the other of the source electrode and the drain electrode, and the oxide A region of 150 overlapping with the insulator 130 functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode. Therefore, in the transistor 10 , the length of the oxide 150 in the region in contact with the insulator 130 sandwiched between the conductor 120 and the conductor 140 (that is, the thickness of the insulator 130 ) is equal to the channel length of the transistor 10 . Equivalent to. With this structure, in the transistor 10, the channel length can be controlled by the film thickness of the insulator 130 when the insulator 130 is formed. can be In addition, since the channel length can be controlled by changing the film thickness of the insulator 130 when the film is formed, there is no need for the accuracy of resist dimensional variation, which is required when the channel length is formed by the lithography method. It is possible to suppress the processing variation between. That is, the transistor 10 according to one embodiment of the present invention is a transistor with a high degree of freedom in design, and a plurality of transistors with small channel lengths can be manufactured with high accuracy within the substrate surface. In addition, since a plurality of transistors with small processing variations can be manufactured within the substrate surface, variations in electrical characteristics between elements can be reduced compared to the case where the channel length is formed by lithography.

In the transistor 10 according to one embodiment of the present invention, the conductor 120 and the conductor 140 functioning as a source electrode or a drain electrode are provided above and below the insulator 130 in addition to the above channel length. It is characterized by A conductor functioning as a source electrode and a conductor functioning as a drain electrode are stacked in a direction perpendicular to the substrate surface as described above with the insulator 130 interposed therebetween. , the area occupied by the conductor functioning as the source electrode or the drain electrode in the substrate plane can be reduced. Thereby, miniaturization of each transistor 10 can be achieved. In addition, since each transistor 10 can be miniaturized, a semiconductor device including the transistor 10 can be highly integrated.

As described above, in the transistor 10 according to one embodiment of the present invention, a “vertical electrode” in which a conductor that serves as one of the source electrode and the drain electrode, an insulator, and a conductor that serves as the other of the source electrode and the drain electrode are sequentially formed. By adopting a "type transistor structure", a plurality of transistors having extremely minute channel lengths can be manufactured with high precision and ease. In addition, a transistor with small variations in electrical characteristics between elements can be manufactured within the substrate surface. Further, miniaturization of the transistor can be achieved. In addition, high integration of a semiconductor device including the transistor can be achieved.

Note that as transistors are miniaturized and the channel length is shortened, Vth in the Vg (gate potential)-Id (drain current) characteristics of the transistor decreases (negatively shifts), and the subthreshold swing value (S value) decreases. Problems such as an increase in off current, a so-called "short channel effect" tend to occur. However, as described above, in the transistor 10 of one embodiment of the present invention, a metal oxide can be used for the oxide 150 having a channel formation region. Therefore, for example, compared with a transistor using Si for a channel formation region, a short channel effect is less likely to occur, and off-current can be significantly reduced. That is, the transistor 10 according to one embodiment of the present invention can have favorable electrical characteristics even when miniaturization is advanced. Details of the metal oxide will be described later in <Constituent Elements of Semiconductor Device>.

The conductor 190 (conductor 195) includes a conductor 120 (conductor 140) functioning as one (the other) of the source electrode and the drain electrode of the transistor 10, and a conductor 185 (conductor 185) functioning as a wiring. 200). A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 190 (the conductor 195). Further, although not shown in FIG. 1, the conductor 190 (the conductor 195) may have a layered structure; A film of titanium, titanium nitride, or the like may be formed in contact with the inner wall of the opening and the top surface (bottom surface) of the conductor 185 (the conductor 200), and the conductive material may be provided inside.

When the conductor 190 (the conductor 195) has a laminated structure, the inner wall of the opening provided in the insulator 110 (the insulator 175, the insulator 176, the insulator 178, and the insulator 180) and the conductor 185 ( As a conductor in contact with the top surface (bottom surface) of the conductor 200), a conductive material having a function of suppressing permeation of impurities such as hydrogen and water is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Further, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. The use of the conductive material prevents impurities such as hydrogen and water from entering the oxide 150 through the conductor 190 (conductor 195) from a layer below (upper layer) the insulator 110 (insulator 180). be able to.

As the conductor 185 (the conductor 200) functioning as a wiring, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. Further, the conductor may have a layered structure, for example, a layered structure of titanium, titanium nitride, and the above conductive material.

The structure examples of the semiconductor device including the transistor 10 according to one embodiment of the present invention have been described above. As described above, in one aspect of the present invention, a plurality of transistors having a channel length of several nanometers or less, which is difficult to fabricate by lithography, can be easily fabricated with high precision within the substrate plane. can be done. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements can be manufactured within the plane of the substrate. Further, according to one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short-channel effect is unlikely to occur while the channel length is short can be manufactured. Further, in one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring and a plug can be manufactured. Further, in one embodiment of the present invention, since the miniaturized transistor can be manufactured, a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield.

<Structure Example 2 of Semiconductor Device>
A structure example of a semiconductor device including the transistor 11 according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device>, will be described below with reference to FIGS.

FIG. 2A is a top view of a semiconductor device having a transistor 11. FIG. FIG. 2(B) is a cross-sectional view of the portion indicated by the dashed-dotted line B1-B2 in FIG. 2(A). FIG. 2(C) is a cross-sectional view of the portion indicated by the dashed-dotted line B3-B4 in FIG. 2(A). Here, the portion indicated by the dashed-dotted line of B1-B2 and the portion indicated by the dashed-dotted line of B3-B4 are orthogonal to each other. In the top view of FIG. 2A, some elements are omitted for clarity of illustration.

In the semiconductor device shown in FIG. 2, structures having the same functions as those constituting the semiconductor device shown in <Structure Example 1 of Semiconductor Device> are denoted by the same reference numerals. Further, in the following, the portions different from the semiconductor device described in <Structure Example 1 of Semiconductor Device> are mainly described, and the contents described in <Structure Example 1 of Semiconductor Device> are referred to for other portions. It shall be possible.

As shown in FIGS. 2A and 2B, the semiconductor device shown in FIGS. 2A and 2B has a conductor functioning as a source electrode or a drain electrode, and functions as a plug that connects the conductor to upper and lower wirings. The semiconductor device described in <Structure Example 1 of Semiconductor Device> is provided in that the conductors and the like have the transistors 11 facing each other with the oxide 150, the insulator 160, and the conductor 170 interposed therebetween. (see Figure 1).

A semiconductor device of one embodiment of the present invention includes a transistor 11 and insulators 100, 102, 105, 110, 175, and 175 which function as interlayer films over a substrate (not shown). 176 , an insulator 178 and an insulator 180 . In addition, conductors 185_1, 185_2, 200_1, and 200_2 which are electrically connected to the transistor 11 and function as wirings, and conductors 190_1, 190_2, 195_1 and 195_1 which function as plugs. It has a conductor 195_2. Here, the conductor 185_1 and the conductor 185_2, the conductor 190_1 and the conductor 190_2, the conductor 195_1 and the conductor 195_2, and the conductor 200_1 and the conductor 200_2 are all the oxide 150, the insulator 160, and the conductor They are provided facing each other across the 170 (see FIG. 2(B)).

A conductor 185_1 (a conductor 185_2) is formed in an opening provided in the insulator 105 . Here, the height of the top surface of the conductor 185_1 (the conductor 185_2) and the height of the top surface of the insulator 105 are preferably approximately the same. Note that although the conductor 185_1 (the conductor 185_2) has a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 185_1 (conductor 185_2) may have a stacked structure of two or more layers.

A conductor 190_1 (a conductor 190_2) is formed in an opening provided in the insulator 110 . The bottom surface of the conductor 190_1 (the conductor 190_2) is provided so as to have a region in contact with the top surface of the conductor 185_1 (the conductor 185_2). Here, the height of the top surface of the conductor 190_1 (the conductor 190_2) and the height of the top surface of the insulator 110 are preferably approximately the same. Note that although the conductor 190_1 (the conductor 190_2) has a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 190_1 (the conductor 190_2) is in contact with the inner wall of the opening provided in the insulator 110 and is formed using a material that suppresses permeation of impurities such as hydrogen and water, and oxygen. A laminated structure of two or more layers in which a conductor made of a material having higher conductivity than that of the conductor is formed on the conductor may be used.

The conductor 195_1 (conductor 195_2) is formed in an opening reaching the upper surface of the conductor 140_1 (conductor 140_2) provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180. Here, the height of the top surface of the conductor 195_1 (the conductor 195_2) and the height of the top surface of the insulator 180 are preferably approximately the same. Note that although the conductor 195_1 (the conductor 195_2) has a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. , the insulator 175, the insulator 176, the insulator 178, and the insulator 180, a conductor is formed using a material that suppresses permeation of impurities such as hydrogen and water, and oxygen. Alternatively, a laminated structure of two or more layers in which a conductor made of a material having a higher conductivity than that of the conductor is formed on the conductor may be used.

The conductor 200_1 (conductor 200_2) is formed over the insulator 180 so as to have a region in contact with the top surface of the conductor 195_1 (conductor 195_2). Note that although the conductor 200_1 (the conductor 200_2) has a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 200_1 (the conductor 200_2) may have a stacked structure of two or more layers.

[Transistor 11]
As illustrated in FIG. 2B, the transistor 11 includes a conductor 120_1, a conductor 120_2, and an oxide 150 over the insulator 110, and an insulator 130_1 over the conductor 120_1. , an insulator 130_2 overlying the conductor 120_2, a conductor 140_1 overlying the insulator 130_1, a conductor 140_2 overlying the insulator 130_2, and overlying the oxide 150. and a conductor 170 disposed on the insulator 160 . Here, the conductor 120_1, the insulator 130_1, and the conductor 140_1 face the conductor 120_2, the insulator 130_2, and the conductor 140_2 with the oxide 150, the insulator 160, and the conductor 170 interposed therebetween. and is provided. In addition, the oxide 150 is provided so as to have regions in contact with side surfaces of the conductor 120_1, the insulator 130_1, and the conductor 140_1, and the conductor 120_2, the insulator 130_2, and the conductor 140_2, which face each other. In addition, the insulator 160 has regions facing side surfaces of the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2) with the oxide 150 interposed therebetween. be provided. In addition, regions of the conductor 170 face side surfaces of the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2) with the oxide 150 and the insulator 160 interposed therebetween. is provided to have

As shown in FIGS. 2B and 2C, a conductor 120_1, a conductor 120_2, an insulator 130_1, an insulator 130_2, a conductor 140_1, and a conductor 140_2 are covered with a An insulator 175 is provided. The insulator 175 is provided with openings in which side surfaces of the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2) partially overlap with the inner walls. An oxide 150 is provided along the inner wall, an insulator 160 is provided over the oxide 150, and a conductor 170 is provided over the insulator 160 to fill the opening. Here, as shown in FIG. 2B, the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175. FIG. Note that although the oxide 150 has a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited thereto. For example, oxide 150 may have a stacked structure of two or more layers.

In the transistor 11, the conductor 120_1 functions as one of the source and drain electrodes, the conductor 140_1 functions as the other of the source and drain electrodes, and the insulator 130_1 of the oxide 150 The overlapping region functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode. Similarly, in transistor 11, conductor 120_2 functions as one of the source and drain electrodes, conductor 140_2 functions as the other of the source and drain electrodes, and oxide 150 is an insulator. A region overlapping with the body 130_2 functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode.

That is, the transistor 11 has one gate electrode (the conductor 170), one gate insulator (the insulator 160), and two pairs of source or drain electrodes (the conductors 120_1 and 140_1, the conductors 120_2 and It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region of the oxide 150 overlapping with the insulator 130_1 and a region of the oxide 150 overlapping with the insulator 130_2). Alternatively, the transistor 11 includes the conductor 170 functioning as a gate electrode, the insulator 160 functioning as a gate insulator, the conductors 120_1 and 140_1 functioning as source or drain electrodes, A transistor including an oxide 150 functioning as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 functioning as a gate electrode, an insulator 160 functioning as a gate insulator, A transistor including a conductor 120_2 and a conductor 140_2 functioning as a source electrode or a drain electrode and an oxide 150 functioning as a channel formation region (a region overlapping with the insulator 130_2). I can say.

When the transistor 11 has the above structure, the transistor 11 can output a larger drain current than the transistor 10 (see FIG. 1) included in the semiconductor device shown in <Structure Example 1 of Semiconductor Device>. For example, the conductor 120_1 and the conductor 120_2 which function as one of the source electrode and the drain electrode of the transistor 11 are electrically connected through the conductor 190_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2. and the conductor 140_1 and the conductor 140_2 functioning as the other of the source electrode and the drain electrode are electrically connected through the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2. think. In this case, by applying a potential at which the transistor 11 is turned on to the conductor 170 functioning as a gate electrode, the transistor 11 has the same potential as that of the transistor 10 when the same potential is applied to the conductor 170 . A double drain current can be output. Since the transistor 11 has the electrical connection configuration as described above, the transistor 11 occupies a smaller area than the case where the two transistors 10 are simply arranged side by side, and is equivalent to the case where the two transistors 10 are arranged side by side. Current output capability can be obtained.

Alternatively, the conductors 185_1 and 185_2 and the conductors 200_1 and 200_2 may not be electrically connected, and the two transistors included in the transistor 11 may be controlled independently. That is, the transistor 11 includes the conductor 170 functioning as a gate electrode, the insulator 160 functioning as a gate insulator, the conductors 120_1 and 140_1 functioning as source or drain electrodes, A transistor including an oxide 150 functioning as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 functioning as a gate electrode, an insulator 160 functioning as a gate insulator, A transistor including a conductor 120_2 and a conductor 140_2 functioning as a source electrode or a drain electrode and an oxide 150 functioning as a channel formation region (a region overlapping with the insulator 130_2) is independently controlled. It is good also as a structure which carries out.

Note that in the transistor 11, the same material as the conductor 185 of the transistor 10 can be used for the conductor 185_1 (the conductor 185_2). The same material as the conductor 190 of the transistor 10 can be used for the conductor 190_1 (the conductor 190_2). The same material as the conductor 120 of the transistor 10 can be used for the conductor 120_1 (the conductor 120_2). The same material as the insulator 130 of the transistor 10 can be used for the insulator 130_1 (the insulator 130_2). The same material as the conductor 140 of the transistor 10 can be used for the conductor 140_1 (the conductor 140_2). The same material as the conductor 195 of the transistor 10 can be used for the conductor 195_1 (the conductor 195_2). The same material as the conductor 200 of the transistor 10 can be used for the conductor 200_1 (the conductor 200_2).

For the structure and effects of the semiconductor device including the transistor 11 other than those described above, the structure and effects of the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device> can be referred to.

The above has described a configuration example of the semiconductor device including the transistor 11 according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device>. As described above, in one aspect of the present invention, a plurality of transistors having a channel length of several nanometers or less, which is difficult to fabricate by lithography, can be easily fabricated with high precision within the substrate plane. can be done. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements can be manufactured within the plane of the substrate. Further, according to one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short-channel effect is unlikely to occur while the channel length is short can be manufactured. Further, in one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring and a plug can be manufactured. Further, in one embodiment of the present invention, a transistor with a large on-state current can be manufactured even though it is miniaturized. Further, in one embodiment of the present invention, since the miniaturized transistor can be manufactured, a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield.

<Structure Example 3 of Semiconductor Device>
A semiconductor device according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 described in <Structure Example 1 of a semiconductor device> and the semiconductor device including the transistor 11 described in <Structure Example 2 of a semiconductor device>, will be described below. A structural example of a semiconductor device including the transistor 12 is described with reference to FIG.

FIG. 3A is a top view of a semiconductor device having a transistor 12. FIG. FIG. 3B is a cross-sectional view of the portion indicated by the dashed-dotted line C1-C2 in FIG. 3A. FIG. 3(C) is a cross-sectional view of the portion indicated by the dashed-dotted line C3-C4 in FIG. 3(A). Here, the portion of C1-C2 indicated by the one-dot chain line and the portion of C3-C4 indicated by the one-dot chain line are orthogonal to each other. In the top view of FIG. 3A, some elements are omitted for clarity of illustration.

In the semiconductor device shown in FIG. 3, structures having the same functions as structures constituting the semiconductor device shown in <Structure Example 1 of Semiconductor Device> or <Structure Example 2 of Semiconductor Device> are denoted by the same reference numerals. ing. Further, in the following description, portions different from the semiconductor device described in <Configuration example 1 of the semiconductor device> or <Configuration example 2 of the semiconductor device> are mainly described, and the other portions are described in <Configuration of the semiconductor device>. Example 1> or <Structure Example 2 of Semiconductor Device> can be referred to.

As shown in FIGS. 3A and 3B, the semiconductor device shown in FIG. 3 has a conductor functioning as a source electrode or a drain electrode, and functions as a plug connecting the conductor and upper and lower wirings. The semiconductor device shown in <Configuration example 1 of semiconductor device> (see FIG. 1) is characterized in that the conductor or the like has the transistors 12 provided facing each other with the insulator 160 and the conductor 170 interposed therebetween. ) is different. In addition, the oxide 150 is provided only in regions facing the side surfaces of the conductor 170 with the insulator 160 interposed therebetween (the oxide 150_1 and the oxide 150_2), and is provided in regions overlapping with the bottom surface of the conductor 170 . It is different from the semiconductor device shown in <Structure Example 2 of Semiconductor Device> (see FIG. 2) in that the semiconductor device is not shown.

A semiconductor device of one embodiment of the present invention includes a transistor 12 and insulators 100, 102, 105, 110, 175, and 175 which function as interlayer films over a substrate (not shown). 176 , an insulator 178 and an insulator 180 . In addition, conductors 185_1, 185_2, 200_1, and 200_2 which are electrically connected to the transistor 12 and function as wirings, and conductors 190_1, 190_2, 195_1 and 195_1 which function as plugs. It has a conductor 195_2. Here, the conductor 185_1, the conductor 190_1, the conductor 195_1, and the conductor 200_1, and the conductor 185_2, the conductor 190_2, the conductor 195_2, and the conductor 200_2 are all the insulator 160 and the conductor 170. They are provided so as to sandwich and face each other (see FIG. 3(B)).

Note that in the semiconductor device illustrated in FIG. 3, the structure can be applied to the conductor 185_1 (the conductor 185_2), the conductor 190_1 (the conductor 190_2), the conductor 195_1 (the conductor 195_2), and the conductor 200_1 (the conductor 200_2). For the above, the contents described in <Structure Example 2 of Semiconductor Device> can be referred to.

[Transistor 12]
As illustrated in FIG. 3B, the transistor 12 includes a conductor 120_1, a conductor 120_2, an oxide 150_1, an oxide 150_2, and an insulator 160 which are provided over the insulator 110 and the conductor 120_1. an insulator 130_1 arranged on the conductor 120_2, an insulator 130_2 arranged on the conductor 120_2, a conductor 140_1 arranged on the insulator 130_1, and a conductor 140_2 arranged on the insulator 130_2. , and a conductor 170 disposed over the insulator 160 . Here, the conductor 120_1 and the conductor 120_2, the insulator 130_1 and the insulator 130_2, the conductor 140_1 and the conductor 140_2, and the oxide 150_1 and the oxide 150_2 face each other with the insulator 160 and the conductor 170 interposed therebetween. and is provided. In addition, the oxide 150_1 (the oxide 150_2) is the conductor 120_2 (the conductor 120_1) of the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2). It is provided so as to have a region in contact with a side surface facing the insulator 130_2 (insulator 130_1) and the conductor 140_2 (conductor 140_1). In addition, the insulator 160 faces side surfaces of the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2) with the oxide 150_1 (the oxide 150_2) interposed therebetween. provided to have an area. In addition, the conductor 170 includes the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2) with the oxide 150_1 (the oxide 150_2) and the insulator 160 interposed therebetween. is provided so as to have a region facing the side of the

As shown in FIGS. 3B and 3C, a conductor 120_1, a conductor 120_2, an insulator 130_1, an insulator 130_2, a conductor 140_1, and a conductor 140_2 are covered with a An insulator 175 is provided. The insulator 175 is provided with openings in which side surfaces of the conductor 120_1 (the conductor 120_2), the insulator 130_1 (the insulator 130_2), and the conductor 140_1 (the conductor 140_2) partially overlap with the inner walls. Oxide 150_1 and oxide 150_2 are provided along the inner wall (side) to cover the facing sides of oxide 150_1 and oxide 150_2 and the top surface of insulator 110 between oxide 150_1 and oxide 150_2. An insulator 160 is provided as above, and a conductor 170 is provided over the insulator 160 so as to fill the opening. Here, as shown in FIG. 3B, the top surfaces of the oxide 150_1, the oxide 150_2, the insulator 160, and the conductor 170 are approximately the same height as the top surface of the insulator 175. is preferred. Note that although the oxide 150_1 (the oxide 150_2) has a single-layer structure in FIG. 3B, one embodiment of the present invention is not limited to this. For example, the oxide 150_1 (oxide 150_2) may have a stacked structure of two or more layers.

In the transistor 12, the conductor 120_1 functions as one of the source electrode and the drain electrode, the conductor 140_1 functions as the other of the source electrode and the drain electrode, and the insulator 130_1 of the oxide 150_1. The overlapping region functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode. Similarly, in transistor 12, conductor 120_2 functions as one of the source or drain electrodes, conductor 140_2 functions as the other of the source or drain electrodes, and the insulating oxide 150_2. A region overlapping with the body 130_2 functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode.

That is, the transistor 12 has one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductors 120_1 and 140_1, conductors 120_2 and It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region of the oxide 150_1 overlapping with the insulator 130_1 and a region of the oxide 150_2 overlapping with the insulator 130_2). Alternatively, the transistor 12 includes the conductor 170 functioning as a gate electrode, the insulator 160 functioning as a gate insulator, the conductors 120_1 and 140_1 functioning as source or drain electrodes, A transistor including an oxide 150_1 functioning as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 functioning as a gate electrode, an insulator 160 functioning as a gate insulator, A transistor including a conductor 120_2 and a conductor 140_2 functioning as a source electrode or a drain electrode and an oxide 150_2 functioning as a channel formation region (a region overlapping with the insulator 130_2). I can say.

When the transistor 12 has the above structure, the transistor 12 can output a larger drain current than the transistor 10 (see FIG. 1) included in the semiconductor device shown in <Structure Example 1 of Semiconductor Device>. For example, the conductor 120_1 and the conductor 120_2 which function as one of the source electrode and the drain electrode of the transistor 12 are electrically connected through the conductor 190_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2. and the conductor 140_1 and the conductor 140_2 functioning as the other of the source electrode and the drain electrode are electrically connected through the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2. think. In this case, by applying a potential at which the transistor 12 is turned on to the conductor 170 functioning as a gate electrode, the transistor 12 has the same potential as that of the transistor 10 when the same potential is applied to the conductor 170. A double drain current can be output. Since the transistor 12 has the electrical connection configuration as described above, the transistor 12 occupies a smaller area than the case where the two transistors 10 are simply arranged side by side, and is equivalent to the case where the two transistors 10 are arranged side by side. Current output capability can be obtained.

Alternatively, the conductors 185_1 and 185_2 and the conductors 200_1 and 200_2 may not be electrically connected, and the two transistors included in the transistor 12 may be controlled independently. That is, the transistor 12 includes the conductor 170 functioning as a gate electrode, the insulator 160 functioning as a gate insulator, the conductors 120_1 and 140_1 functioning as source or drain electrodes, A transistor including an oxide 150_1 functioning as a channel formation region (a region overlapping with the insulator 130_1), a conductor 170 functioning as a gate electrode, an insulator 160 functioning as a gate insulator, A transistor including a conductor 120_2 and a conductor 140_2 functioning as a source electrode or a drain electrode and an oxide 150_2 functioning as a channel formation region (a region overlapping with the insulator 130_2) is independently controlled. It is good also as a structure which carries out.

Here, the transistor 12 included in the semiconductor device illustrated in FIG. 3 has a different shape of oxide having a channel formation region than the transistor 11 included in the semiconductor device illustrated in FIG. Specifically, the transistor 11 includes side surfaces facing each other of the conductor 120_1, the insulator 130_1, and the conductor 140_1, the conductor 120_2, the insulator 130_2, and the conductor 140_2, and part of the top surface of the insulator 110. , and oxide 150 on the sides of conductors 120_1, 130_1, and 140_1 opposite conductors 120_2, 130_2, and 140_2, whereas transistor 12 has oxide 150 on the sides of conductors 120_1, 130_1, and 140_1 opposite conductors 120_2, 130_2, and 140_2. and an oxide 150_2 in contact with the side surfaces of the conductor 120_2, the insulator 130_2, and the conductor 140_2, which face the conductor 120_1, the insulator 130_1, and the conductor 140_1. That is, in the transistor 12, the oxide having the channel formation region is divided into two (the oxide 150_1 and the oxide 150_2) with the insulator 160 and the conductor 170 interposed therebetween. different from An oxide having a channel forming region has conductivity. Therefore, for example, when the two transistors forming the transistor 12 described above are controlled independently, it is possible to suppress the occurrence of leakage through the oxide between the two transistors. As a result, the operation (ON operation, OFF operation) of one transistor constituting the transistor 12 is less likely to affect the other transistor, and the operation of each transistor can be reliably controlled.

Note that in the transistor 12, the same material as the oxide 150 of the transistor 10 can be used for the oxide 150_1 (the oxide 150_2). The same material as the conductor 185 of the transistor 10 can be used for the conductor 185_1 (the conductor 185_2). The same material as the conductor 190 of the transistor 10 can be used for the conductor 190_1 (the conductor 190_2). The same material as the conductor 120 of the transistor 10 can be used for the conductor 120_1 (the conductor 120_2). The same material as the insulator 130 of the transistor 10 can be used for the insulator 130_1 (the insulator 130_2). The same material as the conductor 140 of the transistor 10 can be used for the conductor 140_1 (the conductor 140_2). The same material as the conductor 195 of the transistor 10 can be used for the conductor 195_1 (the conductor 195_2). The same material as the conductor 200 of the transistor 10 can be used for the conductor 200_1 (the conductor 200_2).

Structures and effects of the semiconductor device including the transistor 12 other than those described above are described in the semiconductor device including the transistor 10 described in <Structure Example 1 of the semiconductor device> or in <Structure Example 2 of the semiconductor device>. The structure and effect of the semiconductor device including the transistor 11 can be taken into consideration.

The above description relates to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 described in <Structure Example 1 of a semiconductor device> or the semiconductor device including the transistor 11 described in <Structure Example 2 of a semiconductor device>. The configuration example of the semiconductor device having the transistor 12 has been described. As described above, in one aspect of the present invention, a plurality of transistors having a channel length of several nanometers or less, which is difficult to fabricate by lithography, can be easily fabricated with high precision within the substrate surface. can be done. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements can be manufactured within the plane of the substrate. Further, according to one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short-channel effect is unlikely to occur while the channel length is short can be manufactured. Further, in one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring and a plug can be manufactured. Further, in one embodiment of the present invention, a transistor with a large on-state current can be manufactured even though it is miniaturized. Further, in one embodiment of the present invention, since the miniaturized transistor can be manufactured, a semiconductor device including the transistor can be highly integrated. In one embodiment of the present invention, a highly integrated semiconductor device with small leakage between adjacent transistors can be manufactured. Further, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield.

<Modified Example of Semiconductor Device>
As a modification example of the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device>, a semiconductor device including the transistor 13 according to one embodiment of the present invention will be described below with reference to FIGS.

FIG. 4A is a top view of a semiconductor device having a transistor 13. FIG. FIG. 4B is a cross-sectional view of the portion indicated by the dashed-dotted line D1-D2 in FIG. 4A. FIG. 4(C) is a cross-sectional view of the portion indicated by the dashed-dotted line D3-D4 in FIG. 4(A). Here, the portion of D1-D2 indicated by the one-dot chain line and the portion of D3-D4 indicated by the one-dot chain line are orthogonal to each other. In the top view of FIG. 4A, some elements are omitted for clarity of illustration.

In the semiconductor device shown in FIG. 4, structures having the same functions as the structures constituting the semiconductor devices shown in <Structure Example 1 of Semiconductor Device> to <Structure Example 3 of Semiconductor Device> are denoted by the same reference numerals. ing. Further, in the following description, portions different from the semiconductor devices described in <Structure Example 1 of Semiconductor Device> to <Structure Example 3 of Semiconductor Device> are mainly described, and other portions are described in <Structure of Semiconductor Device>. The contents described in Example 1> to <Structure Example 3 of Semiconductor Device> can be referred to.

4B and 4C, in the semiconductor device shown in FIG. 4, a conductor 171 functioning as a gate electrode has oxide 151 functioning as a channel formation region and The transistor 13 has regions that overlap not only the side surfaces of the conductors 120 , 130 , and 140 but also part of the top surface of the conductor 140 with the functioning insulator 161 interposed therebetween. This is different from the semiconductor device shown in <Structure Example 1 of Semiconductor Device> (see FIG. 1).

A semiconductor device of one embodiment of the present invention includes a transistor 13 and insulators 100, 102, 105, 110, 175, and 175 which function as interlayer films over a substrate (not shown). 176 , an insulator 178 and an insulator 180 . It is also electrically connected to the transistor 13 and has conductors 185 and 200 functioning as wirings and conductors 190 and 195 functioning as plugs.

Note that the description in <Structure Example 1 of Semiconductor Device> can be referred to for structures that can be applied to the conductor 185, the conductor 190, the conductor 195, and the conductor 200 in the semiconductor device illustrated in FIG. can.

[Transistor 13]
As illustrated in FIG. 4B, the transistor 13 includes the conductor 120 and the oxide 151 over the insulator 110, the insulator 130 over the conductor 120, and the insulator 130. It has a conductor 140 overlying it, an insulator 161 overlying the oxide 151 , and a conductor 171 overlying the insulator 161 . Here, the oxide 151 is provided so as to have regions in contact with side surfaces of the conductor 120 , the insulator 130 , and the conductor 140 and part of the top surface of the conductor 140 . The insulator 161 is provided so as to have a region that overlaps with side surfaces of the conductors 120 , 130 , and 140 and part of the top surface of the conductor 140 with the oxide 151 interposed therebetween. In addition, the conductor 171 has a region which overlaps with the side surfaces of the conductors 120, 130, and 140 and part of the top surface of the conductor 140 with the oxide 151 and the insulator 161 interposed therebetween. provided in

As shown in FIG. 4B, an insulator 175 is provided over the conductor 120, the insulator 130, and the conductor 140 so as to cover them. The insulator 175 is provided with openings whose inner walls partially overlap side surfaces of the conductors 120, 130, and 140 and part of the upper surface of the conductor 140. An oxide 151 is provided over the oxide 151, an insulator 161 is provided over the oxide 151, and a conductor 171 is provided over the insulator 161 so as to fill the opening. Here, as shown in FIG. 4B, the heights of the top surfaces of the oxide 151, the insulator 161, and the conductor 171 are preferably approximately the same as the top surface of the insulator 175. FIG. Note that although the oxide 151 has a single-layer structure in FIG. 4B, one embodiment of the present invention is not limited to this. For example, the oxide 151 may have a stacked structure of two or more layers.

In the transistor 13 , the conductor 120 functions as one of the source and drain electrodes, the conductor 140 functions as the other of the source and drain electrodes, and the insulator 130 of the oxide 151 . The overlapping region functions as a channel formation region, the insulator 161 functions as a gate insulator, and the conductor 171 functions as a gate electrode.

Here, the transistor 10 has only one contact surface between the oxide 150 and the insulator 130 shown in FIG. There is a difference in that there are a total of three locations, one location shown in FIG. 4B and two locations shown in FIG. 4C. That is, the transistor 10 and the transistor 13 each have a different area of a region that can function as a channel formation region in their oxides (the oxide 150 or the oxide 151) (the transistor 13 is larger than the transistor 10). , the area of oxide that can function as a channel-forming region is large.). Therefore, the transistor 13 can output a larger drain current than the transistor 10 while having an element size similar to that of the transistor 10 .

Further, the transistor 13 is different from the transistor 10 in that the conductor 171 functioning as a gate electrode has a region that overlaps with part of the top surface of the conductor 140 . With the transistor 13 having this structure, a channel formation region (a region of the oxide 151 overlapping with the insulator 130) can be surrounded by the conductor 171 as shown in FIG. 4C. Therefore, compared with the transistor 10, the transistor 13 can improve the controllability of applying the gate electric field to the channel formation region more reliably. Therefore, the transistor 13 can reliably control carriers during operation (ON operation, OFF operation), and can realize both a larger ON current and a smaller OFF current than the transistor 10 .

Note that the same material as the oxide 150 of the transistor 10 can be used for the oxide 151 in the transistor 13 . Further, the same material as the insulator 160 of the transistor 10 can be used for the insulator 161 . Further, the same material as the conductor 170 of the transistor 10 can be used for the conductor 171 .

In the semiconductor device including the transistor 13, configurations and effects other than those described above are described in the semiconductor device including the transistor 10 described in <Structure Example 1 of the semiconductor device> and in <Structure Example 2 of the semiconductor device>. The structure and effects of the semiconductor device including the transistor 11 or the semiconductor device including the transistor 12 described in <Structure Example 3 of Semiconductor Device> can be referred to.

As a modification example of the semiconductor device including the transistor 10 described in <Structure Example 1 of Semiconductor Device>, the configuration example of the semiconductor device including the transistor 13 according to one embodiment of the present invention has been described above. As described above, in one aspect of the present invention, a plurality of transistors having a channel length of several nanometers or less, which is difficult to fabricate by lithography, can be easily fabricated with high precision within the substrate surface. can be done. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements can be manufactured within the plane of the substrate. Further, in one embodiment of the present invention, a transistor with high on-state current can be manufactured. Further, in one embodiment of the present invention, a transistor with low off-state current can be manufactured. Further, according to one embodiment of the present invention, a transistor having favorable electrical characteristics in which a short-channel effect is unlikely to occur while the channel length is short can be manufactured. Further, in one embodiment of the present invention, a transistor with a small element size including not only a channel length but also a wiring and a plug can be manufactured. In addition, in one embodiment of the present invention, since the miniaturized transistor can be manufactured, a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield.

An example of the semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device including the transistor 10, the transistor 11, the transistor 12, or the transistor 13 (see FIGS. 1 to 4). A semiconductor device according to one embodiment of the present invention can be used by appropriately combining the structures of the semiconductor devices described above.

<Constituent Elements of Semiconductor Device>
Components that can be applied to a semiconductor device (see FIGS. 1 to 4) including the transistor 10, the transistor 11, the transistor 12, or the transistor 13 according to one embodiment of the present invention are described below in detail.

〔substrate〕
As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate including a metal nitride, a substrate including a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, those substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.

Alternatively, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is also a method in which a transistor is manufactured over a non-flexible substrate, separated, and transferred to a flexible substrate. In that case, a peeling layer is preferably provided between the non-flexible substrate and the transistor. As the substrate, a sheet, film, foil, or the like in which fibers are woven may be used. Also, the substrate may have stretchability. The substrate may also have the property of returning to its original shape when bending or pulling is ceased. Alternatively, it may have the property of not returning to its original shape. The substrate has a region with a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of a semiconductor device having a transistor can be reduced. In addition, by making the substrate thin, even when glass or the like is used, it may have stretchability, or may have the property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to mitigate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, a durable semiconductor device can be provided.

As a substrate that is a flexible substrate, for example, metal, alloy, resin, glass, or fibers thereof can be used. A flexible substrate preferably has a lower coefficient of linear expansion because deformation due to the environment is suppressed. As the flexible substrate, for example, a material having a coefficient of linear expansion of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. . Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. In particular, aramid has a low coefficient of linear expansion, so it is suitable as a flexible substrate.

〔Insulator〕
As insulators, there are insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

Examples of the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1 and the insulator 130_2), and the insulator 160 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, Insulators containing silicon, phosphorous, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks. For example, the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1 and the insulator 130_2), and the insulator 160 can include silicon oxide, silicon oxynitride, or silicon nitride. preferable.

The concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulators 105, 110, and 130 (or the insulators 130_1 and 130_2) is preferably low. For example, the amount of desorption of hydrogen from the insulators 105, 110, and 130 (or the insulators 130_1 and 130_2) is determined by thermal desorption spectroscopy (TDS) as follows: When the surface temperature of the film is in the range of 50° C. to 500° C., the amount of desorption in terms of hydrogen molecules per area of the insulator 105, the insulator 110, or the insulator 130 (or the insulator 130_1 or the insulator 130_2). converted to 2×10 ¹⁵ molecules/cm ² or less, preferably 1×10 ¹⁵ molecules/cm ² or less, more preferably 5×10 ¹⁴ molecules/cm ² or less. The insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) are preferably formed using an insulator from which oxygen is released by heating. By using the insulator for the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2), the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1) , and the insulator 130_2) can effectively supply oxygen to the oxide 150 (or the oxide 150_1 and the oxide 150_2).

Moreover, the insulator 160 preferably has an insulator with a high dielectric constant. For example, the insulator 160 can be gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, oxides with aluminum and hafnium, oxynitrides with aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium. It is preferred to have a nitride, or a nitride with silicon and hafnium, or the like. Alternatively, the insulator 160 preferably has a stacked-layer structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with an insulator with a high dielectric constant, it is possible to form a laminated structure with few defects and a thermally stable and high dielectric constant. .

The insulator 160 is preferably placed in contact with the top surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2). The insulator 160 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 160 in contact with the top surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2), oxygen can be effectively supplied to the oxide 150 (or the oxide 150_1 or the oxide 150_2). can supply. Further, similarly to the insulators 105, 110, and 130 (or the insulators 130_1 and 130_2), the concentration of impurities such as water or hydrogen in the insulator 160 is preferably low. . The thickness of the insulator 160 is preferably 1 nm or more and 20 nm or less, for example, about 1 nm.

The insulator 160 preferably contains oxygen. For example, in temperature-programmed desorption spectroscopy (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 160 is measured in a surface temperature range of 100° C. to 700° C. or 100° C. to 500° C. converted to 1×10 ¹⁴ molecules/cm ² or more, preferably 2×10 ¹⁴ molecules/cm ² or more, more preferably 4×10 ¹⁴ molecules/cm ² or more.

The insulator 175, the insulator 176, and the insulator 180 preferably have a low dielectric constant. For example, insulator 175, insulator 176, and insulator 180 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon doped with carbon and nitrogen. It is preferable to use silicon oxide, silicon oxide having pores, resin, or the like. Alternatively, the insulator 175, the insulator 176, and the insulator 180 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, or carbon and nitrogen are added. It preferably has a layered structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. Note that the insulators 175, 176, and 180 are similar to the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1 and the insulator 130_2), the insulator 160, and the like. It is preferable that the concentration of impurities such as water or hydrogen is reduced.

For the insulator 102 and the insulator 178, insulators with high barrier properties against impurities such as hydrogen and water, and oxygen are preferably used. By using the insulator for the insulator 102 and the insulator 178, hydrogen or water is introduced into the transistor 10, the transistor 11, the transistor 12, or the transistor 13 from the lower side (upper side) of the insulator 102 (the insulator 178). It is possible to suppress the contamination of impurities such as In addition, diffusion of oxygen in the transistor 10, the transistor 11, the transistor 12, or the transistor 13 to the lower side (upper side) of the insulator 102 (the insulator 178) can be suppressed. The insulator includes, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. is preferably used in a single layer or laminate.

Further, for example, the insulator includes metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or Silicon nitride or the like may be used. Note that the insulator preferably contains aluminum oxide, hafnium oxide, or the like.

〔conductor〕
Conductor 120 (or conductor 120_1, conductor 120_2), conductor 140 (or conductor 140_1, conductor 140_2), conductor 185 (or conductor 185_1, conductor 185_2), conductor 190 (or , conductor 190_1, conductor 190_2), conductor 195 (or conductor 195_1, conductor 195_2), conductor 200 (or conductor 200_1, conductor 200_2), and conductor 170 include aluminum and chromium. , copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Alternatively, as the conductor, particularly the conductor 170, a conductive material containing oxygen and a metal element contained in a metal oxide that can be applied to the oxide 150 (or the oxides 150_1 and 150_2) may be used. good. Alternatively, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the oxide 150 (or the oxide 150_1 and the oxide 150_2) can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed from an outer insulator or the like.

Alternatively, a plurality of conductive layers formed using any of the above materials may be stacked and used. For example, a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used. Alternatively, a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined. Alternatively, a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.

Note that in the case where oxide is used for the channel formation region of the transistor, the gate electrode preferably has a stacked-layer structure in which the material containing the metal element and the conductive material containing oxygen are combined. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

Note that the conductor 185 (or the conductor 185_1 and the conductor 185_2), the conductor 190 (or the conductor 190_1 and the conductor 190_2), the conductor 195 (or the conductor 195_1 and the conductor 195_2), and the conductor For the material 200 (or the conductors 200_1 and 200_2), a highly embeddable conductive material such as tungsten or polysilicon may be used. Alternatively, a conductive material with high embeddability and a conductive barrier film such as titanium, titanium nitride, or tantalum nitride may be used in combination.

[Oxide]
A metal oxide is preferably used as the oxide 150 (or the oxide 150_1 or the oxide 150_2). However, instead of the oxide 150, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used as a semiconductor material. Sometimes it doesn't matter. A metal oxide that is preferably used for the oxide 150 (or the oxide 150_1 or the oxide 150_2) according to one embodiment of the present invention is described below.

The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Consider the case where the metal oxide is InMZnO with indium, element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other applicable elements for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above elements may be combined.

By using the above metal oxide for a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Moreover, a transistor with favorable reliability can be realized.

Since a transistor including a channel formation region using a metal oxide has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. In addition, since a metal oxide can be deposited by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.

A metal oxide with a low carrier density is preferably used for a channel formation region of a transistor. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film should be lowered to lower the defect level density. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the metal oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and a carrier density of 1×10 ⁻⁹ /cm 3 . cm ³ or more.

In addition, since a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low defect level density, the trap level density may also be low.

In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in a metal oxide with a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. Moreover, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

Here, the effect of each impurity in the metal oxide will be described.

If the metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2. ×10 ¹⁸ atoms/cm ³ or less, preferably 2 × 10 ¹⁷ atoms/cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, the metal may form a defect level in the metal oxide and generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

In addition, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to be n-type. As a result, a transistor using a metal oxide containing nitrogen for a channel formation region tends to have normally-on characteristics. Therefore, nitrogen is preferably reduced as much as possible in the metal oxide. For example, the nitrogen concentration in the metal oxide is less than 5×10 ¹⁹ atoms/cm ³ in SIMS, preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further preferably 1×10 18 atoms/cm 3 or less. It is preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, are generated in some cases. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm Less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

The CAC-OS will be described in detail below. CAC-OS is an example of a function or a material structure that a metal oxide of a transistor according to one embodiment of the present invention can have.

A CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The mixed state is also called a mosaic shape or a patch shape.

For example, CAC-OS in In—Ga—Zn oxide (In—Ga—Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is indium oxide (hereinafter, InO _{and gallium _ _} oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0); ) and the like, and the material is separated into a mosaic shape, and the mosaic InO _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter also referred to as a cloud shape). be.

In other words, CAC-OS is a composite metal oxide having a structure in which a region containing GaO 2 _X3 as a main component and a region containing In _{2 X2} Zn _Y2 O _Z2 or InO 2 _X1 as a main component are mixed. In this specification, for example, the first region means that the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region. Assume that the concentration of In is higher than that of the region No. 2.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1−x0) O ₃ (ZnO) _m0 (−1≦x0≦1, m0 is an arbitrary number). Crystalline compounds are mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

CAC-OS, on the other hand, relates to the material composition of metal oxides. CAC-OS is a material composition containing In, Ga, Zn, and O, in which a region that is observed in the form of nanoparticles containing Ga as the main component in part and nanoparticles containing In as the main component in part. The regions observed in a pattern refer to a configuration in which the regions are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS the crystal structure is a secondary factor.

Note that the CAC-OS does not include a stacked structure of two or more films with different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

Note that it may be difficult to observe a clear boundary between a region containing GaO _X3 as its main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as its main component.

Instead of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. When one type or multiple types are included, the CAC-OS has a region that is partly observed as nanoparticles containing the metal element as the main component and a part that is observed as nanoparticles containing In as the main component. The regions observed in the regions are randomly distributed in a mosaic pattern.

CAC-OS can be formed, for example, by a sputtering method under the condition that the substrate is not intentionally heated. Further, when the CAC-OS is formed by a sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas is used as a deposition gas. Just do it. Further, the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation is preferably as low as possible.

CAC-OS is characterized in that no clear peak is observed when measured using θ/2θ scanning by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. have That is, it can be seen from the X-ray diffraction that the orientation in the ab plane direction and the c-axis direction of the measurement region is not observed.

In addition, CAC-OS has an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam). A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure with no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, GaO _X3 is the main component by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are unevenly distributed and have a mixed structure.

CAC-OS has a structure different from IGZO compounds in which metal elements are uniformly distributed, and has properties different from those of IGZO compounds. That is, the CAC-OS is phase-separated into a region containing GaO 2 _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO 2 _X1 as a main component, and a region containing each element as a main component. has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component has higher conductivity than the region containing GaO _X3 or the like as the main component. That is, when carriers flow through a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, conductivity as a metal oxide is developed. Therefore, a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is distributed in a cloud shape in the metal oxide, so that a transistor using the metal oxide achieves high field effect mobility. can.

On the other hand, a region containing GaO 2 _X3 or the like as a main component has higher insulating properties than a region containing In _X2 Zn _Y2 O _Z2 or InO 2 _X1 as a main component. In other words, by distributing a region containing _GaOx3 or the like as a main component in the metal oxide, a transistor using the metal oxide can suppress leakage current and realize good switching operation.

Therefore, when the CAC-OS is used for a semiconductor element such as a transistor, the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 and the insulation caused by GaO _X3 or the like act complementarily. Therefore, both high on-current and low off-current can be achieved.

In addition, a semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for use in various semiconductor devices such as display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, processors, and electronic devices.

<Method for manufacturing a semiconductor device>
An example of a method for manufacturing a semiconductor device including the transistor 10 according to one embodiment of the present invention is described below with reference to FIGS. 5 to 10, (A) of each figure is a top view of a semiconductor device having a transistor 10. FIG. In addition, (B) of each figure is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in (A) of each figure. In addition, (C) of each figure is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in (A) of each figure. In addition, in the method for manufacturing a semiconductor device having the transistor 10 described below, specific materials for each component (substrate, insulator, conductor, oxide, etc.) applicable to the semiconductor device are described in <Semiconductor device The contents described in the section "Constituent Elements of" can be taken into consideration.

First, a substrate (not shown) is prepared.

Next, an insulator 100 is formed over the substrate. The insulator 100 is formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD. (Atomic Layer Deposition) method or the like can be used.

The CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD) method and an organic metal CVD (MOCVD) method depending on the raw material gas used.

The plasma CVD method can obtain high quality films at relatively low temperatures. Moreover, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased. Moreover, since the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The ALD method is also a film forming method capable of reducing plasma damage to the object to be processed. Also, the ALD method does not cause plasma damage during film formation, so that a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by reaction on the surface of the object to be processed, unlike film forming methods in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.

The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gases. Further, for example, in the CVD method and the ALD method, it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of source gases, the time required for film formation is shortened because the time required for transportation and pressure adjustment, which is required when forming a film using a plurality of film formation chambers, is not required. be able to. Therefore, productivity of semiconductor devices can be improved in some cases.

In this embodiment mode, silicon oxide is deposited as the insulator 100 by a CVD method. Note that silicon oxynitride, for example, may be used as the insulator 100 instead of silicon oxide.

Next, an insulator 102 is formed over the insulator 100 . The insulator 102 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 102 is formed using aluminum oxide by a sputtering method. Moreover, the insulator 102 may have a multilayer structure. For example, a structure in which an aluminum oxide film is formed by a sputtering method and an aluminum oxide film is formed on the aluminum oxide by an ALD method may be employed. Alternatively, a structure may be employed in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide film by a sputtering method.

Next, an insulator 105 is formed over the insulator 102 . The insulator 105 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 105 by a CVD method. Note that silicon oxynitride, for example, may be used as the insulator 105 instead of silicon oxide.

Next, an opening reaching the insulator 102 is formed in the insulator 105 . Here, the opening includes, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing. For the insulator 102, an insulator that functions as an etching stopper film when the insulator 105 is etched to form an opening is preferably selected. For example, when a silicon oxide film is used for the insulator 105 forming the opening, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used for the insulator 102 .

After forming the opening, a film of a conductor to be the conductor 185 is formed. Here, the conductor 185 has a layered structure including a conductor 185a (not shown) having a function of suppressing permeation of oxygen and a conductor 185b (not shown) having a higher conductivity than the conductor 185a. It is preferable to

A conductor to be the conductor 185a preferably contains a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductor to be the conductor 185a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, as the conductor to be the conductor 185a, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is deposited by a sputtering method. By using such a metal nitride as a conductor that forms the conductor 185a, even if a metal such as copper that is easily diffused is used for the conductor 185b described later, diffusion of the metal to the outside from the conductor 185a can be prevented. can be prevented.

Next, a conductor to be the conductor 185b is formed over the conductor to be the conductor 185a. A conductor to be the conductor 185b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a low-resistance conductive material such as copper is deposited as a conductor to be the conductor 185b.

Next, chemical mechanical polishing (CMP) treatment is performed to remove part of the conductor to be the conductor 185a and part of the conductor to be the conductor 185b, and the insulator 105 is exposed. As a result, a conductor to be the conductor 185a and a conductor to be the conductor 185b remain only in the opening. Thus, the conductor 185 including the conductor 185a and the conductor 185b with a flat top surface can be formed (see FIG. 5). Note that part of the insulator 105 is removed by the CMP treatment in some cases.

Next, the insulator 110 is formed over the insulator 105 and the conductor 185 . The insulator 110 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 110 is formed using silicon oxide by a CVD method. Note that silicon oxynitride, for example, may be used as the insulator 110 instead of silicon oxide.

Here, first heat treatment may be performed. The first heat treatment may be performed at 250° C. to 650° C., for example. The first heat treatment is preferably performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment is heat treatment in an atmosphere of nitrogen gas or inert gas, followed by heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for desorbed oxygen. may be performed. By the first heat treatment, impurities such as hydrogen and water contained in the insulators 110 and 105 can be reduced. Alternatively, in the first heat treatment, plasma treatment containing oxygen may be performed under reduced pressure. For plasma treatment containing oxygen, for example, an apparatus having a power supply that generates high-density plasma using microwaves is preferably used. Alternatively, the substrate may have a power supply for applying RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 110 and the insulator 105. be able to. Alternatively, after performing plasma treatment containing an inert gas using this apparatus, plasma treatment containing oxygen may be performed in order to compensate for desorbed oxygen.

Next, an opening is formed in the insulator 110 to reach the conductor 185 . A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing.

After forming the opening, a film of a conductor to be the conductor 190 is formed. Here, the conductor 190 has a laminated structure consisting of a conductor 190a (not shown) having a function of suppressing permeation of oxygen and a conductor 190b (not shown) having a higher conductivity than this. is preferred.

A conductor to be the conductor 190a preferably contains a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductor to be the conductor 190a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, a tantalum nitride film is formed by a sputtering method as the conductor to be the conductor 190a.

Next, a conductor to be the conductor 190b is formed over the conductor to be the conductor 190a. The conductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, as the conductor that serves as the conductor 190b, a film of titanium nitride is formed by an ALD method, and a film of tungsten is formed over the titanium nitride by a CVD method.

Next, by performing CMP treatment, the conductor to be the conductor 190a and part of the conductor to be the conductor 190b are removed, and the insulator 110 is exposed. As a result, a conductor to be the conductor 190a and a conductor to be the conductor 190b remain only in the opening. Thus, the conductor 190 including the conductor 190a and the conductor 190b with a flat top surface can be formed (see FIG. 5). Note that part of the insulator 110 is removed by the CMP treatment in some cases.

Next, a conductor 120 a is formed over the insulator 110 and the conductor 190 . The conductor 120a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A conductor such as tantalum nitride, tungsten, or titanium nitride can be used as the conductor 120a, for example. Alternatively, for example, a structure may be employed in which a tungsten film is formed and a conductor having a function of suppressing permeation of oxygen, such as titanium nitride or tantalum nitride, is formed over the tungsten. With this structure, it is possible to suppress an increase in electrical resistance due to oxidation of tungsten due to oxygen entering from the upper side of the conductor 120a.

Alternatively, the conductor 120a may be a conductive oxide such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium containing titanium oxide. An oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added, or indium gallium zinc oxide containing nitrogen is formed into a film, and aluminum, chromium, Materials containing one or more metal elements selected from copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc., or phosphorus A semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as, or a silicide such as nickel silicide may be deposited.

The oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffusing from the outside, which may improve electrical characteristics and reliability of the transistor 10 . Alternatively, even if titanium is used instead of the oxide, it may have a similar function.

In this embodiment, a film of tungsten is formed as the conductor 120a by a sputtering method.

Next, an insulator 130a is formed over the conductor 120a. The insulator 130a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is deposited by a CVD method as the insulator 130a. Note that silicon oxynitride, for example, may be used instead of silicon oxide as the insulator 130a.

Here, second heat treatment may be performed. The conditions of the first heat treatment can be used for the second heat treatment. Through the heat treatment, impurities such as hydrogen and water contained in the insulator 130a can be reduced. In addition, oxygen can be supplied into the insulator 130a.

Alternatively, an ion implantation method in which an ionized source gas is added after mass separation, an ion doping method in which an ionized source gas is added without being separated by mass, a plasma immersion ion implantation method, or the like is used. may be supplied with oxygen.

Excess oxygen can be added to the insulator 130a by the above-described heat treatment, ion implantation method, or the like. The excess oxygen may be supplied into the oxide 150 by a subsequent heat treatment or the like, and the electrical characteristics and reliability of the transistor 10 may be improved.

Next, a conductor 140a is formed over the insulator 130a (see FIG. 6). The conductor 140a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A conductor such as tantalum nitride, tungsten, or titanium nitride can be used as the conductor 140a, for example. Alternatively, for example, a structure in which a conductor having a function of suppressing permeation of oxygen such as titanium nitride or tantalum nitride is deposited and tungsten is deposited over the conductor may be employed. With such a structure, it is possible to suppress an increase in electrical resistance due to oxidation of tungsten due to oxygen entering from the lower side of the conductor 140a.

Alternatively, the conductor 140a is a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and the like. A material containing one or more elements, or a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide is deposited, and a conductive film is formed thereon. oxides, for example, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide An oxide, indium zinc oxide, indium tin oxide to which silicon is added, or indium gallium zinc oxide containing nitrogen may be deposited.

The oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffusing from the outside, which may improve electrical characteristics and reliability of the transistor 10 . Alternatively, even if titanium is used instead of the oxide, it may have a similar function.

In this embodiment, tungsten is deposited by a sputtering method as the conductor 140a.

Next, the conductor 120a, the insulator 130a, and the conductor 140a are processed by a lithography method or the like so that the conductor 120b, the insulator 130b, and the conductor 120b, the insulator 130b, and the conductor 140a are formed over the insulator 110 so as to have a region overlapping with the conductor 190. and a conductor 140b is formed (see FIG. 7). A dry etching method or a wet etching method can be used for the formation, and the dry etching method is particularly preferable because it is suitable for fine shape processing. Part of the insulator 110 may be removed by the processing.

In the lithography method, first, the resist is exposed through a mask. Next, the exposed regions are removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching treatment through the resist mask. For example, a resist mask may be formed by exposing the resist with KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, direct drawing is performed on the resist, so the mask for resist exposure is not necessary. Note that the resist mask is removed by a method such as performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after dry etching treatment, or performing dry etching treatment after wet etching treatment. can be done.

A hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed over the conductor 140a, a resist mask is formed thereover, and the hard mask material is etched to form a hard mask having a desired shape. can do. The etching of the conductor 120a, the insulator 130a, and the conductor 140a may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the conductor 120a, the insulator 130a, and the conductor 140a, the hard mask may be removed by an etching method. On the other hand, if the hard mask material does not affect the post-process or can be used in the post-process, it is not necessary to remove the hard mask.

As a dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one of the parallel plate electrodes may be used. Alternatively, a configuration in which a high-frequency power source of the same frequency is applied to each parallel plate type electrode may be used. Alternatively, a configuration in which high-frequency power sources with different frequencies are applied to the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source.

Note that when the above treatment such as dry etching is performed, impurities caused by an etching gas or the like might adhere to or diffuse onto or inside the conductor 120b, the insulator 130b, the conductor 140b, or the like. Impurities include, for example, fluorine or chlorine.

Washing may be performed to remove the above impurities and the like. As a cleaning method, wet cleaning using a cleaning solution or the like, plasma treatment using plasma, cleaning by heat treatment, or the like may be used, and the above cleaning may be performed in combination as appropriate.

As wet cleaning, cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

Next, an insulator 175 is formed over the insulator 110, the conductor 120b, the insulator 130b, and the conductor 140b. The insulator 175 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 175 by a CVD method. Note that silicon oxynitride, for example, may be used as the insulator 175 instead of silicon oxide.

Next, the top surface of the insulator 175 is planarized by removing part of the insulator 175 (see FIG. 8). The planarization can be performed by CMP treatment, dry etching treatment, or the like. In this embodiment mode, the top surface of the insulator 175 is planarized by CMP treatment. The top surface of the insulator 175 after the planarization treatment is preferably higher than the top surface of the conductor 140b. Note that in the case where the top surface of the insulator 175 after the film formation is flat, the above planarization treatment may not be performed in some cases.

Here, third heat treatment may be performed. The conditions of the first heat treatment can be used for the third heat treatment. Through the heat treatment, impurities such as hydrogen and water contained in the insulator 175 can be reduced. In addition, oxygen can be supplied into the insulator 175 .

Next, the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are processed by a lithography method to form the opening 145 reaching the upper surface of the insulator 110, the conductor 120, the insulator 130, and the conductor 140. (See FIG. 9). Resist exposure in lithography may be performed through a mask using KrF excimer laser light, ArF excimer laser light, EUV light, or the like, or may be performed using liquid immersion technology. Alternatively, a method of drawing a pattern directly on the resist with an electron beam or an ion beam without using a mask may be used. Exposure using an electron beam or an ion beam is suitable for microfabrication because it can draw a finer pattern on a resist than the above exposure using light. In this embodiment mode, resist exposure is performed using an electron beam.

A dry etching method or a wet etching method can be used as the etching treatment in the lithography method. In this embodiment mode, the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are etched by a dry etching method after the above-described resist exposure with an electron beam and development. It is preferable that the inner wall (side surface) of the opening 145 formed by the etching process be substantially perpendicular to the substrate surface. The closer the inner wall (side surface) of the opening 145 is formed at an angle to the substrate surface, the smaller the transistor 10 can be. Note that part of the insulator 110 is removed by the etching treatment in some cases.

Next, an oxide to be the oxide 150 is deposited over the inner wall of the opening 145 and the insulator 175 . An oxide film to be the oxide 150 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, in the case of forming an oxide to be the oxide 150 by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the deposited oxide can be increased. Further, when the above oxide is formed by a sputtering method, the above In--M--Zn oxide target can be used.

In the case of forming an oxide to be the oxide 150 by a sputtering method, if the oxygen content in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide film is formed. of metal oxides are formed. A transistor in which an oxygen-deficient metal oxide is used for a channel formation region has relatively high field-effect mobility.

In this embodiment, the oxide to be the oxide 150 is formed by a sputtering method using an In—Ga—Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. film. Note that the oxide to be the oxide 150 is preferably formed so as to have characteristics required for the oxide 150 of the transistor 10 by appropriately selecting film formation conditions and an atomic ratio.

Note that, as described above, the oxide 150 may have a stacked structure of two or more layers. For example, when the oxide 150 has a two-layer structure consisting of an oxide 150a (not shown) and an oxide 150b (not shown) from the bottom, the oxide to be the oxide 150a is formed by sputtering In :Ga:Zn=4:2:4.1 [atomic ratio] In—Ga—Zn oxide target, oxygen content in sputtering gas is 1% or more and 30% or less, preferably 5% The film may be formed with a ratio of 20% or less. Then, the oxide to be the oxide 150b is formed by a sputtering method using an In—Ga—Zn oxide target of In:Ga:Zn=1:3:4 [atomic ratio], and oxygen contained in the sputtering gas. is 70% or more, preferably 80% or more, more preferably 100%. When the oxide 150 has this structure, the oxide 150a mainly functions as a channel formation region of the transistor . When the oxide 150 has this structure, oxygen contained in the oxide to be the oxide 150b can be supplied to the oxide to be the oxide 150a by the fourth heat treatment or the like. Note that the fourth heat treatment is preferably performed after deposition of the oxide to be the oxide 150b. As for the conditions of the heat treatment, it is preferable to perform treatment at 400° C. for 1 hour in a nitrogen atmosphere and then continuously perform treatment at 400° C. for 1 hour in an oxygen atmosphere.

Alternatively, for example, when the oxide 150 has a two-layer structure consisting of an oxide 150a (not shown) and an oxide 150b (not shown) from the bottom, the oxide to be the oxide 150a is formed by sputtering. Using an In—Ga—Zn oxide target of In:Ga:Zn=1:3:4 [atomic ratio], the percentage of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, more preferably should be formed as 100%. Then, the oxide to be the oxide 150b is formed by a sputtering method using an In—Ga—Zn oxide target having an atomic ratio of In:Ga:Zn=4:2:4.1 [atomic ratio]. The film may be formed so that the percentage of oxygen contained in the film is 1% or more and 30% or less, preferably 5% or more and 20% or less. When the oxide 150 has this structure, the oxide 150 b mainly functions as a channel formation region of the transistor 10 . When the oxide 150 has this structure, oxygen contained in the oxide to be the oxide 150a can be supplied to the oxide to be the oxide 150b by the fourth heat treatment or the like.

Further, when the oxide 150 has a three-layer structure consisting of the oxide 150a, the oxide 150b, and the oxide 150c (not shown) from the bottom, the oxide that becomes the oxide 150a and the oxide that becomes the oxide 150b is deposited under the above-described conditions, and the oxide to be the oxide 150c is formed by sputtering using an In—Ga—Zn oxide target having an In:Ga:Zn=4:2:4.1 [atomic ratio] is used so that the ratio of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, more preferably 100%. As described above, the fourth heat treatment is preferably performed after forming the oxide to be the oxide 150b. When the oxide 150 has this structure, the oxide 150 b mainly functions as a channel formation region of the transistor 10 . When the oxide 150 has such a structure, in addition to oxygen contained in the oxide that forms the oxide 150a, oxygen contained in the oxide that forms the oxide 150c also becomes the oxide 150b by subsequent heat treatment or the like. Oxides can be supplied.

Next, an insulator to be the insulator 160 is formed over the oxide to be the oxide 150 . The insulator to be the insulator 160 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited by a CVD method as the insulator to be the insulator 160 . Note that, as an insulator to be the insulator 160, silicon oxynitride, for example, may be used instead of silicon oxide.

Here, fifth heat treatment is preferably performed. The conditions of the fourth heat treatment can be used for the fifth heat treatment. By the heat treatment, oxygen contained in the insulator that becomes the insulator 160 (and the oxide that becomes the oxide 150c when the oxide has a three-layer structure) is converted to the oxide that becomes the oxide 150 (the oxide has a three-layer structure, it can be supplied to the oxide that becomes the oxide 150b).

Next, a conductor to be the conductor 170 is formed over the insulator to be the insulator 160 . A conductor to be the conductor 170 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, as a conductor to be the conductor 170, a film of titanium nitride is formed by an ALD method, and then a film of tungsten is formed by a CVD method. Note that the thickness of tungsten is preferably thicker than that of titanium nitride in the conductor to be the conductor 170 . Further, titanium nitride is preferably formed along the inner wall of the opening 145 with an insulator serving as the insulator 160 interposed therebetween, and is preferably formed so as to fill the remaining space in the opening 145 with tungsten. By depositing the conductor to be the conductor 170 in this manner, the conductor 170 having a layered structure of titanium nitride and tungsten can be formed later.

Next, the top surfaces of the conductor to be the conductor 170, the insulator to be the insulator 160, and the oxide to be the oxide 150 are polished until the top surface of the insulator 175 is exposed. and form oxide 150 (see FIG. 10). The polishing can be performed by CMP processing or the like. Further, the top surfaces of the conductor to be the conductor 170, the insulator to be the insulator 160, and the oxide to be the oxide 150 are dry-etched until the top surface of the insulator 175 is exposed, whereby the conductor 170 and the insulator 175 are etched. 160 and oxide 150 may be formed. In this embodiment mode, the conductor 170, the insulator 160, and the oxide 150 are formed by CMP treatment. By the CMP treatment, the height of the top surface of the insulator 175 and the height of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 can be made substantially the same (see FIG. 10). Note that part of the insulator 175 may be removed by the CMP treatment.

Next, insulator 176 is placed on top of insulator 175, oxide 150, insulator 160, and conductor 170, insulator 178 over insulator 176, insulator 180 over insulator 178, and so on. Each film is formed. The insulators 176, 178, and 180 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 176 is formed using silicon oxide by a CVD method, the insulator 178 is formed using aluminum oxide by a sputtering method, and the insulator 180 is formed using silicon oxide by a CVD method. . Note that the insulator 176 or the insulator 180 may be made of, for example, silicon oxynitride instead of silicon oxide. As for the insulator 178, for example, silicon nitride or hafnium oxide may be used instead of aluminum oxide.

Next, openings reaching the conductor 140 are formed in the insulator 180 , the insulator 178 , the insulator 176 , and the insulator 175 . A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing.

After forming the opening, a film of a conductor to be the conductor 195 is formed. Here, the conductor 195 has a layered structure including a conductor 195a (not shown) having a function of suppressing permeation of oxygen and a conductor 195b (not shown) having a higher conductivity than the conductor 195a. It is preferable to

A conductor to be the conductor 195a preferably contains a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductor to be the conductor 195a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, a tantalum nitride film is formed by a sputtering method as the conductor to be the conductor 195a.

Next, a conductor to be the conductor 195b is formed over the conductor to be the conductor 195a. The conductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as a conductor to be the conductor 195b, a film of titanium nitride is formed by an ALD method, and a film of tungsten is formed over the titanium nitride by a CVD method.

Next, by performing CMP treatment, the conductor to be the conductor 195a and part of the conductor to be the conductor 195b are removed, and the insulator 180 is exposed. As a result, a conductor to be the conductor 195a and a conductor to be the conductor 195b remain only in the opening. Accordingly, the conductor 195 including the conductor 195a and the conductor 195b having a flat top surface can be formed. Note that part of the insulator 180 is removed by the CMP treatment in some cases.

Next, a conductor to be the conductor 200 is formed over the insulator 180 and the conductor 195 . Here, the conductor 200 has a layered structure including a conductor 200a (not shown) having a function of suppressing permeation of oxygen and a conductor 200b (not shown) having a higher conductivity than the conductor 200a. It is preferable to

A conductor to be the conductor 200a preferably contains a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductor to be the conductor 200a can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as the conductor to be the conductor 200a, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is deposited by a sputtering method. By using such a metal nitride as a conductor that forms the conductor 200a, even if a metal that is easily diffused, such as copper, is used for the conductor 200b described later, the metal does not pass through the conductor 200a and the conductor 195. , can be prevented from diffusing into transistor 10 .

Next, a conductor to be the conductor 200b is formed over the conductor to be the conductor 200a. A conductor to be the conductor 200b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a film of a low-resistance conductive material such as copper is formed as a conductor to be the conductor 200b.

Next, a conductor to be the conductor 200b and a conductor to be the conductor 200a are processed by a lithography method or the like so as to have a region overlapping with the conductor 195; A conductor 200 made of the conductor 200b can be formed. Note that part of the insulator 180 may be removed by the processing.

Through the above steps, a semiconductor device including the transistor 10 of one embodiment of the present invention can be manufactured (see FIG. 1).

As described above, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a plurality of transistors with a channel length of several nanometers or less, which is difficult to be manufactured by lithography, can be manufactured accurately and easily within the plane of the substrate. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics in which a short-channel effect is unlikely to occur even though the channel length is small can be manufactured. Further, according to one embodiment of the present invention, a semiconductor device having a minute transistor whose element size includes not only a channel length but also a wiring and a plug can be manufactured. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with small variations in electrical characteristics between elements within a substrate surface can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 2)
In this embodiment, one mode of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[Storage device]
A memory device illustrated in FIG. 11 includes a transistor 3000 , a transistor 2000 , and a capacitor 1000 .

A transistor 2000 is a transistor in which a channel is formed in a semiconductor layer including metal oxide. Since the transistor 2000 has a low off-state current, stored data can be retained for a long time by using the transistor 2000 for a memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

In FIG. 11, a first wiring 3001 is electrically connected to the source of the transistor 3000 and a second wiring 3002 is electrically connected to the drain of the transistor 3000 . A third wiring 3003 is electrically connected to one of the source and drain of the transistor 2000 , and a fourth wiring 3004 is electrically connected to the gate of the transistor 2000 . The gate of the transistor 3000 and the other of the source and the drain of the transistor 2000 are electrically connected to one electrode of the capacitor 1000, and the fifth wiring 3005 is electrically connected to the other electrode of the capacitor 1000. It is connected.

Since the memory device illustrated in FIG. 11 has a characteristic that the potential of the gate of the transistor 3000 can be held, data can be written, held, and read as follows.

Writing and holding information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is turned on, so that the transistor 2000 is turned on. Accordingly, the potential of the third wiring 3003 is applied to the node FG electrically connected to the gate of the transistor 3000 and one of the electrodes of the capacitor 1000 . That is, a predetermined charge is applied to the gate of the transistor 3000 (writing). Here, it is assumed that one of charges that give two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is turned off so that the transistor 2000 is turned off, so that charge is held in the node FG (holding).

When the off-state current of the transistor 2000 is small, the charge of the node FG is retained for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 while a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 is supplied with the electric charge held in the node FG. Take a potential corresponding to the amount. Assuming that the transistor 3000 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 3000 is V th_H when a low level charge is applied to the gate of the transistor 3000 is lower than the apparent threshold voltage V _{th_L} of . Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to turn on the transistor 3000 . Therefore, by setting the potential of the fifth wiring 3005 to the potential _V0 between _{Vth_H} and _{Vth_L} , the charge applied to the node FG can be determined. For example, when high-level charge is applied to the node FG in writing, the transistor 3000 is turned on when the potential of the fifth wiring 3005 becomes V ₀ (>V _{th — H} ). On the other hand, when Low-level charge is applied to the node FG, the transistor 3000 remains off even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th — L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

<Structure of storage device>
A memory device of one embodiment of the present invention includes a transistor 3000, a transistor 2000, and a capacitor 1000 as illustrated in FIG. The transistor 2000 is provided above the transistor 3000 , and the capacitor 1000 is provided above the transistors 3000 and 2000 .

The transistor 3000 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. have.

Transistor 3000 can be either p-channel or n-channel.

A region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, the low-resistance regions 314a and 314b serving as a source region or a drain region, and the like preferably contain a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 3000 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In the low-resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, an element imparting n-type conductivity, such as arsenic or phosphorus, or an element imparting p-type conductivity, such as boron, is used. contains elements that

The conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, or an alloy. material, or a conductive material such as a metal oxide material.

Note that since the work function is determined by the material of the conductor, Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

Note that the transistor 3000 illustrated in FIG. 11 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 3000 .

For the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. Just do it.

The insulator 322 may function as a planarization film that planarizes a step caused by the transistor 3000 or the like provided therebelow. For example, the top surface of the insulator 322 may be planarized by CMP treatment or the like to improve planarity.

For the insulator 324, it is preferable to use a film having a barrier property such that hydrogen or impurities do not diffuse from the substrate 311, the transistor 3000, or the like to the region where the transistor 2000 is provided.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including a metal oxide, such as the transistor 2000, electrical characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 2000 and the transistor 3000 . Specifically, the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.

The desorption amount of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen released from the insulator 324 is the amount of hydrogen atoms released per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. , 10×10 ¹⁵ atoms/cm ² or less, preferably 5×10 ¹⁵ atoms/cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324 . For example, the dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, that of the insulator 324 . By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

In the insulators 320 , 322 , 324 , and 326 , conductors 328 , 330 , and the like electrically connected to the capacitor 1000 or the transistor 2000 are embedded. Note that the conductors 328 and 330 function as plugs or wirings. In addition, conductors that function as plugs or wiring may have a plurality of structures collectively given the same reference numerals. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as wiring, and part of the conductor may function as a plug.

As a material of each plug and wiring (the conductor 328, the conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a laminated layer. can be used. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably made of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330 . For example, in FIG. 11, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed over the insulators 350 , 352 , and 354 . The conductor 356 functions as a plug or wiring. Note that the conductor 356 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 350 , for example, an insulator having a barrier property against hydrogen is preferably used, like the insulator 324 . Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, it is preferable to form the conductor 356 having a barrier property against hydrogen in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

Note that tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen, for example. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 3000 can be suppressed while the conductivity of the wiring is maintained. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided over the insulator 354 and the conductor 356 . For example, in FIG. 11, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed over the insulators 360 , 362 , and 364 . The conductor 366 functions as a plug or wiring. Note that the conductor 366 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 360, for example, an insulator having a barrier property against hydrogen is preferably used, like the insulator 324. Further, the conductor 366 preferably contains a conductor having a barrier property against hydrogen. In particular, it is preferable to form the conductor 366 having a barrier property against hydrogen in the opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366 . For example, in FIG. 11, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed over the insulators 370 , 372 , and 374 . The conductor 376 functions as a plug or wiring. Note that the conductor 376 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 370, for example, an insulator having a barrier property against hydrogen is preferably used like the insulator 324. Further, the conductor 376 preferably contains a conductor having a barrier property against hydrogen. In particular, it is preferable to form a conductor 376 having a barrier property against hydrogen in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376 . For example, in FIG. 11, an insulator 380, an insulator 382, and an insulator 384 are stacked in order. A conductor 386 is formed over the insulators 380 , 382 , and 384 . The conductor 386 functions as a plug or wiring. Note that the conductor 386 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 380, for example, an insulator having a barrier property against hydrogen is preferably used like the insulator 324. Further, the conductor 386 preferably contains a conductor having a barrier property against hydrogen. In particular, it is preferable to form the conductor 386 having a barrier property against hydrogen in the opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

An insulator 210 , an insulator 100 , an insulator 102 , and an insulator 105 are stacked in this order over the insulator 384 and the conductor 386 . Any of the insulator 210, the insulator 100, the insulator 102, and the insulator 105 is preferably a film having a barrier property against oxygen or hydrogen.

For example, for the insulators 210 and 102, it is preferable to use a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, a region where the transistor 3000 is provided, or the like to a region where the transistor 2000 is provided. . Therefore, a material similar to that of the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including a metal oxide, such as the transistor 2000, electrical characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 2000 and the transistor 3000 . Specifically, the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.

As a film having a barrier property against hydrogen, for example, the insulators 210 and 102 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

In particular, aluminum oxide has a high shielding effect of preventing the penetration of both oxygen and impurities such as hydrogen and water, which cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide forming the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000 .

Further, for example, the insulator 100 and the insulator 105 can be formed using a material similar to that of the insulator 320 . Further, by using a material with a relatively low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, or the like can be used for the insulators 100 and 105 .

In the insulator 210 , the insulator 100 , the insulator 102 , and the insulator 105 , a conductor 218 , a conductor electrically connected to the transistor 2000 (a conductor 185 ), and the like are embedded. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 1000 or the transistor 3000 . The conductor 218 can be provided using a material similar to that of the conductors 328 and 330 .

In particular, the insulator 210 and the conductor 218 in the region in contact with the insulator 102 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 3000 and the transistor 2000 can be reliably separated from each other by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

A transistor 2000 is provided over the insulator 105 with an insulator 110 interposed therebetween. Note that the transistor included in the semiconductor device described in the above embodiment may be used as the structure of the transistor 2000 . Further, the transistor 2000 illustrated in FIG. 11 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

An insulator 175 , an insulator 176 , and an insulator 178 are provided over the transistor 2000 .

A film having a barrier property against oxygen and hydrogen is preferably used for the insulator 178 . Therefore, a material similar to that of the insulator 102 can be used for the insulator 178 . For example, the insulator 178 is preferably made of metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

In particular, aluminum oxide has a high shielding effect of preventing the penetration of both oxygen and impurities such as hydrogen and water, which cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide forming the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000 .

An insulator 180 is provided over the insulator 178 . A material similar to that of the insulator 320 can be used for the insulator 180 . Further, by using a material with a relatively low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, or the like can be used as the insulator 180 .

In the insulator 110, the insulator 175, the insulator 176, the insulator 178, and the insulator 180, a conductor 246, a conductor 248, and the like are embedded.

The conductors 246 and 248 function as plugs or wirings electrically connected to the capacitor 1000 , the transistor 2000 , or the transistor 3000 . The conductors 246 and 248 can be formed using a material similar to that of the conductors 328 and 330 .

A capacitor 1000 is provided above the transistor 2000 . A capacitor 1000 includes a conductor 1100 , a conductor 1200 , and an insulator 1300 .

Alternatively, the conductor 112 may be provided over the conductor 246 and the conductor 248 . The conductor 112 functions as a plug electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000, or a wiring. A conductor 1100 functions as an electrode of the capacitor 1000 . Note that the conductor 112 and the conductor 1100 can be formed at the same time.

The conductors 112 and 1100 include metals containing elements selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or metal nitrides containing the above elements as components. tantalum, titanium nitride, molybdenum nitride, tungsten nitride) and the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. Conductive materials such as indium tin oxide can also be applied.

FIG. 11 shows a structure in which the conductor 112 and the conductor 1100 have a single-layer structure; however, the present invention is not limited to this structure, and a stacked structure of two or more layers may be employed. For example, between a conductor with barrier properties and a conductor with high conductivity, a conductor with barrier properties and a conductor with high adhesion to the conductor with high conductivity may be formed.

An insulator 1300 is provided as a dielectric of the capacitor 1000 over the conductors 112 and 1100 . The insulator 1300 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like. It may be used as long as it is used, and it can be provided as a laminate or a single layer.

For example, for the insulator 1300, a material with high withstand voltage such as silicon oxynitride is preferably used. With this structure, dielectric breakdown resistance of the capacitor 1000 is improved, and electrostatic breakdown of the capacitor 1000 can be suppressed.

A conductor 1200 is provided over the insulator 1300 so as to overlap with the conductor 1100 . Note that a conductive material such as a metal material, an alloy material, or a metal oxide material can be used for the conductor 1200 . It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In addition, when forming simultaneously with another structure such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) may be used.

An insulator 1500 is provided over the conductor 1200 and the insulator 1300 . The insulator 1500 can be provided using a material similar to that of the insulator 320 . In addition, the insulator 1500 may function as a planarizing film that covers the uneven shape thereunder.

The above is the description of the configuration example of the memory device to which the semiconductor device according to one embodiment of the present invention is applied. By using this structure, in a semiconductor device including a transistor including a metal oxide, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including a metal oxide with high on-state current can be provided. Alternatively, a transistor including a metal oxide with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 3)
In this embodiment, a transistor using a metal oxide for a channel formation region (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied with reference to FIGS. A NOSRAM will be described as an example of a storage device that is used. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Note that, hereinafter, a memory device using an OS transistor, such as a NOSRAM, may be referred to as an OS memory.

The NOSRAM employs a memory device (hereinafter referred to as "OS memory") in which OS transistors are used for memory cells. An OS memory includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor has a very low off-current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

<<NOSRAM1600>>
FIG. 12 shows a configuration example of the NOSRAM. The NOSRAM 1600 shown in FIG. 12 has a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660 and an output driver 1670. The NOSRAM 1600 is a multilevel NOSRAM that stores multilevel data in one memory cell.

The memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a plurality of bit lines BL, and a plurality of source lines SL. Word line WWL is a write word line, and word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (8-level) data.

The controller 1640 controls the entire NOSRAM 1600 and writes data WDA[31:0] and reads data RDA[31:0]. Controller 1640 processes external command signals (eg, chip enable signals, write enable signals, etc.) to generate control signals for row drivers 1650 , column drivers 1660 and output drivers 1670 .

Row driver 1650 has the function of selecting a row to access. Row driver 1650 has row decoder 1651 and word line driver 1652 .

Column drivers 1660 drive source lines SL and bit lines BL. The column driver 1660 has a column decoder 1661 , a write driver 1662 and a DAC (digital-analog conversion circuit) 1663 .

DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts the 32-bit data WDA[31:0] into an analog voltage every 3 bits.

The write driver 1662 has a function of precharging the source line SL, a function of making the source line SL electrically floating, a function of selecting the source line SL, and inputting a write voltage generated by the DAC 1663 to the selected source line SL. a function to precharge the bit line BL, a function to electrically float the bit line BL, and the like.

The output driver 1670 has a selector 1671 , an ADC (analog-digital conversion circuit) 1672 and an output buffer 1673 . The selector 1671 selects the source line SL to access and transmits the voltage of the selected source line SL to the ADC 1672 . The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC1672, and the output buffer 1673 holds the data output from the ADC1672.

<Memory Cells 1611 to 1614>
FIG. 13A is a circuit diagram showing a configuration example of the memory cell 1611. FIG. The memory cell 1611 is a 2T-type gain cell, and is electrically connected to a word line WWL, a word line RWL, a bit line BL, and a source line SL. The memory cell 1611 has a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. A transistor MP61 is a read transistor and is composed of, for example, a p-channel Si transistor. Capacitive element C61 is a holding capacitor for holding the voltage of node SN. A node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

Since the write transistor of the memory cell 1611 is composed of the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

In the example of FIG. 13A, the bit lines are common bit lines for writing and reading. However, as shown in FIG. 13B, write bit lines WBL and read bit lines RBL may be provided. good.

13C to 13E show other structural examples of memory cells. FIGS. 13C to 13E show examples in which write bit lines and read bit lines are provided. may be provided.

A memory cell 1612 shown in FIG. 13C is a modification of the memory cell 1611, in which the reading transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

A memory cell 1613 illustrated in FIG. 13D is a 3T gain cell and is electrically connected to a word line WWL, a word line RWL, a bit line WBL, a bit line RBL, a source line SL, and a wiring PCL. The memory cell 1613 has a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. Transistor MP62 is a read transistor and transistor MP63 is a select transistor.

A memory cell 1614 shown in FIG. 13E is a modification of the memory cell 1613, in which the reading transistor and the selection transistor are changed to n-channel transistors (MN62 and MN63). The transistor MN62 and the transistor MN63 may be OS transistors or Si transistors.

The OS transistors provided in the memory cells 1611 to 1614 may be transistors without bottom gates or transistors with bottom gates.

Since data is rewritten by charging/discharging the capacitive element C61, the NOSRAM 1600 is theoretically free from restrictions on the number of rewrites and can write and read data with low energy. In addition, since data can be held for a long time, refresh frequency can be reduced.

When the semiconductor device described in any of the above embodiments is used for the memory cells 1611, 1612, 1613, and 1614, the transistor 2000 is used as the OS transistor MO61 and MO62, and the transistor 3000 is used as the transistor MP61 and the transistor MN62. can be used. This makes it possible to reduce the area occupied by the transistor when viewed from above, so that the storage device according to this embodiment can be further highly integrated. Therefore, the storage capacity per unit area of the storage device according to this embodiment can be increased.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 4)
In this embodiment, a DOSRAM will be described with reference to FIGS. 14 and 15 as an example of a memory device to which an OS transistor according to one embodiment of the present invention is applied. DOSRAM (registered trademark) is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. The OS memory is applied to the DOSRAM as well as the NOSRAM.

<<DOSRAM1400>>
FIG. 14 shows a configuration example of a DOSRAM. The DOSRAM 1400 shown in FIG. 14 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420").

Row circuit 1410 has decoder 1411 , word line driver circuit 1412 , column selector 1413 and sense amplifier driver circuit 1414 . Column circuit 1415 has global sense amplifier array 1416 and input/output circuit 1417 . Global sense amplifier array 1416 has a plurality of global sense amplifiers 1447 . The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, global bit lines GBLL, and global bit lines GBLR.

(MC-SA array 1420)
MC-SA array 1420 has a laminated structure in which memory cell array 1422 is laminated on sense amplifier array 1423 . Global bit lines GBLL and global bit lines GBLR are stacked on the memory cell array 1422 . The DOSRAM 1400 employs a hierarchical bit line structure in which local bit lines and global bit lines are hierarchized as a bit line structure.

The memory cell array 1422 has N (N is an integer of 2 or more) local memory cell arrays 1425<0> to 1425<N−1>. FIG. 15A shows a configuration example of the local memory cell array 1425. FIG. The local memory cell array 1425 has multiple memory cells 1445, multiple word lines WL, multiple bit lines BLL, and multiple bit lines BLR. In the example of FIG. 15A, the structure of the local memory cell array 1425 is of open bit line type, but may be of folded bit line type.

FIG. 15B shows a circuit configuration example of the memory cell 1445. FIG. The memory cell 1445 has a transistor MW1, a capacitor CS1, and a terminal B1. The transistor MW1 has a function of controlling charging and discharging of the capacitor CS1. The transistor MW1 has a gate electrically connected to the word line, a first terminal electrically connected to the bit line, and a second terminal electrically connected to the first terminal of the capacitive element CS1. A second terminal of the capacitive element CS1 is electrically connected to the terminal B1. A constant potential (for example, a low power supply potential) is input to the terminal B1.

Transistor MW1 may be a transistor with a bottom gate. When the transistor MW1 is a transistor having a bottom gate, for example, the bottom gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1.

The sense amplifier array 1423 has N local sense amplifier arrays 1426<0> to 1426<N−1>. The local sense amplifier array 1426 has one switch array 1444 and a plurality of sense amplifiers 1446 . A bit line pair is electrically connected to the sense amplifier 1446 . The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference of the bit line pair, and a function of holding this potential difference. The switch array 1444 has the function of selecting a bit line pair and making the selected bit line pair and the global bit line pair conductive.

Here, a bit line pair means two bit lines that are simultaneously compared by a sense amplifier. A global bit line pair is two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form one global bit line pair. Hereinafter, it will also be referred to as a bit line pair (BLL, BLR) and a global bit line pair (GBLL, GBLR).

(Controller 1405)
Controller 1405 has the function of controlling the overall operation of DOSRAM 1400 . The controller 1405 has the function of logically operating command signals input from the outside to determine the operation mode, and the function of generating control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , has a function of holding an externally input address signal, and a function of generating an internal address signal.

(row circuit 1410)
Row circuit 1410 has the function of driving MC-SA array 1420 . The decoder 1411 has a function of decoding address signals. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the row to be accessed.

Column selector 1413 and sense amplifier driver circuit 1414 are circuits for driving sense amplifier array 1423 . The column selector 1413 has a function of generating a selection signal for selecting the bit line of the column to be accessed. A selection signal from the column selector 1413 controls the switch array 1444 of each local sense amplifier array 1426 . A plurality of local sense amplifier arrays 1426 are independently driven by control signals from the sense amplifier driver circuit 1414 .

(column circuit 1415)
The column circuit 1415 has a function of controlling input of data signals WDA[31:0] and a function of controlling output of data signals RDA[31:0]. Data signals WDA[31:0] are write data signals and data signals RDA[31:0] are read data signals.

Global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). Global sense amplifier 1447 has a function of amplifying the potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Data is written to and read from the global bit line pair (GBLL, GBLR) by the input/output circuit 1417 .

An outline of the write operation of the DOSRAM 1400 will be explained. Input/output circuit 1417 writes data to the global bit line pair. Global bit line pair data is held by global sense amplifier array 1416 . The switch array 1444 of the local sense amplifier array 1426 designated by the address writes the data of the global bit line pair to the bit line pair of the target column. The local sense amplifier array 1426 amplifies and holds the written data. In the designated local memory cell array 1425, the word line WL of the target row is selected by the row circuit 1410, and the data held in the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.

An outline of the read operation of the DOSRAM 1400 will be explained. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL of the target row is selected and the data of the memory cell 1445 is written to the bit line. Local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data. Switch array 1444 writes the data of the column designated by the address among the data held in local sense amplifier array 1426 to the global bit line pair. Global sense amplifier array 1416 detects and holds data on global bit line pairs. Data held in the global sense amplifier array 1416 is output to the input/output circuit 1417 . The above completes the read operation.

Since data is rewritten by charging/discharging the capacitive element CS1, the DOSRAM 1400 is theoretically free from restrictions on the number of rewrites and can write and read data with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, it is easy to increase the capacity.

The transistor MW1 is an OS transistor. Since the OS transistor has extremely low off-state current, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of DOSRAM 1400 is much longer than that of DRAMs using Si transistors. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, by using the DOSRAM 1400 as a frame memory, power consumption of the display controller IC and the source driver IC can be reduced.

Since the MC-SA array 1420 has a stacked structure, the bit lines can be shortened to the same length as the local sense amplifier array 1426 . By shortening the bit line, the bit line capacitance is reduced, and the storage capacitance of the memory cell 1445 can be reduced. Also, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load to be driven when accessing the DOSRAM 1400 is reduced, so the energy consumption of the display controller IC and the source driver IC can be reduced.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 5)
In this embodiment, a field programmable gate array (FPGA) will be described as an example of a semiconductor device including a transistor (OS transistor) using a metal oxide for a channel formation region, according to one embodiment of the present invention. . In the FPGA of this embodiment, an OS memory is applied to the configuration memory and registers. Here, such an FPGA is called an "OS-FPGA".

An OS memory includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor has a very low off-current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

FIG. 16A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 16A is capable of NOFF (normally off) computing that executes context switching with a multi-context structure and fine-grained power gating for each PLE. The OS-FPGA 3110 has a controller 3111 , a word driver 3112 , a data driver 3113 and a programmable area 3115 .

Programmable area 3115 has two input/output blocks (IOB) 3117 and core 3119 . The IOB3117 has multiple programmable input/output circuits. Core 3119 has a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130 . LAB3120 has several PLE3121. FIG. 16B shows an example in which the LAB 3120 is composed of five PLEs 3121 . As shown in FIG. 16C, the SAB 3130 has a plurality of switch blocks (SB) 3131 arranged in an array. LAB 3120 is connected to its own input terminal and to LAB 3120 in four directions (up, down, left, and right) via SAB 3130 .

The SB3131 will be described with reference to FIGS. 17A to 17C. SB 3131 shown in FIG. 17A receives input of data, datab, signals context[1:0] and word[1:0]. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of OS-FPGA 3110 is 2, and signals context[1:0] are context selection signals. The signal word[1:0] is a word line selection signal, and the wiring to which the signal word[1:0] is input is the word line.

The SB 3131 has PRS (Programmable Routing Switch) 3133[0] and PRS 3133[1]. PRS3133[0], PRS3133[1] have configuration memory (CM) that can store complementary data. PRS3133[0] and PRS3133[1] are referred to as PRS3133 when not distinguished from each other. The same applies to other elements.

FIG. 17B shows a circuit configuration example of PRS3133[0]. PRS3133[0] and PRS3133[1] have the same circuit configuration. PRS3133[0] and PRS3133[1] differ in the input context selection signal and word line selection signal. The signal context[0] and signal word[0] are input to PRS3133[0], and the signal context[1] and signal word[1] are input to PRS3133[1]. For example, in SB3131, PRS3133[0] becomes active when signal context[0] becomes "H".

PRS3133[0] has CM3135 and Si transistor M31. Si transistor M31 is a pass transistor controlled by CM3135. The CM 3135 has a memory circuit 3137 and a memory circuit 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 has a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit 3137B has a capacitive element CB31, an OS transistor MOB31, and an OS transistor MOB32.

The OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 may have bottom gates. For example, when the OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 have bottom gates, these bottom gates may be electrically connected to power supply lines that supply fixed potentials. .

The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. Node N32 and node NB32 are charge retention nodes of CM3135. The OS transistor MO32 controls conduction between the node N31 and the signal line for the signal context[0]. The OS transistor MOB32 controls conduction between the node N31 and the low potential power supply line VSS.

The logic of data held by the memory circuits 3137 and 3137B is complementary. Therefore, either the OS transistor MO32 or the OS transistor MOB32 becomes conductive.

An operation example of PRS3133[0] will be described with reference to FIG. Configuration data has already been written to PRS3133[0], node N32 of PRS3133[0] is at "H", and node NB32 is at "L".

While signal context[0] is "L", PRS3133[0] is inactive. During this period, even if the input terminal of PRS3133[0] transitions to "H", the gate of the Si transistor M31 is maintained at "L", and the output terminal of PRS3133[0] is also maintained at "L".

While signal context[0] is "H", PRS3133[0] is active. When the signal context[0] transitions to "H", the gate of the Si transistor M31 transitions to "H" according to the configuration data stored by the CM3135.

When the input terminal transitions to "H" while PRS3133[0] is active, the gate potential of the Si transistor M31 rises due to boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. do. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving capability, and the gate of the Si transistor M31 becomes floating.

In PRS 3133 with multi-context function, CM 3135 also has multiplexer function.

FIG. 18 shows a configuration example of the PLE3121. PLE 3121 has LUT (lookup table) block 3123 , register block 3124 , selector 3125 and CM 3126 . A LUT block 3123 is configured to select and output data according to inputs inA-inD. A selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to configuration data stored by the CM 3126 .

The PLE 3121 is electrically connected through a power switch 3127 to a power supply line for potential VDD. On/off of the power switch 3127 is set by configuration data stored by the CM 3128 . Fine power gating is possible by providing a power switch 3127 in each PLE 3121 . The fine-grained power gating function enables power gating of PLEs 3121 that are not used after context switching, thus effectively reducing standby power.

To implement NOFF computing, the register block 3124 consists of non-volatile registers. A non-volatile register in the PLE 3121 is a flip-flop (hereinafter referred to as “OS-FF”) with OS memory.

Register block 3124 has OS-FF 3140[1] and OS-FF 3140[2]. Signal user_res, signal load, and signal store are input to OS-FF 3140[1] and OS-FF 3140[2]. Clock signal CLK1 is input to OS-FF 3140[1], and clock signal CLK2 is input to OS-FF 3140[2]. FIG. 19A shows a configuration example of the OS-FF 3140. FIG.

OS-FF 3140 has FF 3141 and shadow register 3142 . FF3141 has node CK, node R, node D, node Q, and node QB. A clock signal is input to the node CK. A signal user_res is input to the node R. Signal user_res is a reset signal. Node D is a data input node and node Q is a data output node. Node Q and node QB have complementary logic.

Shadow register 3142 functions as a backup circuit for FF 3141 . The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back the backed up data to the nodes Q and QB according to the signal load.

Shadow register 3142 has inverter circuit 3188, inverter circuit 3189, Si transistor M37, Si transistor MB37, memory circuit 3143, and memory circuit 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS3133. The memory circuit 3143 has a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B has a capacitive element CB36, an OS transistor MOB35, and an OS transistor MOB36. A node N36 and a node NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge retention nodes, respectively. A node N37 and a node NB37 are gates of the Si transistor M37 and the Si transistor MB37.

The OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 may have bottom gates. For example, when the OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 have bottom gates, these bottom gates may be electrically connected to power supply lines that supply fixed potentials. .

An example of the operating method of the OS-FF 3140 will be described with reference to FIG. 19B.

(Backup)
When the "H" signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data of the FF 3141. FIG. The node N36 becomes "L" by writing the data of the node Q, and the node NB36 becomes "H" by writing the data of the node QB. Power gating is then performed to turn off the power switch 3127 . Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 retains the backup data even when the power is off.

(Recovery)
Power switch 3127 is turned on to supply power to PLE 3121 . After that, when the "H" signal load is input to the OS-FF 3140 , the shadow register 3142 writes back the backed up data to the FF 3141 . Since the node N36 is "L", the node N37 is maintained at "L", and the node NB36 is "H", so the node NB37 becomes "H". Therefore, the node Q becomes "H" and the node QB becomes "L". That is, the OS-FF 3140 returns to the state during the backup operation.

Combining fine-grained power gating with the backup/recovery operation of OS-FF 3140 can effectively reduce the power consumption of OS-FPGA 3110 .

Errors that can occur in memory circuits include soft errors due to incidence of radiation. Soft errors are secondary cosmic events caused by nuclear reactions between alpha rays emitted from materials that make up memory and packages, and primary cosmic rays that enter the atmosphere from outer space. This is a phenomenon in which a transistor is irradiated with ray neutrons, etc., and electron-hole pairs are generated, causing malfunctions such as inversion of data held in memory. An OS memory using an OS transistor has high resistance to soft errors. Therefore, by mounting the OS memory, it is possible to provide a highly reliable OS-FPGA 3110 .

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 6)
In this embodiment, an example of a CPU including a semiconductor device according to one embodiment of the present invention, such as the above memory device, will be described.

<Configuration of CPU>
A semiconductor device 5400 illustrated in FIG. 20 has a CPU core 5401 , a power management unit 5421 , and a peripheral circuit 5422 . The power management unit 5421 has a power controller 5402 and a power switch 5403 . The peripheral circuit 5422 has a cache (Cache) 5404 having a cache memory, a bus interface (BUS I/F) 5405 and a debug interface (Debug I/F) 5406 . The CPU core 5401 includes a data bus 5423, a control unit (Control Unit) 5407, a PC (program counter) 5408, a pipeline register (Pipeline Register) 5409, a pipeline register 5410, an ALU (Arithmetic logic unit) 5411, and a register file ( Register File) 5412. Data exchange between the CPU core 5401 and a peripheral circuit 5422 such as a cache 5404 is performed via a data bus 5423 .

A semiconductor device (cell) can be applied to many logic circuits including the power controller 5402 and the control device 5407 . In particular, it can be applied to all logic circuits that can be configured using standard cells. As a result, a small semiconductor device 5400 can be provided. Further, the semiconductor device 5400 capable of reducing power consumption can be provided. Further, the semiconductor device 5400 whose operation speed can be improved can be provided. Further, the semiconductor device 5400 capable of reducing fluctuation in power supply voltage can be provided.

A p-channel Si transistor and a transistor including the metal oxide (preferably the oxide containing In, Ga, and Zn) described in any of the above embodiments in a channel formation region are used in a semiconductor device (cell). By applying the semiconductor device (cell) to the semiconductor device 5400, the semiconductor device 5400 can be small. Further, the semiconductor device 5400 capable of reducing power consumption can be provided. Further, the semiconductor device 5400 whose operation speed can be improved can be provided. In particular, manufacturing costs can be kept low by using only p-channel Si transistors.

The control device 5407 comprehensively controls the operations of the PC 5408, pipeline registers 5409, pipeline registers 5410, ALU 5411, register file 5412, cache 5404, bus interface 5405, debug interface 5406, and power controller 5402, thereby It has the ability to decode and execute instructions contained in programs such as embedded applications.

The ALU 5411 has a function of performing various arithmetic processing such as four arithmetic operations and logic operations.

The cache 5404 has a function of temporarily storing frequently used data. PC5408 is a register having the function of storing the address of the instruction to be executed next. Although not shown in FIG. 20, the cache 5404 is provided with a cache controller that controls the operation of the cache memory.

A pipeline register 5409 is a register having a function of temporarily storing instruction data.

The register file 5412 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 5411, and the like.

The pipeline register 5410 is a register having a function of temporarily storing data used for arithmetic processing of the ALU 5411 or data obtained as a result of the arithmetic processing of the ALU 5411 .

The bus interface 5405 functions as a data path between the semiconductor device 5400 and various devices outside the semiconductor device 5400 . The debug interface 5406 functions as a signal path for inputting commands for controlling debugging to the semiconductor device 5400 .

The power switch 5403 has a function of controlling supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 . The various circuits described above belong to several power domains, and the various circuits belonging to the same power domain are controlled by the power switch 5403 as to whether or not a power supply voltage is supplied. Also, the power controller 5402 has a function of controlling the operation of the power switch 5403 .

The semiconductor device 5400 having the above structure can perform power gating. An example of the power gating operation flow will be described.

First, the CPU core 5401 sets the timing for stopping the supply of the power supply voltage in the register of the power controller 5402 . Next, the CPU core 5401 sends an instruction to start power gating to the power controller 5402 . Next, various registers and a cache 5404 included in the semiconductor device 5400 start saving data. Next, the power switch 5403 stops the supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 . Next, when an interrupt signal is input to the power controller 5402, supply of power supply voltage to various circuits included in the semiconductor device 5400 is started. Note that the power controller 5402 may be provided with a counter, and the counter may be used to determine the timing of starting the supply of the power supply voltage without depending on the input of the interrupt signal. The various registers and caches 5404 then begin restoring data. Execution of instructions in controller 5407 is then resumed.

Such power gating can be performed throughout the processor or in one or more logic circuits that make up the processor. Also, the power supply can be stopped even for a short time. For this reason, power consumption can be reduced spatially or temporally with fine granularity.

When power gating is performed, it is preferable that information held by the CPU core 5401 and the peripheral circuit 5422 can be saved in a short period of time. By doing so, the power can be turned on and off in a short period of time, and the effect of power saving is increased.

In order to save information held by the CPU core 5401 and the peripheral circuit 5422 in a short period of time, it is preferable that the flip-flop circuit can save data within the circuit (referred to as a flip-flop circuit that can be backed up). In addition, it is preferable that the SRAM cell can save data within the cell (referred to as a backup-capable SRAM cell). A flip-flop circuit or SRAM cell that can be backed up preferably has a transistor including a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, a flip-flop circuit or SRAM cell that can be backed up can retain information without power supply for a long period of time because the transistor has a low off-state current. In addition, since a transistor has a high switching speed, a flip-flop circuit or an SRAM cell that can be backed up can save and restore data in a short period of time in some cases.

An example of a flip-flop circuit that can be backed up will be described with reference to FIG.

A semiconductor device 5500 illustrated in FIG. 21 is an example of a flip-flop circuit that can be backed up. A semiconductor device 5500 includes a first memory circuit 5501 , a second memory circuit 5502 , a third memory circuit 5503 , and a reading circuit 5504 . A potential difference between the potential V1 and the potential V2 is supplied to the semiconductor device 5500 as a power supply voltage. One of the potential V1 and the potential V2 is at high level and the other is at low level. An example of the configuration of the semiconductor device 5500 is described below, taking as an example the case where the potential V1 is at a low level and the potential V2 is at a high level.

The first memory circuit 5501 has a function of holding data when a signal D including data is input while the power supply voltage is supplied to the semiconductor device 5500 . Then, the signal Q including the held data is output from the first memory circuit 5501 while the power supply voltage is supplied to the semiconductor device 5500 . On the other hand, the first memory circuit 5501 cannot hold data while the power supply voltage is not supplied to the semiconductor device 5500 . That is, the first memory circuit 5501 can be called a volatile memory circuit.

The second memory circuit 5502 has a function of reading and storing (or saving) data held in the first memory circuit 5501 . The third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502 . The reading circuit 5504 has a function of reading data held in the second memory circuit 5502 or the third memory circuit 5503 and storing it in the first memory circuit 5501 (or restoring it).

In particular, the third memory circuit 5503 has a function of reading and storing (or saving) data held in the second memory circuit 5502 even during a period when the power supply voltage is not supplied to the semiconductor device 5500 . have.

As illustrated in FIG. 21 , the second memory circuit 5502 includes a transistor 5512 and a capacitor 5519. A third memory circuit 5503 includes a transistor 5513 , a transistor 5515 , and a capacitor 5520 . The reading circuit 5504 includes a transistor 5510 , a transistor 5518 , a transistor 5509 , and a transistor 5517 .

The transistor 5512 has a function of charging and discharging the capacitor 5519 with electric charge according to data held in the first memory circuit 5501 . The transistor 5512 is preferably capable of charging and discharging the capacitor 5519 at high speed according to the data held in the first memory circuit 5501 . Specifically, the transistor 5512 preferably contains crystalline silicon (preferably polycrystalline silicon, more preferably single-crystalline silicon) in a channel formation region.

A conductive state or a non-conductive state is selected for the transistor 5513 according to the charge held in the capacitor 5519 . The transistor 5515 has a function of charging and discharging the capacitor 5520 with electric charge according to the potential of the wiring 5544 when the transistor 5513 is on. The transistor 5515 preferably has extremely low off-state current. Specifically, the transistor 5515 preferably contains a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region.

Specifically, one of the source and the drain of the transistor 5512 is connected to the first memory circuit 5501 . The other of the source and drain of the transistor 5512 is connected to one electrode of the capacitor 5519 , the gate of the transistor 5513 , and the gate of the transistor 5518 . The other electrode of the capacitor 5519 is connected to the wiring 5542 . One of the source and drain of the transistor 5513 is connected to the wiring 5544 . The other of the source and drain of the transistor 5513 is connected to one of the source and drain of the transistor 5515 . The other of the source and drain of the transistor 5515 is connected to one electrode of the capacitor 5520 and the gate of the transistor 5510 . The other electrode of the capacitor 5520 is connected to the wiring 5543 . One of the source and drain of the transistor 5510 is connected to the wiring 5541 . The other of the source and drain of transistor 5510 is connected to one of the source and drain of transistor 5518 . The other of the source and drain of transistor 5518 is connected to one of the source and drain of transistor 5509 . The other of the source and drain of the transistor 5509 is connected to one of the source and drain of the transistor 5517 and the first memory circuit 5501 . The other of the source and drain of the transistor 5517 is connected to a wiring 5540 . Although the gate of transistor 5509 is connected to the gate of transistor 5517 in FIG. 21, the gate of transistor 5509 does not necessarily have to be connected to the gate of transistor 5517 .

The transistor exemplified in the above embodiment can be applied to the transistor 5515 . Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can retain information for a long time without power supply. Since the transistor 5515 has good switching characteristics, the semiconductor device 5500 can perform high-speed backup and recovery.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 7)
In this embodiment, one mode of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

<Semiconductor wafers, chips>
FIG. 22A shows a top view of the substrate 711 before dicing. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711 . A semiconductor device or the like according to one embodiment of the present invention can be provided in the circuit region 712 .

A plurality of circuit regions 712 are each surrounded by an isolation region 713 . A separation line (also referred to as a “dicing line”) 714 is set at a position overlapping with the separation region 713 . A chip 715 including a circuit region 712 can be cut out from the substrate 711 by cutting the substrate 711 along the separation line 714 . An enlarged view of the chip 715 is shown in FIG.

A conductive layer, a semiconductor layer, or the like may be provided in the isolation region 713 . By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD (Electro-Static Discharge) that can occur during the dicing process can be alleviated, and a decrease in yield due to the dicing process can be prevented. In general, the dicing process is performed while supplying pure water in which carbon dioxide gas or the like is dissolved to lower the specific resistance to the cutting portion for the purpose of cooling the substrate, removing shavings, and preventing static electricity. By providing a conductive layer, a semiconductor layer, or the like in the isolation region 713, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. In addition, the productivity of semiconductor devices can be improved.

<Electronic parts>
An example of an electronic component using the chip 715 is described with reference to FIGS. 23A and 23B. The electronic component is also called a semiconductor package or an IC package. There are a plurality of standards, names, etc., for electronic components, depending on the terminal lead-out direction, the shape of the terminals, and the like.

An electronic component is completed by combining the semiconductor device shown in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed on the substrate 711 in the pre-process, a “back surface grinding step” of grinding the back surface of the substrate 711 (the surface on which the semiconductor device or the like is not formed) is performed (step S721). ). By thinning the substrate 711 by grinding, the size of the electronic component can be reduced.

Next, a "dicing process" is performed to separate the substrate 711 into a plurality of chips 715 (step S722). Then, a "die bonding process" is performed to bond the separated chips 715 onto individual lead frames (step S723). For the bonding of the chip 715 and the lead frame in the die bonding process, a suitable method is selected according to the product, such as resin bonding or tape bonding. Note that the chip 715 may be bonded onto the interposer substrate instead of the lead frame.

Next, a "wire bonding process" is performed to electrically connect the leads of the lead frame and the electrodes on the chip 715 with thin metal wires (step S724). A silver wire, a gold wire, or the like can be used as the thin metal wire. Also, wire bonding can be, for example, ball bonding or wedge bonding.

The wire-bonded chip 715 is subjected to a "sealing process (molding process)" in which it is sealed with epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, and the wire connecting the chip 715 and the lead can be protected from external mechanical force. decrease in reliability) can be reduced.

Next, a “lead plating step” is performed to plate the leads of the lead frame (step S726). The plating process prevents the leads from rusting, so that soldering can be performed more reliably when mounting on the printed circuit board later. Next, a "forming process" is performed for cutting and forming the leads (step S727).

Next, a "marking process" is performed to print (mark) the surface of the package (step S728). Then, the electronic component is completed through an "inspection step" (step S729) for checking the quality of the external shape and the presence or absence of malfunction.

A schematic perspective view of the completed electronic component is shown in FIG. FIG. 23B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 shown in FIG. 23B has leads 755 and a chip 715 . The electronic component 750 may have multiple chips 715 .

An electronic component 750 shown in FIG. 23B is mounted on a printed circuit board 752, for example. A plurality of such electronic components 750 are combined and electrically connected to each other on a printed circuit board 752 to complete a board (mounting board 754) on which the electronic components are mounted. The completed mounting substrate 754 is used for electronic equipment and the like.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 8)
<Electronic equipment>
A semiconductor device according to one embodiment of the present invention can be used for various electronic devices. 24A and 24B illustrate specific examples of electronic devices each including a semiconductor device according to one embodiment of the present invention.

FIG. 24A is an external view showing an example of an automobile. An automobile 2980 has a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. Automobile 2980 also includes an antenna, a battery, and the like.

An information terminal 2910 illustrated in FIG. 24B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, operation switches 2915, and the like. The display portion 2912 includes a display panel and a touch screen using a flexible substrate. The information terminal 2910 also includes an antenna, a battery, and the like inside a housing 2911 . The information terminal 2910 can be used as, for example, a smart phone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A notebook personal computer 2920 illustrated in FIG. 24C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The notebook personal computer 2920 also includes an antenna, a battery, and the like inside the housing 2921 .

A video camera 2940 illustrated in FIG. 24D includes a housing 2941, a housing 2942, a display portion 2943, operation switches 2944, a lens 2945, a connection portion 2946, and the like. An operation switch 2944 and a lens 2945 are provided on a housing 2941 , and a display section 2943 is provided on a housing 2942 . The video camera 2940 also includes an antenna, a battery, and the like inside a housing 2941 . The housings 2941 and 2942 are connected by a connecting portion 2946, and the angle between the housings 2941 and 2942 can be changed by the connecting portion 2946. FIG. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and the display/non-display of the image can be switched.

FIG. 24E shows an example of a bangle-type information terminal. An information terminal 2950 includes a housing 2951, a display portion 2952, and the like. The information terminal 2950 also includes an antenna, a battery, and the like inside a housing 2951 . The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display panel using a flexible substrate is included in the display portion 2952, the information terminal 2950 that is flexible, lightweight, and easy to use can be provided.

FIG. 24F shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display section 2962, a band 2963, a buckle 2964, an operation switch 2965, input/output terminals 2966, and the like. The information terminal 2960 also includes an antenna, a battery, and the like inside a housing 2961 . Information terminal 2960 is capable of running a variety of applications such as mobile telephony, e-mail, text viewing and composition, music playback, Internet communication, computer games, and the like.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, by touching an icon 2967 displayed on the display portion 2962, the application can be activated. The operation switch 2965 can have various functions such as time setting, power on/off operation, wireless communication on/off operation, manner mode execution/cancellation, and power saving mode execution/cancellation. . For example, the operating system installed in the information terminal 2960 can set the function of the operation switch 2965 .

In addition, the information terminal 2960 is capable of performing short-range wireless communication that conforms to communication standards. For example, a hands-free call can be made by intercommunicating with a headset capable of wireless communication. In addition, the information terminal 2960 has an input/output terminal 2966, and can directly exchange data with another information terminal via a connector. Also, charging can be performed through the input/output terminal 2966 . Note that the charging operation may be performed by wireless power supply without using the input/output terminal 2966 .

For example, a storage device using the semiconductor device of one embodiment of the present invention can retain control information, control programs, and the like of the above electronic devices for a long period of time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be achieved.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

10: Transistor, 11: Transistor, 12: Transistor, 13: Transistor, 100: Insulator, 102: Insulator, 105: Insulator, 110: Insulator, 112: Conductor, 120: Conductor, 120_1: Conductor , 120_2: conductor, 120a: conductor, 120b: conductor, 130: insulator, 130_1: insulator, 130_2: insulator, 130a: insulator, 130b: insulator, 140: conductor, 140_1: conductor , 140_2: conductor, 140a: conductor, 140b: conductor, 145: opening, 150: oxide, 150_1: oxide, 150_2: oxide, 150a: oxide, 150b: oxide, 150c: oxide, 151: oxide, 160: insulator, 161: insulator, 170: conductor, 171: conductor, 175: insulator, 176: insulator, 178: insulator, 180: insulator, 185: conductor, 185_1: conductor, 185_2: conductor, 185a: conductor, 185b: conductor, 190: conductor, 190_1: conductor, 190_2: conductor, 190a: conductor, 190b: conductor, 195: conductor, 195_1: conductor, 195_2: conductor, 195a: conductor, 195b: conductor, 200: conductor, 200_1: conductor, 200_2: conductor, 200a: conductor, 200b: conductor, 210: insulator, 218: Conductor, 246: Conductor, 248: Conductor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator , 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator , 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator , 386: Conductor, 711: Substrate, 712: Circuit area, 713: Separation area, 714: Separation line, 715: Chip, 750: Electronic component, 752: Printed board, 754: Mounting board, 755: Lead, 1000: 1400: DOSRAM 1405: controller 1410: row circuit 1411: decoder 1412: word line driver circuit 1413: column selector 1414: sense amplifier driver times 1415: column circuit 1416: global sense amplifier array 1417: input/output circuit 1420: memory cell and sense amplifier array 1422: memory cell array 1423: sense amplifier array 1425: local memory cell array 1426: local sense amplifier array, 1444: switch array, 1445: memory cell, 1446: sense amplifier, 1447: global sense amplifier, 1500: insulator, 1600: NOSRAM, 1610: memory cell array, 1611: memory cell, 1612: memory cell, 1613: Memory Cell 1614: Memory Cell 1640: Controller 1650: Row Driver 1651: Row Decoder 1652: Word Line Driver 1660: Column Driver 1661: Column Decoder 1662: Write Driver 1663: DAC 1670: Output Driver 1671: Selector 1672: ADC 1673: Output buffer 2000: Transistor 2910: Information terminal 2911: Case 2912: Display unit 2913: Camera 2914: Speaker unit 2915: Operation switch 2916: External connection unit, 2917: microphone, 2920: notebook personal computer, 2921: housing, 2922: display unit, 2923: keyboard, 2924: pointing device, 2940: video camera, 2941: housing, 2942: housing, 2943 : display unit, 2944: operation switch, 2945: lens, 2946: connection unit, 2950: information terminal, 2951: housing, 2952: display unit, 2960: information terminal, 2961: housing, 2962: display unit, 2963: Band 2964: Buckle 2965: Operation switch 2966: Input/output terminal 2967: Icon 2980: Automobile 2981: Body 2982: Wheel 2983: Dashboard 2984: Light 3000: Transistor 3001: Wiring 3002: wiring, 3003: wiring, 3004: wiring, 3005: wiring, 3110: OS-FPGA, 3111: controller, 3112: word driver, 3113: data driver, 3115: programmable area, 3117: IOB, 3119: core, 3120 : LAB, 3121: PLE, 3123: LUT block, 3124: register block, 3125: selector, 3126: CM, 3127: power switch, 3128: CM, 3130: SAB, 3131: SB, 3133: PRS, 3133[0]: PRS, 3133[1]: PRS, 3135: CM, 3137: memory circuit, 31378: memory circuit, 3140: OS-FF, 3140[1]: OS -FF, 3140 [2]: OS-FF, 3141: FF, 3142: Shadow register, 3143: Memory circuit, 3143B: Memory circuit, 3188: Inverter circuit, 3189: Inverter circuit, 5400: Semiconductor device, 5401: CPU core , 5402: power controller, 5403: power switch, 5404: cache, 5405: bus interface, 5406: debug interface, 5407: control unit, 5408: PC, 5409: pipeline register 5410: pipeline register, 5411: ALU, 5412 : register file, 5421: power management unit, 5422: peripheral circuit, 5423: data bus, 5500: semiconductor device, 5501: memory circuit, 5502: memory circuit, 5503: memory circuit, 5504: readout circuit, 5509: transistor, 5510 : transistor, 5512: transistor, 5513: transistor, 5515: transistor, 5517: transistor, 5518: transistor, 5519: capacitive element, 5520: capacitive element, 5540: wiring, 5541: wiring, 5542: wiring, 5543: wiring 5544 wiring

Claims (1)

a first conductor;
a first insulator on the first conductor;
a second conductor on the first insulator;
an oxide having regions in contact with side surfaces of the first conductor, the first insulator, and the second conductor;
a second insulator on the oxide;
a third conductor on the second insulator;
a third insulator over the first conductor, over the first insulator, and over the second conductor;
the second insulator has a region facing side surfaces of the first conductor, the first insulator, and the second conductor through the oxide;
The third conductor has a region facing side surfaces of the first conductor, the first insulator, and the second conductor through the oxide and the second insulator. death,
the third insulator has an opening,
The semiconductor device according to claim 1, wherein the oxide, the second insulator, and the third conductor have a region embedded in the opening.

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