JP7122229B2 - Semiconductor device and power converter using the same - Google Patents

Description

The present invention relates to a power semiconductor device, a power conversion device using the same, a motor system, an automobile, and a railway vehicle.

In a power metal insulator semiconductor field effect transistor (MISFET), which is one of power semiconductor devices, a power MISFET using a silicon (Si) substrate (hereinafter referred to as a Si power MISFET) has conventionally been used. was mainstream.

On the other hand, a power MISFET using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) (hereinafter referred to as a SiC power MISFET) has higher breakdown voltage and lower loss than the Si power MISFET. It is possible. For this reason, particular attention is focused in the field of power-saving or environmentally friendly inverter technology.

Compared to Si power MISFET, SiC power MISFET can lower the on-resistance at the same breakdown voltage. This is because silicon carbide (SiC) has a dielectric breakdown field strength about seven times as large as that of silicon (Si), and the epitaxial layer that becomes the drift layer can be made thinner. However, considering the original characteristics that should be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained yet, and from the viewpoint of highly efficient use of energy, further reduction in on-resistance is desired. ing.

In Patent Document 1, the high channel parasitic resistance of the conventional DMOS (Double diffused Metal Oxide Semiconductor) structure is improved by forming a trench in the body layer of the (0001) plane substrate to achieve high channel mobility. It is disclosed that the (11-20) plane or (1-100) plane of degree is used to widen the effective channel width (this structure is hereinafter referred to as a trench type DMOS). As a result, the channel parasitic resistance can be reduced and the on-resistance can be reduced without impairing the reliability of the trench bottom when turned off.

Further, Patent Document 2 discloses a structure in which a shallow impurity region (hereinafter referred to as an electric field relaxation layer) having the same polarity as that of the body layer is formed on the substrate surface to increase the withstand voltage of the trench type DMOS.

WO2015/177914 WO2016/116998

In the trench type DMOS disclosed in Patent Document 1, since the bottom of the trench is formed in the body layer, it is necessary to form a current diffusion layer with a higher concentration than the body layer. Since the concentration of the current diffusion layer is much higher than that of the epitaxial layer, it becomes difficult to form a depletion layer necessary for increasing the breakdown voltage of the device, which may reduce the breakdown voltage. Further, due to the relative formation position offset (hereinafter referred to as misalignment) between the current diffusion layer and the body layer, a high concentration region is formed in the JFET region existing between the body layers, resulting in depletion. As a result of the inhibition, the breakdown voltage determined by the weakest cell in the chip can be greatly reduced.

Since the electric field relaxation layer of Patent Document 2 is formed on the substrate surface, it has no effect on misalignment of the current diffusion layer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of improving the breakdown voltage drop due to the current diffusion layer of a trench type DMOS and having high performance and high reliability.

A semiconductor device according to an embodiment of the present invention includes a first conductivity type SiC substrate and a first conductivity type epitaxial layer formed on a first main surface of the SiC substrate and having an impurity concentration lower than that of the SiC substrate. a layer, a drain region formed on a second main surface facing the first main surface of the SiC substrate, first and second body layers of a second conductivity type formed on the epitaxial layer, and a first body. The impurity concentration of the epitaxial layer is in contact with the first source region of the first conductivity type formed in the layer and the JFET region, which is an epitaxial layer sandwiched between the first and second body layers, and the first body layer. a first region of a first conductivity type having an impurity concentration higher than the impurity concentration; a second region of a second conductivity type formed in the JFET region; a first source region; a first body layer; an insulating film formed on the inner wall of the first trench; and a gate electrode formed on the insulating film of the first trench.

To provide a semiconductor device with high performance and high reliability.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

1 is a top view of a semiconductor chip on which a plurality of SiC power MISFETs are mounted; FIG. 1 is a bird's-eye view of a main part of a SiC power MISFET; FIG. 3 is a bird's-eye view of the main part at the terminal end of the SiC power MISFET; FIG. 2B is a cross-sectional view of the main part of the SiC power MISFET taken along line segment AA' in FIG. 2A; FIG. 2B is a cross-sectional view of essential parts of the SiC power MISFET taken along line segment BB' in FIG. 2A; FIG. 2B is a cross-sectional view of the main part of the SiC power MISFET taken along line segment CC' in FIG. 2A; FIG. 10 is a diagram for explaining the depletion layer structure of a SiC power MISFET with a trench type DMOS (no misalignment) when the channel is off; FIG. 10 is a diagram for explaining the depletion layer structure of a SiC power MISFET based on a trench type DMOS (with misalignment) when the channel is off; FIG. 10 is a diagram illustrating the depletion layer structure of the SiC power MISFET (with misalignment) according to Example 1 when the channel is off; FIG. 4 is a diagram explaining a manufacturing process of the silicon carbide semiconductor device according to Example 1; FIG. 4 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P1; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2; FIG. 12 is a fragmentary cross-sectional view of the silicon carbide semiconductor device at the same location as in FIG. 6 during the manufacturing process of the silicon carbide semiconductor device, continued from FIG. 11 ; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P2; FIG. 10 is a top view of the main part of the silicon carbide semiconductor device in process P4; 15 is a fragmentary cross-sectional view taken along line AA' of FIG. 14 of the silicon carbide semiconductor device in process P4; FIG. 15 is a fragmentary cross-sectional view taken along line segment BB' of FIG. 14 of the silicon carbide semiconductor device in process P4; FIG. 15 is a fragmentary cross-sectional view taken along line AA' of FIG. 14 of the silicon carbide semiconductor device in process P4; FIG. FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P5; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P5; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P5; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6; FIG. 10 is a cross-sectional view of the main part of the silicon carbide semiconductor device in process P6; FIG. 10 is a cross-sectional view of a main part of a SiC power MISFET according to Example 2; FIG. 10 is a diagram illustrating the depletion layer structure of a SiC power MISFET based on a trench type DMOS (no misalignment) when the channel is on; FIG. 10 is a diagram illustrating the depletion layer structure of the SiC power MISFET (no misalignment) according to Example 2 when the channel is on; FIG. 11 is a cross-sectional view of a main part of a silicon carbide semiconductor device in a manufacturing process of a silicon carbide semiconductor device according to Example 2; FIG. 10 is a diagram illustrating the depletion layer structure of the SiC power MISFET (with large misalignment) according to Example 1 when the channel is off; FIG. 10 is a diagram illustrating the depletion layer structure of the SiC power MISFET (with large misalignment) according to Example 3 when the channel is off; FIG. 10 is a diagram illustrating the depletion layer structure of the SiC power MISFET according to Example 4 when the channel is on; 4 is a diagram illustrating the depletion layer structure of the SiC power MISFET according to Example 1 when the channel is on; FIG. FIG. 10 is a diagram for explaining the depletion layer structure when the channel of the SiC power MISFET obtained by combining Example 1, Example 2, Example 3, and Example 4 is on; FIG. 10 is a diagram for explaining the depletion layer structure when the channel of the SiC power MISFET (with misalignment) obtained by combining Examples 1, 2, 3, and 4; FIG. 11 is a cross-sectional view of a main part of a SiC power MISFET according to Example 5; FIG. 11 is a cross-sectional view of a main part of a SiC power MISFET according to Example 5; FIG. 11 is a top view of a main portion of a silicon carbide semiconductor device according to Example 6; It is a circuit diagram of a power conversion device (inverter). It is a circuit diagram of a power conversion device (inverter). 1 is a configuration diagram of an electric vehicle; FIG. 1 is a circuit diagram of a boost converter; FIG. 1 is a configuration diagram of a railway vehicle; FIG.

In the following embodiments, when necessary, they are divided into a plurality of sections or embodiments for explanation, but unless otherwise specified, they are not unrelated to each other, and one There is a relationship of part or all of the modification, details, supplementary explanation, etc.

Further, in the drawings used in the following embodiments, even a plan view may be hatched to make the drawing easier to see. In addition, in all the drawings for explaining the following embodiments, in principle, the same reference numerals are given to the components having the same functions, and the repeated description thereof will be omitted. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<<Silicon carbide semiconductor device>>
A structure of a silicon carbide semiconductor device according to Example 1 will be described with reference to FIG. FIG. 1 is a top view of essential parts of a semiconductor chip on which a plurality of SiC power MISFETs are mounted.

As shown in FIG. 1, a semiconductor chip 1 on which a silicon carbide semiconductor device is mounted has an active region (SiC power MISFET formation and an element formation region) and a peripheral formation region surrounding the active region in plan view. In the peripheral formation region, a plurality of p-type floating field limited rings (FLR) 3 formed so as to surround the active region in plan view, and a plurality of p-type An n-type guard ring 4 is formed so as to surround the FLR 3 of.

On the surface side of the active region of an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as SiC epitaxial substrate), a gate electrode of a SiC power MISFET, an n ⁺⁺ -type source region, a channel region, and the like are formed. An n ⁺ -type drain region of the SiC power MISFET is formed on the back side of the epitaxial substrate.

By forming a plurality of p-type FLRs 3 around the active region, the maximum electric field portion sequentially shifts to the outer p-type FLRs 3 when turned off, and breakdown occurs at the outermost p-type FLRs 3. A silicon carbide semiconductor device can have a high breakdown voltage. Although FIG. 1 shows an example in which three p-type FLRs 3 are formed, the present invention is not limited to this. In addition, the n ⁺⁺ type guard ring 4 has a function of protecting the SiC power MISFET formed in the active region.

A plurality of SiC power MISFETs 6 formed in the active region has a stripe pattern in a plan view, and the gate electrodes of all SiC power MISFETs are connected to the respective stripe patterns by lead wiring (gate bus lines). It is electrically connected to the gate wiring electrode 8 .

A plurality of SiC power MISFETs are covered with a source wiring electrode 2 , and the potential fixed layers of the source and body layers of each SiC power MISFET are connected to the source wiring electrode 2 . The source wiring electrode 2 is connected to an external wiring through a source opening 7 provided in a passivation film that protects the semiconductor chip 1 . The gate wiring electrode 8 is formed apart from the source wiring electrode 2 and connected to the gate electrode of each SiC power MISFET. Similarly, the gate wiring electrode 8 is connected to the external wiring through the gate opening 5 provided in the passivation film that protects the semiconductor chip 1 . Also, the n ⁺ -type drain region formed on the back side of the n-type SiC epitaxial substrate is electrically connected to a drain wiring electrode (not shown) formed on the entire back surface of the n-type SiC epitaxial substrate. is doing.

Next, the structure of the SiC power MISFET in this embodiment will be described. FIG. 2A is a bird's-eye view of the essential parts of the SiC power MISFET.

An n ⁻ -type epitaxial layer made of silicon carbide (SiC) having an impurity concentration lower than that of the n ⁺ -type SiC substrate on the surface (first main surface) of an n ⁺ -type SiC substrate 107 made of silicon carbide (SiC). 101 is formed. The n ⁻ -type epitaxial layer 101 functions as a drift layer. The thickness of the epitaxial layer 101 is, for example, approximately 5 to 50 μm.

A p-type body layer (well region) 102 is formed in epitaxial layer 101 to have a predetermined depth from the surface of epitaxial layer 101 . An n ⁺ -type source region 103 containing nitrogen as an impurity is formed in the p-type body layer 102 at a predetermined depth from the surface of the epitaxial layer 101 .

A part of the epitaxial layer 101 sandwiched between the adjacent body layers 102a and 102b is called a JFET region 104. As shown in FIG. An n ⁺ -type current diffusion layer 105 is formed with a predetermined depth from the surface of the epitaxial layer 101 so as to extend over the p-type body layer 102 and the JFET region 104 . A p-type potential fixing layer 130 is formed in a part of the region sandwiched between the n ⁺ -type current diffusion layer 105a and the n ⁺ -type current diffusion layer 105b. This p-type potential fixing layer 130 may be in contact with the current diffusion layer 105 . Moreover, it does not necessarily have to be located in the center of the two adjacent current diffusion layers 105a and 105b.

A plurality of trenches 106 are formed from the n ⁺⁺ -type source region 103 across the p-type body layer 102 and over the n ⁺ -type current diffusion layer 105 . The bottom of trench 106 is in contact with p-type body layer 102 . Although not shown in FIG. 2A, a gate insulating film 110 and an insulating film 117 are formed on the trench 106 as will be described later. A gate electrode 111 is formed on the gate insulating film 110 .

FIG. 2B shows a bird's-eye view of the termination region of the element forming portion. The JFET region 104 is terminated by the p-type body layer 102, and the p-type potential pinning layer 130 may or may not be connected to the body layer 102 forming the termination. When potential fixed layer 130 is not connected to body layer 102, the potential of p-type potential fixed layer 130 is fixed at a value substantially equal to the gate potential when the gate is turned off. This is because the potential of the potential fixed layer 130 is determined by the capacitance division of the pn diode and the gate insulating film with respect to the gate potential, and the capacitance of the pn diode is generally much lower. On the other hand, when connected to the body layer 102, it is connected to the source electrode through the p-type body layer 102 and fixed at the source potential. When the potential fixed layer 130 and the body layer 102 are not connected, the gap width d1 is preferably smaller than the gap width d2 between the p-type potential fixed layer 130 and the p-type body layer 102 in the periodic structure. This is to avoid breakdown from the terminal portion due to a decrease in breakdown voltage, since the breakdown voltage decreases as the width of the gap increases.

The structure of Example 1 will be described in detail with reference to FIGS. 3A to 5. FIG. FIG. 3A is a cross-sectional structure in a plane perpendicular to the main surface of the SiC substrate that includes a line segment AA' on the main surface of the substrate that is parallel to the longitudinal direction of the trench and passes through the region where the trench is formed in FIG. 2A. As shown in FIG. 3A, except for the source contact region (metal silicide layer) 113, the insulating film 117 is formed on the substrate main surface 134 including the flat portion 139 on the surface of the JFET region 104 sandwiched between the body layers 102. As shown in FIG. , the gate electrode 111 is formed on the gate insulating film 110 and the insulating film 117 so as to extend to the source region 103, the body layer 102 and the current diffusion layer 105, and is connected to the adjacent trench.

On the other hand, FIG. 3B is a cross-sectional structure in a plane perpendicular to the main surface of the SiC substrate that includes a line segment BB′ on the main surface of the substrate that is parallel to the longitudinal direction of the trench in FIG. 2A and passes through a region where no trench is formed. An insulating film 117 exists on the entire main surface of the substrate except for the source contact region 113 , and the gate electrode 111 is connected to the source region 103 , the body layer 102 , the current diffusion layer 105 , the JFET region 104 and the p-type potential fixing layer 130 . It is formed on insulating film 117 so as to extend.

FIG. 4 shows a cross-sectional structure in a plane perpendicular to the SiC substrate surface, including a line segment CC′ on the main surface of the substrate which is perpendicular to the longitudinal direction of the trench and passes through the region where the p-type potential fixed layer 130 is formed in FIG. is. An insulating film 117 exists on the SiC substrate surface, and the gate electrode 111 is connected to the adjacent cell on the insulating film 117 . A p-type potential fixed layer 130 is formed at a predetermined depth from the SiC substrate surface and connected to adjacent cells. At the end portion of the active region, as described above, the p ⁺ -type potential fixing layer 130 may or may not be connected to the body layer 120 .

The depth (first depth L1) of the p-type body layer 102 from the surface of the epitaxial layer 101 is, for example, about 0.5 to 2.0 μm. Further, the depth (third depth L3) of the n ⁺⁺ -type source region 103 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 1.0 μm. The depth (fourth depth L4) of the n ⁺ -type current diffusion layer 105 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 1.0 μm. A non-overlapping width W1 between the p-type body layer 102 and the n ⁺ -type current diffusion layer 105 is, for example, about 0.1 to 2.0 μm. The depth of trench 106 from the surface of epitaxial layer 101 (sixth depth L6) is shallower than the depth of p-type body layer 102 from the surface of epitaxial layer 101 (first depth L1), for example 0. 0.1 to 1.5 μm. The length of the trench 106 in the direction parallel to the channel length is, for example, about 0.5 to 3.0 μm. The length of the trench 106 in the direction parallel to the channel width is, for example, about 0.1 to 2.0 μm. A trench interval in a direction parallel to the channel width is, for example, about 0.1 to 2.0 μm. The depth (second depth L2) of the p ⁺⁺ -type body layer contact region 109 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 0.5 μm. The p-type potential fixing layer 130 has a depth of about 0.1 to 2.0 μm, for example, and a width narrower than that of the JFET region 104, for example, about 0.1 to 5.0 μm. The distance between the n ⁺ -type current diffusion layer 105 and the p-type potential fixing layer 130 can be arbitrarily specified, and is, for example, about 0 to 2.0 μm. The gate insulating film 110 has a thickness of, for example, 0.005 μm to 0.015 μm. The thickness of the thick insulating film 117 is always thicker than that of the gate insulating film 110, and is, for example, about 0.1 to 3.0 μm.

Note that " ^- " and " ⁺ " are symbols representing the relative impurity concentration of n-type or p-type conductivity, for example, "n-" ^, "n", "n ⁺ ", "n ⁺⁺ , the impurity concentration of the n-type impurity increases in the order of .

A preferable range of the impurity concentration of the n ⁺ -type SiC substrate 107 is, for example, 1×10 ¹⁸ to 1×10 ²¹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁻ -type epitaxial layer 101 is, for example, 1×10 ¹⁴ to 1×10 ¹⁷ cm ⁻³ . A preferable impurity concentration range of the p-type body layer 102 is, for example, 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ . A preferable range of the maximum impurity concentration of the p-type body layer 102 is, for example, 1×10 ¹⁷ to 1×10 ¹⁹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁺⁺ -type source region 103 is, for example, 1×10 ¹⁹ to 1×10 ²¹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁺ -type current diffusion layer 105 is, for example, 5×10 ¹⁶ to 5×10 ¹⁸ cm ⁻³ . A preferable impurity concentration range of the p ⁺⁺ -type body layer contact region 109 is, for example, 1×10 ¹⁹ to 1×10 ²¹ cm ⁻³ . A preferable range of the maximum impurity concentration of the p-type potential fixing layer 130 is higher than that of the n ⁺ -type current diffusion layer 105, and is 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ .

Next, features of the configuration of the SiC power MISFET according to Example 1 will be described with reference to FIGS. 5 to 7. FIG.

The structure of the depletion layer of the conventional trench-type DMOS when the channel is off will be described with reference to FIG. A depletion layer edge 140a extending from the SiC epitaxial substrate surface 141 above the JFET region 104 and depletion layer edges 140b and 140c extending from the body layer 102 develop as the drain-source applied voltage increases. Contact between depletion layer end 140a extending from SiC epitaxial substrate surface 141 and depletion layer ends 140b and 140c extending from body layer 102 insulates the JFET region by depletion. As a result, the potential of the JFET region 104 is reduced, and the gate-drain breakdown voltage determined by the electric field applied to the gate insulating film 110 and the electric field applied mainly to the junction between the body layer 102 and the JFET region 104 or the epitaxial layer 101 are determined. can increase the main withstand voltage. At this time, since current diffusion layer 105 has a higher concentration than JFET region 104, a depletion layer is less likely to develop in current diffusion layer 105. FIG. Therefore, if misalignment occurs in the current diffusion layer 105, this depletion will be greatly affected, and the withstand voltage will be greatly reduced.

The structure of the depletion layer in the conventional trench type DMOS when misalignment occurs in the current diffusion layer 105 will be described with reference to FIG. When the current diffusion layer 105 shifts to the right side of the substrate, the starting point of the depletion layer end 140a becomes farther from the body layer 102 on the left side, making it difficult to connect the depletion layer end 140a and the depletion layer end 140b. As a result, the potential near the surface of the gate insulating film 110 and the potential of the JFET region 104 remain at the drain potential, and a high electric field is applied to the junction between the gate insulating film 110 or the body layer 102 and the JFET region 104. It leads to insulation breakdown. The withstand voltage of a power device is determined by the minimum withstand voltage of many parallel cells (called a minimum ring model). As the misalignment, it is necessary to assume misalignment that is the sum of misalignment of the body layer 102 with respect to the lithography reference mark, misalignment of the current diffusion layer 105, and rotation of the mask. , the decrease in breakdown voltage due to the misalignment becomes remarkable.

The fact that the device structure of Example 1 improves the structure of the depletion layer will be described with reference to FIG. Also in the device of FIG. 7, it is assumed that the current diffusion layer 105 is shifted horizontally to the right side of the substrate as in FIG. In this case, unlike the trench DMOS shown in FIG. 6, a depletion layer edge 140d extends from the p-type potential fixed layer 130 instead of the depletion layer edge 140a from the SiC substrate surface. Since the starting point of the edge 140d of the depletion layer is located deep from the SiC epitaxial substrate surface 141, the current diffusion layer 105 is less likely to affect this development. Therefore, even when the current diffusion layer 105 is misaligned, depletion is possible, and the withstand voltage of the entire device determined by the minimum ring model is improved.

Furthermore, in the region where the p-type potential fixed layer 130 exists, the pn diode of the JFET region 104-potential fixed layer 130 is inserted in series between the drain and gate electrodes, so the feedback capacitance is greatly reduced. Further, by appropriately designing the aspect ratio of the p-type potential fixing layer 130 to the p-type body layer 102, depletion can be adjusted, so that the feedback capacitance-drain voltage characteristic can be controlled to a desirable characteristic. This effect reduces switching losses and improves reliability with respect to dynamic characteristics such as false firing. As described above, the structure of the first embodiment makes it possible to provide a device that simultaneously achieves lower loss and higher reliability than those of the conventional MOS structure and trench MOS structure.

In addition, it is possible to improve the breakdown voltage and switching characteristics while maintaining the advantages of trench type DMOS with high channel mobility and wide channel width, so it is possible to provide a highly reliable and high performance SiC power MISFET. become.

<<Method for Manufacturing Silicon Carbide Semiconductor Device>>
A method for manufacturing a silicon carbide semiconductor device according to Example 1 will be described below in order of steps with reference to the drawings. 8A to 8D are process diagrams for explaining the manufacturing method of the semiconductor device according to the first embodiment.

<Process P1>
In step P1, an epitaxial layer (drift layer) is formed. First, as shown in FIG. 9, an n ⁺ -type 4H—SiC substrate 107 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 107 . This n-type impurity is nitrogen (N), for example, and the impurity concentration of this n-type impurity is, for example, in the range of 1×10 ¹⁸ to 1×10 ²¹ cm ⁻³ . In addition, the n ⁺ -type SiC substrate 107 has a silicon face and a carbon face and an anisotropic polar face ^. However, it does not limit the use of the carbon surface at all.

Next, an n ⁻ -type epitaxial layer 101 of silicon carbide (SiC) is formed on the surface (first main surface) of the n ⁺ -type SiC substrate 107 by an epitaxial growth method. The n ⁻ -type epitaxial layer 101 is doped with an n-type impurity whose impurity concentration is lower than that of the n ⁺ -type SiC substrate 107 . The impurity concentration of the n ⁻ -type epitaxial layer 101 depends on the device rating of the SiC power MISFET, but is, for example, in the range of 1×10 ¹⁴ to 1×10 ¹⁷ cm ⁻³ . Also, the thickness of the n ⁻ -type epitaxial layer 101 is, for example, 5 to 50 μm. Through the above steps, a SiC epitaxial substrate having an n ⁺ type SiC substrate 107 and an n ⁻ type epitaxial layer 101 is formed.

<Process P2>
Various impurities are implanted in process P2. As shown in FIG. 9 , n ⁺ -type SiC substrate 107 has a predetermined depth (seventh depth L7) from the back surface (second main surface) of n ⁺ -type SiC substrate 107, and n to the back surface of n + -type SiC substrate 107. A ⁺ type drain region 108 is formed. The impurity concentration of the n ⁺ -type drain region 108 is, for example, in the range of 1×10 ¹⁹ to 1×10 ²¹ cm ⁻³ .

Next, as shown in FIG. 10A, a mask M11 is formed on the surface of the n ⁻ -type epitaxial layer 101. Next, as shown in FIG. The thickness of the mask M11 is, for example, about 1.0 to 3.0 μm. The width of the mask M11 in the element formation region is, for example, about 1.0 to 10.0 μm. As the mask material, an inorganic SiO ₂ film, a Si film, a SiN film, an organic resist film, a polyimide film, or the like can be used.

Next, p-type impurities such as aluminum atoms (Al) are ion-implanted into the n ⁻ -type epitaxial layer 101 through the mask M11. As a result, the p-type body layer 102 is formed in the element formation region of the n ⁻ -type epitaxial layer 101 . Although not shown, a p-type FLR 3 is simultaneously formed around the element formation region. The structure of the termination portion is not limited to this, and may be, for example, a Junction Termination Extension (JTE) structure. The p-type FLR 3 may be formed using a mask different from this step.

The depth (first depth L1) of the p-type body layer 102 from the surface of the epitaxial layer 101 is, for example, about 0.5 to 2.0 μm. Also, the impurity concentration of the p-type body layer 102 is, for example, in the range of 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ . Also, the maximum impurity concentration of the p-type body layer 102 is, for example, in the range of 1×10 ¹⁷ to 1×10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 10B, after removing the mask M11, a mask M12 is formed. The thickness of the mask M12 is, for example, about 0.5 to 3.0 μm. The width of the mask M12 in the element forming region is, for example, about 2.0 to 10.0 μm. The mask M12 is formed of, for example, a resist film.

Next, p-type impurities such as aluminum atoms (Al) are ion-implanted into the n ⁻ -type epitaxial layer 101 through the mask M12. Thereby, a p-type potential fixed layer 130 is formed in the JFET region 104 between the p-type body layers 102 . The depth of the p-type potential fixed layer 130 from the surface of the epitaxial layer 101 is, for example, about 0.1 to 2.0 μm. Also, the impurity concentration of the p-type potential fixed layer 130 is, for example, in the range of 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ .

The method of forming the p-type body layer 102 and the p-type potential fixed layer 130 described above can be self-aligned. As shown in FIG. 10C, a mask MSA1 is formed and a mask MSA2 is formed to partially overlap it. A p-type body layer 102 is formed by ion implantation through the masks MSA1 and MSA2. Subsequently, as shown in FIG. 10D, after selectively removing the mask MSA2, a mask MSA3 is formed to partially overlap the mask MSA1. A p-type potential fixed layer 130 is formed by ion implantation through the masks MSA1 and MSA3. The mask MSA1 uses a material that is not etched when the masks MSA2 and MSA3 are removed. For example, a SiO ₂ film, a Si film, or a SiN film can be used for the mask MSA1, and a resist film can be used for the masks MSA2 and MSA3. The thickness of the mask MSA1, mask MSA2, and mask MSA3 is, for example, about 0.5 to 3.0 μm. The width of the mask MSA1 is, for example, about 1.0 to 5.0 μm. The widths of the masks MSA2 and MSA3 are values obtained by subtracting the overlapping width with the mask MSA1 from the values of the masks M11 and M12, respectively. The overlapping width of the mask MSA1 and the mask MSA2 or the mask MSA3 is 0.3 μm to 4.7 μm. This overlap width is preferably larger than the expected misalignment width of the lithographic apparatus used. With the above measures, it is possible to improve the accuracy of the relative positions of the p-type body layer 102 and the p-type potential fixing layer 130, improve the withstand voltage and loss of the device, and improve the yield.

Next, as shown in FIG. 11, after removing all the masks on the substrate, a mask M13 is formed of, for example, a resist film. The thickness of the mask M13 is, for example, approximately 0.5 to 3.0 μm. The width of the mask M13 is, for example, about 0.5 to 4.0 μm. The mask M13 opens the n ⁺⁺ -type source region 103 forming portion. Although not shown, the mask M13 is also provided with an opening in a region where the guard ring 4 is formed on the outer circumference of the FLR3. Through the mask M13, n-type impurities such as nitrogen atoms (N) and phosphorus atoms (P) are ion-implanted into the p-type body layer 102 to form an n ⁺⁺ -type source region 103 (not shown). , an n ⁺⁺ type guard ring 4 is formed in the peripheral formation region.

Next, as shown in FIG. 12, the mask M13 is removed and a mask M14 is formed. The mask M14 is formed of, for example, a resist film. The thickness of the mask M14 is, for example, approximately 0.5 to 3.0 μm. The mask M14 opens the p ⁺⁺ type body layer contact region 109 formation portion. A p ⁺⁺ -type body layer contact region 109 is formed by ion-implanting a p-type impurity into the p-type body layer 102 through the mask M14. The depth (second depth L2) of the p ⁺⁺ -type body layer contact region 109 from the surface of the p-type body layer 102 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the p ⁺⁺ -type body layer contact region 109 is, for example, in the range of 1×10 ¹⁹ to 1×10 ²¹ cm ⁻³ .

Next, as shown in FIG. 13, the mask M14 is removed and a mask M15 is formed of, for example, a resist film. The thickness of the mask M15 is, for example, approximately 1 to 4 μm. The mask M15 has an opening for forming the n ⁺ -type current diffusion layer 105 . An n ⁺ -type current diffusion layer 105 is formed by ion-implanting an n-type impurity into the n ⁻ -type epitaxial layer 101 and the p-type body layer 102 through the mask M15.

<Step P3>
Activation annealing is performed in step P3. After removing the mask M15, although not shown, a carbon (C) film is deposited on the front and rear surfaces of the SiC epitaxial substrate by plasma CVD, for example. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front and back surfaces of the SiC epitaxial substrate with this carbon (C) film, the SiC epitaxial substrate is subjected to heat treatment at a temperature of 1500° C. or higher for about 2 to 3 minutes. As a result, each impurity ion-implanted into the SiC epitaxial substrate is activated. After the heat treatment, the carbon (C) film is removed by oxygen plasma treatment, for example.

<Step P4>
A trench is formed in process P4. 14 is a top view of essential parts of SiC power MISFETs connected in parallel, FIG. 15A is a cross-sectional view of essential parts taken along line segment AA' passing through the region where the trenches of FIG. 14 are formed, and FIG. FIG. 10 is a cross-sectional view of a line segment BB' passing through a non-formed region; As shown in FIGS. 15A and 15B, a mask M16 is formed from an insulating film such as a silicon oxide film. The thickness of the mask M16 is preferably thicker than the gate insulating film 110 to be formed in a later step, and is, for example, about 0.01 to 4 μm. The mask M16 is provided with openings in regions where trenches 106 will be formed in a later step (FIG. 15A). Subsequent steps will be described with reference to FIGS.

As shown in FIG. 16, an anisotropic dry etching process is used to form a trench 106 extending into the n ⁺⁺ -type source region 103, the p-type body layer 102, and the n ⁺ -type current spreading layer 105. As shown in FIG. Form. The depth of the trench to be formed is shallower than the depth of the p-type body layer 102 . The depth of the trench to be formed is, for example, about 0.1 to 1.5 μm. The length of the trench in the direction parallel to the channel length is, for example, about 0.5 to 3.0 μm. The length of the trench in the direction parallel to the channel width is, for example, about 0.1 to 1.0 μm. A trench interval in a direction parallel to the channel width is, for example, about 0.1 to 1.0 μm. During this dry etching process, the shoulders of the openings of the mask M16 are rounded to form the insulating film 117, which reduces the reliability of the insulating film between the JFET region 104 sandwiched between the body layers 102 and the gate electrode and between the source region 103 and the gate electrode. In addition to improving the

<Process P5>
Step P5 forms a gate stack. As shown in FIG. 17, the gate insulating film 110 is formed on the surface of the epitaxial layer 101, the surface of the trench 106 and the surface of the thick insulating film 117 by an isotropic deposition method. The gate insulating film 110 has a uniform film thickness on the bottom surface 135 and the side surfaces 133a. The gate insulating film 110 is composed of a SiO ₂ film formed by thermal CVD, for example. The thickness of the gate insulating film 110 is, for example, approximately 0.005 to 0.15 μm. The gate insulating film 110 may be selectively thickened only at the bottom of the trench. In this case, the carbon surface may be used as the main surface of the substrate, and the gate insulating film 110 may be formed by thermal oxidation. The film thickness of the insulating film 117 may be equal to or less than the film thickness of the gate insulating film 110, but is preferably thicker. Specifically, if the film thickness of the insulating film 117 is three times or more the film thickness of the gate insulating film 110, the insulating film electric field can be effectively reduced.

Next, as shown in FIG. 18, a polycrystalline silicon (Si) film 111A is formed on the gate insulating film 110. Then, as shown in FIG. A polycrystalline silicon (Si) film 111A is deposited along the surface of the insulating film 110 deposited in the previous step. When the insulating film 117 is thick, the polycrystalline silicon (Si) film 111A does not conform to the shape of the surface of the SiC substrate and is separated, so that the electric field concentration at the upper corner of the trench is relieved and the withstand voltage is improved. The thickness of the polycrystalline silicon (Si) film 111A is, for example, approximately 0.01 to 4 μm. The polarity of the polycrystalline silicon (Si) film 111A may be n-type or p-type, and can be adjusted according to the threshold voltage.

Next, as shown in FIG. 19, using a mask M17 (photoresist film), the polycrystalline silicon (Si) film 111A is processed by a dry etching method to form a gate electrode 111. Next, as shown in FIG. In addition to this, the polycrystalline silicon (Si) film 111B on the p-type potential fixed layer 130 sandwiched between the p-type body layers 102 may be opened by dry etching.

<Process P6>
Various electrodes are formed in the process P6. As shown in FIG. 20, an interlayer insulating film 112 is formed on the surface of the body layer 102 by plasma CVD, for example, so as to cover the gate electrode 111 and the gate insulating film 110 .

Next, as shown in FIG. 21, using a mask M18 (photoresist film), the interlayer insulating film 112, the gate insulating film 110, and the insulating film 117 are processed by dry etching to form the n ⁺⁺ source region 103. An opening CNT_S reaching the partial and p ⁺⁺ type body layer contact regions 109 is formed.

Next, as shown in FIG. 22, after removing the mask M18, a portion of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer contact region 109 exposed at the bottom surface of the opening CNT_S are exposed. A metal silicide layer 113 is formed on the surface. First, although illustration is omitted, on the surface of the epitaxial layer 101, a first metal film, such as nickel (Ni ). The thickness of this first metal film is, for example, about 0.05 μm. Subsequently, a silicidation heat treatment is performed at 600 to 1000° C. to react the first metal film and the epitaxial layer at the bottom surface of the opening CNT_S, thereby opening, for example, a nickel silicide (NiSi) layer as the metal silicide layer 113. It is formed on the surfaces of a portion of n ⁺⁺ -type source region 103 and p ⁺⁺ -type body layer contact region 109 exposed at the bottom surface of portion CNT. Subsequently, the unreacted first metal film is removed by wet etching. Sulfuric acid-hydrogen peroxide mixture, for example, is used for the wet etching method.

Next, although not shown, an opening CNT_G reaching the gate electrode 111 is formed by processing the interlayer insulating film 112 using a mask (photoresist film). The opening CNT_G is provided to connect the gate wiring electrode 8 and the gate electrode 111 .

Next, as shown in FIG. 23, an opening CNT_S reaching the metal silicide layer 113 formed on each surface of part of the n ⁺⁺ -type source region 103 and the p ⁺⁺ -type body layer contact region 109, and the gate Lamination of a third metal film, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film on the interlayer insulating film 112 including the inside of the opening CNT_G (not shown) reaching the electrode 111 Deposit a film. The thickness of the aluminum (Al) film is preferably 2.0 μm or more, for example. Subsequently, by processing the third metal film, a part of the n ⁺⁺ type source region 103 and the p ⁺⁺ type body layer contact region 109 are electrically connected through the metal silicide layer 113 in the opening CNT_S. The source wiring electrode 2 and the gate wiring electrode 8 electrically connected to the gate electrode 111 through the opening CNT_G are formed.

Next, although not shown, a SiO ₂ film or a polyimide film is deposited as a passivation film so as to cover the gate wiring electrode 8 and the source wiring electrode 2 .

Next, although not shown, the passivation film is processed to form passivation. At that time, the source electrode opening 7 and the gate electrode opening 5 are formed.

Next, although not shown, a second metal film is deposited on the n ⁺ -type drain region 108 by sputtering, for example. The thickness of this second metal film is, for example, about 0.1 μm.

Next, as shown in FIG. 24, a laser silicidation heat treatment is performed to react the second metal film with the n ⁺ -type drain region 108 to form a metal silicide layer 115 covering the n + -type drain region 108 . to form Subsequently, a drain wiring electrode 116 is formed to cover the metal silicide layer 115 . The drain wiring electrode 116 is formed by depositing a laminated film of a Ti film, a Ni film and a gold (Au) film to a thickness of 0.5 to 1.0 μm.

After that, external wirings are electrically connected to the source wiring electrode 2, the gate wiring electrode 8, and the drain wiring electrode 116, respectively.

As described above, according to the first embodiment, as described above, the formation of the p-type potential fixing layer 130 reduces the influence of misalignment of the current diffusion layer 105 and realizes an improvement in breakdown voltage based on the minimum ring model. This greatly improves the reliability of MISFETs.

Furthermore, in the normal DMOS structure and the trench type DMOS, the surfaces of the current diffusion layer 105 and the epitaxial layer 101 facing the gate electrode 111 with the insulating film 117 and the gate insulating film 110 interposed therebetween serve as capacitors, which contribute to feedback capacitance. 24, in the structure of Example 1, the portion where the p-type potential fixed layer 130 exists is equivalent to inserting a pn junction in series. Therefore, the capacitance of this portion can be ignored and the feedback capacitance is greatly reduced. This effect leads to reduction of switching loss and prevention of false ignition. Furthermore, as described in this embodiment, the p-type potential fixing layer 130 can be formed in self-alignment with the p-type body layer 102 . Therefore, the JFET resistance does not increase significantly.

As described above, by forming the p-type potential fixed layer 130, it is possible to improve the breakdown voltage, which has been a problem, and realize even better switching characteristics without impairing the low channel resistance comparable to that of a normal trench-type MOS structure. Therefore, it is possible to provide a SiC power MISFET with higher reliability and lower loss than the conventional trench type DMOS. Thereby, a highly reliable silicon carbide semiconductor device and a method for manufacturing the same can be provided.

FIG. 25 is a fragmentary cross-sectional view of the SiC power MISFET according to Example 2, and is an enlarged view of the vicinity of the JFET region 204 in particular. The difference from Example 1 is that the p-type electric field relaxation layer 231 is formed directly under the SiC substrate surface from the n ⁺ -type current diffusion layer 205 to the JFET region 204 and the p-type potential fixed layer 230 . . In this way, by simultaneously using the p-type potential fixing layer 230 and the p-type electric field relaxation layer 231, it is possible to obtain a greater improvement in breakdown voltage while minimizing the disadvantages of each method. As in Patent Document 2, the electric field relaxation layer 231 is effective in improving the withstand voltage of the trench DMOS and protecting the gate insulating film 110 . However, as described above, the high withstand voltage is insufficient for the misalignment of the current diffusion layer 205 . Further, as shown in the depletion layer distribution diagram of the conventional trench-type DMOS when the channel is turned on in FIG. There is a trade-off relationship in that the depletion layer also extends from the substrate surface above 204, narrowing the current path and increasing the JFET resistance. Although not shown, even when the p-type potential fixed layer 230 exists alone, a depletion layer develops from the p-type potential fixed layer 230, and there is a similar trade-off relationship. Since the position of the depletion layer formed in these two structures is the same in both cases, by simultaneously using the p-type electric field relaxation layer 231 and the p-type potential fixing layer 230, only one of the structures Compared to the case of applying , it is possible to realize a large improvement in withstand voltage while suppressing an increase in new resistance.

The depletion layer distribution when the channel is on in the structure of Example 2 will be described with reference to FIG. Since the p-type potential fixed layer 230 is arranged in the region where the depletion layer from the n-type electric field relaxation layer 231 was present, the depletion layer width due to the addition of the p-type potential fixed layer 230, that is, the JFET resistance increase is slight. On the other hand, if the benefit of the significant improvement in breakdown voltage due to the p-type potential fixing layer 230 is used to widen the JFET width defined by the gap width of the p-type body layer 202, a lower JFET resistance can be obtained. can. As described above, by simultaneously using the p-type electric field relaxation layer 231 and the p-type potential fixing layer 230, a SiC power MISFET with lower loss and higher withstand voltage can be realized.

25 to 27, reference numeral 202 denotes a p-type body layer, reference numeral 206 denotes a trench, reference numeral 210 denotes a gate insulating film, and reference numeral 217 denotes an insulating film, although detailed description is omitted.

<<Method for Manufacturing Silicon Carbide Semiconductor Device>>
A method for manufacturing a silicon carbide semiconductor device according to Example 2 will be described with reference to FIG. 28 only for the essential points.

The p-type electric field relaxation layer 231 can be inserted in any step after the body layer formation step and before the activation step in the first embodiment. For example, FIG. 28 shows an example of forming the p-type electric field relaxation layer 231 after forming the n-type current diffusion layer 205 in the process of the first embodiment.

The procedure is the same as in Example 1 until an n-type current diffusion layer 205 is formed and all masks are removed. Subsequently, a mask M21 is formed using, for example, a resist film. A p-type impurity such as aluminum atoms (Al) is ion-implanted through the mask M21 to form a p-type electric field relaxation layer 231 . The thickness of the mask M21 is, for example, approximately 1 to 4 μm. The width of the opening of the mask M21 is preferably such that the entire surface of the n-type current diffusion layer 205 can be filled. The impurity concentration of the p-type electric field relaxation layer 231 is higher than the concentration of the n-type current diffusion layer 205 at the same point in the substrate, eg, in the range of 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ .

The p-type electric field relaxation layer 231 may be implanted in two or more steps using the same mask as the p-type current diffusion layer 205 and a mask with an opening in the JFET region 204 . In this case, since it is self-aligned with the current diffusion layer 205, the influence on the channel can be reduced.

By using the p-type electric field relaxation layer 231 and the p-type potential fixing layer 230 together in this way, the structure of the depletion layer can be effectively used, and it is possible to simultaneously achieve high withstand voltage and low loss. . Furthermore, since the area of the insulating film exposed to the n-type region is reduced, the feedback capacitance is also reduced, thereby reducing switching loss and preventing erroneous ignition.

FIG. 30 is an enlarged view of a cross-sectional view of a main portion of the SiC power MISFET according to Example 3, particularly in the vicinity of the JFET region 304. FIG. A difference from the first embodiment described above is that the p-type potential fixing layer 330 is formed to a position deeper than the n-type current diffusion layer 305 .

For comparison, FIG. 29 shows the structure of the depletion layer in the structure of Example 1 with a larger misalignment than, for example, the example shown in FIG. If the n-type current diffusion layer 105 also exists under the p-type potential fixed layer 130, the depletion layer edge 140d from the p-type potential fixed layer 130 cannot develop. In this case, the depletion layer cannot be blocked by the p-type potential fixing layer 130, and the breakdown voltage may be greatly reduced.

Therefore, in Example 3, as shown in FIG. 30, the p-type potential fixing layer 330 is formed deeper than the n-type current diffusion layer 305 . In this case, even if the n-type current diffusion layer 305 overlaps with the p-type potential fixing layer 330 and the misalignment occurs, the depletion layer 340 can be reliably blocked. Although detailed description is omitted in FIG. 30, reference numeral 302 denotes a p-type body layer, reference numeral 306 denotes a trench, reference numeral 310 denotes a gate insulating film, and reference numeral 317 denotes an insulating film.

As described above, the trench type DMOS using the structure of Example 3 reliably prevents a significant decrease in breakdown voltage due to the misalignment of the n-type current diffusion layer 305, and achieves low loss, high breakdown voltage, and high breakdown voltage. A SiC power MISFET with a high yield and a manufacturing method thereof can be realized.

FIG. 31 shows the structure of the depletion layer of the SiC power MISFET according to Example 4 when the channel is on. The difference from the first embodiment described above is that an n-type region 432 (hereinafter referred to as a counter) having a higher concentration than the JFET region 404 is formed directly below the p-type potential fixed layer 430. .

For comparison, FIG. 32 shows the structure of the depletion layer in the structure of Example 1 when the channel is on. When the p-type potential fixed layer 130 exists, the edge 140e of the depletion layer develops even when the channel is on. Since the JFET region 104 is a low-concentration n-type region, the end 140e of the depletion layer extends deep into the JFET region 404, increasing the resistance of the JFET region.

On the other hand, as shown in FIG. 31, in the structure of this embodiment, since the high-concentration n-type counter 432 exists, the depletion layer end 440e from the p-type potential fixed layer 430 is the n-type counter. It stops within 432 and does not constrict the current path. Furthermore, the current can be diffused to the center of the JFET region through the n-type counter 432 with a high carrier density, and loss can be reduced. Also in the structure of the fourth embodiment, the straight line connecting the p-type body layer 402 and the p-type potential fixed layer 430 is a low-concentration region. The effect of increasing the withstand voltage is not lost.

Furthermore, by using the electric field relaxation layer of Example 2 and the deep potential fixing layer of Example 3 together, a power device with higher performance can be realized. Description will be made with reference to FIGS. 33 and 34 showing the structure of the depletion layer during channel on/off of a trench type DMOS in which a p-type electric field relaxation layer 431, a deep p-type potential fixing layer 430a and an n-type counter 432 are formed. do. When the channel is turned on as shown in FIG. 33, by appropriately designing the concentration of the n-type counter 432, it is possible to reduce the loss as compared with the case where only the p-type electric field relaxation layer 431 is used. When the channel is turned off as shown in FIG. 34, the depletion layer extending from the side surface of the deep p-type potential fixed layer 430a increases the withstand voltage even when the n-type current diffusion layer 405 is accompanied by a large misalignment. Although detailed description is omitted in FIGS. 31 to 34, reference numeral 406 denotes a trench, reference numeral 410 denotes a gate insulating film, and reference numeral 417 denotes an insulating film.

As described above, by forming the n-type counter 432 with a higher concentration than the JFET region 404 immediately below the p-type potential fixed layer 430, the resistance of the JFET region is reduced, and a SiC power MISFET with lower loss and higher withstand voltage is realized. can do.

<<Method for Manufacturing Silicon Carbide Semiconductor Device>>
A method for manufacturing a silicon carbide semiconductor device according to Example 4 will be described. Although illustration is omitted, in the first, second, or third embodiment, when the p-type potential fixed layer 430 is formed, the same mask as the p-type potential fixed layer 430 is used to apply n-type impurities to the p-type potential. This is achieved by implanting ions of higher energy than the fixed layer.

FIG. 35 is a fragmentary cross-sectional view of a SiC power MISFET according to Example 5. FIG. The difference from the first embodiment described above is that the central portions of the gate electrode 511, the insulating film 517, and the interlayer insulating film 512 are open, and the source electrode 2 is connected to the p-type potential fixing layer 530. FIG. be. The p-type potential fixing layer 530 can be connected to the source electrode 2 through the p-type body layer 502 and the p ⁺⁺ -type body layer contact region 509 in the termination structure. May float during switching. In the structure of the fifth embodiment, the potential of the p-type potential fixed layer 530 is directly fixed to the source potential over the entire area, so reliability during high-speed switching can be improved.

Furthermore, as shown in FIG. 36, instead of connecting the source electrode 2 and the p-type potential fixed layer 530 via a silicide layer, the source electrode 2 is connected so as to protrude from the p-type potential fixed layer 530 . can be In this case, it can operate as a Schottky barrier diode, and by reducing the current of the built-in body diode, it is possible to prevent crystal defects from expanding during reverse conduction and improve long-term reliability.

Although detailed description is omitted in FIGS. 35 and 36, reference numeral 501 denotes an n ⁻ -type epitaxial layer, reference numeral 502 denotes a p-type body layer, reference numeral 503 denotes an n ⁺⁺ -type source region, and reference numeral 505 denotes an n ⁺ layer. 506 is a trench, 507 is an n ⁺ -type SiC substrate, 508 is an n ⁺ -type drain region, 509 is a p ⁺⁺ -type body layer contact region, 510 is a gate insulating film, Reference numeral 513 denotes a metal silicide layer, reference numeral 515 denotes a metal silicide layer, and reference numeral 516 denotes a drain wiring electrode.

<<Method for Manufacturing Silicon Carbide Semiconductor Device>>
Regarding the method of manufacturing a silicon carbide semiconductor device according to the fifth embodiment, differences from the first embodiment will be described.

When the gate electrode 511 is processed, etching is performed using a mask that also opens the p-type potential fixed layer 530 . Furthermore, in the step of etching the interlayer insulating film 512 , the gate insulating film 510 and the insulating film 517 to form the metal silicide layer 513 , etching is performed using a mask that opens right above the p-type potential fixed layer 530 . conduct. Alternatively, after forming the metal silicide layer 513, the contact portion of the p-type potential fixing layer 530 may be opened using another mask. In this case, the p-type potential fixing layer 530 can be contacted without forming silicide. The opening width on the p-type potential fixing layer 530 is, for example, 0.5 to 5.0 μm.

As described above, according to the fifth embodiment, it is possible to realize a silicon carbide semiconductor device having a higher reliability than the trench type DMOS structure and a method for manufacturing the same, as in the first embodiment. can be fixed to the source potential to improve reliability during high-speed switching. Furthermore, by using an appropriate opening width without using silicide for the contact of the p-type potential fixed layer 530, it is possible to incorporate a Schottky barrier diode and suppress deterioration during reverse conduction. A SiC power MISFET with long-term reliability in addition to loss and high-speed switching can be realized.

FIG. 37 is a top view of essential parts of a SiC power MISFET according to Example 6. FIG. The difference from the first embodiment described above is that the p-type potential fixing layers 630 are not striped, but arranged side by side at regular intervals and arranged on the longitudinal extension of the trench.

While the p-type potential fixing layer 630 improves the breakdown voltage, it increases the resistance of the JFET region. In the sixth embodiment, by promoting depletion only in the vicinity of the trench 606 formation region where the electric field is most concentrated, it is possible to greatly improve the withstand voltage while minimizing the increase in loss. Although detailed description is omitted in FIG. 37, reference numeral 603 denotes an n ⁺⁺ -type source region, reference numeral 605 denotes an n ⁺ -type current diffusion layer, and reference numeral 609 denotes a p ⁺⁺ -type body layer contact region.

<<Method for Manufacturing Silicon Carbide Semiconductor Device>>
The method of manufacturing the silicon carbide semiconductor device according to the sixth embodiment can be realized by changing the opening of the mask in forming the p-type potential fixed layer 630 from the stripe shape to the island shape in the first embodiment. The pitch of the p-type potential fixing layers 630 in the direction perpendicular to the longitudinal direction of the trench is preferably equal to the pitch of the trenches 606, but may be, for example, double the pitch. The width of the p-type potential fixing layer 630 in the direction perpendicular to the longitudinal direction of the trench is, for example, in the range of 0.3 μm to 1.0 μm.

As described above, according to the fifth embodiment, as in the first embodiment, it is possible to realize a silicon carbide semiconductor device having a more reliable trench type DMOS structure and a method for manufacturing the same, and in addition, it is possible to minimize an increase in loss. .

As described above, the semiconductor device having the SiCMISFET described in Examples 1 to 6 can be used for various devices. FIG. 38 is a circuit diagram showing an example of a power converter (inverter).

As shown in FIG. 38, inverter 802 has SiCMISFET 804 as a switching element and diode 805 . In each single phase, a SiCMISFET 804 and a diode 805 are connected in antiparallel between the power supply potential (Vcc) and the input potential to the load (three-phase motor in this example) 801 (upper arm). A SiCMISFET 804 and a diode 805 are also connected in antiparallel between the input potential and the reference potential (GND) (lower arm). That is, for the load 801, two SiCMISFETs 804 and two diodes 805 are provided for each single phase, and six switching elements 804 and six diodes 805 are provided for three phases. A control circuit 803 is connected to the gate electrode of each SiCMISFET 804 , and the SiCMISFET 804 is controlled by this control circuit 803 . Therefore, the load 801 can be driven by controlling the current flowing through the SiCMISFET 804 forming the inverter 802 with the control circuit 803 .

The function of the SiCMISFET 804 forming the inverter 802 will be described below. In order to control and drive a load 801 such as a motor, it is necessary to input a sine wave of a desired voltage to the load 801 . The control circuit 803 controls the SiCMISFET 804 to perform a pulse width modulation operation that dynamically changes the pulse width of the rectangular wave. The output rectangular wave passes through an inductor and is smoothed into a desired pseudo sine wave. The SiCMISFET 804 has the function of generating a square wave for performing this pulse width modulation operation.

By using the semiconductor device described in the first to sixth embodiments as the SiCMISFET 804, the performance of a power conversion device such as an inverter can be improved. In addition, by using a semiconductor device with long-term reliability as the SiCMISFET 804, it is possible to extend the service life of a power conversion device such as an inverter. As a result, the motor system (FIG. 38) using the power conversion device using the semiconductor device described in the first to sixth embodiments can be improved in performance and can be used for a long period of time.

FIG. 39 is a circuit diagram showing another example of the power converter (inverter). The inverter 902 has a SiCMISFET 904 which is a switching element. Also in this example, the load 901 is a three-phase motor. In each single phase, a SiCMISFET 904 is connected (upper arm) between the power supply potential (Vcc) and the input potential to the load (for example, motor) 901, and between the input potential of the load 901 and the reference potential (GND) SiCMISFET 904 is also connected to (lower arm). That is, in the load 901, two SiCMISFETs 904 are provided for each single phase, and six switching elements 904 are provided for three phases. A control circuit 903 is connected to the gate electrode of each SiCMISFET 904 , and the SiCMISFET 904 is controlled by this control circuit 903 . Therefore, the load 901 can be driven by controlling the current flowing through the SiCMISFET 904 forming the inverter 902 with the control circuit 903 .

The function of the SiCMISFET 904 forming the inverter 902 will be described below. Here, as a function of the SiCMISFET, it produces a square wave for performing pulse width modulation operation and also plays a role of the diode 805 in the inverter of FIG. In the inverter 902, if the load 901 includes an inductance such as a motor, the energy stored in the inductance must be released (return current) when the SiCMISFET 904 is turned off. While the diode 805 plays this role in the power converter of FIG. 38, the SiCMISFET 904 plays this role in the power converter of FIG. That is, synchronous rectification drive is used. Here, synchronous rectification driving refers to a method of turning on the gate of the SiCMISFET 904 during freewheeling to reverse conduct the SiCMISFET 904 .

Therefore, the freewheeling conduction loss is determined by the characteristics of the SiCMISFET 904, not the characteristics of the diode. Further, when synchronous rectification driving is performed, in order to prevent the upper and lower arms from being short-circuited, a non-operating time during which both the upper and lower SiCMISFETs are turned off is required. During this dead time, the built-in pn diode formed by the drift layer and p-type body layer of SiCMISFET 904 drives. However, SiC has a shorter carrier mileage than Si and less loss during dead time. For example, the diode 805 is equivalent to a SiC Schottky barrier diode.

Thus, by using the semiconductor device described in Embodiments 1 to 6 as the SiCMISFET 904, the loss during freewheeling can be reduced, and since a diode is not used, a power conversion device such as an inverter can be miniaturized. can. In addition, by using a semiconductor device with long-term reliability as the SiCMISFET 904, it is possible to extend the service life of a power conversion device such as an inverter. Further, the power converter using the semiconductor devices described in the first to sixth embodiments may be a motor system. As a result, it is possible to realize higher performance and longer service life of the motor system using the power conversion device using the semiconductor device described in the first to sixth embodiments.

The motor system as described above can be used in vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles. An automobile using the motor system will be described with reference to FIGS. 40 and 41. FIG. FIG. 40 is a schematic diagram showing an example of the configuration of an electric vehicle, and FIG. 41 is a circuit diagram showing an example of a boost converter used in the electric vehicle.

As shown in FIG. 40, the electric vehicle includes a three-phase motor 1003 capable of inputting and outputting power to a drive shaft 1002 to which drive wheels 1001a and 1001b are connected, and an inverter 1004 for driving the three-phase motor 1003. , a battery 1005, a boost converter 1008, a relay 1009, and an electronic control unit 1010. The boost converter 1008 connects a power line 1006 to which the inverter 1004 is connected and a power line 1007 to which the battery 1005 is connected. It is connected to the.

The three-phase motor 1003 is a synchronous generator-motor having a rotor embedded with permanent magnets and a stator wound with three-phase coils. For inverter 1004, an inverter as shown in FIG. 38 or 39 can be used.

As shown in FIG. 41, boost converter 1008 has a configuration in which reactor 1011 and smoothing capacitor 1012 are connected to inverter 1013 . The inverter 1013 is composed of a SiCMISFET 1014, and the semiconductor device described in the first to sixth embodiments is used.

The electronic control unit 1010 of FIG. 40 includes a microprocessor, a storage device, and an input/output port, and receives signals from a sensor that detects the rotor position of the three-phase motor 1003, charge/discharge values of the battery 1005, and the like. receive. It outputs signals for controlling inverter 1004 , boost converter 1008 and relay 1009 .

The power converter shown in FIG. 38 or 39 can be used for the inverter 1004 which is a power converter. A three-phase motor system using the power converter shown in FIG. 38 or 39 can be used as a three-phase motor system including a three-phase motor 1003, an inverter 1004, and the like. As a result, energy saving, downsizing, weight saving, and space saving of the electric vehicle can be achieved.

Although an electric vehicle has been described, the above three-phase motor system can be similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 1005 is a fuel cell stack. It can also be used for railway vehicles. A railway vehicle using a three-phase motor system is shown in FIG. FIG. 42 is a circuit diagram showing an example of a converter and an inverter provided in a railway vehicle.

As shown in FIG. 42, electric power is supplied to the railway vehicle from the overhead wire OW (for example, 25 kV) via the pantograph PG. The voltage is stepped down to 1.5 kV through transformer 1109 and converted from AC to DC by converter 1107 . Furthermore, the direct current is converted into alternating current by an inverter 1102 via a capacitor 1108 to drive a three-phase motor, which is a load 1101 . The element configuration in converter 1107 may use both SiCMISFET and diode as shown in FIG. 38, or may use SiCMISFET alone as shown in FIG. The example of FIG. 42 shows an example configured with a single SiCMISFET 1104 . Note that the control circuit is omitted in this figure. Further, in the drawing, reference character RT indicates a track, reference character WH indicates a wheel, and a three-phase motor 1101 can input/output power to a drive shaft to which the wheel WH is connected.

In this way, by using the three-phase motor system using the semiconductor devices described in the first to sixth embodiments for the inverter and converter in the railway vehicle, it is possible to reduce the energy consumption of the railway vehicle and reduce the size and weight of the underfloor parts. be able to.

The invention made by the present inventor has been specifically described above based on the embodiment, but the present invention is not limited to the above embodiment, and can be variously modified without departing from the scope of the invention. Needless to say.

For example, the material, conductivity type, manufacturing conditions, etc. of each part are not limited to those described in the above-described embodiments, and needless to say, many modifications are possible. Here, for convenience of explanation, the conductivity types of the semiconductor substrate and the semiconductor film are fixed, but the conductivity types are not limited to those described in the above embodiments.

1: semiconductor chip, 2: electrode for source wiring, 3: floating field limiting ring, 4: guard ring, 5: gate opening, 6: SiC power MISFET, 7: source opening, 8: gate wiring electrode, 101, 201, 501: epitaxial layer, 102, 202, 302, 402, 502: body layer, 103, 203, 503, 603: source region, 104, 204, 304, 404, 504: JFET region, 105 , 205, 305, 405, 505, 605: current diffusion layer, 106, 206, 306, 406, 506, 606: trench, 107, 207, 507: SiC substrate, 108, 208, 508: drain region, 109, 509 , 609: body layer contact region, 110, 210, 310, 410, 510: gate insulating film, 111, 511: gate electrode, 112, 512: interlayer insulating film, 113, 513: source contact region (metal silicide layer), 115, 515: metal silicide layer, 116, 516: drain wiring electrode, 117, 217, 317, 417, 517: insulating film, 130, 230, 330, 430, 530, 630: potential fixing layer, 140, 240, 340: edge of depletion layer, 141: SiC epitaxial substrate surface, 231, 431: electric field relaxation layer, 432: counter, 801, 901: load, 802, 902: inverter, 803, 903: control circuit, 804, 904: SiCMISFET, 805: diode, 1001: drive wheel, 1002: drive shaft, 1003: three-phase motor, 1004: inverter, 1005: battery, 1006: power line, 1007: power line, 1008: boost converter, 1009: relay, 1010 : electronic control unit, 1011: reactor, 1012: smoothing capacitor, 1013: inverter, 1014: SiCMISFET, 1101: load, 1102: inverter, 1104: SiCMISFET, 1107: converter, 1108: capacitor, 1109: transformer.

Claims (13)

a first conductivity type SiC substrate;
a first conductivity type epitaxial layer formed on the first main surface of the SiC substrate and having an impurity concentration lower than that of the SiC substrate;
a drain region formed on a second main surface facing the first main surface of the SiC substrate;
first and second body layers of a second conductivity type formed on the epitaxial layer;
a first conductivity type first source region formed in the first body layer;
a first conductivity type second source region formed in the second body layer;
a JFET region which is the epitaxial layer sandwiched between the first and second body layers and the first body layer, and which has an impurity concentration higher than that of the epitaxial layer; a first first region;
a second first region of a first conductivity type that is in contact with the JFET region and the second body layer and has a higher impurity concentration than the epitaxial layer;
a second region of a second conductivity type formed in the JFET region;
a first trench extending through the first source region, the first body layer and the first first region;
a second trench extending through the second source region, the second body layer and the second first region;
an insulating film formed on inner walls of the first trench and the second trench ;
a gate electrode formed on the insulating film of the first trench and the second trench ;
A semiconductor device comprising a second conductivity type third region covering the first and second first regions, the JFET region and the second region . In claim 1 ,
the first and second body layers, the first and second source regions, and the first and second first regions each have a stripe pattern in plan view,
A semiconductor device in which a straight line passing through the first trench and the second trench intersects the longitudinal direction of the stripe pattern. In claim 1 ,
The semiconductor device, wherein the second region is formed deeper than the first and second first regions. In claim 1 ,
A semiconductor device having a first conductivity type fourth region having an impurity concentration higher than that of the epitaxial layer immediately below the second region. In claim 2 ,
The second region is a semiconductor device having a stripe pattern extending in the longitudinal direction of the stripe pattern. a first conductivity type SiC substrate;
a first conductivity type epitaxial layer formed on the first main surface of the SiC substrate and having an impurity concentration lower than that of the SiC substrate;
a drain region formed on a second main surface facing the first main surface of the SiC substrate;
first and second body layers of a second conductivity type formed on the epitaxial layer;
a first conductivity type first source region formed in the first body layer;
a first conductivity type second source region formed in the second body layer;
a JFET region which is the epitaxial layer sandwiched between the first and second body layers and the first body layer, and which has an impurity concentration higher than that of the epitaxial layer; a first first region;
a second first region of a first conductivity type that is in contact with the JFET region and the second body layer and has a higher impurity concentration than the epitaxial layer;
a second region of a second conductivity type formed in the JFET region;
a first trench extending through the first source region, the first body layer and the first first region;
a second trench extending through the second source region, the second body layer and the second first region;
an insulating film formed on inner walls of the first trench and the second trench;
a gate electrode formed on the insulating film of the first trench and the second trench;
the first and second body layers, the first and second source regions, and the first and second first regions each have a stripe pattern in plan view,
a straight line passing through the first trench and the second trench intersects the longitudinal direction of the stripe pattern;
The semiconductor device , wherein the second region is formed in an island shape in plan view in a region sandwiched between the first trench and the second trench . In claim 1 ,
a second conductivity type first fifth region formed in the first body layer and having an impurity concentration higher than that of the first body layer;
a second conductivity type second fifth region formed in the second body layer and having an impurity concentration higher than that of the second body layer;
A semiconductor device comprising a source electrode connecting the first source region, the first fifth region, the second source region, and the second fifth region. In claim 7 ,
The semiconductor device, wherein the second region is connected to the source electrode. In claim 8 ,
The semiconductor device, wherein the source electrode is in contact with the JFET region around the second region. a power supply potential;
a reference potential;
a load input potential;
a first switching element connected between the power supply potential and the load input potential;
a second switching element connected between the reference potential and the load input potential;
A control circuit that controls the first switching element and the second switching element,
A power converter using the semiconductor device according to any one of claims 1 to 9 as the first switching element and the second switching element. In claim 10 ,
a first diode connected in anti-parallel to the first switching element;
A power converter comprising a second diode connected in anti-parallel to the second switching element. a power conversion device that converts DC power to AC power;
a motor driven by the power converter,
A motor system using the power converter according to claim 10 as the power converter. wheels and
a drive shaft connected to the wheel;
13. A vehicle in which power can be input to and output from the drive shaft by the motor system according to claim 12 .

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