JP7105621B2 - LIQUID JET HEAD AND LIQUID JET RECORDING APPARATUS - Google Patents

Description

The present disclosure relates to a liquid jet head and a liquid jet recording apparatus.

2. Description of the Related Art A liquid jet recording apparatus having a liquid jet head is used in various fields, and various types of liquid jet heads have been developed. Further, for example, Japanese Laid-Open Patent Publication No. 2002-100001 proposes a method of data transfer in a liquid jet head.

JP 2015-116737 A

Such a liquid jet head is generally required to reduce the number of signal lines for data transfer. It is desirable to provide a liquid jet head and liquid jet recording apparatus capable of reducing the number of signal lines.

A first liquid jet head according to an embodiment of the present disclosure includes a jet section having a plurality of nozzles for jetting liquid, and an image data signal and a clock signal supplied from an external head control section. and a plurality of drive circuit units for generating a drive signal for ejecting the liquid from and outputting the drive signal to the ejection unit. Each of the plurality of drive circuit sections includes a drive signal generation section that generates a drive signal for each of a plurality of nozzles, a jitter suppression circuit that suppresses and outputs jitter in a predetermined input signal, and an output signal from the jitter suppression circuit. and other signals including an image data signal are respectively input as a plurality of input signals, and a parallel/serial conversion section for adjusting skew between the plurality of input signals . An output signal from this parallel/serial conversion section is output to the outside of the drive circuit section. Between the plurality of drive circuit units, the signal after jitter suppression by the jitter suppression circuit in the drive circuit unit located relatively at the front stage side is input to the drive circuit unit located at the relatively rear stage side. Thus, a plurality of drive circuit units are connected in series with each other in multiple stages.
A second liquid jet head according to an embodiment of the present disclosure includes a jet section having a plurality of nozzles for jetting liquid, and an image data signal and a clock signal supplied from an external head control section. and a plurality of drive circuit units for generating a drive signal for ejecting the liquid from and outputting the drive signal to the ejection unit. Each of the plurality of drive circuit sections has a drive signal generation section that generates a drive signal for each of the plurality of nozzles, and a jitter suppression circuit that suppresses and outputs jitter in a predetermined input signal. An image data signal and a clock signal supplied from the head controller to the drive circuit are differential transmission signals. Between the plurality of drive circuit units, the signal after jitter suppression by the jitter suppression circuit in the drive circuit unit located relatively at the front stage side is input to the drive circuit unit located at the relatively rear stage side. Thus, a plurality of drive circuit units are connected in series with each other in multiple stages.
A third liquid jet head according to an embodiment of the present disclosure includes a jet section having a plurality of nozzles for jetting liquid, and an image data signal and a clock signal supplied from an external head control section. and a plurality of drive circuit units for generating a drive signal for ejecting the liquid from and outputting the drive signal to the ejection unit. Each of these plurality of drive circuit sections has a drive signal generation section that generates a drive signal for each of the plurality of nozzles, and a jitter suppression circuit that suppresses and outputs jitter in a clock signal. The drive signal generation section has a shift register section that sequentially transfers and holds the image data signals from the front stage side to the rear stage side in correspondence with the drive signals for each of the plurality of nozzles. performs sequential transfer from the front stage side to the rear stage side in synchronization with the AND signal of the clock signal and the strobe signal. Between the plurality of drive circuit units, the signal after jitter suppression by the jitter suppression circuit in the drive circuit unit located relatively at the front stage side is input to the drive circuit unit located at the relatively rear stage side. Thus, a plurality of drive circuit units are connected in series with each other in multiple stages.

A liquid jet recording apparatus according to an embodiment of the present disclosure includes a liquid jet head (one of the first to third liquid jet heads) according to the embodiment of the present disclosure, and an image data signal. and a head controller for supplying a clock signal to the liquid jet head.

According to the liquid jet head and the liquid jet recording apparatus according to the embodiment of the present disclosure, it is possible to reduce the number of signal lines.

1 is a block diagram showing a schematic configuration example of a liquid ejecting apparatus according to an embodiment of the present disclosure; FIG. 2 is a block diagram showing a configuration example inside each drive circuit board in the liquid jet head shown in FIG. 1; FIG. 3 is a block diagram showing a configuration example of each drive circuit section shown in FIG. 2; FIG. 4 is a block diagram showing a configuration example of a drive signal generation unit shown in FIG. 3; FIG. 4 is a timing chart schematically showing an operation example in each drive circuit unit shown in FIG. 3; FIG. 3 is a block diagram showing a configuration example of each drive circuit unit in a liquid jet head according to a comparative example; FIG. 4A and 4B are schematic timing charts comparing operation examples according to the embodiment and the comparative example; FIG.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. Embodiment (an example of cascading a plurality of drive circuit units including jitter suppression circuits)
2. Modification

<1. Embodiment>
[Configuration of Printer 3]
FIG. 1 is a block diagram showing a schematic configuration example of a printer 3 as a liquid jet recording apparatus according to an embodiment of the present disclosure. FIG. 2 is a block diagram showing a configuration example inside each drive circuit board (inside drive circuit boards 52a, 52b, and 52c, which will be described later) in the inkjet head 1 as the liquid jet head shown in FIG. . FIG. 3 is a block diagram showing a configuration example of each drive circuit section (drive circuit sections 12a, 12b, 12c and 12d to be described later) shown in FIG. FIG. 4 is a block diagram showing a configuration example of the drive signal generator (drive signal generator 122 described later) shown in FIG. In FIGS. 1 to 4, "/N" (N: a positive integer) shown on the signal wiring indicates the number of wiring, and in the subsequent block diagram (FIG. 6 to be described later) The same is true for Also, in each drawing used for the description of this specification, the scale of each member is appropriately changed so that each member has a recognizable size.

The printer 3 is an inkjet printer that uses ink 9 to be described later to record (print) images, characters, and the like on a recording medium (eg, recording paper). This printer 3 comprises an ink jet head 1 and a head controller 2 as shown in FIG.

The inkjet head 1 corresponds to a specific example of the "liquid jet head" in the present disclosure, and the printer 3 corresponds to a specific example of the "liquid jet recording apparatus" in the present disclosure. Also, the ink 9 corresponds to a specific example of "liquid" in the present disclosure.

(A. Head controller 2)
The head controller 2 supplies various information (data) to the inkjet head 1 . Specifically, as shown in FIG. 1, the head control unit 2 supplies two serial data signals Ds1 and Ds2 and one clock signal CLK to each of the plurality of driving units 12 in the inkjet head 1, which will be described later. and , respectively.

Here, these serial data signals Ds1 and Ds2 and clock signal CLK are each transmitted by, for example, LVDS (Low Voltage Differential Signaling). That is, as shown in FIG. 1, each of the serial data signals Ds1 and Ds2 and the clock signal CLK is configured using a pair (two) of differential transmission signals. As a result, high-speed transmission using small-amplitude signals becomes possible, and the ability to remove common-mode noise is improved by using differential transmission signals. Furthermore, although the details will be described later (FIG. 5), each of the serial data signals Ds1 and Ds2 is synchronized with the clock signal CLK, and within one clock period (period of one period T described later), 7 bits worth of Contains serial data. However, the serial data is not limited to 7 bits, and may be serial data with a number of bits other than 7 bits (one or a plurality of bits).

Further, in the present embodiment, each of these serial data signals Ds1 and Ds2, which will be described in detail later (see FIG. 5), has an m-bit (m: integer of 2 or more, 4 bits in this example) serial pixel Other signals are multiplexed with the data signal PDs. Specifically, in this example, the serial data signal Ds1 includes a 4-bit serial pixel data signal PDs and a strobe signal STB, which will be described later. In this example, the serial data signal Ds2 includes a 4-bit serial pixel data signal PDs and a firing signal (ejection start signal) FIRE, which will be described later. Further, in the present embodiment, the serial data signal Ds1 includes a serial pixel data signal PDs individually defined corresponding to odd-numbered nozzles among a plurality of nozzles in the inkjet head 1, which will be described later. It is designed to be On the other hand, the serial data signal Ds2 includes serial pixel data signals PDs individually defined corresponding to even-numbered nozzles among a plurality of nozzles in the inkjet head 1, which will be described later. .

Note that such a serial pixel data signal PDs corresponds to a specific example of "image data signal" in the present disclosure.

(B. Inkjet head 1)
1 and 2, the ink jet head 1 ejects droplets of ink 9 onto a recording medium from a plurality of nozzles, which will be described later, to form images and characters. It is a head that performs recording such as. This inkjet head 1, as shown in FIG. 1, includes one connector 50, one relay board 51, and four drive circuit boards 52a, 52b, 52c, and 52d.

As shown in FIG. 1, the connector 50 receives serial data signals Ds1 and Ds2 and a clock signal CLK supplied from the head controller 2 to the inkjet head 1 (each drive circuit board 52a, 52b, 52c, 52d). are input, respectively.

The relay board 51, as shown in FIG. 1, is a board that relays the serial data signals Ds1 and Ds2 and the clock signal CLK between the connector 50 and the drive circuit boards 52a, 52b, 52c and 52d.

Each of the drive circuit boards 52a, 52b, 52c, and 52d is a board provided with the injection section 11 and the drive section 12, as shown in FIG. Serial data signals Ds1 and Ds2 and a clock signal CLK are input from the head control section 2 through the connector 50 and the relay board 51 to the drive sections 12 on these drive circuit boards 52a, 52b, 52c and 52d, respectively. It is designed to be 2, each drive section 12 has a plurality of drive circuit sections (in this example, four drive circuit sections 12a, 12b, 12c, and 12d).

(B-1. Injection portion 11)
The injection unit 11 has a plurality of nozzles described above, and according to the driving signal Sd (driving voltage Vd) supplied from the driving unit 12 (each driving circuit unit 12a, 12b, 12c, 12d), these nozzles Ink 9 is jetted (see FIGS. 1 and 2).

Such an injection section 11 includes, for example, a piezoelectric actuator (actuator plate) 111 and a nozzle plate 112 as shown in FIG.

The nozzle plate 112 is a plate made of a film material such as polyimide or a metal material, and as shown in FIG. , and nozzle holes Hn). These nozzle holes Hn1 to Hn512 are, for example, arranged in a straight line (one row) at predetermined intervals, and have a circular shape, for example.

Each of these nozzle holes Hn1 to Hn512 (plurality of nozzle holes Hn) corresponds to a specific example of "nozzle" in the present disclosure.

The piezoelectric actuator 111 is a plate made of a piezoelectric material such as PZT (lead zirconate titanate). This piezoelectric actuator 111 is provided with a plurality of channels (pressure chambers) (not shown). These channels are portions for applying pressure to the ink 9, and are arranged side by side so as to be parallel to each other with a predetermined interval. Each channel is defined by a drive wall (not shown) made of a piezoelectric material, and forms a recessed groove when viewed in cross section.

Such channels include ejection channels for ejecting the ink 9 and dummy channels (non-ejection channels) for not ejecting the ink 9 . In other words, the ejection channels are filled with the ink 9 while the dummy channels are not filled with the ink 9 . Each discharge channel communicates with the nozzle hole Hn in the nozzle plate 112, while each dummy channel does not communicate with the nozzle hole Hn. These ejection channels and dummy channels are arranged alternately.

A drive electrode (not shown) is provided on each of the opposing inner surfaces of the drive wall. The drive electrodes include a common electrode (common electrode) provided on the inner surface facing the ejection channel, and an active electrode (individual electrode) provided on the inner surface facing the dummy channel. These drive electrodes and drive circuit portions 12a, 12b, 12c, and 12d, which will be described later, are electrically connected via a plurality of extraction electrodes (not shown) formed on a flexible substrate (not shown). ing. As a result, the driving voltage Vd (driving signal Sd) described above is applied to each driving electrode from the driving circuit portions 12a, 12b, 12c, and 12d via the flexible substrate (FIGS. 1 to 1). See Figure 4).

(B-2. Drive circuit units 12a, 12b, 12c, 12d)
As shown in FIG. 2, the drive circuit units 12a, 12b, 12c, and 12d each generate a drive signal Sd for ejecting the ink 9 from each of the corresponding nozzle holes Hn in the ejection unit 11. (driving voltage Vd). Specifically, the drive circuit units 12a, 12b, 12c and 12d respectively generate the drive signal Sd based on the serial data signals Ds1 and Ds2 and the clock signal CLK supplied from the head control unit 2 described above. The drive circuit units 12 a , 12 b , 12 c , and 12 d are adapted to output the drive signals Sd thus generated to the corresponding plurality of nozzle holes Hn in the injection unit 11 .

As shown in FIG. 2, the driving circuit portion 12a outputs the driving signal Sd corresponding to the nozzle holes Hn1 to Hn128, and the driving circuit portion 12b outputs the driving signal Sd corresponding to the nozzle holes Hn129 to Hn256. is being output. The driving circuit portion 12c outputs a driving signal Sd corresponding to the nozzle holes Hn257 to Hn384, and the driving circuit portion 12d outputs a driving signal Sd corresponding to the nozzle holes Hn385 to Hn512. That is, drive signals Sd corresponding to 128 nozzle holes Hn are output from the drive circuit portions 12a, 12b, 12c, and 12d (see FIG. 2).

Further, as shown in FIG. 2, the plurality of drive circuit units 12a, 12b, 12c, and 12d are arranged in series with each other in the inkjet head 1 (on the respective drive circuit boards 52a, 52b, 52c, and 52d). They are connected in multiple stages (cascade connection). In other words, the number of stages of cascade connection between the drive circuit portions 12a, 12b, 12c, and 12d in the inkjet head 1 (on each of the drive circuit boards 52a, 52b, 52c, and 52d) is four. Specifically, as shown in FIG. 2, the head control unit 2, the drive circuit unit 12d (front stage), the drive circuit unit 12c, the drive circuit unit 12b, and the drive circuit unit 12a (last stage) are arranged in this order from the front stage side. A cascade connection is made to the rear stage side, and data transfer is performed in this order, although the details will be described later.

Here, for example, as shown in FIG. 3, such drive circuit units 12a, 12b, 12c, and 12d are serial/parallel conversion unit 121, drive signal generation unit 122, parallel/serial conversion unit 123, and jitter suppressor, respectively. It has a circuit 124 .

(Serial/parallel converter 121)
The serial/parallel converter 121 converts a predetermined value based on the serial data signals Ds1 and Ds2 each containing the m-bit (in this example, 4-bit) serial pixel data signal PDs and the clock signal CLK. This is a circuit that performs serial/parallel conversion. Through such serial/parallel conversion, an m-bit (4-bit in this example) parallel pixel data signal PDp (PDp[3:0]) is generated as shown in FIG.

Specifically, as shown in FIG. 3, the serial/parallel conversion unit 121 performs such serial/parallel conversion to convert the 4-bit parallel pixel data signal PDp, the strobe signal STB and the firing signal described above. They each generate a signal FIRE. A clock signal CLK is also output from the serial/parallel converter 121 (see FIG. 3).

(Drive signal generator 122)
The drive signal generator 122 generates the aforementioned drive signal Sd (drive voltage Vd) for each of the plurality of nozzle holes Hn. Specifically, as shown in FIG. 3, the drive signal generator 122 generates an m-bit (4-bit in this example) parallel pixel data signal PDp, a strobe signal STB, a firing signal FIRE, and a clock signal CLK. and the sample clock signal SCLK, such a drive signal Sd is generated. The sample clock signal SCLK is individually supplied to each of the drive circuit sections 12a, 12b, 12c and 12d in each of the drive circuit boards 52a, 52b, 52c and 52d ( See Figure 2).

Such a drive signal generation section 122 has a shift register section 122A, a latch circuit section 122B, a waveform selection circuit section 122C, a level conversion section 122D and a waveform generation circuit 122E, as shown in FIG. 4, for example.

The waveform generation circuit 122E is a circuit that generates the latch enable signal EN and the ejection waveform data Dw based on the sample clock signal SCLK and the firing signal FIRE, as shown in FIG. The latch enable signal EN generated in this manner is output to each latch circuit 42 in the latch circuit section 122B described later, and the ejection waveform data Dw is output to each waveform selection circuit 43 in the waveform selection circuit section 122C described later. (See FIG. 4).

As shown in FIG. 4, the shift register unit 122A shifts the parallel pixel data signal PDp for each of the plurality of nozzle holes Hn from the front stage side to the rear stage side in correspondence with the drive signal Sd for each of the plurality of nozzle holes Hn. This is a circuit that sequentially transfers and holds data. The shift register section 122A has the same number of FF (flip-flop) circuits 41 as the number of corresponding nozzle holes Hn (128 in this example). It is possible to hold the pixel data signal PDp. Further, to each FF circuit 41, as a shift clock for sequential transfer, for example, a logical product signal (AND signal) of a clock signal CLK and a strobe signal STB (shift enable signal) is input. (See Figure 4). In other words, the shift register section 122A sequentially transfers the parallel pixel data signals PDp in synchronization with such AND signals.

As shown in FIG. 4, the latch circuit section 122B converts the 4-bit parallel pixel data signal PDp for each of the plurality of nozzle holes Hn, which is output from each FF circuit 41 in the shift register section 122A, into the above latch enable signal. This is a circuit for holding in synchronism with the signal EN. The latch circuit section 122B has the same number of latch circuits 42 as the number of corresponding nozzle holes Hn (128 in this example). can be retained.

As shown in FIG. 4, the waveform selection circuit section 122C includes a 4-bit parallel pixel data signal PDp for each of the plurality of nozzle holes Hn, which is output from each latch circuit 42 in the latch circuit section 122B, and the above-described discharge signal. It is a circuit that generates a waveform signal that is the basis of the drive signal Sd based on the waveform data Dw. The waveform selection circuit section 122C has the same number of waveform selection circuits 43 as the number of corresponding nozzle holes Hn (128 in this example). is generated.

As shown in FIG. 4, the level conversion unit 122D converts each of the plurality of nozzle holes Hn based on the waveform signals of the plurality of nozzle holes Hn output from the waveform selection circuits 43 in the waveform selection circuit unit 122C. is a circuit for generating the drive signal Sd of . The level conversion section 122D has the same number of level conversion circuits 44 as the number of corresponding nozzle holes Hn (128 in this example). Each level conversion circuit 44 converts the level (voltage value) of each waveform signal to generate a drive signal Sd having a drive voltage Vd corresponding to each nozzle hole Hn. (See Figure 4).

(Jitter suppression circuit 124)
The jitter suppression circuit 124 is a circuit that suppresses jitter in a predetermined input signal and outputs the signal. Specifically, as shown in FIG. 3, the jitter suppression circuit 124 suppresses and outputs jitter in the clock signal CLK output from the serial/parallel converter 121 (outputs the clock signal CLK1 after jitter suppression). ).

The clock signal CLK input to the jitter suppression circuit 124 in this manner corresponds to a specific example of the "predetermined input signal" in the present disclosure. The clock signal CLK (CLK1) output from the jitter suppression circuit 124 corresponds to one specific example of "signal after jitter suppression" and "output signal from the jitter suppression circuit" in the present disclosure.

(Parallel/serial converter 123)
The parallel/serial conversion unit 123 is a circuit that performs predetermined parallel/serial conversion based on the m-bit (in this example, 4-bit) parallel pixel data signal PDp and the clock signal CLK. By such parallel/serial conversion, as shown in FIG. 3, the two serial data signals Ds1 and Ds2 described above are generated (regenerated), respectively, and these serial data signals Ds1 and Ds2 and the clock signal CLK are respectively generated. , to the outside of each of the drive circuit sections 12a, 12b, 12c and 12d.

Specifically, the parallel/serial conversion unit 123 converts the 4-bit parallel pixel data signal PDp output from the last-stage FF circuit 41 (see FIG. 4) in the shift register unit 122A and the The above parallel/serial conversion is performed based on the clock signal CLK (CLK1) after jitter suppression, the strobe signal STB, and the firing signal FIRE (see FIG. 4).

The parallel/serial converter 123 also functions as a skew adjuster, as shown in FIG. Specifically, the parallel/serial conversion unit 123 converts the jitter-suppressed clock signal CLK (CLK1) output from the jitter suppression circuit 124 to other signals including the parallel pixel data signal PDp (a plurality of these signals). input signals). That is, the parallel/serial converter 123 performs such skew adjustment between the clock signal CLK1, the parallel pixel data signal PDp, the strobe signal STB and the firing signal FIRE (see FIG. 3).

Each of these parallel pixel data signal PDp, strobe signal STB, and firing signal FIRE corresponds to a specific example of "another signal including an image data signal" in the present disclosure. Also, the clock signal CLK (CLK1), the parallel pixel data signal PDp, the strobe signal STB, and the firing signal FIRE each correspond to a specific example of "plurality of input signals" in the present disclosure.

Here, as shown in FIGS. 2 and 3, the serial data signals Ds1 and Ds2 and the clock signal CLK output from the parallel/serial conversion section 123 in the drive circuit section located relatively at the front stage are as follows. It is input to the serial/parallel conversion section 121 in the drive circuit section located relatively on the rear stage side. That is, the signal (clock signal CLK1) after jitter suppression by the jitter suppression circuit 124 in the drive circuit section located relatively in the front stage is input as the clock signal CLK to the drive circuit section located relatively in the rear stage. (See Fig. 3).

Specifically, as shown in FIG. 2, the serial data signals Ds1 and Ds2 and the clock signal CLK (CLK1) output from the drive circuit section 12d in the relatively preceding stage (the foremost stage) are arranged in the relatively subsequent stage. is input to the side drive circuit section 12c. Similarly, the serial data signals Ds1 and Ds2 and the clock signal CLK (CLK1) output from the drive circuit section 12c on the relatively front stage side are input to the drive circuit section 12b on the relatively rear stage side. Similarly, the serial data signals Ds1 and Ds2 and the clock signal CLK (CLK1) output from the drive circuit section 12b on the relatively front stage side are input to the drive circuit section 12a on the relatively rear stage side (last stage). It is Thus, as shown in FIG. 2, the plurality of drive circuit sections 12a, 12b, 12c, and 12d are serially connected in multiple stages (cascaded).

[Operation and action/effect]
(A. Basic operation of printer 3)
In this printer 3, the following operation of ejecting ink 9 by the inkjet head 1 is used to perform a recording operation (printing operation) of images, characters, etc. on a recording medium. Specifically, in the inkjet head 1 of the present embodiment, the ejection operation of the ink 9 using the shear mode is performed as follows.

First, the drive circuit units 12a, 12b, 12c, and 12d in each drive unit 12 apply a drive voltage Vd (a drive signal Sd) is applied. Specifically, each of the drive circuit units 12a, 12b, and 12c applies a drive voltage Vd to each of the drive electrodes arranged on the pair of drive walls that define the aforementioned ejection channel. As a result, the pair of drive walls are deformed so as to protrude toward the dummy channel adjacent to the ejection channel.

At this time, the driving wall bends and deforms in a V shape centering on the intermediate position in the depth direction of the driving wall. Due to such bending deformation of the driving wall, the ejection channel is deformed as if it were expanding. In this way, the volume of the ejection channel increases due to bending deformation due to the piezoelectric thickness slip effect in the pair of drive walls. As the volume of the ejection channel increases, the ink 9 is guided into the ejection channel.

Next, the ink 9 guided into the ejection channel in this manner becomes a pressure wave and propagates inside the ejection channel. Then, at the timing when this pressure wave reaches the nozzle hole Hn of the nozzle plate 112, the drive voltage Vd applied to the drive electrode becomes 0 (zero)V. As a result, the driving wall is restored from the bending deformation state described above, and as a result, the once increased volume of the discharge channel returns to its original volume.

In this way, when the volume of the ejection channel is restored, the pressure inside the ejection channel increases and the ink 9 inside the ejection channel is pressurized. As a result, ink droplets 9 are ejected to the outside (toward the recording medium) through the nozzle holes Hn (see FIGS. 1 and 2). In this manner, the ink 9 is ejected from the inkjet head 1, and as a result, an image, characters, or the like is printed on the recording medium.

(B. Data transfer operation)
Next, with reference to FIGS. 5 to 7 in addition to FIGS. 1 to 4, the relationship between the head control section 2 and the drive circuit section 12d and between the drive circuit sections 12a, 12b, 12c, and 12d is described. The data transfer operation will be described in detail while comparing with a comparative example (FIG. 6) described later.

(B-1. Present embodiment)
FIG. 5 is a schematic timing chart showing an operation example (data transfer operation example) in each of the drive circuit units 12a, 12b, 12c, and 12d shown in FIG. In FIG. 5, one cycle of the clock signal CLK is indicated as a cycle T, and the same applies to FIG. 7 described later.

In FIG. 5, (A) to (D) are respectively output from the serial/parallel conversion unit 121 in each of the drive circuit units 12a, 12b, 12c, and 12d and input to the parallel/serial conversion unit 123. Shows parallel data. Specifically, (A) is the strobe signal STB, (B) is the 4-bit parallel pixel data signal PDp[3:0] (each bit data of PDp[0] to PDp[3]), ( C) indicates the firing signal FIRE, and (D) indicates the clock signal CLK.

On the other hand, in FIG. 5, (E) to (G) are respectively input to the serial/parallel conversion section 121 in each of the drive circuit sections 12a, 12b, 12c, and 12d and output from the parallel/serial conversion section 123. , showing the serial data. Specifically, (E) represents the clock signal CLK, and (F) and (G) represent the serial data signals Ds1 and Ds2, each of which includes a 4-bit serial pixel data signal PDs[3:0]. showing.

In FIG. 5, for the parallel pixel data signal PDp and the serial pixel data signal PDs, a signal corresponding to the n-th nozzle hole Hn (n: an integer from 1 to 512) among the plurality of nozzle holes Hn is used. For convenience, they are shown as PDp(n) and PDs(n), respectively.

The data transfer operation of this embodiment is as follows in each of the drive circuit sections 12a, 12b, 12c, and 12d, as shown in FIG.

That is, first, each of the serial data signals Ds1 and Ds2 synchronizes with the clock signal CLK and includes 7-bit serial data within a period of the period T (one clock period) (Fig. 5(E) to See timings t1-t2, t3-t4, t5-t6 in (G)). Of these serial data signals Ds1 and Ds2, the serial data signal Ds1 is serial/parallel converted by the serial/parallel conversion unit 121 to be a 4-bit parallel pixel data signal PDp[3:0] (odd-numbered (corresponding to the positioned nozzle hole Hn) and the strobe signal STB are respectively generated (see FIG. 5(F)). On the other hand, the serial data signal Ds2 undergoes serial/parallel conversion in the serial/parallel converter 121 to be converted into a 4-bit parallel pixel data signal PDp[3:0] (corresponding to even-numbered nozzle holes Hn). , and the firing signal FIRE are respectively generated (see FIG. 5(G)). In this example, the serial pixel data signals PDs[3:0] are the four bits from the beginning of the serial data signals Ds1 and Ds2.
there is

Here, the shift clock (the above-described clock AND signal of signal CLK and strobe signal STB) is input. Therefore, this period becomes an effective period of data input (input of the parallel pixel data signal PDp) to the shift register section 122A (see FIG. 5B).

During this period, first, 4-bit parallel pixel data signals PDp(1) to PDp(512) corresponding to the nozzle holes Hn1 to Hn512 are sequentially input to the shift register section 122A (see FIGS. 4 and 5). (B)). As described above, each of the drive circuit units 12a, 12b, 12c, and 12d processes parallel pixel data signals PDp corresponding to 128 nozzle holes Hn. 1) to PDp(128). Next, in the shift register section 122A, the parallel pixel data signals PDp(1) to PDp(128) sequentially transferred and held are synchronized with the latch enable signal EN and stored in the latch circuit section 122B. It is held in the latch circuit 42 (see FIG. 4). Subsequently, at the timing when the firing signal FIRE changes from "L (0)" to "H (1)", each waveform selection circuit 43 in the waveform selection circuit section 122C is held in each latch circuit 42. Based on the parallel pixel data signals PDp(1) to PDp(128), generation of the waveform signal that is the basis of the drive signal Sd is started (see FIGS. 4 and 5(C)). Based on these waveform signals, the level converter 122D generates driving signals Sd (Sd(1) to Sd(128)) corresponding to the 128 nozzle holes Hn. Ink 9 is discharged from each nozzle hole Hn based on (see FIGS. 1, 2, and 4).

Also, at this time, the 4-bit parallel pixel data signal PDp[3:0] output from the last-stage FF circuit 41 of the shift register section 122A is parallel/serial-converted in the parallel/serial conversion section 123. (See FIGS. 3 and 4). Specifically, based on the 4-bit parallel pixel data signal PDp[3:0], the firing signal FIRE, the strobe signal STB, and the clock signal CLK (CLK1) output from the jitter suppression circuit 124, The serial data signals Ds1 and Ds2 are regenerated by parallel/serial conversion (see FIGS. 3 and 5(E) to (G)). The serial data signals Ds1 and Ds2 regenerated in this manner are output together with the clock signal CLK from the parallel/serial conversion section 123 to the outside of the drive circuit sections 12a, 12b, 12c and 12d ( 3, FIG. 5(F), and FIG. 5(G)).

Further, in this embodiment, the data transfer operation of the drive unit 12 as a whole shown in FIG. 2 is as follows.

That is, first, the 4-bit parallel pixel data signal PDp in the drive circuit section 12d at the frontmost stage becomes the serial data signals Ds1 and Ds2 as described above, and the drive circuit section 12c at the rear stage of the drive circuit section 12d is converted to the serial data signals Ds1 and Ds2. output to Similarly, the 4-bit parallel pixel data signal PDp in the drive circuit section 12c becomes the serial data signals Ds1 and Ds2 as described above, and is output to the drive circuit section 12b in the subsequent stage of the drive circuit section 12c. be done. Similarly, the 4-bit parallel pixel data signal PDp in the drive circuit section 12b becomes the serial data signals Ds1 and Ds2 as described above, and the drive circuit section in the latter stage (last stage) of the drive circuit section 12b is generated. 12a.

In this way, the parallel pixel data signals PDp for the drive circuit sections 12a, 12b, 12c, and 12d are sequentially shifted together with the clock signal CLK (CLK1) from the drive circuit section 12d to the drive circuit section 12c, respectively. 12b and 12a are sequentially transferred (see FIG. 2).

(B-2. Comparative example)
Here, FIG. 6 is a block diagram showing a configuration example of each of the drive circuit units 102a, 102b, and 102c in the liquid jet head (inkjet head 101) according to the comparative example. In the inkjet head 101 of this comparative example, as in the inkjet head 1 of the present embodiment shown in FIG. , are serially connected in multiple stages (cascade connection).

The drive circuit sections 102a, 102b, 102c, and 102d in the inkjet head 101 correspond to the drive circuit sections 12a, 12b, 12c, and 12d (see FIG. 3) in the inkjet head 1 as follows. there is That is, as shown in FIG. 6, each of the drive circuit units 102a, 102b, 102c, and 102d does not include the jitter suppression circuit 124 in each of the drive circuit units 12a, 12b, 12c, and 12d. , and other configurations are basically the same.

Further, since the jitter suppression circuit 124 is not provided, the drive circuit units 102a, 102b, 102c, and 102d are configured as follows. That is, the clock signal CLK output from the serial/parallel converter 121 is input as it is (without jitter suppression) to the parallel/serial converter 123 as the clock signal CLK2 (see FIG. 6). ).

Therefore, in the inkjet head 101 of this comparative example, the following may occur due to noise generated in the cascade-connected drive circuit units 102a, 102b, 102c, and 102d themselves and outside thereof. That is, when the jitter in the input clock signal CLK and the jitter in the own circuit caused by such noise are combined into the output clock signal CLK, the jitter increases. There is As the jitter increases in this way, it becomes difficult to increase the number of stages of cascade connection. number of lines) will increase. Specifically, the number of signals between the head control section 2 and the drive circuit section 102d and between the drive circuit sections 102a, 102b, 102c, and 102d increases (see FIG. 2). As a result of the increase in the number of signal lines in this way, in this comparative example, there is a possibility that the inkjet head 101 will become larger and the degree of freedom in designing the inkjet head 101 will decrease.

(B-3. Action and effect)
On the other hand, in the inkjet head 1 of the present embodiment, as shown in FIG. A suppression circuit 124 is provided. In addition, the clock signal CLK (CLK1) after jitter suppression by the jitter suppression circuit 124 in the drive circuit section located relatively on the front stage side is input to the drive circuit section located on the relatively rear stage side. As a result, these drive circuit sections 12a, 12b, 12c, and 12d are serially connected in multiple stages (cascaded) (see FIG. 2).

As a result, in the inkjet head 1 of the present embodiment, compared with the inkjet head 101 of the comparative example, in which such a jitter suppression circuit 124 is not provided in each of the drive circuit units 102a, 102b, 102c, and 102d, the following become that way.

That is, in the present embodiment, the number of stages of cascade connections in the cascade connection between the plurality of drive circuit units 12a, 12b, 12c, and 12d can be easily increased as compared with the comparative example. Specifically, since the jitter suppression circuit 124 is provided in each of the drive circuit units 12a, 12b, 12c, and 12d, the above-described increase in jitter (jitter in the input clock signal CLK and An increase in jitter due to synthesizing the jitter with the clock signal CLK to be output is suppressed. Therefore, in this embodiment, the jitter contained in the output signal (clock signal CLK1) from the jitter suppression circuit 124 is kept small, so that the number of stages of cascade connection can be easily increased.

In this way, in the present embodiment, the number of stages of cascade connection can be easily increased. (the number of signal lines can be reduced). Specifically, the number of signal lines between the head control unit 2 and the drive circuit unit 12d and between the drive circuit units 12a, 12b, 12c, and 12d can be reduced compared to the comparative example. becomes (see FIG. 2).

As described above, in the inkjet head 1 of the present embodiment, the number of signal lines can be reduced. It is possible to improve the degree and the like. Specifically, since the degree of freedom in design increases, for example, it is possible to expand the number of nozzles (the number of nozzle holes Hn) without changing the hardware of the printer 3 . Further, for example, it is possible to perform high-speed data transfer while using the low-speed clock signal CLK.

Further, in the present embodiment, in parallel/serial conversion section 123, skew adjustment between the output signal (jitter-suppressed clock signal CLK1) from jitter suppression circuit 124 and other signals (between a plurality of input signals) is performed. is output to the outside of each drive circuit section 12a, 12b, 12c, 12d (see FIGS. 2 and 3). That is, the output signals (serial data signals Ds1 and Ds2) subjected to skew adjustment in addition to the jitter suppression described above are sent to the outside of each of the drive circuit units 12a, 12b, 12c and 12d (for example, the drive circuit units in the latter stage). is output, the number of stages of cascade connection can be increased more easily. Therefore, in the present embodiment, it is possible to further reduce the size of the inkjet head 1 and further improve the degree of freedom in designing the inkjet head 1 .

Here, FIG. 7 is a schematic timing chart showing the above-described jitter suppression and skew adjustment by comparing the operation examples according to the present embodiment and the comparative example. Specifically, in FIG. 7, (A) shows the clock signal CLK1 (the jitter-suppressed clock signal CLK output from the jitter suppression circuit 124) in this embodiment. (B) shows serial data signals Ds1 and Ds2 after jitter suppression and skew adjustment (data signal Data1: see FIG. 3). On the other hand, (C) shows the clock signal CLK2 (the clock signal CLK directly input from the serial/parallel converter 121 to the parallel/serial converter 123) in the comparative example (see FIG. 6). (D) shows the serial data signals Ds1 and Ds2 (data signal Data2: see FIG. 6) output to the outside of the drive circuit units 102a, 102b, 102c, and 102d of the comparative example.

First, since the jitter suppression circuit 124 is not provided in the comparative example, the jitter contained in the clock signal CLK2 causes a change from "L (Low)" to "H (High)" in the clock signal CLK2. is not constant but fluctuates (see periods T1, T2, T3 and T4 in FIG. 7(C)). When the clock signal CLK2 including such jitter is directly input to the parallel/serial conversion unit 123 and skew-adjusted, the data signal Data2 including jitter is, for example, as indicated by solid lines in FIGS. As indicated by the arrow, after the delay time Δt, the parallel/serial conversion section 123 outputs (see FIG. 7(D)). The clock signal CLK2 and the data signal Data2 output from the parallel/serial conversion unit 123 in this manner are processed as input data at synchronous timing in the subsequent drive circuit unit. Data reception may occur (see dashed arrows in FIGS. 7C and 7D).

On the other hand, in the present embodiment, in the clock signal CLK1 after jitter suppression output from the jitter suppression circuit 124, the period T of change from "L" to "H" is constant (Fig. See period T in 7(A)). When the jitter-suppressed clock signal CLK1 is input to the parallel/serial converter 123 and skew-adjusted, the jitter-suppressed and skew-adjusted data signal Data1 is, for example, shown in FIGS. ), it is output from the parallel/serial converter 123 after a delay time Δt (see FIG. 7B). When the clock signal CLK1 and the data signal Data1 output from the parallel/serial conversion unit 123 in this manner are processed as input data at synchronized timings in the drive circuit unit in the subsequent stage, the comparative example In contrast, normal data can be received (see dashed arrows in FIGS. 7A and 7B). It can be said that it is very significant to use the clock signal CLK1 after jitter suppression by the jitter suppression circuit 124 as an input signal to the parallel/serial conversion unit 123 that performs skew adjustment in this way.

Further, in the present embodiment, the input signals (serial data signals Ds1, Ds2 and clock signal CLK) to the drive circuit units 12a, 12b, 12c, 12d are all differential transmission signals (LVDS described above). Therefore (see FIGS. 1 to 4), it is as follows. That is, when data is transmitted from the head control section 2 to the drive circuit sections 12a, 12b, 12c, and 12d, high-speed transmission can be realized and noise resistance can be improved.

Furthermore, in the present embodiment, the clock signal CLK is used as the input signal to the jitter suppression circuit 124, and the jitter in the clock signal CLK is suppressed (see FIG. 3). becomes possible. This is because the effect of suppressing jitter increases as the frequency of the signal increases. This is because the frequency of errors in receiving data becomes more conspicuous if jitter is not suppressed when the frequency of the signal is high (see FIG. 7 above).

In addition, in the present embodiment, since the parallel pixel data signal PDp is sequentially transferred from the front stage side to the rear stage side in the shift register section 122A, the position number (nozzle number) of the nozzle hole Hn to be driven is , the transfer of the parallel pixel data signal PDp can be performed. As a result, for example, it is possible to reduce the circuit size and simplify the data transfer procedure. Further, since the parallel pixel data signal PDp is sequentially transferred in the shift register section 122A in synchronization with the AND signal of the clock signal CLK and the strobe signal STB (shift enable signal), the strobe signal STB, that is, such With the operation enable signal for the sequential transfer operation, unnecessary circuit operation time can be reduced, and power can be saved.

<2. Variation>
Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to these embodiments, and various modifications are possible.

For example, in the above-described embodiment, specific configuration examples (shape, arrangement, number, etc.) of each member in the printer 3 and the inkjet head 1 have been described, but they are not limited to those described in the above-described embodiment. , other shapes, arrangements, numbers, and the like.

Moreover, as the structure of the inkjet head, it is possible to apply each type. That is, for example, a so-called side shoot type inkjet head that ejects the ink 9 from the central portion in the extending direction of each ejection channel in the piezoelectric actuator 111 may be used. Alternatively, for example, a so-called edge shoot type inkjet head that ejects the ink 9 along the extending direction of each ejection channel may be used. Furthermore, the printer system is not limited to the system described in the above embodiment, and examples include a thermal system (bubble jet (registered trademark) system), a MEMS (Micro Electro Mechanical Systems) system, a thermal paper system, a dot Various methods such as an impact method can be applied.

Furthermore, for example, it may be either a circulating inkjet head that circulates the ink 9 between the ink container and the inkjet head, or a non-circulating inkjet head that uses the ink 9 without circulating it. However, it is possible to apply the present disclosure.

In addition, in the above-described embodiment, the data transfer method is explained by giving specific examples, but the data transfer method is not limited to the example given in the above-described embodiment, and data transfer is performed using other methods. good too.

Also, the series of processes described in the above embodiment may be performed by hardware (circuit) or by software (program). When it is performed by software, the software consists of a program group for executing each function by a computer. Each program, for example, may be installed in the computer in advance and used, or may be installed in the computer from a network or a recording medium and used.

Furthermore, in the above embodiment, the printer 3 (inkjet printer) was described as a specific example of the "liquid jet recording apparatus" in the present disclosure, but the invention is not limited to this example, and other apparatuses other than the inkjet printer can be used. It is also possible to apply the present disclosure to In other words, the "liquid jet head" (inkjet head) of the present disclosure may be applied to devices other than inkjet printers. Specifically, for example, the "liquid jet head" of the present disclosure may be applied to devices such as facsimiles and on-demand printers.

Additionally, the various examples described so far may be applied in any combination.

Note that the effects described in this specification are merely examples and are not limited, and other effects may be provided.

In addition, the present disclosure can also be configured as follows.
(1)
an injection unit having a plurality of nozzles for injecting liquid;
a plurality of driving signals for ejecting the liquid from the nozzles based on an image data signal and a clock signal supplied from an external head control unit, and outputting the driving signals to the ejecting unit; with a drive circuit and
Each of the plurality of drive circuit units
a drive signal generator that generates the drive signal for each of the plurality of nozzles;
a jitter suppression circuit that suppresses and outputs jitter in a predetermined input signal,
Between the plurality of drive circuit units,
A signal after jitter suppression by the jitter suppression circuit in the drive circuit section located relatively on the front stage side is
By being input to the drive circuit section located relatively on the rear stage side,
The liquid jet head, wherein the plurality of drive circuit units are connected in series with each other in multiple stages.
(2)
Each of the plurality of drive circuit units
A parallel/serial conversion unit that receives an output signal from the jitter suppression circuit and another signal including the image data signal as a plurality of input signals, and adjusts skew between the plurality of input signals. further having
The liquid jet head according to (1) above, wherein an output signal from the parallel/serial conversion section is output to the outside of the drive circuit section.
(3)
The liquid jet head according to (1) or (2), wherein the image data signal and the clock signal supplied from the head control section to the drive circuit section are differential transmission signals.
(4)
The liquid jet head according to any one of (1) to (3), wherein the predetermined input signal is the clock signal.
(5)
The drive signal generation unit has a shift register unit that sequentially transfers and holds the image data signal from the front stage side to the rear stage side in accordance with the drive signal for each of the plurality of nozzles,
The liquid jet head according to (4) above, wherein the shift register section performs sequential transfer from the front stage side to the rear stage side in synchronization with an AND signal of the clock signal and the strobe signal.
(6)
a liquid jet head according to any one of (1) to (5) above;
and a head control unit that supplies the image data signal and the clock signal to the liquid jet head.

DESCRIPTION OF SYMBOLS 1... Inkjet head 11... Ejection part 111... Piezoelectric actuator (actuator plate) 112... Nozzle plate 12... Drive part 12a, 12b, 12c, 12d... Drive circuit part 121... Serial/parallel conversion part 122 122A: Shift register section 122B: Latch circuit section 122C: Waveform selection circuit section 122D: Level conversion section 122E: Waveform generation circuit 123: Parallel/serial conversion section (skew adjustment section) 124 Jitter suppression circuit 2 Head controller 3 Printer 41 FF circuit 42 Latch circuit 43 Waveform selection circuit 44 Level conversion circuit 50 Connector 51 Relay board 52a, 52b , 52c, 52d... Drive circuit board 9... Ink Hn, Hn1 to Hn512... Nozzle hole Ds1, Ds2... Serial data signal Data1, Data2... Data signal PDs... Serial pixel data signal PDp... Parallel pixel data signal , Dw... ejection waveform signal, CLK, CLK1, CLK2... clock signal, SCLK... sample clock signal, STB... strobe signal, EN... latch enable signal, FIRE... firing signal, Sd... drive signal, Vd... drive voltage, t . . . time, t1 to t6 .. timing, .DELTA.t .

Claims (6)

an injection unit having a plurality of nozzles for injecting liquid;
a plurality of driving signals for ejecting the liquid from the nozzles based on an image data signal and a clock signal supplied from an external head control unit, and outputting the driving signals to the ejecting unit; drive circuit and
with
Each of the plurality of drive circuit units
a drive signal generator that generates the drive signal for each of the plurality of nozzles;
a jitter suppression circuit that suppresses and outputs jitter in a predetermined input signal; ,
A parallel/serial conversion unit that receives an output signal from the jitter suppression circuit and another signal including the image data signal as a plurality of input signals, and adjusts skew between the plurality of input signals. When
and
an output signal from the parallel/serial conversion unit is output to the outside of the drive circuit unit;
Between the plurality of drive circuit units,
The signal after jitter suppression by the jitter suppression circuit in the drive circuit section located relatively on the front stage side is
By being input to the drive circuit section located relatively on the rear stage side,
The plurality of drive circuit units are connected in series with each other in multiple stages.
liquid jet head. 2. The liquid jet head according to claim 1 , wherein the image data signal and the clock signal supplied from the head control section to the drive circuit section are differential transmission signals. an injection unit having a plurality of nozzles for injecting liquid;
a plurality of driving signals for ejecting the liquid from the nozzles based on an image data signal and a clock signal supplied from an external head control unit, and outputting the driving signals to the ejecting unit; drive circuit and
with
Each of the plurality of drive circuit units
a drive signal generator that generates the drive signal for each of the plurality of nozzles;
a jitter suppression circuit that suppresses and outputs jitter in a predetermined input signal;
and
the image data signal and the clock signal supplied from the head control unit to the drive circuit unit are differential transmission signals, respectively;
Between the plurality of drive circuit units,
A signal after jitter suppression by the jitter suppression circuit in the drive circuit section located relatively on the front stage side is
By being input to the drive circuit section located relatively on the rear stage side,
The plurality of drive circuit units are connected in series with each other in multiple stages.
liquid jet head. The liquid jet head according to any one of claims 1 to 3, wherein the predetermined input signal is the clock signal. an injection unit having a plurality of nozzles for injecting liquid;
a plurality of driving signals for ejecting the liquid from the nozzles based on an image data signal and a clock signal supplied from an external head control unit, and outputting the driving signals to the ejecting unit; drive circuit and
with
Each of the plurality of drive circuit units
a drive signal generator that generates the drive signal for each of the plurality of nozzles;
a jitter suppression circuit that suppresses and outputs jitter in the clock signal;
and
The drive signal generation unit has a shift register unit that sequentially transfers and holds the image data signals from the front stage side to the rear stage side in accordance with the drive signals for each of the plurality of nozzles, and
The shift register section performs sequential transfer from the front stage side to the rear stage side in synchronization with a logical product signal of the clock signal and the strobe signal,
Between the plurality of drive circuit units,
A signal after jitter suppression by the jitter suppression circuit in the drive circuit section located relatively on the front stage side is
By being input to the drive circuit section located relatively on the rear stage side,
The plurality of drive circuit units are connected in series with each other in multiple stages.
liquid jet head. a liquid jet head according to any one of claims 1 to 5;
and a head control unit that supplies the image data signal and the clock signal to the liquid jet head.

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