JP7173653B2 - Display element mounting board and display device - Google Patents

Description

The present disclosure relates to a display element mounting substrate and a display device.

In recent years, micro LED displays have attracted attention as next-generation displays. A micro-LED display is intended to achieve a high-definition display with a wide viewing angle by arranging LED elements in high density. In addition, the micro LED display can be configured with any screen size and aspect ratio according to the installation location by pasting together a plurality of display units each having a plurality of LED elements. is expected.

For example, Patent Literature 1 discloses a technique of configuring a large-screen micro LED display by bonding printed circuit boards made of resin on which a plurality of LED elements are mounted in a tile shape.

JP 2015-197544 A

However, when mounting a plurality of LED elements on a printed circuit board made of resin, there is a problem that the printed circuit board is more likely to warp as the area of the printed circuit board increases. Moreover, when the number of wiring layers laminated on the front surface and the back surface of the printed circuit board is different, the stress applied to the printed circuit board also causes the printed circuit board to warp.

If the printed circuit board on which the LED elements are mounted is thus warped, there arises a problem that the printed circuit board cannot be laid out at high density. In addition, it becomes difficult to seamlessly bond printed circuit boards. Therefore, it becomes difficult to manufacture a high-definition display device.

Accordingly, one object of the present disclosure is to provide a display element mounting substrate with reduced substrate warpage. Another object is to provide a high-definition display device.

The display device mounting substrate according to the present disclosure is
A display element mounting substrate on which one display element and one drive IC for controlling one display element are mounted,
a glass substrate having a first side and a second side;
a first multilayer wiring layer provided on the first surface;
a second multilayer wiring layer provided on the second surface;
an insulating layer provided between the first multilayer wiring layers;
a bump connected to a first wiring layer provided in the uppermost layer of the first multilayer wiring layer;
has
The number of layers of the second multilayer wiring layer is smaller than the number of layers of the first multilayer wiring layer,
The driving IC is provided on the same surface as the display element,
A first wiring layer provided in the uppermost layer of the first multilayer wiring layer is electrically connected to the display element and the driving IC via bumps.

In the above configuration, the glass substrate has a through-hole extending through the first surface and the second surface.

The above configuration further includes through electrodes provided in the first surface, the second surface, and the through holes.

In the above structure, the insulating layer has an opening in a region overlapping the through hole, and further has a through electrode provided in the opening and the through hole.

In the above configuration, the through electrode is electrically connected to the first wiring layer.

In the above structure, the driver IC is provided on the same surface as the display element.

In the above configuration, the display elements are LED elements or EL elements.

The display device according to the present disclosure is
a plurality of display element mounting substrates arranged in a matrix;
a control circuit for controlling a plurality of display element mounting substrates,
The display element mounting board is
a wiring board;
one display element arranged on the wiring substrate;
one driving IC for controlling one display element;
has
The wiring board
a glass substrate having a first side and a second side;
a first multilayer wiring layer provided on the first surface;
a second multilayer wiring layer provided on the second surface;
an insulating layer provided on the first multilayer wiring layer;
a bump connected to a first wiring layer provided in the uppermost layer of the first multilayer wiring layer;
has
The number of layers of the first multilayer wiring layer is greater than the number of layers of the second multilayer wiring layer,
The driving IC is provided on the same surface as the display element,
A first wiring layer provided in the uppermost layer of the first multilayer wiring layer is electrically connected to the display element and the driving IC via bumps.

In the above configuration, the glass substrate has a through-hole extending through the first surface and the second surface.

The above configuration further includes through electrodes provided in the first surface, the second surface, and the through holes.

In the above structure, the insulating layer has an opening in a region overlapping the through hole, and further has a through electrode provided in the opening and the through hole.

In the above configuration, the through electrodes are electrically connected to the first wiring layer.

In the above structure, the driver IC is provided on the same surface as the display element.

In the above configuration, the display elements are LED elements or EL elements.

Accordingly, one object of the present disclosure is to provide a display element mounting substrate with reduced substrate warpage. Another object is to provide a large-screen display device.

1 is a plan view for explaining a display device according to the present disclosure; FIG. 2 is a cross-sectional view along line A1-A2 of the display device shown in FIG. 1; FIG. 4 is a pixel circuit of a display device according to the present disclosure; 4 is a pixel circuit of a display device according to the present disclosure; 1 is a plan view for explaining a display element mounting substrate according to the present disclosure; FIG. 1 is a plan view for explaining a display element mounting substrate according to the present disclosure; FIG. 6B is a cross-sectional view taken along line B1-B2 shown in FIG. 6A; FIG. Sectional drawing explaining the wiring board which concerns on this indication. 4A to 4C are cross-sectional views for explaining the manufacturing process of the wiring board according to the present disclosure; 4A to 4C are cross-sectional views for explaining the manufacturing process of the wiring board according to the present disclosure; 4A to 4C are cross-sectional views for explaining the manufacturing process of the wiring board according to the present disclosure; 4A to 4C are cross-sectional views for explaining the manufacturing process of the wiring board according to the present disclosure; Sectional drawing explaining the wiring board which concerns on this indication. Sectional drawing explaining the wiring board which concerns on this indication. Sectional drawing explaining the wiring board which concerns on this indication.

Hereinafter, the display element mounting substrate and the display device according to the present disclosure will be described in detail with reference to the drawings. The embodiments shown below are examples, and the present disclosure should not be construed as being limited to these embodiments. In the drawings referred to in the following embodiments, the same reference numerals or similar reference numerals are given to the same portions or portions having similar functions, and repeated description thereof may be omitted. Also, the dimensional ratios in the drawings may differ from the actual ratios for convenience of explanation, and some configurations may be omitted from the drawings.

<First Embodiment>
A display device 100 according to the first embodiment will be described in detail with reference to FIGS. 1 to 11. FIG.

[Structure of display device]
FIG. 1 shows an example of a planar configuration of a display device 100 according to the first embodiment. As shown in FIG. 1, the display device 100 has a display area 102 and a control circuit 103 that controls the display area 102 on a substrate 101 . A plurality of display element mounting substrates 110 arranged in a matrix are provided in the display area 102 . In the display area 102, a plurality of display element mounting substrates 110 are laid out in a tiled manner.

The substrate 101 is preferably made of a material with high rigidity, and for example, a glass substrate, a stainless steel substrate, or the like can be used. Also, the control circuit 103 may be an external driver IC, or may be a circuit built into the substrate 101 .

FIG. 2 shows a cross-sectional view of the display device 100 shown in FIG. 1 along line A1-A2. As shown in FIG. 2, a plurality of display element mounting substrates 110 are provided on the substrate 101 . The display element mounting board 110 also includes a wiring board 111 , a display element 112 provided on the wiring board 111 , and a driving IC 113 . Also, the display element 112 and the driving IC 113 are connected to the wiring board 111 by a plurality of bumps 114 . Also, the driving IC 113 is provided on the same surface as the display element 112 .

A substrate constituting the wiring substrate 111 is preferably made of a material having high rigidity. Therefore, as a substrate constituting the wiring substrate 111, a glass substrate, a quartz substrate, a sapphire substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO ₂ ) substrate, or A substrate in which these substrates are laminated can be used. Further, the substrate constituting the wiring substrate 111 may include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate. The wiring configuration of the wiring board 111 will be described in detail later.

Also, one through electrode 115 is provided for each of the plurality of display element mounting substrates 110 . The through-electrode 115 is provided in a through-hole passing through the first surface (upper side in FIG. 7) of the wiring substrate 111 and the second surface opposite to the first surface. The through electrode 115 has a function of electrically connecting the wiring extending from the control circuit 103 of the substrate 101 and the wiring extending on the first surface of the wiring substrate 141 .

Wiring extending on the first surface of the wiring substrate 111 is connected to the display element 112 and the driving IC via a plurality of bumps 114 .

An LED element can be used as the display element 112 . As the LED element, it is preferable to use a chip of micrometer order, for example, it is preferable to use an LED chip of several tens of μm square. In the LED element, an LED that emits red light, an LED that emits green light, and an LED that emits blue light may be composed of different LED chips, or may be composed of a common LED chip. good. A light-emitting element such as an organic EL element can also be used as the display element 112 . Note that the emission colors of the display element 112 are not limited to three colors, and may be four or more colors.

Further, the driving IC 113 has a function of controlling the display element 112 . Although the driver IC 113 and the display element 112 are shown as different components in FIG. 2, the present disclosure is not limited to this, and an integrated circuit including the display element and the driver IC can also be used.

[Pixel circuit]
FIG. 3 shows a pixel circuit in region 104 of display device 100 shown in FIG. In the area 104, display element mounting substrates 110 are provided in 2 rows×2 columns. A display element 112 and a driving IC 113 are provided on each of the four display element mounting substrates 110 . Note that the display element mounting substrate 110 shown in FIG. 3 corresponds to one pixel of the display device 100 .

As shown in FIG. 3, the display area 102 includes gate lines 211 and voltage lines 212 extending in the row direction, a plurality of signal lines 213 extending in the column direction, reference voltage lines 214 and 215, and a power supply line 216. , 217 and a ground line 218 are provided.

A display element 112 and a driver IC 113 are provided for each pixel. The drive IC 113 is connected to gate lines 211 , voltage lines 212 , signal lines 213 , reference voltage lines 214 and 215 , power supply lines 216 and 217 and a ground line 218 . Also, the display element 112 is connected to the driving IC 113 and the ground line 218 . Note that in the pixel circuit illustrated in FIG. 3 , different blocks are used to clarify the functions of the display element and the driver IC, but the present disclosure is not limited to this. An integrated circuit in which the display element and the driving IC are packaged together may be used.

As shown in FIG. 3, each row of the plurality of gate lines 211 is provided with a through electrode 115a, and each row of the plurality of voltage lines 212 is provided with a through electrode 115b. Each column of the plurality of signal lines 213 is provided with a through electrode 115c, and each column of the plurality of ground lines 218 is provided with a through electrode 115d. The through electrodes 115a are connected to the drive ICs 113 via the gate lines 211 . The through electrode 115b, the through electrode 115c, and the through electrode 115d are similarly connected to the drive ICs 113 via the voltage line 212, the signal line 213, and the ground line 218, respectively.

FIG. 3 shows an example in which the through electrodes 115a are provided in each row of the gate lines 211, but the present invention is not limited to this. The penetrating electrodes may be provided for each of a plurality of rows or for each of a plurality of columns.

FIG. 4 shows an example in which the display element mounting substrate 110 is provided in 3 rows×3 columns. In FIG. 4, for the sake of explanation, the wiring is omitted as appropriate. The plurality of gate lines 211 are provided with through electrodes 115a for each row, and the plurality of signal lines 213 are provided with through electrodes 115c for each column. The through electrodes 115b are connected to voltage lines 212 in three rows, and the through electrodes 115d are connected to ground lines 218 in three columns. Thus, the number of through electrodes 115a to 115d may be different. Also, the number of drive ICs 113 controlled by one through electrode is not particularly limited. The through electrodes 115a to 115d can be appropriately provided according to the pixel layout.

Although not shown in FIGS. 3 and 4, the reference voltage lines 214 and 215 and the power supply lines 216 and 217 can also be provided with through electrodes.

A signal for selecting the display element 112 is input to the gate line 211 from the control circuit 103 through the through electrode 115a. The signal that selects the display element 112 is, for example, a signal that starts sampling of the signal input to the signal line 213, inputs the sampled signal to the display element 112, and causes the display element 112 to start emitting light.

A signal corresponding to the video signal is input to the signal line 213 from the control circuit 103 via the through electrode 115c. Further, the signal according to the video signal is, for example, a signal for controlling the light emission luminance of the display element 112 . Note that FIG. 4 shows the case where a single signal line 213 is provided, but the present invention is not limited to this. The number of signal lines 213 can be provided according to the number of emission colors of the display element. For example, if the display element 112 has three colors of red, green, and blue, three signal lines 213 can be provided.

Reference voltage lines 214 and 215, power lines 216 and 217, and ground line 218 receive fixed voltages from the control circuit. A signal having, for example, a sawtooth waveform is input to the voltage line 212 from the control circuit.

As described above, the wiring extending from the control circuit 103 provided on the substrate 101 is connected to the gate line 211, the voltage line 212, and the signal line extending on the first surface of the wiring substrate 111 by the through electrodes 115a to 115d. It can be connected to each of the line 213 and the ground line 218 .

[Connecting part between wiring board and display element]
Next, a connection portion between the wiring board 111 and the display element and the driver IC will be described in detail. FIG. 5 shows a plan view when the wiring substrate 111 is viewed from above. In FIG. 5 , a plurality of wiring layers 122 are provided on the plurality of wiring layers 121 , and a plurality of wiring layers 123 are provided on the plurality of wiring layers 122 . Also, the plurality of wiring layers 121 extend along the first direction, and the plurality of wiring layers 122 extend along the second direction crossing the first direction. An integrated circuit 116 including a display element and a driver IC is provided over the plurality of wiring layers 123 . In FIG. 5, the area indicated by the solid line is the area where the integrated circuit 116 is provided. The integrated circuit 116 has, for example, 24 pins, 16 pins on the outer circumference and 8 pins on the inner circumference. Note that the number of pins of the integrated circuit 116 is not limited to 24 pins.

The wiring layers 311 to 316 and the wiring layers 321 to 326 are, for example, the gate line 211, the voltage line 212, the signal line 213, and the power lines 216 and 217 shown in FIG. These wirings are connected to the integrated circuit 116 .

FIG. 6B shows a cross-sectional view of wiring substrate 111 along line B1-B2 in region 120 where integrated circuit 116 is provided. As shown in FIG. 6B , the wiring substrate 111 has a multilayer wiring layer 130 provided on the first surface 140 a of the substrate 140 . FIG. 6B shows an example in which three wiring layers are provided in the multilayer wiring layer 130, but the present disclosure is not limited to this, and four or more wiring layers may be provided.

A wiring layer 131 is provided on the first surface 140 a of the substrate 140 , and an insulating layer 124 is provided on the wiring layer 131 . Wiring layers 133 and 134 are provided over the insulating layer 124 , and an insulating layer 125 is provided over the wiring layers 133 and 134 . A wiring layer 137 and a wiring layer 139 are provided over the insulating layer 125 . Furthermore, an insulating layer 126 is provided over the wiring layer 137 and the wiring layer 139 .

The wiring layer 131 is connected to the wiring layer 133 through the via 132 , the wiring layer 133 is connected to the wiring layer 137 through the via 135 , and the wiring layer 137 is connected to the under bump metal 143 . It is connected. Also, the wiring layer 134 is connected to the wiring layer 139 via the via 138 , and the wiring layer 139 is connected to the under bump metal 144 . Then, the under bump metals 143 and 144 are connected to the solder balls of the integrated circuit 116 (the plurality of bumps 114 shown in FIG. 2).

As shown in FIG. 6A, the pins provided on the inner circumference of the integrated circuit 116 are provided at a narrow pitch. Therefore, vias connected to pins provided on the inner circumference of the integrated circuit 116 are preferably provided as so-called stacked vias in which the positions of the under bump metal 143 and the vias 135 overlap. Moreover, vias connected to pins provided on the periphery of the integrated circuit 116 are preferably provided as so-called staggered vias in which the positions of the under bump metal 144 and the vias 138 do not overlap.

A signal output from the control circuit 103 shown in FIG. 1 is input to the integrated circuit 116 via the multilayer wiring layer 130 shown in FIG. 6B.

[Configuration example of wiring board]
A wiring board according to the present disclosure can take various forms. A cross-sectional configuration of a wiring board according to the present disclosure will be described with reference to FIGS. 7 to 11. FIG.

FIG. 7 shows a cross-sectional view of a wiring board 141 according to the present disclosure. The wiring substrate 141 includes a substrate 140 having a first surface 140a and a second surface 140b opposite to the first surface 140a. The substrate 140 is preferably made of a highly rigid material, such as a glass substrate, a quartz substrate, a sapphire substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO ₂ ) substrate. , or a substrate in which these substrates are laminated can be used. Further, the substrate 140 may include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate. The thickness of the substrate 140 is not particularly limited.

The substrate 140 is provided with a through hole 142 penetrating through the substrate 140 from the first surface 140a to the second surface 140b. The hole diameter of the opening of the through-hole 142 is 5 μm or more and 300 μm or less, preferably 20 μm or more and 100 μm or less. In this specification, the hole diameter refers to the diameter of the through hole, and when the cross section of the through hole is not circular, the diameter of the circle whose circumference is the length of the circumference of the cross section is the diameter of the through hole. Width, that is, pore size.

A multilayer wiring layer 150 is provided on the first surface 140 a of the substrate 140 . In FIG. 7, the number of wiring layers in the multilayer wiring layer 150 is three. The wiring layer 151 is connected to the wiring layer 152 via vias, and the wiring layer 152 is connected to the under bump metal 154 . An insulating layer 159 is provided between the wiring layers. The insulating layer 159 has openings 158 in regions overlapping the through holes 142 of the substrate 140 . A through electrode 153 is provided in the opening 158 of the insulating layer 159 and the through hole 142 of the substrate 140 . The through electrode 153 provided on the second surface 140b side is connected to wiring extending from the control circuit 103 on the substrate 101 shown in FIG. 1 or FIG.

Further, as shown in FIG. 7, an example in which an insulator 155 is provided in the through-hole 142 of the substrate 140 and an insulator 156 is provided in the opening 158 of the insulating layer 159 is shown, but the present disclosure is not limited to The through hole 142 may be provided with a conductor instead of the insulator 155 , and the opening 158 may be provided with a conductor instead of the insulator 156 . Also, the through hole 142 and the opening 158 may not necessarily be provided with an insulator or conductor.

Note that FIG. 7 shows an example in which the substrate 140 has the through holes 142, but the present disclosure is not limited to this. As described with reference to FIGS. 1 to 3 , in the display device according to the present disclosure, the display element mounting substrates 110 having the through-holes 142 may be provided at a ratio of one to the plurality of display element mounting substrates 110 .

In the wiring board 141 according to the present disclosure, the number of multilayer wiring layers 150 provided on the first surface 140a is different from the number of multilayer wiring layers provided on the second surface 140b. FIG. 7 shows a case where the number of multilayer wiring layers 150 on the first surface 140a provided with the integrated circuit 116 and the driving IC 113 is larger than the number of multilayer wiring layers provided on the second surface 140b. there is

[Method for manufacturing wiring board]
Next, a method for manufacturing the wiring board 141 shown in FIG. 7 will be described with reference to FIGS. 8A to 8D.

FIG. 8A is a cross-sectional view illustrating a step of forming the through-hole 142 and the wiring layer 151. FIG. First, through holes 142 are formed in the substrate 140 so as to penetrate the first surface 140a and the second surface 140b.

Note that the through holes 142 may be formed by, for example, irradiating the substrate 140 with high-power laser light to melt the substrate 140 . For example, when a glass substrate is used as the substrate 140, a CO ₂ laser or the like can be used as a laser capable of melting the glass substrate. When using an excimer laser, an Nd:YAG laser, or a femtosecond laser Nd:YAG laser as a laser for laser processing, a fundamental wave with a wavelength of 1064 nm, a second harmonic with a wavelength of 532 nm, and a wavelength of A third harmonic of 355 nm or the like can be used.

Alternatively, the through-holes 142 can be formed by appropriately combining laser light irradiation and wet etching. First, a modified layer is formed in a region of the substrate 140 where the through hole 142 is to be formed by irradiating laser light. Alternatively, the through holes 142 of the substrate 140 may be formed by blasting the substrate 140 with an abrasive.

When a glass substrate is used as the substrate 140, hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), surfactant-added buffered hydrofluoric acid (LAL), or the like is used as a chemical used for wet etching. As chemical solutions other than hydrofluoric acid, sulfuric acid (H ₂ SO ₄ ), nitric acid (HNO ₃ ), hydrochloric acid (HCl), etc. are used. Alternatively, a chemical solution obtained by mixing the above chemical solutions may be used. A chemical used for wet etching can be appropriately selected according to the material of the substrate 140 .

In addition, dry etching may be used to form the through holes 142. For example, a reactive ion etching (RIE) method or a DRIE (Deep Reactive Ion Etching) method using the Bosch process may be used. good too. Alternatively, the through holes 142 may be formed by a laser ablation method. The shape of the through-hole 142 may be adjusted by performing a discharge treatment on the inside of the formed through-hole 142 after the through-hole 142 is formed by the laser ablation method.

For the formation of the through holes 142, wet etching may be combined with the processing method including the above dry etching.

Next, the wiring layer 151 is formed on the first surface 140 a of the substrate 140 . The thickness of the wiring layer 151 is, for example, 0.5 μm or more and 10 μm or less. As the wiring layer 151, a metal such as copper, gold, platinum, tin, aluminum, nickel, chromium, titanium, or tungsten, or an alloy combining these metals can be used. As a method for forming the wiring layer 151, for example, after forming a conductive film on the substrate 140 by a sputtering method, a resist pattern is formed by a photolithography method, and the conductive film is etched using the resist pattern as a mask. Etching can be performed by dry etching or wet etching. After that, the wiring layer 151 can be formed by removing the resist pattern.

As another method for forming the wiring layer 151, a seed layer is formed by a vapor deposition method, a sputtering method, or the like. Next, a resist pattern is formed on the seed layer by photolithography, and a metal layer is formed on the seed layer by electroplating. Next, after removing the resist pattern, the seed layer is removed by etching. Etching can be performed by dry etching or wet etching.

As materials for the metal layer, metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, or alloys of these metals can be used. Also, the metal layer can have a single-layer structure or a laminated structure using the above materials. As the material of the seed layer, the same material as that of the metal layer may be used. An alloy combining these metals is sometimes used. Also, the seed layer can have a single-layer structure or a laminated structure using the above materials. In addition, although the method of forming the wiring layer 151 by the electroplating method has been described above, the method is not limited to this, and the electroplating method and the electroless plating method may be combined.

FIG. 8B is a cross-sectional view illustrating a step of forming the insulating layer 157 and the wiring layer 152 on the first surface 140a of the substrate 140. FIG. First, the insulating layer 157 is formed on the first surface 140 a of the substrate 140 . At this time, the through hole 142 may also be filled with an insulator. For example, the insulating layer 157 can be formed by covering the first surface 140a of the substrate 140 with a resin film and performing heat treatment in a vacuum atmosphere. As a material of the insulating layer 157, curable resin such as polyimide resin, epoxy resin, phenolic resin, cycloolefin, PBO (polybenzoxazole) resin can be used. Alternatively, the insulating layer 157 may be formed by applying an organic material by spin coating. Polyimide, epoxy, and acrylic materials can be used as organic materials. The thickness of the insulating layer 157 is, for example, 0.5 μm or more and 10 μm or less.

Next, the insulating layer 157 is patterned by photolithography to form an opening through which the wiring layer 151 is exposed. After that, a conductive film is formed over the insulating layer 157 by a sputtering method, and then patterning is performed by a photolithography method to form the wiring layer 152 . The thickness of the wiring layer 152 is, for example, 0.5 μm or more and 10 μm or less. As the wiring layer 152, metals such as copper, gold, platinum, tin, aluminum, nickel, chromium, titanium, tungsten, or alloys of these metals can be used. In addition to the sputtering method, the conductive film can be formed by adjusting the type and thickness of the film by combining a method using a vacuum apparatus such as a vapor deposition method or a CVD method with a plating method such as electrolytic plating or electroless plating. good too. Note that since the material and formation method of the wiring layer 152 are the same as those of the wiring layer 151, the description of the wiring layer 151 can be referred to.

FIG. 8C is a cross-sectional view illustrating a step of further forming an insulating layer 159 on the insulating layer 157 and the wiring layer 152 and forming an opening 158. FIG. An insulating layer 159 is further formed over the insulating layer 157 and the wiring layer 152 . For the insulating layer 159, the method and material given for the insulating layer 157 can be used. Also, the thickness of the insulating layer 159 is, for example, 0.5 μm or more and 10 μm or less. Next, patterning is performed by a photolithography method, so that openings 158 can be formed in the insulating layer 159 in regions overlapping with the through holes 142 . Here, the insulating layer 157 provided inside the through hole 142 is also removed. Simultaneously with the formation of the opening 158, an opening exposing the wiring layer 152 is formed. Note that FIG. 8C shows that the insulating layer 159 and the insulating layer 157 are integrated with each other by forming the insulating layers 159 and 157 from the same material. In addition, the thicknesses of the insulating layers 157 and 159 can be adjusted by the thicknesses of the wiring layers 151 and 152 .

Through the steps described above, the multilayer wiring layer 150 can be formed on the first surface 140 a of the substrate 140 .

FIG. 8D is a cross-sectional view illustrating a step of forming the through electrode 153 in the opening 158 and the through hole 142. FIG. A conductive film is formed on the insulating layer 157, the opening 158, the through hole 142, and the second surface of the substrate 140 by a sputtering method. Next, the through electrode 153 can be formed by patterning by photolithography. As the through electrode 153, for example, metals such as copper, gold, platinum, tin, aluminum, nickel, chromium, titanium, and tungsten, or alloys in which these metals are combined can be used. The through electrode 153 is provided on the insulating layer 157 , the opening 158 , the through hole 142 , and the second surface 140 b of the substrate 140 . Also, the through electrode 153 is connected to the wiring layer 152 through the opening of the insulating layer 159 .

Next, the inside of the through-hole 142 of the substrate 140 is filled with an insulator 155 , and the inside of the opening 158 of the insulating layer 157 is filled with an insulator 156 . Finally, by forming the under bump metal 154 in the opening of the insulating layer 159, the wiring board 141 shown in FIG. 7 can be manufactured.

The wiring board 141 according to the present disclosure uses a board with high rigidity as the board 140 . Therefore, even if the number of wiring layers provided on each of the first surface 140a and the second surface 140b of the substrate 140 is different, the warping of the substrate 140 can be suppressed. Thereby, the wiring substrate 141 in which warping of the substrate is suppressed can be manufactured. Moreover, by mounting the integrated circuit 116 and the driving IC 113 on such a wiring board 141, it is possible to manufacture the display element mounting board 110 in which warping of the board is suppressed. The display element mounting substrate 110 according to the present disclosure suppresses the warping of the substrate, so that it can be laid out at high density. Also, a plurality of display element mounting substrates 110 can be seamlessly pasted together. Thereby, a high-definition display device can be manufactured.

Next, an example of a wiring board 161 that is partially different from the wiring board 141 shown in FIG. 7 will be described with reference to FIG. In addition, in FIG. 9, the same reference numerals are given to the parts showing the same configurations and materials as those in FIG.

A multilayer wiring layer 160 is provided on the first surface 140 a of the substrate 140 . In FIG. 9, the number of wiring layers in the multilayer wiring layer 160 is three. The wiring layer 151 is connected to the wiring layer 152 through vias, and the wiring layer 152 is connected to the wiring layer 163 through vias. Also, the wiring layer 163 is connected to the under bump metal 154 . Insulating layers 164 are provided between the wiring layers.

Further, through electrodes 162 are provided on the first surface 140 a and the second surface 140 b of the substrate 140 and the through holes 142 . The through electrode 162 and the wiring layer 151 can be formed by forming a conductive film on the substrate 140 by sputtering and then patterning it by photolithography. Although FIG. 8A to FIG. 8D describe the case where the through electrode 153 is formed after the multilayer wiring layer is formed, the through electrode 162 can also be formed in the same process as the wiring layer 151 .

Next, an example of a wiring board 171 that is partially different from the wiring board 161 shown in FIG. 9 will be described with reference to FIG. In addition, in FIG. 10 , the same reference numerals are given to the same configurations and materials as in FIG. 9 .

In the wiring substrate 171 shown in FIG. 10, the multilayer wiring layer 170 is provided not only on the first surface 140a of the substrate 140 but also on the second surface 140b. A wiring layer 172 is provided on the second surface 140 b of the multilayer wiring layer 170 , and a wiring layer 173 is provided via an opening in the insulating layer 164 . The wiring layer 172 can be formed in the same process as the through electrode 162 and the wiring layer 151 , and the wiring layer 173 can be formed in the same process as the wiring layer 152 . Thus, in the wiring board 171 according to the present disclosure, the multilayer wiring layers 160 and 170 are provided on the first surface 140a and the second surface 140b of the substrate 140, respectively, and the multilayer wiring layer 170 provided on the second surface 140b is The number of wiring layers can be less than the number of multilayer wiring layers provided on the first surface 140a.

Next, an example of a wiring board 181 that is partially different from the wiring board 141 shown in FIG. 7 will be described with reference to FIG. In addition, in FIG. 11 , the same reference numerals are given to the same configurations and materials as in FIG. 7 .

A multilayer wiring layer 180 is provided on the first surface 140 a of the substrate 140 . In FIG. 11, the number of wiring layers in the multilayer wiring layer 180 is two. The wiring layer 151 is connected to the wiring layer 152 via vias, and the wiring layer 152 is connected to the under bump metal 154 . An insulating layer 164 is provided between the wiring layers 151 and 152 and the under bump metal 154 .

Further, through electrodes 162 are provided on the first surface 140 a and the second surface 140 b of the substrate 140 and the through holes 142 . The through electrode 162 and the wiring layer 151 can be formed by forming a conductive film on the substrate 140 by sputtering and then patterning it by photolithography. As shown in FIG. 11, the number of wiring layers provided in the multilayer wiring layer 160 may be two.

As described with reference to FIGS. 7 to 11, the wiring board according to the present disclosure can take various forms. In the wiring boards 141, 161, and 181 according to the present disclosure, an example in which the multilayer wiring layer 160 is provided on the first surface 140a side of the substrate 140 and the single-layer wiring layer is provided on the second surface 140b side is shown. However, the present disclosure is not limited to this. A single wiring layer may be provided on the first surface 140a side, and a multilayer wiring layer may be provided on the second surface 140b side. Also, a multilayer wiring layer may be provided on each of the first surface 140a and the second surface 140b, and the number of wiring layers may be different between the first surface 140a side and the second surface 140b side. Since the wiring board according to the present disclosure uses a board with high rigidity, the board 140 has high rigidity even if the number of wiring layers provided is different between the first surface 140a and the second surface 140b. Therefore, warping of the wiring board can be suppressed.

Therefore, by mounting the display element and the driving IC on the wiring substrates 111, 141, 161, 171, and 181 according to the present disclosure, it is possible to manufacture a display element mounting substrate in which warping of the substrate is suppressed. The display element mounting substrate according to the present disclosure suppresses the warpage of the substrate, so that it can be laid out at high density. In addition, the display element mounting substrate can be seamlessly attached. Thereby, a high-definition display device can be manufactured. In addition, since the number of display element mounting substrates to be bonded together can be adjusted according to the installation location of the display device, a large-screen display device can be manufactured.

Each of the embodiments described above as embodiments of the present disclosure can be implemented in combination as appropriate as long as they do not contradict each other. In addition, based on each embodiment, addition, deletion, or design change of constituent elements as appropriate by those skilled in the art is also included in the scope of the present disclosure as long as it includes the gist of the present disclosure.

In addition, even if there are other effects that are different from the effects brought about by each of the above-described embodiments, those that are obvious from the description of this specification or those that can be easily predicted by those skilled in the art are of course It is understood that provided by the present disclosure.

100: display device, 101: substrate, 102: display area, 103: control circuit, 104: area, 110: display element mounting board, 111: wiring board, 112: display element, 113: drive IC, 114: bump, 115a 115d: through electrode, 120: region, 121: wiring layer, 122: wiring layer, 123: wiring layer, 124: insulating layer, 125: insulating layer, 126: insulating layer, 130: multilayer wiring layer, 131: wiring layer , 132: via, 133: wiring layer, 134: wiring layer, 135: via, 137: wiring layer, 138: via, 139: wiring layer, 140: substrate, 140a: first surface, 140b: second surface, 141 : wiring substrate 142: through hole 143: under bump metal 144: under bump metal 150: multilayer wiring layer 151: wiring layer 152: wiring layer 153: through electrode 154: under bump metal 155: Insulator 156: Insulator 157: Insulating layer 158: Opening 159: Insulating layer 160: Multilayer wiring layer 161: Wiring substrate 162: Penetrating electrode 163: Wiring layer 164: Insulating layer 170 : multilayer wiring layer, 171: wiring board, 172: wiring layer, 173: wiring layer, 180: multilayer wiring layer, 181: wiring board, 211: gate line, 212: voltage line, 213: signal line, 214: reference voltage line, 215: reference voltage line, 216: power supply line, 217: power supply line, 218: ground line

Claims (18)

A display element mounting substrate on which one display element and one drive IC for controlling the one display element are mounted,
a glass substrate having a first side and a second side;
a first multilayer wiring layer provided on the first surface;
a second multilayer wiring layer provided on the second surface;
an insulating layer provided between the first multilayer wiring layers;
a bump connected to a first wiring layer provided in the uppermost layer of the first multilayer wiring layer;
has
The number of layers of the second multilayer wiring layer is smaller than the number of layers of the first multilayer wiring layer,
The drive IC is provided on the same surface as the display element,
The display element mounting substrate, wherein the first wiring layer provided in the uppermost layer of the first multilayer wiring layer is electrically connected to the display element and the driving IC via the bumps. 2. The display element mounting board according to claim 1, wherein said glass substrate has a through hole passing through said first surface and said second surface. 3. The display element mounting substrate according to claim 2, further comprising through electrodes provided in said first surface, said second surface, and said through holes. The insulating layer has an opening in a region overlapping with the through hole,
3. The display element mounting substrate according to claim 2, further comprising through electrodes provided in said openings and said through holes. 5. The display element mounting substrate according to claim 3, wherein said through electrode is electrically connected to said first wiring layer provided in the uppermost layer of said first multilayer wiring layer. The first multilayer wiring layer has a second wiring layer provided in the lowest layer among the first multilayer wiring layers,
4. The display element mounting substrate according to claim 3, wherein said second wiring layer and said through electrodes are made of the same conductive film. 7. The display element mounting substrate according to any one of claims 1 to 6, further comprising an insulating layer on said first wiring layer provided as the uppermost layer among said first multilayer wiring layers. the wiring layers of the first multilayer wiring layer are connected via vias,
An integrated circuit including the display element and the driving IC is provided on the first wiring layer provided in the uppermost layer of the first multilayer wiring layer,
the bump connected to a pin provided inside the integrated circuit overlaps the via connected to the first wiring layer;
8. The display element mounting substrate according to claim 1, wherein said bumps connected to pins provided outside said integrated circuit do not overlap positions of said vias connected to said first wiring layer. . 9. The display element mounting substrate according to claim 1, wherein said display element is an LED element or an EL element. a plurality of display element mounting substrates arranged in a matrix;
a control circuit for controlling the plurality of display element mounting substrates,
The display element mounting substrate,
a wiring board;
one display element arranged on the wiring substrate;
one driving IC for controlling one display element;
has
The wiring board is
a glass substrate having a first side and a second side;
a first multilayer wiring layer provided on the first surface;
a second multilayer wiring layer provided on the second surface;
an insulating layer provided on the first multilayer wiring layer;
a bump connected to a first wiring layer provided in the uppermost layer of the first multilayer wiring layer;
has
The number of layers of the first multilayer wiring layer is larger than the number of layers of the second multilayer wiring layer,
The drive IC is provided on the same surface as the display element,
The display device, wherein the first wiring layer provided in the uppermost layer of the first multilayer wiring layer is electrically connected to the display element and the driving IC via the bumps. 11. The display device according to claim 10, wherein said glass substrate has a through hole passing through said first surface and said second surface. 12. The display device according to claim 11, further comprising through electrodes provided in said first surface, said second surface, and said through holes. The insulating layer has an opening in a region overlapping with the through hole,
12. The display device according to claim 11, further comprising through electrodes provided in said openings and said through holes. 14. The display device according to claim 12, wherein said through electrode is electrically connected to said first wiring layer provided in the uppermost layer of said first multilayer wiring layer. The first multilayer wiring layer has a second wiring layer provided in the lowest layer among the first multilayer wiring layers,
13. The display device according to claim 12, wherein said second wiring layer and said through electrodes are made of the same conductive film. 16. The display device according to any one of claims 10 to 15, further comprising an insulating layer on said first wiring layer provided as an uppermost layer among said first multilayer wiring layers. the wiring layers of the first multilayer wiring layer are connected via vias,
An integrated circuit including the display element and the driving IC is provided on the first wiring layer provided in the uppermost layer of the first multilayer wiring layer,
the bump connected to a pin provided inside the integrated circuit overlaps the via connected to the first wiring layer;
17. The display device according to claim 10, wherein said bumps connected to pins provided outside said integrated circuit do not overlap positions of said vias connected to said first wiring layer. 18. The display device according to any one of claims 10 to 17, wherein said display element is an LED element or an EL element.

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