JP7163554B2 - APPARATUS, METHOD, PROGRAM, SYSTEM AND COMPUTER READABLE STORAGE MEDIUM - Google Patents

Description

The present disclosure relates to computing systems, and in particular (but not exclusively) to point-to-point interconnections.

Advances in semiconductor processing and logic design have allowed for an increased amount of logic that can reside in an integrated circuit device. As a corollary, computer system architecture has evolved from single or multiple integrated circuits in the system to multiple cores, multiple hardware threads, and multiple logical processors residing on individual integrated circuits, and integrated within such processors. evolved into other interfaces that were A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, and the like.

The popularity of smaller computing devices has increased as a result of being able to fit more processing power in smaller packages. Smartphones, tablets, ultra-thin notebooks, and other user devices are growing exponentially. However, these smaller devices rely on servers for both data storage and complex processing beyond the form factor. Consequently, demand in the high-performance computing market (ie, the server space) is also increasing. For example, current servers typically have not only a single processor with multiple cores, but also multiple physical processors (also called multi-sockets) to increase computing power. However, as processing power increases along with the number of devices in computing systems, communication between sockets and other devices becomes more critical.

In fact, interconnects have grown from traditional multi-drop buses that primarily handled telecommunications to full-blown interconnect architectures that facilitate high-speed communications. Unfortunately, as demands on future processors for even higher speeds, demands are placed on the capabilities of existing interconnect architectures.

The same reference numbers and symbols in the various drawings identify the same elements.

1 illustrates an embodiment of a computing system including an interconnection architecture; Fig. 3 shows an embodiment of an interconnect architecture including a layered stack; 4 illustrates embodiments of requests or packets generated or received within the interconnect architecture. Fig. 3 shows an embodiment of a transmitter and receiver pair for interconnect architecture; Figure 3 shows an embodiment of an interconnection channel consisting of two exemplary connectors; 1 is a simplified block diagram of a cross-section of an interconnect structure including multiple vias; FIG. FIG. 4 is a cross-sectional representation of an interconnect employing via stub back-drilling; FIG. Fig. 2 is a block diagram representing a functional structure including a lane error status register; 1 is a simplified diagram showing data flow over a multi-lane interconnect; FIG. 4 shows a representation of an exemplary framing token symbol; 1 is a simplified diagram showing a data flow including an ordered set of exemplary skips (SKPs); FIG. FIG. 4 is a simplified block diagram showing lane errors that can be reported to an error register; FIG. 10 is a flow chart illustrating an exemplary technique for reporting lane errors for links; FIG. FIG. 10 is a flow chart illustrating an exemplary technique for reporting lane errors for links; FIG. FIG. 10 is a flow chart illustrating an exemplary technique for reporting lane errors for links; FIG. FIG. 10 is a flow chart illustrating an exemplary technique for reporting lane errors for links; FIG. 1 shows a block diagram of an embodiment for a computing system including a multi-core processor; FIG. FIG. 2 depicts a block diagram of another embodiment for a computing system including a multi-core processor; 1 shows a block diagram of an embodiment of a processor; FIG. 2 illustrates a block diagram of another embodiment of a computing system including a processor; FIG. 1 illustrates a block of an embodiment of a computing system including multiple processors; 1 shows an exemplary system implemented as a system-on-chip (SoC).

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. certain types of processors and system configurations, certain hardware structures, certain design and microdesign details, certain register configurations, certain instruction types, certain system components, certain dimensions/heights, 1 is an illustration of specific processor pipeline stages, operations, and the like; However, it will be apparent to one skilled in the art that these specific details need not be employed to practice the present invention. In other examples, specific and alternative processor architectures, specific logic circuitry/code for the described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials. , specific compiler implementations, specific representations of algorithms in code, specific power-down and gating techniques/logic, and other specific operational details of computer systems are not necessary for the present invention. not described in detail to avoid obscuring the

Although the following embodiments may be described with respect to energy conservation and energy efficiency in specific integrated circuits such as computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. is. Similar techniques and teachings of the embodiments described herein are applicable to other types of circuits or semiconductor devices, which may also benefit from greater energy efficiency and savings. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. It can also be used in other devices such as handheld devices, tablets, other thin notebooks, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include mobile phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (net PCs), set-top boxes, network hubs, wide area network (WAN) switches, or as taught below. Including any other system capable of performing the functions and operations. Additionally, the apparatus, methods and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will be readily apparent from the detailed description below, the method, apparatus, and system embodiments described herein (whether in terms of hardware, firmware, software, or combinations thereof) provide performance Considerations and balance are essential to the future of 'green technology'.

As computing systems have advanced, their components have become more complex. As a result, the interconnect architecture for coupling and communicating between components has also increased in complexity to ensure that bandwidth requirements for optimal component operation are met. Moreover, different market segments require different aspects of interconnect architectures to meet market needs. For example, servers require more performance, while the mobile ecosystem can sometimes sacrifice overall performance for power savings. However, the sole purpose of most fabrics is to provide the highest possible performance with maximum power savings. A number of the interconnections described below could potentially benefit from the aspects of the invention described herein.

One interconnect fabric architecture includes Peripheral Component Interconnect (PCI) Express (PCIe) architecture. The primary purpose of PCIe is to enable components and devices from different vendors to interoperate in an open architecture across multiple market segments: clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices. to do. PCI Express is a high performance general purpose I/O interconnect defined for a wide variety of future computing and communications platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interface, have been preserved through the revision, whereas previous parallel bus implementations were highly scalable, fully serial superseded by interfaces. More recent versions of PCI Express take advantage of advances in point-to-point interconnects, switch-based technology, and packetized protocols to deliver new levels of performance and features. Power management, quality of service (QoS), hot-plug/hot-swap support, data integrity, and error handling are among some of the advanced features supported by PCI Express.

Referring to FIG. 1, one embodiment of a fabric made up of point-to-point links interconnecting a series of components is shown. System 100 includes processor 105 and system memory 110 coupled to controller hub 115 . Processor 105 includes any processing element such as a microprocessor, host processor, embedded processor, co-processor, or other processor. Processor 105 is coupled to controller hub 115 via front side bus (FSB) 106 . In one embodiment, FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial, differential interconnect architecture conforming to a different interconnect standard.

System memory 110 includes any memory device such as random access memory (RAM), nonvolatile (NV) memory, or other memory accessible by devices in system 100 . System memory 110 is coupled to controller hub 115 via memory interface 116 . Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

In one embodiment, controller hub 115 is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of controller hubs 115 include chipset, memory controller hub (MCH), northbridge, interconnect controller hub (ICH), southbridge, and root controller/hub. The term chipset often refers to two physically separate controller hubs, namely a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems typically include an MCH integrated with processor 105, while controller 115 communicates with I/O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported via root complex 115 .

Here, controller hub 115 is coupled to switch/bridge 120 via serial link 119 . Input/output modules 117 and 121 , which may also be referred to as interfaces/ports 117 and 121 , contain/implement layered protocol stacks to provide communication between controller hub 115 and switch 120 . In one embodiment, multiple devices can be coupled to switch 120 .

The switch/bridge 120 is connected upstream from the device 125, i.e., up the hierarchy to the root complex, to the controller hub 115, and downstream, i.e., down the hierarchy from the root controller, from the processor 105 or system memory 110 to the device 125, a plurality of Route packets/messages. In one embodiment, switch 120 is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Devices 125 include I/O devices, network interface controllers (NICs), add-in cards, audio processors, network processors, hard drives, storage devices, CD/DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, It includes any internal or external device or component coupled to an electronic system, such as Firewire devices, Universal Serial Bus (USB) devices, scanners, and other input/output devices. PCIe terminology typically refers to such devices as endpoints. Although not specifically shown, device 125 may include a PCIe to PCI/PCI-X bridge to support legacy or other versions of PCI devices. Endpoint devices in PCIe are typically classified as legacy endpoints, PCIe endpoints, or root complex integrated endpoints.

Graphics accelerator 130 is also coupled to controller hub 115 via serial link 132 . In one embodiment, graphics accelerator 130 is coupled to MCH, which is coupled to ICH. Switch 120, and therefore I/O device 125, is then coupled to the ICH. I/O modules 131 and 118 also implement a layered protocol stack for communicating between graphics accelerator 130 and controller hub 115 . Similar to the MCH description above, the graphics controller or graphics accelerator 130 itself may be integrated into the processor 105 .

Turning to FIG. 2, one embodiment of a layered protocol stack is shown. Layered protocol stack 200 includes any form of layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or any other layered stack. Although the description immediately below with respect to FIGS. 1-4 relates to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack that includes transaction layer 205 , link layer 210 and physical layer 220 . Interfaces such as interfaces 117 , 118 , 121 , 122 , 126 and 131 in FIG. 1 may be represented as communication protocol stack 200 . What is represented as a communication protocol stack may also be referred to as a module or interface that implements/encloses the protocol stack.

PCI Express uses packets to communicate information between components. Packets are formed at the transaction layer 205 and data link layer 210 to carry information from the sending component to the receiving component. As the transmitted packet flows through other layers, it is augmented with additional information necessary to process the packet at those layers. On the receiving side, the reverse process occurs and the packet is transformed from what is represented as the physical layer 220 to what is represented as the data link layer 210 and finally (for transaction layer packets) the receiving device's transaction It is converted into a form that can be processed by layer 205 .

transaction layer

In one embodiment, transaction layer 205 provides an interface between the device's processing cores and interconnect architectures such as data link layer 210 and physical layer 220 . In this regard, the primary role of the transaction layer 205 is the assembly and disassembly of packets (ie, transaction layer packets or TLPs). Transaction layer 205 typically manages credit-based flow control for TLPs. PCIe implements split transactions, i.e., transactions with requests and responses separated by time, allowing the link to carry other traffic while the target device collects data for the response. .

PCIe also utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of a plurality of respective receive buffers within transaction layer 205 . An external device at the other end of the link, such as controller hub 115 of FIG. 1, counts the number of credits used by each TLP. A transaction may be submitted if the transaction does not exceed the credit limit. Once the response is received, the credit amount is restored. An advantage of the credit scheme is that credit return latency does not impact performance unless a credit limit is encountered.

In one embodiment, the four transaction address spaces include configuration address space, memory address space, input/output address space, and message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from memory-mapped locations. In one embodiment, memory space transactions can use two different address formats, eg, a short address format, such as 32-bit addresses, or a long address format, such as 64-bit addresses. A configuration space transaction is used to access the configuration space of a PCIe device. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

Thus, in one embodiment, transaction layer 205 assembles packet header/payload 206 . Formats for the current packet header/payload can be found in the PCIe specification at the PCIe specification website.

With quick reference to FIG. 3, one embodiment of a PCIe transaction descriptor is shown. In one embodiment, transaction descriptor 300 is a mechanism for conveying transaction information. In this regard, transaction descriptor 300 supports the identification of transactions within the system. Other potential uses include tracking modifications to the default transaction ordering and channel-to-transaction associations.

Transaction descriptor 300 includes global identifier field 302 , attribute field 304 and channel identifier field 306 . In the illustrated example, global identifier field 302 is shown to include local transaction identifier field 308 and source identifier field 310 . In one embodiment, the global transaction identifier 302 is unique for all outstanding requests.

According to one implementation, the local transaction identifier field 308 is a requesting agent-generated field that is unique for all outstanding requests requiring completion for that requesting agent. be. Further, in this example, source identifier 310 uniquely identifies the requesting agent within the PCIe hierarchy. Thus, the Local Transaction Identifier 308 field together with the Source ID 310 provide global identification of the transaction within the hierarchical domain.

Attributes field 304 specifies the characteristics and relationships of the transaction. In this regard, attribute field 304 is potentially used to provide additional information that allows modifications to the default processing of transactions. In one embodiment, attribute fields 304 include priority field 312 , reserved field 314 , ordering field 316 , and no snoop field 318 . Here, the priority subfield 312 may be modified by the initiator to assign a priority to that transaction. Reserved attribute field 314 is reserved for future or vendor-defined use. Possible usage models using priority or security attributes may be implemented using reserved attribute fields.

In this example, the ordering attribute field 316 is used to supply any information conveying the ordering type that can modify the default ordering rule. According to one exemplary implementation, an ordering attribute of '0' indicates that the default ordering rule applies, where an ordering attribute of '1' indicates relaxed ordering, where writes are identical Writes in one direction can pass, and read completions can pass writes in the same direction. Snoop attribute field 318 is utilized to determine if a transaction is snooped. As shown, channel ID field 306 identifies the channel with which the transaction is associated.

link layer

Link layer 210 , also called data link layer 210 , operates as an intermediate stage between transaction layer 205 and physical layer 220 . In one embodiment, the role of data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between the two components of the link. One side of the data link layer 210 accepts TLPs assembled by the transaction layer 205, applies packet sequence identifiers 211, i.e. identification or packet numbers, calculates and applies error detection codes, i.e. CRCs 212, Send the modified TLP to the physical layer 220 for transmission over the external device.

physical layer

In one embodiment, physical layer 220 includes a logical sub-block 221 and an electrical sub-block 222 for physically transmitting packets to external devices. Here, logical sub-block 221 is responsible for the “digital” functions of physical layer 221 . In this regard, the logical sub-block comprises a transmit section for preparing outgoing information for transmission by the physical sub-block 222 and a receive section for identifying and preparing received information before passing it to the link layer 210. including.

Physical block 222 contains a transmitter and a receiver. The transmitter is supplied symbols by logic sub-block 221, and the transmitter serializes and transmits them to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signal into a bitstream. The bitstream is deserialized and provided to logical sub-block 221 . In one embodiment, an 8b/10b transmission code is employed, in which 10-bit symbols are transmitted/received. Here, a special symbol is used to frame a packet with multiple frames 223 . In one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As noted above, the transaction layer 205, link layer 210, and physical layer 220 are described with respect to a particular embodiment of the PCIe protocol stack, but the layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, a typical port/interface for a layered protocol includes: (1) a first layer for assembling packets, the transaction layer; a second layer for ordering packets, the link layer; It includes three layers, the physical layer. As a specific example, the Common Standard Interface (CSI) layered protocol is utilized.

Turning now to Figure 4, an embodiment of a PCIe serial point-to-point fabric is shown. Although an embodiment of a PCIe serial point-to-point link is shown, serial point-to-point link includes any transmission path for transmitting serial data and is not so limited. In the illustrated embodiment, the basic PCIe link includes two low voltage, differentially driven signal pairs, a transmit pair 406/411 and a receive pair 412/407. Accordingly, device 405 includes transmitting logic 406 for transmitting data to device 410 and receiving logic 407 for receiving data from device 410 . In other words, two transmit paths, paths 416 and 417, and two receive paths, paths 418 and 419, are included in the PCIe link.

A transmission path refers to any path for transmitting data, such as a transmission line, copper wire, optical line, wireless communication channel, infrared communication link, or other communication path. For example, a connection between two devices, such as device 405 and device 410, is referred to as a link, such as link 415. A link may support one lane, with each lane representing a set of differential signal pairs (one pair for transmission and one pair for reception). To expand bandwidth, a link may aggregate multiple lanes denoted as xN, where N is, for example, 1, 2, 4, 8, 12, 16, 32, 64, or wider, any is the supported link width of .

A differential pair refers to two transmission paths such as lines 416 and 417 for transmitting differential signals. As an example, when line 416 switches from a low voltage level to a high voltage level, ie a rising edge, line 417 drives from a high logic level to a low logic level, ie a falling edge. Differential signals potentially exhibit better electrical properties, such as better signal integrity, ie, cross-coupling, voltage overshoot/undershoot, ringing, and the like. This allows for better timing windows and thus faster transmission frequencies.

fast channel

The revision to the PCIe I/O specification is PCIe Revision 4.0 (or PCIe 4.0). At 16GT/s bit rate, PCIe 4.0 aims to double the interconnect performance bandwidth over the PCIe 3.0 specification while maintaining compatibility with software and machine interfaces. Increased performance bandwidth over previous generation PCIe with the goal of providing lower cost, lower power, and minimal disruption at the platform level, while increasing bandwidth from a variety of developing applications It can provide performance scaling consistent with requirements. One of the key factors in the widespread adoption of the PCIe architecture is its high volume capability and its responsiveness to materials such as lower cost circuit boards, lower cost connectors, and the like.

The 16GT/s bitrate aims to provide the best tradeoff between performance, manufacturability, cost, power and compatibility. A feasibility analysis was performed to recommend characteristics for devices and channels supporting PCIe 4.0's 16 GT/s bit rate. PCI-SIG analysis spanned multiple topologies. For example, analysis determined that 16 GT/s on copper is technically feasible at nearly PCIe 3.0 power levels, which doubles the bandwidth relative to the PCIe 3.0 specification. . Here, the 16GT/s interconnect is potentially manufactured in mainstream silicon processing technology, using existing low-cost materials and infrastructure, while maintaining compatibility with previous generation PCIe architectures. Be expanded.

Higher data rate serial I/O (e.g., 16 GT/s under PCIe 4.0) can consume significant power and increase circuit complexity, which potentially reduces silicon ( Si) leading to increased use of the region. These considerations also have the potential to limit the integration of PCIe 4.0 (and other such high-speed interconnect architectures) into CPUs and systems that utilize higher lane counts. In some exemplary implementations, limits are imposed on the length of interconnects and the number of connectors employed within high-speed architectures such as PCIe 4.0. For example, such limits are defined at the specification level. In one example, the interconnect channel length is limited to one connector and less than 12 inches (30.48 centimeters) or 12 inches (30.48 centimeters).

Imposing restrictions on interconnect channels may limit their application to some systems. For example, in server interconnect applications, platform interconnects are sometimes up to 20 inches (50.8 centimeters) or longer and may have two connectors. For an architecture that limits interconnect channels to a maximum length of 12 inches (30.48 centimeters) and a single connector, among other potential examples, two 12-inch (30.48 centimeters) A separate repeater chip or other additional device would be included to combine the 48 cm) channels and accommodate the distance between multiple devices in the server system.

In some implementations, interconnect links configured to be compliant with PCIe 4.0 and other interconnects can be provided, allowing for lengths of 20 GT/s while still supporting data rates of 16 GT/s. Allows a channel consisting of two connectors equal to or longer than an inch (50.8 centimeters). For example, circuits and interconnects can be optimized together so that repeaters and other devices can be omitted from longer interconnect channel runs. This can help reduce manufacturing costs, reduce I/O latency, and extend the applicability of higher bandwidth architectures to further applications. For example, repeater chips may include transmitters, receivers, clock generation (eg, phase-locked loops (PLLs)), clock recovery, and related logic functions. Such components can utilize valuable board area. Moreover, for x16 PCIe 4.0 interconnects, among other potential drawbacks, each repeater consumes extra power and can introduce additional costs to the manufacturing of the system. For example, repeaters can also introduce additional I/O latency.

FIG. 5 shows an example of two connector channel configurations. For example, a channel 500 can include multiple sections, such as a section on a socket (e.g., a CPU), a motherboard, add-on cards, riser boards, among other elements, over which channel links extend and system can connect two devices (eg, 505, 510) within. In this example, each of the multiple channel sections can have a respective length, L1 = 1 inch (2.54 centimeters), L2 = 10.5 inches (26.67 centimeters), L3 = 0 .5 inches (1.27 centimeters), L4 = 4 inches (10.16 centimeters), L5 = 3 inches (7.62 centimeters), and L6 = 1 inch (2.54 centimeters), channel The total length of the 500 is 20 inches (50.8 centimeters). A channel can be connected to each device 505, 510 using a respective connector 515, 520 (in each package).

Using conventional techniques, a configuration such as that shown in FIG. 5 can create a negative margin across the link. In one example, minimizing connector stub via effects, minimizing SPU socket effects, and leveraging improved low-loss personal computer board (PCB) advances, among other potential features. a 20 inch (50.8 cm) two connector interconnect (e.g., 500) supporting a 16 GT/s bit rate that provides an increase in on-chip receiver front-end gain, and Provides positive gain across the link.

A connector can include one or more vias that are used to form electrical connections between layers. For example, vias can be used to carry signals and power between multiple layers of a circuit board or component. In high speed systems, the portion of a via left on a connector, chip, or substrate is that portion that is not used in the point-to-point electrical link utilizing that via. Turning to FIG. 6, a simplified cross-sectional representation 600 of a circuit board or other component is shown. A component may include one or more stub vias 605 , 610 . Vias can form electrical connections between multiple layers on a printed circuit board, such as through plated through hole (PTH) technology. For example, vias can connect multiple pins of a connector to inner signal layers (eg, traces). For example, in the example of FIG. 6, to connect to another portion (eg, a trace (eg, 625) that extends along a layer 630 of a component over a link (or channel) to another component, another via, etc.). A portion of the link can be implemented using portions of the PTH vias (eg, 615, 620). The remainder of the via (eg, 635) may be considered a stub. In high-speed connections that utilize vias, via stubs 635 can cause resonant effects (eg, nulls at resonant frequencies), thereby resulting in signal degradation for channels (eg, lanes). Accordingly, in some implementations, via stubs can be back-drilled as shown at 650 to mitigate such effects. Back-drilling removes the stub portion of the via that is responsible for these adverse electromagnetic effects. In some cases, back-drilling can be performed as a post-drilling process, where the back-drilled holes are larger in diameter than the original plated-through holes (PTH).

Via stubs in the two connectors employed in the 20 inch (50.8 cm) 16 GT/s channel can be eliminated or minimized through, for example, back drilling, U-turn vias, and other solutions. For back drilling, the connector type may be selected based on the connector types that are good candidates for back drilling. For example, some connectors may mechanically fail and fail if back-drilled. Other types of connectors, such as surface mount connectors, may be more suitable.

In addition to improving the electrical quality of the connector via back drilling, the electrical quality of the CPU socket is also improved, allowing a 20 inch (50.8 cm) 16 GT/s channel on the socket. . For example, each pin of a CPU socket or other device corresponding to a 20 inch (50.8 centimeter) 16 GT/s channel lane connected using vias and routed through the board is back-drilled. be able to. The length of the socket stubs of these longer, two-connector high-speed channels can also be reduced by reserving layers closer to the pins for the traces utilized by the channels. This allows the length of the socket stubs (of vias) to be bounded by routing these lanes through multiple such layers of the board.

To minimize CPU socket impact, design the board pinout and breakout layout so that layout priority is given to lanes of 20 inch (50.8 cm) 16 GT/s channels. can be included. For example, the channels can be designed to be routed on a layer so that a back-drill is available for each pin of a CPU connected to a 20 inch (50.8 centimeter) 16 GT/s channel. Alternatively (or additionally), a 20 inch (50.8 centimeter) 16 GT/s channel can be routed to utilize multiple layers to allow socket stub lengths to be constrained. is designable.

FIG. 7 is a simplified representation of a cross-section of the board through which two devices 705, 710 are connected by an exemplary two-connector link (e.g., a 20 inch (50.8 cm) 16GT/ , which embodies the seconds channel). In this example, multiple pin breakouts of devices 705, 710 can be designed such that back drilling can be applied without blocking other breakout channels in the pin field. For example, inner pins (eg, 715) can be designed to breakout to layers above breakouts of outer pins (eg, 720) that route to lower layers of the board. Additionally, the pins are positioned so that any pin whose via stub is drilled out (e.g., a pin of a 20 inch (50.8 cm) 16 GT/sec channel) is not located adjacent to a power via. It is possible to design as much as possible. This is because back drills (eg, 725a-725f) can run the risk of drilling holes in power planes and geometries, potentially resulting in an inefficient power delivery network. Also, among other rules and examples, ground pins may be placed based on holes that provide ground planes after back-drilling.

Additional features were included in the 20 inch (50.8 cm) two connector channel to allow bit rates to meet or exceed 16 GT/s while still providing positive gain across the link. obtain. For example, low loss PC boards, such as boards with trace differential insertion loss less than or substantially equal to 0.48 dB/in at 4 GHz, are feasible.

In addition to mitigating the effects of stubs in the two connector 12 inch (30.48 cm) channel of the connector and socket, and providing the channel with a low loss board, at least a 20 inch (50 cm) channel A 16 GT/s rate in a .8 centimeter) channel is potentially achievable by also providing additional gain in the receiver front-end and/or additional peaking in the continuous-time linear equalizer (CTLE). be. In some examples, among other potential examples, the receiver front-end includes, for example, a CTLE, an automatic gain control (AGC), a decision-feedback equalizer (DFE), and/or a data sampler (slicer). ) coupled in the signal data path. For example, in one implementation, adding approximately 6 dB of total gain (e.g., above the PCIe 4.0 baseline) at the receiver front end and/or CTLE provides a 20 inch (50.8 centimeter) It can help achieve a 16 GT/s channel. Among other examples, achieving a modest amount of gain (e.g., approximately 6 dB) may be achieved with only a modest increase in power and circuit complexity, e.g., by adding a single gain stage. achievable. Additionally, in some systems the gain is adjustable or separately configurable on the channel. For example, for applications utilizing 16 GT/s speeds, among other examples, the channel can be programmatically adjusted and the gain turned off for applications using lower speeds. can.

Reliability, Availability, and Serviceability (RAS)

In some implementations, interconnect architectures such as PCIe may include enhancements to reliability, availability, and serviceability (RAS) in the system. While this problem may apply to all data transfer rates, some architectures may apply specific encoding schemes in the context of higher data transfer rates. For example, PCIe 4.0 (as well as PCIe Revision 3.0) employs a 128b/130b encoding scheme for data rates above 8 GT/s, for example. In the 128b/130b scheme, among other examples, per-lane parity is provided for each ordered set of SKPs (or "skips") (SKP OS), and which lane in the link Identifies that predictive analysis could not have been performed and, if appropriate, could not have operated at the reduced link width. Lane parity can be an effective tool in identifying errors in a particular lane of a link. However, in some instances, if the link is predominantly idle (e.g., has a Logical Idle Framing Token (IDL) on the link), there is a risk that the detection functionality provided via parity bits will be compromised. gender may exist. This is because an error in the framing token (eg, IDL) can result in link recovery that removes parity information up to that point. There can be additional blind spots that can cause errors to be underestimated in the error detection mechanisms of conventional architectures. For example, among other shortcomings, the interconnect architecture may detect fewer or no defective lanes for detected framing token errors.

In some architectures, registers can be provided to identify errors detected or expected on a link, and possibly the particular lane on which the error occurs. For example, as shown in FIG. 8, PCIe can provide a Lane Error Status (LES) register 805 associated with a functional structure such as a second PCIe extended function structure. Such functional structure 800 may include, in addition to LES registers 805 , second PCIe extension header 810 , link control 3 register 815 and equalization control register 820 . In some implementations, the LES register may contain a 32-bit vector, where each bit corresponds to one lane (eg, identified by a lane number) in the link and which lane has an error. Indicates if detected. PCIe defines a set of errors that can result in the reporting of error events in the LES registers. For example, among other examples, in the payload of all data blocks transmitted after the scrambling after the last SKP OS (or Ordered Set of Start of Data Stream (SDS)) as introduced above. Data parity may be implemented via a data parity bit included in the SKP OS that indicates if even parity is detected to be present in the SKP OS. However, data parity can be calculated independently for each lane. The receiving and transmitting devices compute parity using the same technique, and the receiver compares the computed parity for each lane with the parity computed by the transmitter (as identified by the parity bit). to identify potential errors. For example, if the calculated and received values do not match, a bit in the LES register (eg, corresponding to the lane number where the mismatch was detected) can be set.

As described above and shown in simplified representation 900 of FIG. 9, data can be transmitted on two or more lanes of the link. For example, as shown in exemplary PCIe, the basic entity of data transmission can be symbols, such as symbols implemented as 8-bit data characters. The payload of a data block is a stream of symbols defined as a data stream that can include framing tokens, transaction layer packets (TLPs), data link layer packets (DLLPs), and so on. Each symbol of the data stream may be placed on a single lane of the link for transmission, with the stream of symbols placed in strips across all lanes of the link, spanning multiple block boundaries. Additionally, in some examples, the physical layer can use per-lane block codes. Each block may contain a 2-bit sync header and payload. PCIe defines two valid sync header encodings, 10b and 01b, that define the payload type a block contains. For example, sync header 10b may indicate a data block and sync header 01b may indicate an ordered set of blocks. As an example, FIG. 9 shows transmission of data streams on four lanes, lanes 0, 1, 2, and 3. FIG. All lanes of a multi-lane link transmit multiple blocks simultaneously with the same sync header. The transmission order of the bits can start with a sync header (located as 'H0-H1' on the lane and denoted by 'H1H0'), then start with 'S0' and end with 'S7'. Followed by a first symbol labeled "S7-S6-S5-S4-S3-S2-S1-S0" located above.

PCIe provides receivers with the option of reporting errors corresponding to mismatched or invalid sync headers in the data stream to the LES register. For example, synchronization where one or more of the lanes (eg, in the first two UIs in the data stream) have invalid values (eg, 00b, 11b), among other examples. Identifying the inclusion of a header can be identified as an error on that lane, which can be reported to the LES register.

Turning to FIG. 10, representations of exemplary framing tokens 1005, 1010, 1015, 1020, 1025 are shown. A framing token (or "token") may be a physical layer data encapsulation that specifies or implies a number of symbols associated with that token, thereby identifying the location of the next framing token. A framing token for a data stream may be located at the first symbol (symbol 0) of the first lane (eg, lane 0) of the first data block of the data stream. In one example, PCIe includes a start of TLP (STP) token 1005, an end of data stream (EDS) token 1010, an end bad (EDB) token 1015, a start of DLLP (SDP) token 1020, and a logical idle (IDL) token 1025. Define five framing tokens, including The STP token 1005 is four symbols long and may be followed by data link layer information. An exemplary EDS token 1010 may be four symbols long to indicate that the next block is an ordered set of blocks. The EDB token 1015 is also four symbols long and confirms that the TLP was "wrong" and invalidated. EDB always follows TLP data. Additionally, the SDP token 1020 may be two symbols long, which is shorter, followed by DLLP information. The IDL token 1025 at the end of this example is a single symbol that is sent when no TLP, DLLP, or other framing token is sent on the link.

FIG. 11 shows a display 1100 showing exemplary data transmitted over an exemplary x8 link, showing characteristics of data streams defined according to a particular interconnect architecture, such as PCIe. In this example, the data may include transmission of an ordered set of SKPs. In this example, the stream can start with the transmission of a sync header H1H0=10b indicating a data block. Thus, an STP framing token can be sent as the first symbol 0 on lanes 0-3 to indicate the start of the TLP stream. A link cyclic redundancy check (LCRC) follows the TLP data, followed by an SDP header indicating that DLLP data is being transmitted (eg, at symbols 3-4). Cyclic redundancy check (CRC) data may also be provided in association with the DLLP data.

In the example of FIG. 11, a Logical Idle (IDL) token is sent when no data is sent on the link during a series of UIs. An EDS token may then be sent, indicating a transition to an ordered set of data on the multiple lanes. For example, another sync header (eg, at 1105) may be sent encoded as '01b' to indicate that the next plurality of data blocks are an ordered set of data blocks. In this particular example, the transmitted ordered set is the SKP ordered set (OS). As noted above, in some implementations, the SKP OS may include parity bits that indicate the parity state of each lane (eg, lanes 0-7) of the link. The SKP OS may also have a defined layout that is identifiable to the receiver. For example, for PCIe 128b/130b encoding, the SKP OS may contain a base of 16 symbols. Groupings of 4 SKP symbols may be added or deleted by port, and accordingly the SKP OS may be 8, 12, 16, 20, or 24 symbols, and so on. Further, as shown in FIG. 11, among other examples, a SKP_END symbol is provided on the lanes to indicate the location of the end of SKP OS and the next block to be transmitted on the lanes. can indicate the location of the sync header in the

In some example implementations, logic may be provided to detect multiple additional lane errors in the interconnect architecture. Software in the system can monitor registers, such as the LES register, to track multiple errors on a lane-by-lane basis over time. A single lane error may not indicate a problem with the error. However, when errors occur at a statistically significant frequency in one or more particular lanes of a link, system software may determine that a potential problem exists with respect to the particular lanes. can. Further, in some implementations, among other examples, in error-prone lanes, avoiding the transmission of at least some system data, reconfiguring links, generating tickets for closer scrutiny of links Corrective measures can be taken. Some errors can be difficult to detect on a lane-by-lane basis. While several mechanisms are provided for detecting and reporting portions of errors on the link (e.g., based on parity or erroneous sync headers), we identify further additional examples of lane specific rules. Other architectural features and rules may be leveraged to achieve this. Along with traditional lane error reporting, these errors can also be reported to a register for review, to build a more complete picture of the health of individual lanes of the link, among other examples and considerations. is.

In a first example, such as the PCIe example above, if a lane receives an ordered set of blocks with an immediately preceding invalid (mismatched, erroneous, or unexpected) EDS token, It can be inferred that an error occurred on the lane where the invalid EDS token was detected. Additionally, errors for invalid EDS tokens on that lane may be reported to an error register, such as by setting the corresponding bit in the PCIe LES register.

In another example, a predefined format for a particular ordered set can be utilized to identify additional lane errors. For example, the SKP OS may contain well-defined SKP symbols until a SKP END symbol is sent to identify the end of the ordered set. If an invalid or erroneous SKP symbol is identified on a particular lane within the expected SKP symbol (and before the SKP END symbol) of the ordered set, using the identification of the erroneous SKP symbol, Reporting of errors for a particular lane into an error register such as the LES register can be triggered. Additionally, the defined timing of specific OS symbols can also be used to identify when an unexpected symbol is received on a lane. For example, continuing with the SKP ordered set example, among other potential examples, when the number of symbols in the SKP OS is an integer multiple of 4, one or more identification of the link. Not receiving a SKP_END in symbols 8, 12, 16, 20, or 24 on a particular lane may cause the corresponding bit in the error register to be set for that particular lane.

Various framing errors can occur and be detected in some implementations. For example, when processing symbols that are expected to be framing tokens, receiving a symbol or sequence of symbols that does not match the definition of a framing token can be a framing error. Additionally, some framing tokens can be defined to follow other types of data, and unexpected arrival (or delay) of a particular framing token can be a framing error. By way of example only, among many other examples, it is possible to specify that the EDB token is received immediately after the TLP, and receiving the EDB token at any other time (other than immediately after the TLP) will cause the PCIe can trigger framing errors such as the framing errors defined in the specification. While framing errors can be identified within the system, in some implementations framing errors are not determined on a lane-by-lane basis or mapped to specific lanes of a link. Indeed, in some instances, among other instances, a framing error may cause link recovery to be initiated, and link recovery may be used for parity calculation and reporting (e.g., parity bits sent in the SKP OS). through) further complicates lane error detection.

In some implementations, logic included in the logical PHY (eg, in the receiving device) can also identify defective lanes from the framing token. In a first example, the symbols of the framing token are specifiable (as shown in the example of FIG. 10) and detecting an error in one of a plurality of symbols that deviate from the expected symbol value; As well as lanes in which erroneous token symbols are identified are identifiable. For example, if the first symbol of the framing token is identifiable and the first symbol does not match the first symbol of any one of the set of defined framing tokens for the PHY, An error may be thrown. This error can be logged, for example, in the LES register. In the PCIe framing token example, if the first symbol of the received framing token does not match the first symbol defined for PCIe IDL, SDP, STP, EDB, or EDS, then the first An error may be determined for the lane in which the framing token symbol of is represented, and the error may be logged in the lane error registry for the identified lane.

Second, in another example, an IDL framing token that is only one symbol long is specified to be sent for all lanes of the link when no TLP, DLLP, or other framing token is sent. obtain. Thus, if a first IDL appears on a lane with links having 4 or more lanes, multiple instances of that IDL will appear on lanes n+1, n+2, and n+3 (where the first lane n( n modulo 4=0)) can also be expected to appear. After sending an IDL token, the first symbol of the next STP or SDP token can be specified to be sent on lane 0 at future symbol times. Therefore, given these constraints on the use and expected use of IDL tokens, if an IDL does not repeat as expected, or if the first IDL appears in the wrong lane, the non-repeated IDL or other The lane in which the error symbol appeared can be identified and logged as the particular lane error in an error register, such as the LES register.

In yet another example, EDB tokens may be defined to a specific length, such as four symbols long in PCIe. As a result, framing errors can occur by identifying the first EDB symbol, but not identifying the additional EDB symbols within the immediately following symbols included in the next defined length. For example, in PCIe, if the framing token EDB is detected on lane n (n modulo 4=0) immediately after the TLP, but not on any of lanes +1, n+2, or n+3, then expected An error may be reported to the error register of any lane (eg, lane n+1, n+2, or n+3) where a valid EDB symbol is not displayed. Additionally, the first symbol of the EDB token can be defined to be placed immediately after the TLP stream, meaning that the preceding framing token, STP, is the last framing token displayed on the link. . Thus, among other examples, if the first symbol of an EDB token is displayed on lane n, but the framing token immediately preceding it is other than the STP token, then an error on lane n is identified and an error It can be reported to the register.

Similar to the EDB token framing error example, framing errors can also be based on length, format, and deviations from the alignment of other framing tokens. For example, in another example, the first symbol of SDP is detected in lane n, consistent with valid SDP token placement rules (e.g., precedes DLLP traffic), but lane +1 is the SDP token's If there is no match with the expected second symbol, the logic PHY logic may identify an error on lane n+1 and log the error in an error register.

FIG. 12 shows enhanced detection and 1 is a simplified block diagram showing logging; FIG. For example, in addition to reporting a sync header lane error 1205, and a parity bit error 1210, additional detectable errors are an OS block without a previous EDS token error 1215 and a SKP OS error 1220 (described in the example above). including multiple ordered sets of lane errors, such as For example, first symbol framing token error 1225, IDL, among other possible examples leveraging the rules defined for ordered sets, data blocks, and framing tokens within the architecture. Framing token error 1230 (e.g., for properly repeating IDL after the first IDL on lane n), EDB framing token error 1235 (e.g., for error in placement of EDB token symbols, as outlined by way of example above) ), and multiple framing token lane errors such as SDP framing token error 1240 (eg, for an error detected in the second symbol of the SDP token).

As noted above, in some cases errors or other events that force link recovery can compromise lane error detection mechanisms such as parity determination. As described above, receiving and transmitting devices can determine parity for a data stream or other stream, and the parity information determined by the transmitter matches the received parity information determined by the receiver for the same data stream. can be communicated to the receiver for comparison with the corresponding parity information (for that lane) received. Parity information may be sent periodically. For example, a transmit SKP OS can be transmitted that includes one or more parity bits in the SKP OS symbol that indicate the parity determined for each lane by the transmitter. However, in some conventional systems, link recovery or other events may cause parity information to be erased and/or restarted before the previously determined parity information is communicated to the receiver. can be brought down. Thus, in such instances, errors determined for a particular lane based on parity information may also be lost and remain unreported, compromising the accuracy of error reporting for that particular lane.

In one embodiment, by forcing link recovery to be automatically preceded by the SKP OS, or other data set containing data reporting parity information for each lane of the link being recovered, the parity information can be maintained. For example, the link recovery protocol can be redefined such that SKP OS (including parity bits) is sent in response to framing errors or other events that trigger link recovery. The SKP OS can thereby carry the parity information determined by the transmitter up to the moment link recovery is triggered, allowing the receiver to identify multiple potential lane errors based on the parity information.

In one example, parity information can be sent before recovery by sending a SKP OS before letting the link enter recovery from an active state (eg, L0). For example, each transmitter can transmit a SKP OS followed by an additional data block with an EDS token (eg, according to a predefined interval such as the maximum interval between SKP OSs) before entering recovery. This ensures that the receiver receives parity for previous data blocks received by the receiver, including one or more data blocks that may have caused a framing error. The receiver can also log the error in the appropriate LES if the parity bit comparison indicates an error.

In another example, rather than prematurely dumping parity information prior to recovery or other events (e.g., attempting to ensure that parity information is communicated before it is lost), the SKP OS Parity information, such as parity, can be extended to cover parity across data streams while the link is active (eg, "LinkUp=1b" in PCIe). Furthermore, parity information can also be persistently maintained for each lane of the link such that the parity information persists throughout recovery events. Persistent storage of parity information ensures that parity remains available throughout recovery, whereas conventional link recovery causes parity information in preceding data blocks to be lost (e.g., interrupted by recovery). , may be maintained and communicated after recovery (eg, in the first SKP OS after recovery). Furthermore, parity information for new data blocks sent after link restoration (and before the next SKP OS), among other examples, may also be determined in some cases, and may also be maintained. This combined parity information may be communicated, for example, in the next SKP OS, in addition to the pre-recovery parity information being stored.

It should be understood that the above examples are non-limiting illustrations and are provided only for the purpose of illustrating certain principles and features. Moreover, some systems may include various combinations of two or more of the features and components described above. As an example, a system may include a combination of the exemplary error detection features described above, such as the lane error detection features described above.

13A-13D, exemplary flowcharts 1300a-1300d illustrating exemplary techniques for detecting errors on multiple lanes of a link are shown. For example, in FIG. 13A, data may be received on a link that includes multiple lanes (1305). The data may include symbols, which may be monitored to determine if one or more of the symbols are erroneous symbols (1310). Erroneous symbols may be framing tokens (e.g., EDB, EDS, STP, IDL, SDP, etc.), ordered sets (e.g., SKP OS, etc.), or have erroneous values, among other examples. , in the wrong or unexpected order, transmitted on the wrong or unexpected lane, and may contain multiple symbols in other defined sequences that do not belong to a particular defined sequence. Among other examples, the lane on which the erroneous symbol was transmitted may be identified (1315), and the lane error for the identified lane reported based on the erroneous symbol, e.g., to a lane error register. (1320).

Referring to FIG. 13B, data may be sent 1325 on a link that includes multiple lanes. Parity information may be maintained for each lane on the link (1330). In response to identifying (1335) that the link is exiting the active state (eg, related to link recovery), an indication of such parity information may be sent (1340) prior to exiting from the active link state. ). In one example, an indication of parity information may be included in an ordered set of parity bits, such as a PCIe SKP ordered set, sent to a receiver. The indication of parity information can be used (eg, by a recipient of a particular information) to compare that parity information with parity information received by the recipient. A discrepancy in parity information may be identified as evidence of a lane error for the lane corresponding to the discrepant parity information.

In the example of FIG. 13C, data may be transmitted on multiple lanes of the link (1345), and based on the transmitted data identified on each lane, parity information may be determined for each of the multiple lanes (1350). ). Link recovery may occur and parity information may be maintained throughout recovery (1355). After recovery, an indication of parity information for each lane may be communicated (1370), which may be based on parity information maintained throughout link recovery. Optionally, after link recovery, additional data may be sent 1360 on the link, and parity information for each lane may be determined based on this post-recovery data. The parity information for each lane may be updated (1365) based on both pre-recovery and post-recovery data on each lane, and an indication of the communicated parity information (1370) may be the combined parity information. can be shown.

Corresponding to the example of FIG. 13C, in FIG. 13D, first data may be received on the link (1375), and based on the data received on the plurality of lanes, first parity information is generated for each lane. can be determined (1380). This parity information may be maintained 1385 throughout the recovery of the link after receiving the first data. After restoration of the link, second parity data, as identified in the ordered set of parity bits of the received SKP, may be received (1398). This second parity data can be compared with parity information maintained throughout (and beyond) link recovery. Optionally, among other examples, configuring the determined parity information for the lanes based on second data received 1390 on the lanes after link recovery. To do so, the maintained parity information can be updated (1394) (eg, corresponding to updating the parity information by the corresponding transmitter based on this post-recovery data transmission).

While many of the principles and examples above are described in the context of PCIe and specific revisions of the PCIe specification, the principles, solutions, and features described herein apply equally to other protocols and systems. Note that it is possible. For example, similar lane errors are specified in other links with respect to similar symbols, data streams and tokens, and the use, placement, and formatting of such structures within data transmitted over these other links. It can be detected on other links using other protocols based on the rules described above. Additionally, alternative mechanisms and structures (eg, other than PCIe LES registers or SKP OS) can be used to provide lane error detection and reporting functionality within the system. Further, combinations of the above solutions, including, among other examples, combinations of logical and physical enhancements to links and their corresponding logic described herein, may be used within a system. can be applied in

Note that the apparatus, methods, and systems described above may be implemented in any electronic device or system, as described above. As a specific example, the following figures provide exemplary systems for utilizing the invention described herein. As the system below is described in more detail, a number of different interconnections are disclosed, described, and reviewed from the discussion above. As will be readily apparent, the above advances can be applied to any of those interconnects, fabrics or architectures.

Referring to FIG. 14, a block diagram of one embodiment of a computing system including a multi-core processor is shown. Processor 1400 can be any processor such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, handheld processor, application processor, co-processor, system-on-chip (SOC), or other device that executes code or Including processing devices. In one embodiment, processor 1400 includes at least two cores, cores 1401 and 1402, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 1400 may include any number of processing elements that may be symmetrical or asymmetrical.

In one embodiment, a processing element refers to hardware or logic that supports software threads. Examples of hardware processing elements include thread units, thread slots, threads, processing units, contexts, context units, logical processors, hardware threads, cores, and/or processor states such as execution state or architectural state. Contains any other elements that can be held. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) generally refers to an integrated circuit potentially containing any number of other processing elements such as cores or hardware threads.

A core generally refers to logic located on an integrated circuit capable of maintaining independent architectural states, each independently maintained architectural state being associated with at least some dedicated execution resources. In contrast to a core, a hardware thread generally refers to any logic located on an integrated circuit capable of maintaining independent architectural state, the independently maintained architectural state providing access to execution resources. share it. As can be seen, the line between hardware thread names and core names overlaps when certain resources are shared and other resources are dedicated to certain architectural states. More often, cores and hardware threads are viewed by the operating system as individual logical processors, in which case the operating system can schedule operations to each logical processor individually.

As shown in FIG. 14, physical processor 1400 includes two cores, cores 1401 and 1402 . Here, cores 1401 and 1402 are considered to be symmetric cores, ie cores with identical configuration, functional units and/or logic. In another embodiment, core 1401 comprises an out-of-order processor core, while core 1402 comprises an in-order processor core. However, cores 1401 and 1402 are a native core, a software management core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated instruction set architecture (ISA), a joint Any type of core may be individually selected, such as engineered cores, or other known cores. In a heterogeneous core environment (ie, asymmetric cores), some form of transformation, such as binary transformation, may be utilized to schedule or execute code on one or both cores. Although not already described, the illustrated functional units within core 1401 are described in greater detail below. The units in core 1402 operate in a similar manner in the illustrated embodiment.

As shown, core 1401 includes two hardware threads 1401a and 1401b, which may also be referred to as hardware thread slots 1401a and 1401b. Thus, in one embodiment, a software entity such as an operating system sees processor 1400 as four separate processors, potentially four logical processors or processing elements capable of simultaneously executing four software threads. As alluded to above, a first thread may be associated with architectural state register 1401a, a second thread may be associated with architectural state register 1401b, a third thread may be associated with architectural state register 1402a, and a fourth thread may be associated with architectural state register 1402a. threads may be associated with the architectural state register 1402b. Here, each of the architectural state registers (1401a, 1401b, 1402a, and 1402b) may be referred to as processing elements, thread slots, or thread units, as described above. As shown, architectural state register 1401a is replicated in architectural state register 1401b so that individual architectural states/contexts can be stored for logical processor 1401a and logical processor 1401b. In core 1401, other smaller resources such as instruction pointers and rename logic in allocation and rename block 1430 may also be duplicated for threads 1401a and 1401b. Some resources such as reordering buffers in reordering/retirement unit 1435, ILTB 1420, load/store buffers, and queues may be shared through partitioning. Other resources such as general purpose internal registers, page table base registers, low level data cache and data TLB 1420, execution unit 1440, and portions of out-of-order unit 1435 are potentially fully shared.

Processor 1400 typically includes a number of other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In FIG. 14, a purely exemplary processor embodiment with exemplary logical units/resources of the processor is illustrated. Note that the processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not shown. . As shown, core 1401 includes a simplified representative out-of-order (OOO) processor core. However, an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer 1420 that predicts branches to be taken/taken, and an instruction translation buffer (I-TLB) 1420 that stores address translation entries for instructions.

Core 1401 further includes a decode module 1425 coupled to fetch unit 1420 that decodes fetched elements. In one embodiment, the fetch logic includes individual sequences associated with thread slots 1401a, 1401b, respectively. Core 1401 is typically associated with a first ISA that defines/specifies instructions executable on processor 1400 . Machine code instructions, which are typically part of the first ISA, include a portion of the instruction (referred to as an opcode), which references/specifies the instruction or action to be performed. Decode logic 1425 includes circuitry that recognizes these instructions from their opcodes and pipelines the decoded instructions for processing as defined by the first ISA. For example, as described in detail below, in one embodiment decoder 1425 includes logic designed or adapted to recognize specific instructions, such as transaction instructions. As a result of recognition by decoder 1425, architecture or core 1401 takes specific predefined actions to perform the tasks associated with the appropriate instructions. Any of the tasks, blocks, acts, and methods described herein may be performed in response to single or multiple instructions, some of which may be new or old instructions. It is important to note that the Note that in one embodiment, decoder 1426 recognizes the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoder 1426 recognizes a second ISA (either a subset of the first ISA or a separate ISA).

In one example, allocation and rename block 1430 includes an allocator that reserves resources such as register files that store instruction processing results. However, threads 1401a and 1401b are potentially capable of out-of-order execution, in which case allocation and rename block 1430 also reserves other resources such as reorder buffers to track instruction results. Unit 1430 may also include a register renamer that renames program/instruction reference registers to other registers internal to processor 1400 . Reorder/retire unit 1435 includes components such as the reorder buffer, load buffer, and store buffer described above to support out-of-order execution and subsequent in-order retirement of out-of-order executed instructions. .

Scheduler and execution unit block 1440, in one embodiment, includes a scheduler unit that schedules instructions/operations to execution units. For example, floating point instructions are scheduled on ports of execution units that have available floating point execution units. Also included are register files associated with the execution units for storing information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

A lower level data cache and data translation buffer (D-TLB) 1450 is coupled to execution unit 1440 . A data cache stores recently used/manipulated elements such as data operands, which are potentially maintained in a memory coherency state. The D-TLB stores recent virtual/linear translations to physical addresses. As a specific example, a processor may include a page table structure that divides physical memory into multiple virtual pages.

Here, cores 1401 and 1402 share access to higher level or farther caches, such as the second level cache associated with on-chip interface 1410 . Note that higher level or further away refers to cache levels that have increased or are further away from the execution unit. In one embodiment, the higher level cache is a last level data cache, ie, the last cache of the memory hierarchy of processor 1400, such as a second or third level data cache. However, higher level caches are not so limited and may be associated with or include an instruction cache. A trace cache, a type of instruction cache, may alternatively be chained after decoder 1425 to store recently decoded traces. Here, an instruction potentially refers to a macroinstruction (ie, a general instruction recognized by a decoder), which may be decoded into multiple microinstructions (micro-operations).

In the illustrated configuration, processor 1400 also includes on-chip interface module 1410 . Historically, memory controllers have been included in computing systems external to processor 1400, as described in more detail below. In this scenario, on-chip interfaces 1410 include devices external to processor 1400, such as system memory 1475, a chipset (typically a memory controller hub that connects to memory 1475, and an I/O controller hub that connects to peripheral devices). ), memory controller hub, northbridge, or other integrated circuit. Also in this scenario, bus 1405 may include any known interconnect, such as multidrop bus, point-to-point interconnect, serial interconnect, parallel bus, coherent (eg, cache coherent) bus, layered protocol architecture. , a differential bus, and a GTL bus.

Memory 1475 may be dedicated to processor 1400 or shared with other devices in the system. Examples of common types of memory 1475 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Devices 1480 may be graphics accelerators, processors or cards coupled to a memory controller hub, data storage coupled to an I/O controller hub, wireless transceivers, flash devices, audio controllers, network controllers, or other known devices. Note that it may contain

Recently, however, more logic and devices have been integrated onto a single die, such as the SOC, and each of these devices may be incorporated onto processor 1400 . For example, in one embodiment, a memory controller hub is on the same package and/or die as processor 1400 . Here, the portion of core 1410 (on-core portion) includes one or more controllers for interfacing with memory 1475 or other devices such as graphics device 1480 . Configurations that include interconnects and controllers for interfacing with such devices are commonly referred to as on-core (or uncore configurations). As an example, on-chip interface 1410 includes a ring interconnect for on-chip communications and a high speed serial point-to-point link 1405 for off-chip communications. Moreover, in the SOC environment, many more devices such as network interfaces, co-processors, memory 1475, graphics processor 1480, and any other known computing device/interface are integrated onto a single die or integrated circuit. , may provide a small form factor with high functionality and low power consumption.

In one embodiment, processor 1400 includes a compiler, optimizer to compile, transform, and/or optimize application code 1476 to support or interface with the apparatus and methods described herein. , and/or transform code 1477 can be executed. A compiler typically includes a program or set of programs for transforming source text/code into target text/code. Compilation of program/application code by a compiler typically occurs in multiple phases and passes to translate high-level programming language code into low-level machine or assembly language code. However, a single pass compiler may also be used for easy compilation. Compilers may utilize any known compilation techniques and may perform any known compiler operations such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization. .

Larger compilers usually contain multiple phases, but in most cases these phases are contained within two general phases: (1) Front end. That is, in general syntactic processing, semantic processing, and some transformations/optimizations can be done there. (2) Backend. That is, in general, analysis, transformation, optimization, and code generation are performed there. Some compilers are called middle, which gives a vague picture between the front end and the back end in a compiler. As a result, references to insertion, association, generation, or other actions of the compiler may be made in any of the aforementioned phases or passes, as well as in any other known phases or passes of the compiler. As an illustrative example, the compiler potentially inserts operations, calls, functions, etc. during one or more phases of compilation. For example, inserting calls/operations during the front-end phase of compilation, then translating the calls/operations into lower-level code during the translation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may not only insert such operations/calls, but also optimize the code for execution during runtime. As a particular example, binary code (already compiled code) may be dynamically optimized during runtime. Here, program code may include dynamically optimized code, binary code, or a combination thereof.

Similar to compilers, translators, such as binary translators, translate code either statically or dynamically in order to optimize and/or translate the code. Thus, references to executing code, application code, program code, or any other software environment may include (1) compiling program code, maintaining software structures, performing other operations, optimizing code, or (2) main program code, including operations/calls, such as optimized/compiled application code; (3) execution of other program code, such as libraries associated with the main program code, to maintain the software structure, perform other software-related operations, or optimize the code; or (4) these may refer to a combination of

Referring now to Figure 15, a block diagram of one embodiment of a multi-core processor is shown. As shown in the embodiment of FIG. 15, processor 1500 includes multiple domains. Specifically, core domain 1530 includes multiple cores 1530A-1530N and graphics domain 1560 includes one or more graphics engines with media engine 1565 and system agent domain 1510 .

In various embodiments, system agent domain 1510 handles power control events and power management, such that individual units of domains 1530 and 1560 (eg, multiple cores and/or graphics engines) are assigned specific unit dynamic in terms of the activity (or inactivity) that occurs within the independently controllable to operate Each of domains 1530 and 1560 may operate at a different voltage and/or power, and each individual unit within the multiple domains potentially operates at an independent frequency and voltage. Note that although shown with only three domains, the scope of the invention is not limited in this respect and additional domains may be present in other embodiments.

As shown, each core 1530 further includes low-level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled together and into a shared cache memory formed from multiple units or slices of Last Level Cache (LLC) 1540A-1540N. These LLCs typically contain storage and cache controller functions, shared between these cores and potentially also with the graphics engine.

As can be seen, ring interconnect 1550 links the cores together and provides interconnection between core domain 1530, graphics domain 1560, and system agent circuitry 1510 via a plurality of ring stops 1552A-1552N. Each such ring stop exists at the connection between the core and the LLC slice. As shown in FIG. 15, interconnect 1550 is used to carry various information including address information, data information, acknowledgment information, and snoop/invalidate information. Although a ring interconnect is shown, any known on-die interconnect or fabric may be utilized. By way of example, some of the fabrics described above (e.g., another on-die interconnect, an on-chip system fabric (OSF), an Advanced Microcontroller Bus Architecture (AMBA) interconnect, a multi-dimensional mesh fabric, or other known interconnect architectures) may be used in a similar manner.

As further shown, system agent domain 1510 includes a display engine 1512 that provides control over and interfaces to associated displays. The system agent domain 1510 may include other units such as an integrated memory controller 1520 that provides an interface to system memory (eg, DRAM implemented with multiple DIMMs), coherency logic 1522 that performs memory coherency operations. . There may be multiple interfaces that enable interconnection between the processor and other circuits. For example, in one embodiment, at least one Direct Media Interface (DMI) 1516 interface and one or more PCIe™ interfaces 1514 are provided. The display engine and their interfaces are typically coupled to memory via PCIe™ bridge 1518 . Additionally, one or more other interfaces may be provided to provide communication between other agents, such as additional processors or other circuitry.

Referring to FIG. 16, a block diagram of a representative core is shown. Specifically, the back-end logical blocks of a core such as core 1530 in FIG. In general, the structure shown in FIG. 16 fetches incoming instructions and performs various processing (eg, caching, decoding, branch prediction, etc.) and passing multiple instructions/operations to an out-of-order (OOO) engine 1680. It includes an out-of-order processor with a front-end unit 1670 used for processing. OOO engine 1680 performs further processing on the decoded instructions.

Specifically, in the FIG. 16 embodiment, out-of-order engine 1680 receives decoded instructions, which may be in the form of one or more micro-instructions or micro-operations, from front-end unit 1670 and stores them in registers, etc. , including an allocation unit 1682 that allocates appropriate resources for the . The instructions are then provided to reservation station 1684, which reserves and schedules resources for execution on one of a plurality of execution units 1686A-1686N. Various types of execution units may be present, including, for example, arithmetic logic units (ALUs), load and store units, vector processing units (VPUs), floating point execution units, among others. Results from these different execution units are provided to a reorder buffer (ROB) 1688, which takes the unordered results and puts them back into the correct program order.

Still referring to FIG. 16, note that both front-end unit 1670 and out-of-order engine 1680 are coupled to different levels of memory hierarchy. Specifically, instruction level cache 1672 is shown, which is then coupled to mid level cache 1676 and then to last level cache 1695 . In one embodiment, last level cache 1695 is implemented in an on-chip (sometimes referred to as uncore) unit 1690 . As an example, unit 1690 is similar to system agent 1510 of FIG. As noted above, uncore 1690 communicates with system memory 1699, which in the illustrated embodiment is implemented via ED RAM. Note that various execution units 1686 within out-of-order engine 1680 communicate with first level cache 1674 , which also communicates with mid-level cache 1676 . Note also that additional cores 1630N2-1630N can be coupled to LLC1695. Although shown at this high level in the embodiment of FIG. 16, it should be understood that various modifications and additional components may exist.

Referring to FIG. 17, there is shown a block diagram of an exemplary computer system formed of processors including execution units for executing instructions, in which one or more interconnects are part of the present invention. Implements one or more features according to an embodiment. System 1700 includes components such as processor 1702 that employ execution units that include logic to execute algorithms for process data in accordance with the present invention such as embodiments described herein. System 1700 is a typical processing based on PENTIUM® III™, Pentium® 4™, Xeon™, Itanium, XScale™ and/or StrongARM™ microprocessors system, other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In one embodiment, sample system 1700 runs a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., but other operating systems (e.g., UNIX and Linux). (trademark)), embedded software, and/or graphical user interfaces may also be used. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and software.

Embodiments are not limited to computer systems. Multiple alternative embodiments of the present invention may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include mobile phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. An embedded application may be a microcontroller, digital signal processor (DSP), system-on-chip, network computer (NetPC), set-top box, network hub, wide area network (WAN) switch, or one or more instructions according to at least one embodiment. any other system capable of performing

In this illustrated embodiment, processor 1702 includes one or more execution units 1708 that implement algorithms to execute at least one instruction. Although one embodiment may be described in the context of a single-processor desktop or server system, alternative embodiments may be included in multi-processor systems. System 1700 is an example of a "hub" system architecture. Computer system 1700 includes a processor 1702 for processing data signals. As an example, processor 1702 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or For example, any other processor device such as a digital signal processor. Processor 1702 is coupled to processor bus 1710 , which communicates data signals between processor 1702 and other components within system 1700 . Elements of system 1700 (e.g., graphics accelerator 1712, memory controller hub 1716, memory 1720, I/O controller hub 1724, wireless transceiver 1726, flash BIOS 1728, network controller 1734, audio controller 1736, serial expansion port 1738, I/O controller 1740) perform conventional functions well known to those skilled in the art.

In one embodiment, the processor 1702 includes a level 1 (L1) internal cache memory 1704 . Depending on the architecture, processor 1702 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external caches, depending on the particular implementation and needs. Register file 1706 stores different types of data in various registers, including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

An execution unit 1708 containing logic to perform integer and floating point operations is also present in processor 1702 . Processor 1702, in one embodiment, includes a microcode (μcode) ROM that stores microcode that, when executed, implements algorithms for specific microinstructions or handles complex scenarios. Here, the microcode can potentially be updated to handle logic bugs/fixes for processor 1702 . For one embodiment, execution unit 1708 includes logic for processing packed instruction set 1709 . By including the packed instruction set 1709 in the instruction set of the general purpose processor 1702, along with the associated circuitry for executing the instructions, operations used by many multimedia applications can be performed on the general purpose processor 1702 packed data. may be performed using Therefore, many multimedia applications are accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data. This potentially eliminates the need to transfer smaller data units, one data element at a time, across the processor's data bus to perform one or more operations.

Alternative embodiments of execution unit 1708 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1700 includes memory 1720 . Memory 1720 includes dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 1720 stores instructions and/or data represented by data signals for execution by processor 1702 .

Note that any of the aforementioned features or aspects of the invention may be utilized with one or more of the interconnects illustrated in FIG. For example, an on-die interconnect (ODI), not shown, for coupling internal units of processor 1702 implements one or more aspects of the invention described above. Alternatively, the present invention provides a processor bus 1710 (e.g., otherwise known as a high performance computing interconnect), a high bandwidth memory path 1718 to memory 1720, a point-to-point link to graphics accelerator 1712 (e.g., a peripheral component interconnect). Express (PCIe compliant fabric), controller hub interconnect 1722, I/O or other interconnects (eg, USB, PCI, PCIe) for coupling other illustrated components. Some examples of such components include audio controller 1736, firmware hub (flash BIOS) 1728, wireless transceiver 1726, data storage 1724, legacy I/O controller 1710 with user input and keyboard interface 1742, universal It includes a serial expansion port 1738 such as a serial bus (USB) and a network controller 1734 . Data storage devices 1724 may comprise hard disk drives, floppy disk drives, CD-ROM devices, flash memory devices, or other mass storage devices.

Turning now to Figure 18, a block diagram of a second system 1800 is shown in accordance with one embodiment of the present invention. As shown in FIG. 18, multiprocessor system 1800 is a point-to-point interconnection system and includes a first processor 1870 and a second processor 1880 coupled via point-to-point interconnection 1850. As shown in FIG. Each of processors 1870 and 1880 may be some version of a processor. In one embodiment, 1852 and 1854 are part of a serial point-to-point coherent interconnection fabric, such as a high performance architecture. Consequently, the present invention may be implemented within the QPI architecture.

Although only two processors 1870, 1880 are shown, it should be understood that the scope of the invention is not so limited. In other embodiments, one or more additional processors may be present in a particular processor.

Processors 1870 and 1880 are shown including integrated memory controller units 1872 and 1882, respectively. Processor 1870 also includes, as part of its own bus controller unit, point-to-point (PP) interfaces 1876 and 1878; similarly, second processor 1880 includes PP interfaces 1886 and 1888. Processors 1870 , 1880 may exchange information via PP interface 1850 using point-to-point (PP) interface circuits 1878 , 1888 . As shown in FIG. 18, IMCs 1872 and 1882 couple the processors to respective memories, memory 1832 and memory 1834, which are portions of main memory locally attached to the respective processors. you can

Processors 1870, 1880 exchange information with chipset 1890 via respective PP interfaces 1852, 1854 using point-to-point interface circuits 1876, 1894, 1886, 1898, respectively. Chipset 1890 also exchanges information with high performance graphics circuitry 1838 via interface circuitry 1892 along high performance graphics interconnect 1839 .

A shared cache (not shown) may be internal to either processor, or external to both processors, but local caches of either or both processors, even if the processors are in low power mode. Multiple processors are connected via PP interconnects so that information can be stored in a shared cache.

A chipset 1890 may be coupled to first bus 1816 via interface 1896 . In one embodiment, the first bus 1816 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, but is within the scope of the present invention. is not so limited.

As shown in FIG. 18, various I/O devices 1814 are coupled to a first bus 1816 along with a bus bridge 1818 that couples the first bus 1816 to a second bus 1820. . In one embodiment, second bus 1820 comprises a low pin count (LPC) bus. Various devices are coupled to second bus 1820, such as a keyboard and/or mouse 1822, a communication device 1827, and typically a disk drive or other mass storage containing instructions/code and data 1830 in one embodiment. It includes a storage unit 1828 such as a device. Additionally, audio I/O 1824 is shown coupled to the second bus 1820 . Note that other architectures are possible, with varying components and interconnection architectures involved. For example, instead of the point-to-point architecture of Figure 18, the system may implement a multi-drop bus or other such architecture.

Turning now to Figure 19, one embodiment of a system-on-chip (SOC) design according to the present invention is shown. As a particular example, SOC 1900 is included in user equipment (UE). In one embodiment, UE is used by an end-user to communicate, such as a mobile phone, smart phone, tablet, ultrathin notebook, notebook with broadband adapter, or any other similar communication device. refers to any other device that A UE typically connects to a base station or node, potentially corresponding to an intrinsic mobile station (MS) in a GSM network.

Here, SOC 1900 includes two cores, 1906 and 1907. Similar to above, cores 1906 and 1907 are Intel® Architecture Core™ based processors, Advanced Micro Devices, Inc. (AMD) processors, MIPS-based processors, ARM-based processor designs, or the instruction set architectures of their customers, licensees or adopters. Cores 1906 and 1907 are coupled to cache control 1908 associated with bus interface unit 1909 and L2 cache 1911 for communicating with other portions of system 1900 . Interconnect 1910 includes on-chip interconnects, such as IOSF, AMBA, or other interconnects mentioned above, potentially implementing one or more aspects described herein.

Interface 1910 includes a subscriber identity module (SIM) 1930 that interfaces with a SIM card, a boot ROM 1935 that holds boot code executed by cores 1906 and 1907 to initialize and boot SOC 1900, external memory (e.g., DRAM 1960 ), flash controller 1945 to interface with non-volatile memory (e.g. flash 1965), peripheral control 1950 (e.g. serial peripheral interface) to interface with peripherals, input (e.g. touch-enabled input ) to display and receive video codec 1920 and video interface 1925, GPU 1915 to perform graphics-related computations, and other components. Any of these interfaces may incorporate aspects of the invention described herein.

The system also shows communication peripherals such as a Bluetooth® module 1970, a 3G modem 1975, a GPS 1985, and a WiFi 1985. Note that, as noted above, the UE includes a radio for communication. Consequently, not all of these peripheral communication modules are required. However, at the UE some form of radio communication is included for external communication.

While this invention has been described with respect to a limited number of embodiments, numerous modifications and variations therefrom will occur to those skilled in the art. The appended claims intend all such modifications and variations to fall within the true spirit and scope of the invention.

A design may go through various stages from creation to simulation to manufacturing. Data representing a design may represent the design in a number of ways. First, to be useful in simulation, hardware may be represented using a hardware description language or another functional description language. Also, a circuit level model with logic and/or transistor gates may be generated at some stage of the design process. Moreover, at some stage, many designs arrive at a level of data that represents the physical placement of various devices in the hardware model. When conventional semiconductor manufacturing techniques are used, the data representing the hardware model specifies the presence or absence of various features in different mask layers for masks used in the fabrication of integrated circuits. can be data. In any representation of the design, the data may be stored on any form of machine-readable medium. Magnetic or optical storage, such as a memory or disk, may be such machine-readable medium, transmitted via optical or electrical waves, modulated or otherwise generated, for transmitting such information store the information that is When an electrical carrier wave representing or carrying code or design is transmitted, new copies are made to the extent that electrical signals are copied, buffered, or retransmitted. Accordingly, a communications or network provider may at least temporarily store items embodying the techniques of embodiments of the present invention, such as carrier-encoded information, on a tangible, machine-readable medium. .

A module, as used herein, may refer to any combination of hardware, software, and/or firmware. As an example, a module includes hardware associated with non-transitory media for storing code adapted to be executed by a microcontroller, such as a microcontroller. Thus, in one embodiment, references to modules refer to hardware specifically configured to recognize and/or execute code held on non-transitory media. Furthermore, in another embodiment, the use of modules refers to non-transitory media containing code specifically adapted to be executed by a microcontroller to perform predetermined operations. Furthermore, as can be inferred, in yet another embodiment the term module (in this example) may refer to the combination of said microcontroller and said non-transitory medium. Normally, the boundaries of modules shown separately generally vary and potentially overlap. For example, the first and second modules may share hardware, software, firmware, or a combination thereof, while potentially maintaining some independent hardware, software, or firmware. you can In one embodiment, use of the term logic includes hardware such as transistors, registers, or other hardware such as programmable logic devices.

In one embodiment, use of the word "configured" refers to the arrangement, assembly, manufacture, sale of devices, hardware, logic, or elements to perform a specified or determined task. means offering, importing and/or designing In this example, if the non-operating device or elements thereof are designed, coupled, and/or interconnected to perform the specified task, they will still perform the specified task. "It is configured. Purely by way of example, a logic gate may provide a 0 or 1 during operation. However, a logic gate "configured" to provide an enable signal to a clock does not include all potential logic gates that can provide a 1 or a 0. Instead, the logic gates are interlocked in some manner such that an output of 1 or 0 enables the clock during operation. Use of the term "configured" does not require an action, but instead emphasizes the potential state of the device, hardware, and/or elements, in which case the potential It should again be noted that, in a generic state, the device, hardware and/or elements are designed to perform a specific task while the device, hardware and/or elements are in operation.

Further, use of the words "to", "capable of", and/or "operable", in one embodiment, enable the device, logic, hardware and/or elements to be used in the specified manner. refers to any device, logic, hardware, and/or element designed to As noted above, the use of capable or operable refers, in one embodiment, to potential states of devices, logic, hardware and/or elements, where devices, logic, hardware, Note that the and/or elements are not in motion, but are designed in a manner to enable use of the device in a specified manner.

A value as used herein may include any known representation of a number, state, logic state, or binary logic state. Commonly, the use of logic level, logic value, or logic value is also simply referred to as 1 and 0 levels or values representing binary logic states. For example, 1 refers to high logic level and 0 refers to low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems are used. For example, the decimal number 10 can be represented as the binary value 1010, or as the letter A in hexadecimal. A value thus includes any representation of information that can be retained in a computer system.

Further, states may be represented by values or portions of values. As an example, a first value such as logic 1 may represent a default or initial state, while a second value such as logic 0 may represent a non-default state. Also, in one embodiment, the terms reset and set refer to default and updated values or states, respectively. For example, the default value potentially includes a logic high value, ie reset, while the updated value potentially includes a logic low value, ie set. Note that any combination of values may be used to represent any number of states.

Any of the above-described method, hardware, software, firmware or code embodiments may be implemented via instructions or code stored on a computer-readable medium that is machine-accessible, machine-readable, computer-accessible, or executable by a processing element. may be implemented as A non-transitory machine-accessible/readable medium includes any mechanism that provides (ie, stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), ROM, magnetic or optical storage media, flash memory devices, electrical storage devices. , optical storage devices, acoustic storage devices, other forms of storage devices for retaining information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals), etc., which are , are distinguished from non-transitory media from which information can be received.

The instructions used to program the logic implementing embodiments of the present invention may be stored within memory within the system, such as DRAM, cache, flash memory, or other storage. Additionally, the instructions may be distributed over a network or by other computer-readable medium. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). Such as, but not limited to, floppy disks, optical disks, compact disks, read-only memory (CD-ROM) and magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or electrical, optical, acoustic or other forms of propagating signals (e.g. carrier waves) , infrared signals, digital signals, etc.). Thus, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

The following examples relate to embodiments in accordance with this specification. One or more embodiments are an apparatus, system, machine-readable for providing a channel based on the Peripheral Component Interconnect (PCI) Express (PCIe) protocol supporting a bit rate of at least 16 giga-transfers per second (GT/S). Storage, machine-readable media, hardware-based and/or software-based logic, and methods may be provided wherein the channel includes two connectors and has a length greater than 12 inches (30.48 centimeters).

In at least one example, the channel includes at least one via and the via's stub is at least partially removed.

In at least one example, the via is back-drilled to remove the stub.

In at least one example, the via is a via of a first connector of the plurality of connectors.

In at least one example, each via utilized by the connector to connect to the first device is back-drilled.

In at least one example, vias of a second one of the plurality of connectors utilized to connect to a second device are back-drilled.

In at least one example, the via is a processor socket via.

In at least one example, each lane of the channel includes a corresponding portion of a respective processor socket, and each of the plurality of processor sockets corresponding to a lane of the channel having via stubs is back-drilled.

In at least one example, a low loss circuit board is provided and the channel is at least partially mounted on the circuit board.

In at least one example, the low loss circuit board has less trace differential insertion loss. In at least one example, gain is applied at the receiver front end of the channel.

In at least one example, the gain includes approximately 6 dB.

In at least one example, the gain is applied to a continuous time linear equalizer for the channel.

In at least one example, the combined gain applied to the receiver front end and the continuous time linear equalizer is approximately 6 dB.

In at least one example, the channel includes at least one via with a back-drilled stub, the channel is at least partially mounted on a low-loss circuit board, and a combined gain of approximately 6 dB is provided for the channel. Applied in one or more of the receiver front-end and the continuous time linear equalizer of the channel.

In at least one example, the length of the channel is at least 20 inches (50.8 centimeters).

One or more embodiments provide an apparatus, system, machine-readable storage, machine-readable medium, hardware-based for transmitting data at a bit rate of at least 16 GT/s over a channel comprising a multi-lane link consisting of two connectors and/or software-based logic and methods may be provided wherein the length of the channel is greater than 12 inches (30.48 centimeters).

In at least one example, the length of the channel is at least 20 inches (50.8 centimeters).

In at least one example, the channel includes one or more vias, and the stubs of the vias are back-drilled.

In at least one example, the one or more vias are included in one or both of the two connectors.

In at least one example, the channel includes a plurality of processor sockets, and the plurality of processor sockets includes the plurality of vias.

In at least one example, the channel includes at least one via with a back-drilled stub, the channel is at least partially mounted on a low-loss circuit board, and a combined gain of approximately 6 dB is provided for the channel. Applied in one or more of the receiver front-end and the continuous time linear equalizer of the channel.

In at least one example, the channels include PCIe-based channels.

One or more embodiments provide an apparatus, system, machine-readable storage, machine-readable medium for receiving data transmitted at a bit rate of at least 16 GT/s over a channel comprising a multi-lane link consisting of two connectors; Hardware-based and/or software-based logic and methods may be provided, wherein the length of the channel is greater than 12 inches (30.48 centimeters).

In at least one example, the length of the channel is at least 20 inches (50.8 centimeters).

In at least one example, the channel includes one or more vias, and the stubs of the vias are back-drilled.

In at least one example, the one or more vias are included in one or both of the two connectors.

In at least one example, the channel includes a plurality of processor sockets, and the plurality of processor sockets includes the plurality of vias.

In at least one example, the channel includes at least one via with a back-drilled stub, the channel is at least partially mounted on a low-loss circuit board, and a combined gain of approximately 6 dB is provided for the channel. Applied in one or more of the receiver front-end and the continuous time linear equalizer of the channel.

In at least one example, the channels include PCIe-based channels.

In at least one example, a system is provided that includes a first device and a second device communicatively coupled to the first device using an interconnection channel, the interconnection channel having a speed of at least 16 GT/s. It includes a Peripheral Component Interconnect (PCI) Express (PCIe) protocol-based link that supports bitrates, said link including two connectors and having a length greater than 12 inches (30.48 centimeters).

In at least one example, the system includes a server chipset.

In at least one example, the first device includes a processor device.

One or more embodiments identify a first lane error on a particular one of a plurality of lanes of a link based on detection of at least one erroneous symbol transmitted on the particular lane. and an apparatus, system, machine-readable storage, machine-readable medium, hardware- and/or software-based logic, and method for reporting said first lane error to a lane error register.

In at least one example, lane errors reported in the lane error register identify corresponding lanes in the plurality of lanes.

In at least one example, a second lane error is identified on the link based on detection of an error synchronization header in at least one of the plurality of lanes, the second lane error being recorded in the lane error register. Reported.

In at least one example, a third lane error is identified based on a determination of mismatched parity information for data streams transmitted over the link, and the third lane error is reported to the lane error register.

In at least one example, parity information is received in an ordered set of SKPs (SKP OS).

In at least one example, the I/O logic includes physical layer logic.

In at least one example, the erroneous symbols include errors for symbols included in SKP OS.

In at least one example, the erroneous symbols include non-SKP OS symbols detected between a first SLP OS symbol in the SKP OS and an SLP END marker in the SKP OS.

In at least one example, the erroneous symbol includes a SKP END located in a symbol other than symbol 8, 12, 16, 20 or 24 of SKP OS.

In at least one example, the erroneous symbol includes the first symbol of the framing token.

In at least one example, the framing token includes a PCIe framing token.

In at least one example, the framing tokens include a logical idle token (IDL), a data link layer packet (DLLP) start of data token (SDP), a transaction layer packet (TLP) start of data token (STP), and a bad TLP token. including at least one of End (EDB).

In at least one example, the erroneous symbols include erroneous IDL token symbols.

In at least one example, a first IDL token is included in a particular lane n of the plurality of lanes, and the erroneous symbol is detected in any one of lanes n+1, n+2, and n+3 of the plurality of lanes. contains non-IDL symbols.

In at least one example, the erroneous symbol includes an EDB token symbol.

In at least one example, a first EDB token follows a TLP on a particular lane n of the plurality of lanes, and the error symbol is any one of lanes n+1, n+2, and n+3 of the plurality of lanes. contains non-EDB symbols detected in

In at least one example, the error symbol includes a symbol of an EDB token, the EDB token following a framing token other than an SDP token.

In at least one example, the erroneous symbols include SDP token symbols.

In at least one example, a first symbol of an SDP token is included in a particular lane n of the plurality of lanes, and the error symbol includes a non-SDP symbol detected on lane n+1 of the plurality of lanes.

In at least one example, the lane error registers include PCIe lane error status (LES) registers.

In at least one example, the link includes a PCIe compliant link.

In at least one example, a second lane error is identified on the link based on detection of blocks in the ordered set lacking a preceding EDS token.

In at least one example, lane errors based on detection of errors in any one of the ordered set of symbols, the IDL token symbol, the SDP token symbol, the STP token symbol, and the EDB token symbol, are identified and reported. .

In at least one example, a lane error register is monitored to identify lane errors for a particular lane, and based on the identified errors for the particular lane in the lane error register, the particular lane. It can be determined that the lane is defective.

In at least one example, determining that the particular lane is defective includes statistical analysis of the plurality of errors.

One or more embodiments identify that a link including multiple lanes exits an active state and update parity information for the multiple lanes based on data previously transmitted over the link. apparatus, system, machine-readable storage, machine-readable medium, hardware- and/or software-based logic, and methods for maintaining and transmitting an indication of said parity information prior to said exit from said active state; may provide.

In at least one example, the indication of the parity information is sent in response to the termination.

In at least one example, the indication of parity information is sent in an ordered set.

In at least one example, the indication of the parity information for each lane is included in respective parity bits for each lane included in the ordered set.

In at least one example, the ordered set includes a PCIe SKP OS.

In at least one example, the link exits the active state upon link restoration.

In at least one example, the link recovery is based on errors detected on the link.

In at least one example, the error includes a framing token error.

One or more embodiments transmit data over a link including multiple lanes, maintain parity information for each of the multiple lanes based on the transmitted data, and the link is active. An apparatus, system, machine-readable storage, machine-readable medium, hardware-based and/or software-based for identifying exiting a state and transmitting said parity information prior to said exit from said active state Logic and methods may be provided.

One or more embodiments maintain first parity information for each of the plurality of lanes of the link based on data previously transmitted over the link, and second parity information in response to events. wherein the event causes the link to exit an active state and the second parity information is transmitted prior to the exit from the active state; Machine-readable storage, machine-readable medium, hardware-based and/or software-based logic, and methods may be provided. The first parity information is compared to the second parity information to identify potential lane errors on one or more of the lanes.

In at least one example, the second parity information is included in an ordered set.

In at least one example, the second parity information is included in a plurality of parity bits included in the ordered set.

In at least one example, the ordered set includes SKP OS.

In at least one example, upon restoration of the link, the link exits the active state.

In at least one example, the recovery is triggered by an error detected on the link.

In at least one example, the error includes a framing token error.

In at least one example, multiple potential lane errors are reported to a lane error register.

In at least one example, the lane error register includes a LES register.

In at least one example, the event includes an error detected on the link.

In at least one example, recovery of the link is triggered based on the error, and recovery causes the link to exit the active state.

In at least one example, potential lane errors are identified based on detecting that the first parity information does not match the second parity information.

One or more embodiments receive data over a link including a plurality of lanes, maintain first parity information for each of the plurality of lanes based on the data, and in response to an event, 2 parity information and for comparing the first parity information with the second parity information to identify potential lane errors on one or more of the lanes. An apparatus, system, machine-readable storage, machine-readable medium, hardware-based and/or software-based logic, and method may be provided wherein said event causes said link to exit an active state, said second parity information is sent prior to said exit from said active state.

One or more embodiments maintain parity information for each of the plurality of lanes of the link based on a first portion of data transmitted over the link, and after restoration of the link, the parity An apparatus, system, machine-readable storage, machine-readable medium, hardware- and/or software-based logic, and method may be provided for resuming computation of information, said parity information during recovery of said link, The parity information is further based on a second portion of data transmitted over the link, the second portion of data being considered persistent.

In at least one example, the first portion of the data corresponds to a first data block and the second portion of the data corresponds to a different second data block.

In at least one example, the first data block is interrupted by the recovery and the second block starts after the recovery.

In at least one example, the recovery is based on errors detected on the link.

In at least one example, an indication of said parity information calculated based on said first and said second portions of said data is transmitted to a receiving device.

In at least one example, the parity information includes first parity information, and the I/O logic further receives from a transmitting device a first parity information calculated by the transmitting device based on the first and second portions of the data. receiving an indication of parity information of 2 and comparing said indication of said second parity information with said first parity information.

In at least one example, whether potential errors exist on one or more of the lanes based on the comparison of the indication of the second parity information and the first parity information. It is decided what.

In at least one example, the multiple potential errors are reported to a lane error register.

In at least one example, the lane error registers include PCIe LES registers.

In at least one example, the indication of the second parity information is included in SKP OS.

In at least one example, the indication of the second parity information includes parity bits of the SKP OS.

In at least one example, the link includes a PCIe compliant link.

One or more embodiments transmit first data over a link including multiple lanes and determine parity information for each of the multiple lanes based on the transmitted first data. , an apparatus, system for participating in restoration of said link, transmitting second data over said link after said restoration of said link, and updating said parity information to generate updated parity information. , machine-readable storage, machine-readable media, hardware-based and/or software-based logic, and methods, wherein the parity information is maintained during the restoration of the link, and the updated parity information is , based on the first data and the second data.

One or more embodiments receive first data from a device, determine parity information for each of the plurality of lanes based on the received first data, and participate in restoring the link. and receiving second data over said link from said device after said recovery of said link and updating said parity information to generate updated parity information. , a machine-readable medium, hardware-based and/or software-based logic, and methods, wherein the first data is received over a link including a plurality of lanes, the parity information is the The updated parity information maintained during recovery is based on the first data and the second data.

In at least one example, the particular parity information can be compared with other parity information to determine one or more potential lane errors.

In at least one example, the other parity information is included in the SKP OS.

In at least one example, the other parity information is distinguishable from parity bits included in the SKP OS.

One or more embodiments receive first data from a device, determine parity information for each of the plurality of lanes based on the received first data, and recover the link. Apparatus, system, machine-readable for joining and receiving second data over said link from said device after said recovery of said link and updating said parity information to generate updated parity information. Storage, machine-readable media, hardware-based and/or software-based logic, and methods may be provided, wherein the first data is received over a link including multiple lanes, the parity information is the The updated parity information maintained during the recovery is based on the first data and the second data.

Throughout this specification, when referring to "one embodiment" or "an embodiment," the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the invention. means that Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places in this specification are not necessarily all referring to the same embodiment. Moreover, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the foregoing specification, detailed descriptions have been given with respect to specific exemplary embodiments. It will, however, be evident that various changes and modifications may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and accompanying drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Moreover, the above uses of embodiments and other exemplary language do not necessarily refer to the same embodiment or the same example, but to different and distinct embodiments and potentially the same embodiment. Sometimes.
(Item 1)
identifying that a link containing multiple lanes exits the active state;
maintaining parity information for the plurality of lanes based on data previously transmitted over the link;
An apparatus comprising I/O logic for transmitting an indication of said parity information prior to said exit from said active state.
(Item 2)
The apparatus of item 1, wherein said indication of said parity information is sent in response to said termination.
(Item 3)
The apparatus of item 1, wherein the indication of parity information is sent in an ordered set.
(Item 4)
4. The apparatus of item 3, wherein the indication of the parity information for each lane is included in respective parity bits for each lane included in the ordered set.
(Item 5)
4. The apparatus of item 3, wherein the ordered set includes a PCIe SKP OS.
(Item 6)
2. The apparatus of item 1, wherein the link exits the active state upon link recovery.
(Item 7)
7. The apparatus of item 6, wherein the link recovery is based on errors detected on the link.
(Item 8)
8. Apparatus according to item 7, wherein the error comprises a framing token error.
(Item 9)
transmitting data over a link including multiple lanes;
maintaining parity information for each of the plurality of lanes based on the transmitted data;
identifying that the link exits an active state;
sending an indication of said parity information prior to said exit from said active state.
(Item 10)
10. Method according to item 9, wherein said indication of said parity information is transmitted in SKP OS.
(Item 11)
10. The method of item 9, wherein the indication of parity information is transmitted prior to a scheduled transmission of parity information based on identifying that the link will exit the active state.
(Item 12)
10. The method of item 9, wherein the link exits the active state based on link recovery triggered by an error detected on the link.
(Item 13)
13. The method of item 12, further comprising receiving data indicative of said error from a receiving device.
(Item 14)
at least one machine-accessible storage medium having code stored thereon, said code, when executed in a machine, causing said machine to:
cause data to be sent on a link containing multiple lanes,
maintain parity information for each of the plurality of lanes based on the transmitted data;
The link identifies that it is exiting the active state,
At least one machine-accessible storage medium causing said parity information to be transmitted prior to said exit from said active state.
(Item 15)
maintaining first parity information for each of a plurality of lanes of the link based on data previously transmitted over the link;
receiving second parity information in response to an event;
I/O logic for comparing the first parity information with the second parity information to identify potential lane errors on one or more of the lanes;
The apparatus of claim 1, wherein the event causes the link to exit an active state, and wherein the second parity information is transmitted prior to the exit from the active state.
(Item 16)
16. Apparatus according to item 15, wherein the second parity information is included in an ordered set.
(Item 17)
17. Apparatus according to item 16, wherein the second parity information is included in a plurality of parity bits included in the ordered set.
(Item 18)
17. The apparatus of item 16, wherein the ordered set includes SKP OS.
(Item 19)
16. The apparatus of item 15, wherein the link exits the active state upon recovery of the link triggered by an error detected on the link.
(Item 20)
20. The apparatus of item 19, wherein said error comprises a framing token error.
(Item 21)
16. The apparatus of item 15, wherein the I/O logic further reports multiple potential lane errors to a lane error register.
(Item 22)
22. The apparatus of item 21, wherein the lane error register comprises a LES register.
(Item 23)
receiving data over a link including multiple lanes;
maintaining first parity information for each of the plurality of lanes based on the data;
receiving second parity information in response to an event;
comparing the first parity information with the second parity information to identify potential lane errors on one or more of the lanes;
The method, wherein the event causes the link to exit the active state and the second parity information is sent prior to the exit from the active state.
(Item 24)
24. The method of item 23, wherein the event includes an error detected on the link.
(Item 25)
24. The method of item 23, wherein recovery of said link is triggered based on said error, said recovery causing said link to exit said active state.
(Item 26)
24. The method of item 23, further comprising reporting multiple potential lane errors to a lane error register.
(Item 27)
further comprising monitoring the lane error register to determine if one or more of the lanes is defective based on lane errors reported in the lane error register. 26. The method according to 26.
(Item 28)
24. The method of item 23, wherein a plurality of potential lane errors are identified based on detecting that the first parity information does not match the second parity information.
(Item 29)
at least one machine-accessible storage medium having code stored thereon, said code, when executed in a machine, causing said machine to:
receive data over a link containing multiple lanes,
maintaining first parity information for each of the plurality of lanes based on the data;
receive second parity information in response to an event;
comparing the first parity information to the second parity information to identify potential lane errors on one or more of the lanes;
At least one machine-accessible storage medium, wherein the event causes the link to exit an active state, and wherein the second parity information is transmitted prior to the exit from the active state.
(Item 30)
a data link including multiple lanes;
a first device;
a second device communicatively coupled to the first device using the data link;
The second device is
transmitting data to the first device over the link;
maintaining parity information for each of the plurality of lanes based on the transmitted data;
identifying that the link exits the active state;
A system comprising I/O logic for sending an indication of said parity information prior to said exit from said active state.
(Item 31)
The parity information includes first parity information, and the first device is configured to:
maintaining second parity information for each of the plurality of lanes based on the data;
receiving the indication of the first parity information;
I/O logic for comparing the first parity information with the second parity information to identify potential lane errors on one or more of the lanes; 31. The system of item 30.
(Item 32)
The I/O logic of the first device further determines a potential error for a particular one of the plurality of lanes based on comparing the first parity information and the second parity information. 32. The system of item 31, wherein the system determines:
(Item 33)
31. The system of item 30, wherein the indication of the parity information is included in a SKP OS sent by the second device to the first device.

Claims (15)

a device,
A receiver for receiving physical layer symbols having framing tokens over a link having multiple lanes , the framing tokens being defined physical layer symbols according to a defined layout of the framing tokens. wherein the defined layout defines values to be applied to each physical layer symbol included in the defined sequence, each physical layer symbol including a respective 8-bit data, the framing The token is one of a start of transaction layer packet (STP) framing token, an end bad (EDB) framing token, a start of data link layer packet (SDP) token, or an end of data stream (EDS) framing token. a receiver that is
A received physical layer symbol of a framing token received on a particular lane of the plurality of lanes does not match an expected physical layer symbol of the framing token based on the defined layout. and identify an error on the particular lane based on a mismatch of values in the received physical layer symbols with corresponding values in the expected physical layer symbols;
error reporting logic for reporting the error in a lane error status (LES) register for the particular lane if the error detection logic detects the error. 2. The apparatus of claim 1, wherein the framing token is defined according to a Peripheral Component Interconnect Express-based (PCIe-based) protocol. 3. The apparatus of claim 2, wherein the PCIe-based protocol comprises a protocol conforming to PCIe generation 4 protocol. 4. The apparatus of any one of claims 1-3 , wherein the received physical layer symbol is a physical layer symbol after a first physical layer symbol, which is the first physical layer symbol of the framing token. The error detection logic determines the received physical layer symbol based on the received physical layer symbol following a defined physical layer symbol in a defined length not matching the expected physical layer symbol. does not match the expected physical layer symbol . 6. Apparatus according to any preceding claim, wherein the error detection logic or the error reporting logic is included in physical layer (PHY) logic. a method,
receiving physical layer symbols over a link having multiple lanes, said physical layer symbols having framing tokens, said framing tokens defining physical layer symbols according to a defined layout of said framing tokens; a defined sequence, wherein the defined layout defines values to be applied to each physical layer symbol included in the defined sequence, each physical layer symbol including a respective 8-bit data; The framing token is one of a start of transaction layer packet (STP) framing token, an end bad (EDB) framing token, a start of data link layer packet (SDP) token, or an end of data stream (EDS) framing token. are the stages and
determining that a received physical layer symbol of a framing token does not match an expected physical layer symbol for the framing token based on the defined layout, the received physical layer symbol comprising: received on a particular lane of the plurality of lanes;
identifying errors on the particular lane based on values in the received physical layer symbols not matching corresponding values in the expected physical layer symbols;
and reporting the error in a lane error status (LES) register for the particular lane if the error is detected. a system,
A means for receiving physical layer symbols over a link having multiple lanes, said physical layer symbols comprising framing tokens, said framing tokens defining physical layer symbols according to a defined layout of said framing tokens. a defined sequence, wherein the defined layout defines values to be applied to each physical layer symbol included in the defined sequence, each physical layer symbol including a respective 8-bit data; The framing token is one of a start of transaction layer packet (STP) framing token, an end bad (EDB) framing token, a start of data link layer packet (SDP) token, or an end of data stream (EDS) framing token. the means for receiving , which is
means for determining that a received physical layer symbol of a framing token does not match an expected physical layer symbol for the framing token based on the defined layout, the received physical layer symbol comprising: said means for determining received on a particular lane of said plurality of lanes;
means for identifying an error on the particular lane based on a mismatch of values in the received physical layer symbols with corresponding values in the expected physical layer symbols;
and means for reporting said error in a lane error status (LES) register for said particular lane if said error is detected. A system comprising a point-to-point serial interconnect link, a first device, and a second device coupled to the first device by the point-to-point serial interconnect link, wherein
The second device is
A receiver for receiving physical layer symbols including framing tokens over said point-to-point serial interconnect link , said framing tokens being defined physical layer symbols according to a defined layout of said framing tokens. wherein the defined layout defines values to be applied to each physical layer symbol included in the defined sequence, each physical layer symbol including a respective 8-bit data, the framing The token is one of a start of transaction layer packet (STP) framing token, an end bad (EDB) framing token, a start of data link layer packet (SDP) token, or an end of data stream (EDS) framing token. a receiver that is
A received physical layer symbol of a framing token received on a particular lane of a plurality of lanes does not match an expected physical layer symbol for the framing token based on the defined layout . and error detection logic for identifying an error on the particular lane based on a mismatch of values in the received physical layer symbols with corresponding values in the expected physical layer symbols;
error reporting logic for reporting the error in a lane error status (LES) register for the particular lane if the error detection logic detects the error. 10. The system of claim 9 , wherein the point-to-point serial interconnect link has multiple lanes. 11. A system according to claim 9 or 10 , wherein one of said first device and said second device comprises a processor. 12. The system of any one of claims 9-11 , wherein one of the first device and the second device has a root complex. 13. The system of any one of claims 9-12 , wherein one of the first device and the second device comprises a graphics processor. 14. The system of any one of claims 9-13 , wherein the first device and the second device are included on a system-on-chip. 15. A system as claimed in any one of claims 9 to 14 , wherein the system comprises a server chipset.

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