JP7162251B2 - Imaging device - Google Patents

Description

The present disclosure relates to imaging devices.

CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital still cameras, digital cameras, and the like. As is well known, these image sensors have photodiodes formed on semiconductor substrates.

On the other hand, a structure has been proposed in which a photoelectric conversion section having a photoelectric conversion layer is arranged above a semiconductor substrate (for example, Patent Document 1). An imaging device having such a structure is sometimes called a stacked imaging device. A stacked imaging device has a floating node, which is a node electrically connected to a photoelectric conversion unit and temporarily stores one of positive and negative charges generated by photoelectric conversion as signal charges. This floating node typically has a diffusion region formed in a semiconductor substrate that supports the photoelectric conversion section, and a conductive structure that electrically connects the photoelectric conversion section and the diffusion region to each other. A CCD circuit or a CMOS circuit is provided on the semiconductor substrate, and a signal corresponding to the amount of charge accumulated in the floating node is read out via the CCD circuit or the CMOS circuit.

WO2012/147302

In the field of imaging devices, there is a demand for noise reduction. In imaging devices, an obtained image may deteriorate due to leakage current from or to an impurity region that accumulates charges generated by photoelectric conversion. Therefore, it would be beneficial to be able to reduce such leakage current. Hereinafter, a leak current from or to an impurity region that accumulates charges generated by photoelectric conversion may be simply referred to as "dark current".

According to certain non-limiting exemplary embodiments of the present disclosure, the following are provided.

a semiconductor substrate having a first impurity region of n-type conductivity; a photoelectric conversion portion electrically connected to the first impurity region for converting light into charge; a first terminal and a second terminal; a capacitive element having the first terminal electrically connected to the first impurity region; and a voltage supply circuit electrically connected to the second terminal, wherein the voltage supply circuit has different first voltages. An imaging device, wherein a voltage and a second voltage are supplied to the second terminal, and the first impurity region accumulates positive charges among charges generated in the photoelectric conversion unit.

A generic or specific aspect may be implemented in an element, device, module, system or method. Also, the generic or specific aspects may be implemented by any combination of elements, devices, apparatus, modules, systems and methods.

Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. Benefits and/or advantages are provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of these.

According to an embodiment of the present disclosure, an imaging device with suppressed dark current is provided.

FIG. 1 is a diagram schematically showing an exemplary configuration of an imaging device according to a first embodiment of the present disclosure; FIG. FIG. 2 is a cross-sectional view schematically showing an exemplary device structure of pixel 10. As shown in FIG. FIG. 3 is a diagram schematically showing a typical example of the circuit configuration of the pixel 10A shown in FIG. 2. As shown in FIG. FIG. 4A is a timing chart for explaining exemplary operations of the pixel 10A having the circuit configuration shown in FIG. FIG. 4B is a timing chart for explaining exemplary operations when a p-type transistor is applied to the reset transistor 76 of the pixel 10A. FIG. 4C is a timing chart for explaining another example of the operations of the pixels 10A, 10Ap and 10Aq. FIG. 5 is a diagram schematically showing another circuit configuration example of the pixel 10. As shown in FIG. FIG. 6 is a diagram schematically showing still another circuit configuration example of the pixel 10. As shown in FIG. FIG. 7A is a diagram schematically showing still another example of the circuit configuration of the pixel 10. FIG. FIG. 7B is a diagram schematically showing still another circuit configuration example of the pixel 10. As shown in FIG. FIG. 8 is a timing chart for explaining exemplary operations of the pixel 10Ar shown in FIG. 7A or the pixel 10As shown in FIG. 7B. FIG. 9A is a diagram schematically showing still another example of the circuit configuration of the pixel 10. FIG. FIG. 9B is a diagram schematically showing still another circuit configuration example of the pixel 10. As shown in FIG. FIG. 10 is a timing chart for explaining exemplary operations of the pixel 10At shown in FIG. 9A or the pixel 10Au shown in FIG. 9B. FIG. 11A is a diagram schematically showing still another example of the circuit configuration of the pixel 10. FIG. FIG. 11B is a diagram schematically showing still another circuit configuration example of the pixel 10. As shown in FIG. FIG. 11C is a diagram schematically showing still another circuit configuration example of the pixel 10. As shown in FIG. FIG. 12 is a diagram schematically showing an example of the circuit configuration of pixels 10B included in the imaging device according to the second embodiment of the present disclosure. FIG. 13 is a diagram showing a more specific example to which the circuit configuration shown in FIG. 12 is applied. FIG. 14A is a timing chart for explaining exemplary operations of the pixel 10Bf having the circuit configuration shown in FIG. FIG. 14B is a timing chart for explaining exemplary operations when p-type transistors are applied to the reset transistor 76 and the transistor 78 of the pixel 10Bf. FIG. 15 is a diagram showing a modification of the imaging device according to the second embodiment of the present disclosure. FIG. 16 is a diagram showing another modification of the imaging device according to the second embodiment of the present disclosure. FIG. 17A is a timing chart for explaining exemplary operations of the pixel 10Br having the circuit configuration shown in FIG. FIG. 17B is a timing chart for explaining an exemplary operation when p-type transistors are applied to the reset transistor 76 and transistor 78 of the pixel 10Br and electrons are used as signal charges. FIG. 18 is a diagram showing still another modification of the imaging device according to the second embodiment of the present disclosure. 19A is a diagram schematically illustrating an example of a circuit configuration of pixels included in an imaging device according to a third embodiment of the present disclosure; FIG. 19B is a diagram schematically illustrating another example of a circuit configuration of pixels included in the imaging device according to the third embodiment of the present disclosure; FIG. FIG. 20 is a timing chart for explaining exemplary operations of the pixel 10D having the circuit configuration shown in FIG. 19A. FIG. 21 is a diagram schematically illustrating an example of a circuit configuration of pixels included in an imaging device according to the fourth embodiment of the present disclosure; FIG. 22A is a timing chart for explaining exemplary operations of the pixel 10C having the circuit configuration shown in FIG. FIG. 22B is a timing chart for explaining exemplary operations when a p-type transistor is applied to the reset transistor 76 of the pixel 10C and electrons are used as signal charges. FIG. 23 is a diagram showing a modification of the imaging device according to the fourth embodiment of the present disclosure. FIG. 24 is a functional block diagram that schematically illustrates an exemplary camera system according to the fifth embodiment of the disclosure.

This specification discloses an imaging device described in the following items.

[Item 1]
a semiconductor substrate having an n-type conductivity first impurity region;
a photoelectric conversion unit that is electrically connected to the first impurity region and converts light into charge;
a capacitive element having a first terminal and a second terminal, the first terminal being electrically connected to the first impurity region;
a voltage supply circuit electrically connected to the second terminal;
the voltage supply circuit supplies a first voltage and a second voltage different from each other to the second terminal;
The imaging device, wherein the first impurity region accumulates positive charges among the charges generated in the photoelectric conversion unit.

[Item 2]
further comprising a first transistor including the first impurity region as one of a source and a drain;
The voltage supply circuit supplies the first voltage to the second terminal during a first period when the first transistor is on, and supplies the first voltage to the second terminal after the first period and during a second period when the first transistor is off. The imaging device according to Item 1, wherein the second voltage is supplied to the second terminal.

[Item 3]
further comprising a first transistor including the first impurity region as one of a source and a drain;
The voltage supply circuit supplies the first voltage to the second terminal during a first period for accumulating the positive charges in the first impurity region, and the first transistor is on after the first period. The imaging device according to item 1, wherein the second voltage is supplied to the second terminal during a second period.

[Item 4]
The semiconductor substrate has a second impurity region,
the first transistor includes the second impurity region as the other of a source and a drain;
4. The imaging device according to item 2 or 3, wherein the first terminal is connected to the second impurity region.

[Item 5]
5. The imaging device according to any one of items 2 to 4, wherein the second voltage is higher than the first voltage.

[Item 6]
a semiconductor substrate having a first impurity region of p-type conductivity;
a photoelectric conversion unit that is electrically connected to the first impurity region and converts light into charge;
a capacitive element having a first terminal and a second terminal, the first terminal being electrically connected to the first impurity region;
a voltage supply circuit electrically connected to the second terminal;
the voltage supply circuit supplies a first voltage and a second voltage different from each other to the second terminal;
The imaging device, wherein the first impurity region accumulates negative charges among the charges generated in the photoelectric conversion unit.

[Item 7]
further comprising a first transistor including the first impurity region as one of a source and a drain;
The voltage supply circuit supplies the first voltage to the second terminal during a first period when the first transistor is on, and supplies the first voltage to the second terminal after the first period and during a second period when the first transistor is off. 7. The imaging device according to item 6, wherein the second voltage is supplied to the second terminal.

[Item 8]
further comprising a first transistor including the first impurity region as one of a source and a drain;
The voltage supply circuit supplies the first voltage to the second terminal during a first period during which the negative charges are accumulated in the first impurity region, and the first transistor is on after the first period. 7. The imaging device according to item 6, wherein the second voltage is supplied to the second terminal during a second period.

[Item 9]
The semiconductor substrate has a second impurity region,
the first transistor includes the second impurity region as the other of a source and a drain;
9. The imaging device according to Item 7 or 8, wherein the first terminal is connected to the second impurity region.

[Item 10]
10. The imaging device according to any one of items 7 to 9, wherein the second voltage is lower than the first voltage.

[Item 11]
the capacitive element and the first impurity region are at least part of a charge storage node that stores one polarity of charge generated in the photoelectric conversion unit;
11. The imaging device according to any one of items 1 to 10, wherein a capacitance value of the capacitive element is smaller than a capacitance value of a portion of the charge storage node other than the capacitive element.

[Item 12]
The photoelectric conversion unit is
a first electrode;
a second electrode facing the first electrode;
a photoelectric conversion layer positioned between the first electrode and the second electrode;
12. The imaging device according to any one of items 1 to 11, wherein the first electrode is electrically connected to the first impurity region.

[Item 13]
10. The imaging device according to any one of items 1 to 4 and 6 to 9, wherein the photoelectric conversion unit is a buried photodiode.

In addition, this specification discloses an imaging device described in the following items.

[Item 1]
a semiconductor substrate having a first impurity region and a second impurity region;
a photoelectric conversion unit electrically connected to the first impurity region;
a first transistor including a first impurity region as one of a source region and a drain region and a second impurity region as the other of the source region and the drain region;
a voltage supply circuit electrically connected to the second impurity region;
The voltage supply circuit applies a first voltage to the second impurity region during a first period when the first transistor is on, and applies the first voltage to the second impurity region after the first period and during a second period when the first transistor is off. An imaging device, wherein a different second voltage is applied to the second impurity region.

According to the configuration of item 1, it is possible to prevent dark current from being generated due to forward bias being applied to the pn junction between the first impurity region and its surroundings when the first transistor is turned off.

[Item 2]
The imaging device according to item 1, further comprising a capacitive element connected between the second impurity region and the voltage supply circuit.

According to the configuration of item 2, voltages with a smaller voltage difference can be applied as the first voltage and the second voltage.

[Item 3]
3. The imaging device according to item 2, further comprising a second transistor in which one of the source region and the drain region is electrically connected to the second impurity region.

[Item 4]
further comprising a second transistor having one of the source region and the drain region electrically connected to the second impurity region;
2. The imaging device according to item 1, wherein the voltage supply circuit is connected to the other of the source region and the drain region of the second transistor.

According to the configuration of Item 4, it is possible to prevent dark current from being generated due to forward bias being applied to the pn junction between the second impurity region and its surroundings when the second transistor is turned off.

[Item 5]
5. The imaging device according to item 3 or 4, wherein the second period is a period in which the second transistor is on, excluding the first period.

According to the configuration of item 5, it is possible to suppress the occurrence of dark current due to fluctuations in the potential of the first impurity region due to coupling via the first transistor.

[Item 6]
5. The imaging device according to item 3 or 4, wherein the second period of time starts when the second transistor is switched from on to off.

According to the configuration of item 6, it is possible to suppress the occurrence of dark current due to fluctuations in the potential of the second impurity region due to coupling via the second transistor.

[Item 7]
a semiconductor substrate having a first impurity region;
a photoelectric conversion unit electrically connected to the first impurity region;
a first transistor including a first impurity region as one of a source region and a drain region and switching between supply and cutoff of a reset voltage to the first impurity region;
a voltage supply circuit electrically connected to the first impurity region;
The voltage supply circuit applies a first voltage to the first impurity region during a first period when the first transistor is on, and applies the first voltage and the first voltage during a second period following the first period when the first transistor is off. applying a different second voltage to the first impurity region.

According to the configuration of item 7, it is possible to prevent dark current from being generated due to forward bias being applied to the pn junction between the first impurity region and its surroundings when the first transistor is turned off.

[Item 8]
8. The imaging device according to item 7, further comprising a capacitive element connected between the first impurity region and the voltage supply circuit.

According to the configuration of item 8, voltages with a smaller voltage difference can be applied as the first voltage and the second voltage.

[Item 9]
further comprising a second transistor having one of its source and drain regions electrically connected to the other of the source and drain regions of the first transistor;
9. The imaging device according to Item 7 or 8, wherein the voltage supply circuit is connected to the first impurity region through the first transistor.

[Item 10]
10. The imaging device according to item 3, 4, 5, 6, or 9, further comprising a feedback circuit that includes a second transistor and negatively feeds back the electrical signal generated by the photoelectric conversion unit.

According to the configuration of item 10, it is possible to reduce the kTC noise using negative feedback.

[Item 11]
the first transistor is n-type;
11. The imaging device according to any one of items 1 to 10, wherein the second voltage is higher than the first voltage.

According to the configuration of item 11, it is possible to prevent the potential of the first impurity region and/or the potential of the node between the first transistor and the second transistor from falling below the substrate potential of the semiconductor substrate.

[Item 12]
the first transistor is p-type;
11. The imaging device according to any one of items 1 to 10, wherein the second voltage is lower than the first voltage.

According to the configuration of item 12, it is possible to prevent the potential of the first impurity region and/or the potential of the node between the first transistor and the second transistor from exceeding the substrate potential of the semiconductor substrate.

[Item 13]
a semiconductor substrate having a first impurity region;
a photoelectric conversion unit electrically connected to the first impurity region;
a reset transistor including a first impurity region as one of a source region and a drain region and switching between supply and cutoff of a reset voltage to the first impurity region;
a drive circuit connected to the gate of the reset transistor;
The driving circuit sequentially applies to the gate a first voltage that turns on the reset transistor, a second voltage that turns off the reset transistor, and a third voltage between the first voltage and the second voltage, to the gate. 1. An imaging device that resets the potential of one impurity region.

According to the configuration of item 13, deterioration of image quality due to dark current can be prevented while avoiding excessive complication of the circuit.

[Item 14]
the reset transistor is n-type,
14. The imaging device according to item 13, wherein the third voltage is lower than the first voltage and higher than the second voltage.

According to the configuration of item 14, it is possible to prevent the potential of the first impurity region and/or the potential of the node between the first transistor and the second transistor from falling below the substrate potential of the semiconductor substrate.

[Item 15]
15. The imaging device according to item 13 or 14, wherein the third voltage is a voltage that makes the potential of the first impurity region higher than the substrate potential of the semiconductor substrate in a state where the third voltage is applied from the drive circuit to the gate. .

According to the configuration of item 15, the effect of dark current on the signal corresponding to the voltage level of the charge storage node after reset can be suppressed.

[Item 16]
the reset transistor is p-type,
14. The imaging device according to item 13, wherein the third voltage is higher than the first voltage and lower than the second voltage.

According to the configuration of item 16, it is possible to prevent the potential of the first impurity region and/or the potential of the node between the first transistor and the second transistor from exceeding the substrate potential of the semiconductor substrate.

[Item 17]
17. The imaging device according to item 13 or 16, wherein the third voltage is a voltage that makes the potential of the first impurity region lower than the substrate potential of the semiconductor substrate in a state where the third voltage is applied from the drive circuit to the gate. .

According to the configuration of item 17, the effect of dark current on the signal corresponding to the voltage level of the charge storage node after reset can be suppressed.

[Item 18]
Driving an imaging device comprising a photoelectric conversion unit, a charge accumulation node electrically connected to the photoelectric conversion unit, a detection circuit for detecting signal charge accumulated in the charge accumulation node, and a reset transistor for discharging the signal charge a method,
A first voltage for turning on the reset transistor, a second voltage for turning off the reset transistor, and a third voltage between the first voltage and the second voltage are sequentially applied to the gate of the reset transistor to generate a charge. A method of driving an image pickup device that resets the potential of a storage node.

According to the configuration of item 18, deterioration of image quality due to dark current can be prevented while avoiding excessive complexity of the circuit.

[Item 19]
the charge storage node includes an n-type first impurity region formed in the semiconductor substrate;
19. The imaging device according to item 18, wherein the third voltage is lower than the first voltage and higher than the second voltage.

[Item 20]
20. A method of driving an imaging device according to Item 19, wherein a voltage that makes the potential of the charge storage node lower than the substrate potential of the semiconductor substrate is applied as the second voltage.

[Item 21]
the charge storage node includes a p-type first impurity region formed in the semiconductor substrate;
19. The imaging device according to item 18, wherein the third voltage is higher than the first voltage and lower than the second voltage.

[Item 22]
22. A method of driving an imaging device according to Item 21, wherein a voltage that makes the potential of the charge storage node higher than the substrate potential of the semiconductor substrate is applied as the second voltage.

[Item 23]
The photoelectric conversion part is
a first electrode supported by a semiconductor substrate;
a second electrode;
a photoelectric conversion layer positioned between the first electrode and the second electrode;
23. The imaging device according to any one of Items 1 to 17 or 19 to 22, wherein the first electrode is electrically connected to the first impurity region.

[Item 24]
24. The imaging device according to any one of items 1 to 23, wherein the photoelectric conversion unit is an embedded photodiode.

[Item 25]
An imaging device comprising a plurality of pixels,
Each pixel of the plurality of pixels is
a photoelectric conversion unit that generates an electric charge by photoelectric conversion;
a charge storage node that stores charge;
a reset transistor electrically connected to the charge storage node for resetting the potential of the charge storage node to a reference potential;
an amplification transistor electrically connected to the charge storage node and outputting a signal voltage corresponding to the charge stored in the charge storage node;
a capacitive element having one end electrically connected to the charge storage node and the other end connected to a voltage source;
with
A first voltage is applied to the other end of the capacitive element during an exposure period in which charges are accumulated in the charge storage node, and a voltage different from the first voltage is applied to the other end during a reset period during a non-exposure period other than the exposure period. 2 voltage is applied,
The imaging device, wherein the reset period is part of the non-exposure period, and is a period during which the reset transistor resets the potential of the charge storage node to the reference potential.

According to the image pickup device described in item 25, an image pickup device capable of reducing leakage current is provided.

[Item 26]
26. The imaging device according to item 25, wherein the second voltage is applied to the other end of the capacitive element during the entire non-exposure period.

According to the imaging device described in item 26, for example, when holes are used as signal charges, the potential of the charge storage node is set to a low potential during the exposure period, and the potential of the charge storage node is set to a high potential during the non-exposure period. By setting the potential, the dark current can be reduced without deteriorating the circuit characteristics.

[Item 27]
27. The imaging device according to item 25 or 26, wherein the capacitive element is electrically connected to the gate of the amplification transistor.

According to the imaging device described in item 27, the voltage change of the control signal applied to the other end of the capacitive element can be applied to the FD node via the capacitive element.

[Item 28]
further comprising a selection transistor electrically connected to the amplification transistor and selectively outputting a signal voltage;
28. The imaging device according to item 26 or 27, wherein a control signal for the selection transistor is connected to the other end of the capacitive element.

According to the image pickup apparatus described in item 28, any control signal in the pixel can be used as the control signal to be applied to the capacitive element, so the number of control signal lines to be used can be reduced.

[Item 29]
Item 26, further comprising a switch transistor electrically connected between one end of the capacitive element and the charge storage node or between the voltage source and the other end for switching connection/disconnection of the capacitive element and the charge storage node. Or the imaging device according to 27.

According to the imaging device described in item 29, for example, it is possible to selectively use an FD potential control mode for controlling the potential of the charge storage node and a high gain mode for efficiently converting signal charges.

[Item 30]
the charge is a hole,
30. The imaging device according to any one of items 25 to 29, wherein the second voltage is higher than the first voltage.

According to the image pickup device described in item 30, it is possible to provide an image pickup device that uses holes as signal charges and is capable of reducing leakage current.

[Item 31]
31. The imaging device according to item 30, wherein the reset transistor and the amplification transistor are N-type transistors.

According to the imaging device described in item 31, when holes are used as signal charges, leak current can be appropriately reduced.

[Item 32]
charge is an electron,
30. The imaging device according to any one of items 25 to 29, wherein the second voltage is lower than the first voltage.

According to the image pickup device described in item 32, it is possible to provide an image pickup device that uses electrons as signal charges and is capable of reducing leakage current.

[Item 33]
33. The imaging device according to item 32, wherein the reset transistor and the amplification transistor are P-type transistors.

According to the imaging device described in item 33, when electrons are used as signal charges, leak current can be appropriately reduced.

[Item 34]
31. The imaging device according to item 30, wherein the first voltage is a ground voltage.

According to the imaging device described in item 34, it is possible to suppress power supply noise of the control signal applied to the capacitative element from entering the charge accumulation node.

[Item 35]
31. The imaging device according to item 30, wherein the second voltage is a ground voltage.

According to the imaging device described in item 35, it is possible to suppress power supply noise of the control signal applied to the capacitative element from entering the charge accumulation node.

[Item 36]
36. The imaging device according to any one of items 25 to 35, wherein the amplification transistor is a depression type transistor.

According to the imaging device described in item 36, a high output can be obtained from the amplification transistor even for a low-level potential of the charge storage node, so a voltage range required for operation of the current source of the source follower circuit can be secured. It becomes possible.

[Item 37]
The photoelectric conversion part is
a first electrode;
a second electrode facing the first electrode;
a photoelectric conversion film positioned between the first electrode and the second electrode for generating electric charge by photoelectric conversion;
37. The imaging device according to any one of items 25 to 36, comprising:

According to the imaging device described in Item 37, there is provided an imaging device including a photoelectric conversion unit having a photoelectric conversion film that can reduce leakage current.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that the embodiments described below are all comprehensive or specific examples. Numerical values, shapes, materials, components, arrangement and connection forms of components, steps, order of steps, and the like shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described herein are combinable with each other unless inconsistent. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in independent claims representing the highest concept will be described as optional constituent elements. In the following description, constituent elements having substantially the same functions are denoted by common reference numerals, and their description may be omitted.

(First embodiment)
FIG. 1 schematically shows an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. An imaging device 100 shown in FIG. 1 has a pixel array 110 including a plurality of pixels 10 and a peripheral circuit 120 .

The pixel array 110 includes a plurality of pixels 10 arranged in a matrix of m rows and n columns, for example. Here, m and n are natural numbers. The pixels 10 form an imaging region by being arranged, for example, two-dimensionally on the semiconductor substrate 60 . The number and arrangement of pixels 10 in pixel array 110 are not limited to the illustrated example. For example, the number of pixels 10 included in the imaging device 100 may be one. If the arrangement of the pixels 10 in the pixel array 110 is one-dimensional, the imaging device 100 can be used as a line sensor.

Each pixel 10 includes a photoelectric converter that receives incident light and generates charges. The photoelectric conversion portion of each pixel 10 has a structure including a buried photodiode formed in the semiconductor substrate 60 or part of a photoelectric conversion layer arranged above a region of the semiconductor substrate 60 corresponding to the imaging region. obtain. In this specification, terms such as “upper” and “lower” are used only to specify the mutual arrangement of members, and are not intended to limit the orientation of the imaging device 100 when it is used.

In the configuration illustrated in FIG. 1, the peripheral circuit 120 includes a vertical scanning circuit 122, a signal holding circuit 123, a horizontal scanning circuit 124, an output stage amplifier 126, and a predetermined voltage to each pixel 10 in the pixel array 110. and a voltage supply circuit 128 for supplying the voltage. Here, the peripheral circuit 120 is provided on the semiconductor substrate 60 on which the pixel array 110 described above is formed. However, the arrangement of peripheral circuit 120 is not limited to this example, and part or all of peripheral circuit 120 may be arranged on another substrate different from semiconductor substrate 60 .

The vertical scanning circuit 122 is also called a row scanning circuit, and has connections with, for example, address signal lines and reset signal lines provided corresponding to each row of the plurality of pixels 10 . By supplying predetermined signals to the address signal line and the reset signal line, the vertical scanning circuit 122 can accumulate and read signal charges in the pixels 10 and reset the accumulated signal charges on a row-by-row basis. can. The peripheral circuit 120 may have two or more vertical scanning circuits 122 . In FIG. 1, illustration of various signal lines such as an address signal line and a reset signal line is omitted in order to avoid complicating the drawing. Arrows in FIG. 1 schematically show the flow of signals supplied to various signal lines such as an address signal line and a reset signal line.

The signal holding circuit 123 is connected to a vertical signal line (not shown) provided corresponding to each column of the plurality of pixels 10, and has a function of temporarily holding a signal output to the vertical signal line. Signals may be held in the form of analog values or may be held in the form of analog-to-digital converted digital values. The signal holding circuit 123 outputs to the horizontal scanning circuit 124, for example, the difference between the signal read out from the pixel 10 after the signal charge is accumulated and the signal read out from the pixel 10 after the signal charge is reset. . Operations between signals may be performed in either analog or digital form. The horizontal scanning circuit 124 is also called a column scanning circuit and typically includes an analog-to-digital conversion circuit as part thereof. The horizontal scanning circuit 124 has a function of reading the differential signal obtained by the signal holding circuit 123 for each row of the plurality of pixels 10 to the output stage amplifier 126 .

The voltage supply circuit 128 is electrically connected to each pixel 10 and configured to switch and supply two or more predetermined voltages to each pixel 10 when the imaging device 100 operates. The voltage supply circuit 128 switches between, for example, the first voltage V _A and the second voltage V _B and supplies the voltage to each pixel 10 . Here, the second voltage V _B is a voltage different from the first voltage _VA .

The voltage supply circuit 128 is not limited to a specific power supply circuit as long as it can apply a predetermined voltage to each pixel 10 during operation of the imaging device 100 . The voltage supply circuit 128 may be a circuit that generates a predetermined voltage, or a circuit that converts a voltage supplied from another power source into a predetermined voltage. Voltage supply circuit 128 may be part of vertical scanning circuit 122 . The voltage applied to each pixel 10 from the voltage supply circuit 128 is not limited to two different voltages. The voltage supply circuit 128 may be configured to be able to switch between three or more different voltages and supply them to each pixel 10 .

(Device structure of pixel 10)
FIG. 2 schematically shows a cross-section of an exemplary device structure for pixel 10 . FIG. 2 schematically shows the shape, size and arrangement of each part in the pixel 10, and the shape, size and arrangement of each part shown in FIG. 2 do not necessarily reflect the shape, size and arrangement of the actual device. The same applies to other drawings of the present disclosure.

A pixel 10A shown in FIG. 2 is an example of the pixel 10 described above. Pixel 10A roughly includes a portion of semiconductor substrate 60 and photoelectric conversion section 50A supported by interlayer insulating layer 40 covering semiconductor substrate 60 . In the example shown in FIG. 2, the photoelectric conversion section 50A includes a photoelectric conversion layer 54 located above a region of the semiconductor substrate 60 corresponding to the imaging region. That is, here, a stacked imaging device is exemplified as the imaging device 100 .

As schematically shown in FIG. 2, the semiconductor substrate 60 includes a support substrate 60S and one or more semiconductor layers formed on the support substrate 60S. Here, a p-type silicon substrate is exemplified as the support substrate 60S. A semiconductor substrate 60 is provided with impurity regions 60 a to 60 e and an element isolation region 65 . Each of impurity regions 60a-60e is typically an n-type diffusion region.

As shown in FIG. 2, the photoelectric conversion unit 50A supported by the semiconductor substrate 60 includes a pixel electrode 52 on the interlayer insulating layer 40, a counter electrode 56 located farther from the semiconductor substrate 60 than the pixel electrode 52, and a pixel electrode 56. and a photoelectric conversion layer 54 positioned between the electrode 52 and the counter electrode 56 . The pixel electrode 52 is an electrode formed of a metal such as aluminum or copper, a metal nitride, or polysilicon to which conductivity is imparted by being doped with impurities. The pixel electrode 52 is electrically isolated from the pixel electrodes 52 in other adjacent pixels 10A by being spatially separated. Counter electrode 56 is formed from a transparent conductive material such as ITO. "Transparent" as used herein means transmitting at least a portion of light in the wavelength range to be detected, and does not necessarily transmit light over the entire wavelength range of visible light. The counter electrode 56 can be formed over a plurality of pixels 10A, while the pixel electrode 52 is separated between the pixel electrodes 52 in other adjacent pixels 10A. Counter electrode 56 is typically disposed over semiconductor substrate 60 in the form of a continuous single electrode.

Photoelectric conversion layer 54 is formed from an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 54 may be formed by vacuum deposition, for example, and may have a thickness of approximately 500 nm. The photoelectric conversion layer 54 may have a layer made of an organic material and a layer made of an inorganic material. The photoelectric conversion layer 54 receives light incident through the counter electrode 56 and generates positive and negative charges through photoelectric conversion. Similar to the counter electrode 56, the photoelectric conversion layer 54 may also be disposed above the semiconductor substrate 60 in the form of a single layer that is continuous across multiple pixels 10A.

Although not shown in FIG. 2, a voltage line connected to a power supply (not shown) is connected to the counter electrode 56, and the counter electrode 56 is applied with a predetermined bias voltage when the imaging device 100 is in operation. receive supply. By controlling the potential of the counter electrode 56 by applying a predetermined bias voltage, one of positive and negative charges generated by photoelectric conversion can be collected by the pixel electrode 52 as signal charges.

The bias voltage applied to the counter electrode 56 may be supplied from the voltage supply circuit 128 described above. When positive charges are used as signal charges, a bias voltage that makes the potential higher than that of the pixel electrode 52 may be applied to the counter electrode 56 . In the following, unless otherwise specified, an example in which positive charges are used as signal charges will be described. A typical positive charge as a signal charge is a hole. Of course, it is also possible to use negative charges, for example electrons, as signal charges. When negative charges are used as signal charges, a bias voltage that makes the potential lower than that of the pixel electrode 52 may be applied to the counter electrode 56 .

Pixel 10A includes connection portion 42 disposed in interlayer insulating layer 40 . As schematically shown in FIG. 2 , one end of the connection portion 42 is connected to the pixel electrode 52 of the photoelectric conversion portion 50 . The connection portion 42 includes a plurality of wiring layers and a plurality of plugs, and electrically connects the photoelectric conversion portion 50A to the circuit formed on the semiconductor substrate 60. As shown in FIG. The multiple wiring layers and the multiple plugs are typically formed from metals such as copper or tungsten, or metal compounds such as metal nitrides or metal oxides. In this example, a semiconductor substrate 60 is formed with a signal detection transistor 72 , an address transistor 74 and a reset transistor 76 .

Hereinafter, n-channel field effect transistors represented by n-channel MOS are exemplified as the signal detection transistor 72, the address transistor 74 and the reset transistor 76 unless otherwise specified. As will be described later, it is also possible to apply p-type transistors instead of n-type transistors. In this case, an n-type silicon substrate may be used as the support substrate 60S, and the p-type is selected as the conductivity type of the impurity regions 60a to 60e.

The reset transistor 76 includes, for example, an impurity region 60a formed in the semiconductor substrate 60 as one of the drain region and the source region, and an impurity region 60b as the other of the drain region and the source region. As schematically shown in FIG. 2, the connection portion 42 is connected to the impurity region 60a, and therefore the impurity region 60a is electrically connected to the pixel electrode 52 of the photoelectric conversion portion 50A through the connection portion 42. It is connected.

Although not shown in FIG. 2, the impurity region 60b is connected to a reset voltage line that supplies a reset voltage, which is a reset reference voltage. The reset transistor 76 is switched between ON and OFF to switch supply and cutoff of the reset voltage supplied from the reset voltage line to the impurity region 60a. Which of the impurity regions 60a and 60b functions as the drain region of the reset transistor 76 is determined by the potentials of the impurity regions 60a and 60b. In the following, for the sake of convenience, the impurity regions 60a and 60b are assumed to be the drain region and the source region, respectively. However, depending on how the imaging device 100 is used, the drain region and the source region may be interchanged. If the imaging device 100 has other transistors connected in series with the reset transistor 76, the same applies to other transistors connected in series with the reset transistor 76. FIG.

Signal detection transistor 72 includes a gate insulating layer 72g on semiconductor substrate 60, a gate electrode 72e on gate insulating layer 72g, an impurity region 60c as a drain region, and an impurity region 60d as a source region. A power supply line (not shown) is connected to the impurity region 60c, and a power supply voltage of, for example, 3.3 V is applied to the impurity region 60c from the power supply line when the imaging device 100 is in operation.

As shown in FIG. 2 , the connection portion 42 is also connected to the gate electrode 72 e of the signal detection transistor 72 . That is, the gate electrode 72e of the signal detection transistor 72 is electrically connected to the pixel electrode 52 of the photoelectric conversion section 50A through the connection section 42. As shown in FIG.

In the configuration illustrated in FIG. 2, address transistor 74 includes impurity region 60d as a drain region and impurity region 60e as a source region. Here, address transistor 74 is electrically connected to signal detection transistor 72 by sharing impurity region 60 d with signal detection transistor 72 . A vertical signal line (not shown) is connected to the impurity region 60e. Note that the circuit in the pixel 10A is electrically isolated from the circuits in the other adjacent pixels 10A by the element isolation region 65. FIG. As shown in FIG. 2, the element isolation region 65 is also provided between the signal detection transistor 72 and the reset transistor 76 .

As described above, the connection portion 42 has a connection with the pixel electrode 52 . Also, the impurity region 60 a and the gate electrode 72 e of the signal detection transistor 72 are electrically connected to the pixel electrode 52 through the connection portion 42 . The pixel electrode 52, the connection portion 42, the impurity region 60a, and the gate electrode 72e function as a charge storage node that temporarily retains signal charges collected by the pixel electrode 52. FIG.

In the configuration illustrated in FIG. 2 , the pixel 10A further has a control line 81 electrically connected to the connection portion 42 . A control line 81 is a signal line connected to the voltage supply circuit 128 described above. That is, here, the impurity region 60a has an electrical connection with the voltage supply circuit 128 described above. Note that a capacitive element or the like may be interposed between the impurity region 60a and the voltage supply circuit 128, as will be described later. _A voltage supply circuit 128 is electrically connected to a connection 42 forming part of the charge storage node to switch the output of the voltage supply circuit 128 between a first voltage _VA and a second voltage VB. This makes it possible, for example, to temporarily change the potential of the charge storage node after reset.

Here, the details of the configuration of the semiconductor substrate 60 will be described. As described above, the semiconductor substrate 60 has one or more semiconductor layers on the support substrate 60S. In this example, the semiconductor layers on the support substrate 60S include a first p-type semiconductor layer 61p, an n-type semiconductor layer 61n and a second p-type semiconductor layer 62p. As schematically shown in FIG. 2, the impurity regions 60a to 60e and the element isolation region 65 are formed in a second p-type semiconductor layer 62p as a p-well.

The n-type semiconductor layer 61n is located between the first p-type semiconductor layer 61p and the second p-type semiconductor layer 62p, and through a well contact (not shown) provided outside the imaging region during operation of the imaging device 100. Its potential is controlled. The n-type semiconductor layer 61n suppresses the inflow of minority carriers from the support substrate 60S or the peripheral circuit 120 to the charge storage node that stores signal charges.

In the configuration illustrated in FIG. 2, the semiconductor substrate 60 is a p-type semiconductor layer provided between the second p-type semiconductor layer 62p and the support substrate 60S so as to penetrate the first p-type semiconductor layer 61p and the n-type semiconductor layer 61n. It has a region 63 . The p-type region 63 has a relatively high impurity concentration and electrically connects the second p-type semiconductor layer 62p and the support substrate 60S to each other. Substrate contacts (not shown) are provided outside the imaging region, and the potentials of the support substrate 60S and the second p-type semiconductor layer 62p are controlled via the substrate contacts during operation of the imaging device 100 . In other words, during operation of the imaging device 100, the substrate potential of the semiconductor substrate 60 is controlled via the substrate contact. The voltage supply circuit 128 described above may be configured to supply the substrate potential of the semiconductor substrate 60 via substrate contacts. When n-type transistors are applied as signal detection transistor 72, address transistor 74 and reset transistor 76, as in the example described here, the substrate potential is typically ground.

(Suppression of dark current)
As described above, the impurity region 60a constitutes part of the charge storage node that temporarily stores the signal charge generated by the photoelectric conversion section 50A. This is because the junction capacitance formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p functions as a capacitance that stores at least part of the signal charge.

However, the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p produces a depletion layer. Lattice defects exist in the semiconductor substrate 60 , and in particular, various lattice defects due to impurities, dangling bonds, etc. exist on the surface of the semiconductor substrate 60 . If lattice defects exist in the depletion layer, for example, charge different from the original signal charge is likely to enter the impurity region 60a. In other words, lattice defects located in the depletion layer can cause dark current. The dark current lowers the SN ratio and degrades the image quality of the obtained image. If the depletion layer in the semiconductor substrate 60 can be reduced as much as possible to reduce the lattice defects located in the depletion layer among the lattice defects, it is advantageous because deterioration of image quality caused by dark current can be suppressed.

According to studies by the present inventors, in order to reduce the depletion layer formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p, the impurity region 60a after the signal charge is discharged from the impurity region 60a. It is effective to make the potential of the substrate as close to the substrate potential as possible. That is, it is effective to bring the potential of the impurity region 60a after reset as close to the substrate potential as possible. For example, when the signal charges are holes and the substrate potential is ground, it is beneficial to apply a voltage as low as possible, close to 0V, as the reset voltage.

However, if the potential difference between the potential of the impurity region 60a after resetting and the substrate potential is too small, the potential of the impurity region 60a will increase due to electrical coupling via a circuit element such as a transistor connected to the impurity region 60a. If it fluctuates, the potential of the impurity region 60a may drop below the substrate potential.

For example, if a field effect transistor is connected to an n-type impurity region in a floating node that stores signal charges, the effect of electrical coupling via the parasitic capacitance between the source and the drain will turn the transistor on and off. The potential of the impurity region may drop due to switching off. At this time, if the potential of the impurity region becomes lower than the substrate potential, a forward bias is applied to the pn junction between the impurity region and the surrounding p-well, and the p-type silicon substrate as the support substrate is applied with a forward bias. Holes flow into the impurity region. That is, dark current is generated, and the image quality of the obtained image may be degraded.

In view of the above, the inventors of the present invention have made extensive studies and found that, for example, by switching the first voltage V _A and the second voltage V _B to change the potential of the charge storage node after resetting, an impurity region that stores signal charges is formed. It has been found that it is possible to prevent charge different from the original signal charge from being mixed into the impurity region when the transistor connected to the transistor is switched on and off.

FIG. 3 schematically shows a typical example of the circuit configuration of the pixel 10A shown in FIG. In order to avoid making the drawing overly complicated, FIG. 2 omits illustration of a voltage line for supplying a predetermined bias voltage to the counter electrode 56 of the photoelectric conversion unit 50A. Similarly, in the subsequent drawings, the illustration of voltage lines for supplying a predetermined bias voltage to the opposing electrode 56 is omitted.

As shown in FIG. 3, the gate of the signal detection transistor 72 is connected to the photoelectric conversion section 50A. It can be said that the node FDa between the photoelectric conversion unit 50A and the signal detection transistor 72 corresponds to a charge accumulation node. A voltage corresponding to the signal charge accumulated in the node FDa is applied to the gate of the signal detection transistor 72 . As shown, the drain of the signal detection transistor 72 is connected to a power supply line 82 as a source follower power supply for supplying the power supply voltage Vdd, and the source of the signal detection transistor 72 is connected to the vertical signal through the address transistor 74. Line 89 is connected. That is, signal detection transistor 72 and address transistor 74 form a source follower. An address signal line 84 connected to the vertical scanning circuit 122 is connected to the gate of the address transistor 74 . The vertical scanning circuit 122 can read the signal from the pixel 10A to the vertical signal line 89 under the control of the address signal Φsel applied to the address signal line 84 .

Focus on node FDa. A reset transistor 76 is also connected to the node FDa. The side of the source and drain of reset transistor 76 that is not connected to node FDa is connected to reset voltage line 85 . During operation of the imaging device 100 , for example, a predetermined reset voltage Vr is applied to the reset voltage line 85 . A reset signal line 86 connected to the vertical scanning circuit 122 is connected to the gate of the reset transistor 76 . The vertical scanning circuit 122 can turn on the reset transistor 76 and apply the reset voltage Vr to the charge accumulation node under the control of the reset signal Φrst applied to the reset signal line 86 . As described with reference to FIG. 2, reset transistor 76 includes impurity region 60a forming part of the charge storage node as a drain region or a source region. When the reset transistor 76 is turned on, the signal charge is discharged from the charge storage node and the potential of the charge storage node is reset.

Here, voltage supply circuit 128 is further electrically connected to node FDa. In this example, a capacitive element C 1 is interposed between node FDa and control line 81 connected to voltage supply circuit 128 . In other words, the node FDa is connected to one of the two terminals of the capacitive element C1. That is, in this example, one terminal of the capacitive element C1 is electrically connected to the impurity region 60a. A voltage supply circuit 128 is connected to the other of the two terminals of the capacitive element C1.

There is no particular limitation on the specific configuration of the capacitive element C1. The capacitive element C1 may be, for example, an MIS (metal-insulator-semiconductor) structure arranged in the interlayer insulating layer 40, or may be a depletion type MOS (DMOS) capacitor. Alternatively, it may have an MIM (metal-insulator-metal) structure. Employing the MIM structure facilitates obtaining a larger capacitance value.

In the configuration illustrated in FIG. 3, voltage supply circuit 128 has switching elements 128a and 128b formed of field effect transistors or the like. That is, here, the voltage supply circuit 128 switches the voltage Vc applied to the control line 81 between the first voltage V _A and the second voltage V _B by switching on and off the switching elements 128a and 128b. It is possible.

(First example of operation of imaging device 100)
Next, an example of the operation of the imaging device 100 will be described with reference to FIG. 4A. FIG. 4A is a timing chart for explaining exemplary operations of the pixel 10A having the circuit configuration shown in FIG. In FIG. 4A, the top chart shows pulses of the horizontal sync signal HD. A period from the rise of one pulse to the rise of the next pulse corresponds to 1H, which is one horizontal scanning period. During this 1H period, among the plurality of pixels 10A included in the pixel array 110, the pixels 10A belonging to one row are reset and signals are read out from the pixels 10A. A double-headed arrow SEL in FIG. 4A indicates a selected period in which the address transistor 74 of the pixel of interest is turned on, and an arrow ACC indicates a non-selected period in which the address transistor 74 is turned off.

In FIG. 4A, the bottom chart shows the temporal change of the potential of the node _FDa , that is, the potential VFD of the impurity region 60a, and the second chart from the bottom shows the voltage applied from the voltage supply circuit 128 to the control line 81. Fig. 3 shows temporal changes in voltage Vc. Here, the first voltage V _A is applied to the control line 81 at time T1.

After signal charges are accumulated by exposure, the address signal Φsel is set to high level at time T1. By setting the address signal Φsel to high level, a first signal having a voltage level corresponding to the signal charge accumulated in the charge accumulation node is read out to the vertical signal line 89 via the signal detection transistor 72 and the address transistor 74 . The read first signal is temporarily held in the signal holding circuit 123 shown in FIG.

Next, at time T2, the reset signal Φrst is set to high level to turn on the reset transistor 76 . When the reset transistor 76 is turned on, the signal charge is discharged from the charge storage node and the potential of the charge storage node is reset. At this time, the potential VFD of the impurity region 60a is lowered to Vr by applying the reset voltage Vr to the node _FDa . A voltage higher than the substrate potential Vsub is used as the reset voltage Vr. Therefore, here Vr>Vsub. When the substrate potential Vsub is 0V, a positive voltage near 0V is used as the reset voltage Vr.

Next, at time T3, the reset signal Φrst is set to low level to turn off the reset transistor 76 . As described with reference to FIG. 2, reset transistor 76 includes impurity region 60a as a drain region or a source region. Therefore, when the reset transistor 76 is turned off, the electrical coupling caused by the parasitic capacitance of the reset transistor 76 may further reduce the potential _VFD of the impurity region 60a from Vr. As already explained, if the potential VFD becomes lower than the substrate potential _Vsub at this time, excess holes flow into the impurity region 60a.

However, here, not only is the reset signal _Φrst set to low level at time T3, but also the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched to the second voltage VB. Here, a voltage higher than the first voltage _VA is used as the second voltage _VB .

By switching the voltage Vc from the first voltage _VA to the second voltage VB higher than the first voltage _VA , the potential of the node _FDa can be increased via the capacitive element C1. In this example, the potential VFD of the impurity region 60a immediately after the reset transistor 76 is turned off is _V1a , which satisfies the relationship Vr>V1a>Vsub. For example, when the reset voltage Vr is 0.5V, V1a can be about 0.2V. That is, by appropriately selecting the second voltage V _B and switching the output from the voltage supply circuit 128 between the first voltage V _A and the second voltage V _B , the potential V _FD of the impurity region 60a is reduced to the substrate potential Vsub. is prevented from falling below In this example, a potential difference of 0.2 V can be ensured in the potential _VFD of the impurity region 60a with the substrate potential as a reference. In other words, excess holes are prevented from flowing into the impurity region 60a due to the potential VFD falling below the substrate potential _Vsub . In other words, dark current is suppressed. As a specific value of the second voltage V _B , the potential V _FD satisfies the relationship of V1a>Vsub when the reset transistor 76 is off, considering the magnitude of the parasitic capacitance between the source and the drain of the reset transistor 76. It is sufficient to select voltages that are different from each other.

After the reset transistor 76 is turned off, a second signal corresponding to the voltage level of the charge accumulation node after discharging the signal charge is applied through the address transistor 74 in a period until time T4 when the next pulse of the horizontal synchronizing signal HD rises. to the vertical signal line 89. The signal holding circuit 123 outputs the difference Δ between the first signal and the second signal to the horizontal scanning circuit 124 as a signal representing an image. After acquiring the second signal, the address transistor 74 is turned off to start accumulating the signal charge for the next frame.

In the example described above, the voltage supply circuit 128 applies the first voltage V _A to the impurity region 60a during the first period from time T2 to T3 when the reset transistor 76 is turned on. In the subsequent second period from time T3 to T4, the voltage applied to the impurity region 60a is switched to the second voltage _VB . As described with reference to FIG. 4A, by switching the voltage applied from the voltage supply circuit 128 to the impurity region 60a to the second voltage _VB higher than the first voltage _VA at the timing when the reset transistor 76 is turned off, Therefore, it is possible to prevent the potential VFD of the impurity region 60a from falling below the substrate potential _Vsub when the reset transistor 76 is turned off. Therefore, it is possible to suppress the dark current caused by excess holes flowing into the impurity region 60a.

Further, in the example shown in FIG. 3, the voltage Vc applied to the control line 81 is switched between the first voltage V _A and the second voltage V _B to change the potential of the node FDa via the capacitive element C1. . Thus, by interposing the capacitive element C1 between the impurity region 60a and the voltage supply circuit 128, the potential of the charge storage node can be controlled without affecting the signal charges stored in the charge storage node. becomes possible.

Here, as can be seen by referring to FIG. 3, since the capacitive element C1 is electrically connected to the node FDa, at least one of the charge accumulation nodes that temporarily hold the signal charge is similar to the impurity region 60a. compose the department. In other words, the connection of capacitive element C1 to node FDa increases the capacitance value of the entire charge storage node. For the following two reasons, it is advantageous to make the capacitance value of the capacitive element C1 as small as possible.

The first reason is that an increase in the overall capacitance value of the charge storage node results in a reduction in conversion gain. If the conversion gain decreases, the influence of noise in the subsequent circuit increases, and there is a risk of a decrease in the SN ratio. Therefore, from the viewpoint of avoiding a decrease in the SN ratio, it is beneficial to make the capacitance value of the capacitive element C1 as small as possible.

The second reason is that if capacitive element C1 has a relatively large capacitance value, the influence of noise on control line 81 entering node FDa through capacitive element C1 may increase. Noise contained in the voltage applied to control line 81 may enter node FDa due to electrical coupling via capacitive element C1. In particular, a configuration in which the voltage supplied to the control line 81 is commonly applied to the charge storage nodes of the pixels belonging to the same row via the capacitive element C1, in other words, the first voltage V _A and the second voltage V _B , noise on the control line 81 can appear on the image as horizontal line noise. Since horizontal line noise tends to be more noticeable to an image viewer than pixel-by-pixel random noise, it is beneficial to be able to suppress horizontal line noise.

Let C 1 be the capacitance value of the capacitive element C ₁ , and C _FD be the capacitance value of the portion of the charge storage node other than the capacitive element C 1 . C ₁ /(C ₁ +C _FD )). Therefore, from the viewpoint of suppressing horizontal line noise, it is advantageous for the capacitance value _C1 of the capacitive element C1 to be as small as possible.

Also, it is beneficial if the capacitance value C1 of the capacitive element C1 is smaller than _CFD for the portion of the charge storage node _other than the capacitive element C1. By making the capacitance value C1 of the capacitance element C1 smaller than the capacitance value CFD of the portion of the charge storage node _other than the capacitance element C1, the decrease in the SN ratio caused by connecting the capacitance element C1 to the node _FDa is suppressed. The degree can be made smaller than the degree of reduction in the S/N ratio when the F-number is increased by one step. For example, if the capacitance value C1 of the capacitive element C1 is set to about 1/2 or less of the capacitance value _CFD , the degree of decrease in the SN ratio due to the connection of the capacitive element C1 to the node _FDa is converted to the F value. Then, the change can be kept to about (1/2) stage or less.

Even when electrons are used as signal charges instead of holes, the same operation as the operation described with reference to FIG. 4A can be applied. However, when electrons are used as the signal charge, the potential V _FD of the impurity region 60a decreases as the signal charge amount is accumulated in the charge accumulation node, compared to the case where holes are used as the signal charge. Therefore, when electrons are used as signal charges, a larger positive voltage, such as _3.V , is used as the reset voltage Vr from the viewpoint of ensuring a sufficient potential difference between the substrate potential and the potential VFD of the impurity region 60a. Voltages on the order of 3V may be used.

Since a larger positive voltage is used as the reset voltage _Vr , the effect of a decrease in the potential VFD of the impurity region 60a due to electrical coupling caused by the parasitic capacitance of the reset transistor 76 when the reset transistor 76 is turned off is small. It can be said. However, when electrons are used as signal charges, it is necessary to use a higher voltage as the reset voltage Vr in order to improve the number of saturated electrons. It is advantageous to use holes as charges.

It is also possible to apply a p-type transistor as the reset transistor 76 . In this case, the conductivity type of each region in the semiconductor substrate 60 may be switched between n-type and p-type. However, when a p _- type transistor is used as the reset transistor 76, a voltage lower than the first voltage _VA is used as the second voltage VB as described below.

FIG. 4B is a timing chart for explaining exemplary operations when a p-type transistor is applied to the reset transistor 76 of the pixel 10A. When a p-type transistor is used as the reset transistor 76, a higher voltage than when an n-type transistor is used as the reset transistor 76 is used as the substrate potential Vsub. The substrate potential Vsub can be, for example, approximately 3.3V.

When a p-type transistor is used as the reset transistor 76, the use of holes as the signal charge is less affected by changes in the potential _VFD of the impurity region 60a due to electrical coupling caused by the parasitic capacitance of the reset transistor 76. is small. This is for the same reason as when an n-type transistor is used as the reset transistor 76 and electrons are used as signal charges. However, in order to secure a sufficient number of saturated electrons, it is necessary to secure a sufficient potential difference between the substrate potential and the potential _VFD of the impurity region 60a. On the other hand, if the signal charge is an electron, a voltage in the vicinity of 3.3 V, which is the substrate potential, may be used as the reset voltage Vr. Using electrons makes it easier to ensure a sufficient number of saturated electrons for the required dynamic range while avoiding circuit complication.

Therefore, an example of operation when electrons are used as signal charges will be described here. FIG. 4B shows an example of operation when a p-type transistor is used as the reset transistor 76 and electrons are used as signal charges. When reset transistor 76 is a p-type transistor and electrons are used as signal charges, typically signal detection transistor 72 and address transistor 74 are also formed in semiconductor substrate 60 as p-type transistors.

In the example shown in FIG. 4B, focusing on the period up to time T1, the potential VFD of the impurity region _60a is gradually lowered due to accumulation of signal charges due to exposure. After accumulating the signal charge, the address signal Φsel is set to low level at time T1 to turn on the address transistor 74 and read out the first signal to the vertical signal line 89 .

Next, at time T2, the reset signal Φrst is set to low level to turn on the reset transistor 76 . As shown in FIG. 4B, by turning on the reset transistor 76, the potential _VFD of the impurity region 60a rises to Vr. As the reset voltage Vr at this time, a voltage near the substrate potential Vsub and lower than the substrate potential Vsub, for example, 2.8V is used.

Next, at time T3, the reset signal Φrst is set to high level to turn off the reset transistor 76 . When the reset transistor 76 is turned off, electrical coupling caused by the parasitic capacitance of the reset transistor 76 can further increase the potential _VFD of the impurity region 60a from Vr. At this time, if the potential VFD exceeds the substrate potential _Vsub , a forward bias is applied to the pn junction between the impurity region 60a and its surroundings, and an excess voltage is applied to the impurity region 60a from the n-type silicon substrate as the supporting substrate. electrons flow in. In other words, dark current is generated.

Here, not only is the reset signal _Φrst set to high level at time T3, but also the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched to the second voltage VB lower than the first voltage _VA . . By switching the voltage Vc from the first voltage V _A to the second voltage V _B , the potential of the node FDa between the photoelectric conversion unit 50A and the signal detection transistor 72 can be lowered via the capacitive element C1. As shown in 4B, it is possible to prevent the potential VFD of the impurity region 60a from exceeding the substrate potential _Vsub . In this example, the potential _VFD of the impurity region 60a immediately after the reset transistor 76 is turned off is V1b, which satisfies the relationship Vsub>V1b>Vr. V1b may be on the order of 3.1V.

After the reset transistor 76 is turned off, the second signal corresponding to the voltage level of the charge storage node after discharging the signal charge is read out to the vertical signal line 89, and the absolute value of the difference Δ between the first signal and the second signal is obtained. obtained as an image signal. After acquiring the second signal, the address transistor 74 is turned off to start accumulating signal charge for the next frame.

(Second example of operation of imaging device 100)
An example of the operation of the imaging device according to the embodiment of the present disclosure is not limited to the example described with reference to FIGS. 4A and 4B. For example, as described below, between an exposure period during which signal charges are accumulated in the charge accumulation node and a period for resetting during a non-exposure period other than the exposure period in one frame period, the control line 81 Different voltages may be supplied.

FIG. 4C is a timing chart for explaining another example of the operations of the pixels 10A, 10Ap and 10Aq. As in the examples shown in FIGS. 4A and 4B, in the operation example shown in FIG. 4C, the exposure period for accumulating the signal charge in the charge accumulation node and the non-exposure period other than the exposure period are alternately repeated. A part of the non-exposure period includes a reset period for resetting the potential of the charge storage node to a predetermined potential.

Here, the pixel 10A shown in FIG. 3 is exemplified. First, at time T1, the address signal Φsel is set to high level. Also, at this time, the voltage applied to the control line 81 is switched from the first voltage V _A to the relatively higher second voltage V _B .

By switching the voltage applied to the control line 81 from the first voltage V _A to the second voltage V _B , the potential of the node FDa temporarily rises due to capacitive coupling via the capacitive element C1. At this time, the amount of change ΔV _FD in the potential of the node FDa is expressed by the following equation (1).

ΔV _FD =(V _B −V _A )(C ₁ /(C ₁ +C _FD )) (1)
The potential of the node FDa at this time is read out to the vertical signal line 89 via the signal detection transistor 72 and the address transistor 74 as a first signal representing a voltage level corresponding to the signal charge accumulated in the charge accumulation node.

At time T2, the reset signal Φrst is brought to a high level. As a result, the signal charge is discharged from the charge storage node via the reset transistor 76, and the potential of the charge storage node is reset to the reset voltage Vr.

At time T3, the reset signal Φrst is set to low level to turn off the reset transistor 76 . Between time T3 and time T4 when the next pulse of the horizontal synchronizing signal HD rises, a second signal corresponding to the voltage level of the charge storage node after discharging the signal charge is applied to the vertical signal via the address transistor 74. Read out on line 89.

In this example, the difference Δ between the first signal read out from time T1 to time T2 and the second signal read out from time T3 to time T4 expresses the image. A true pixel signal is obtained.

At time T4, the voltage applied to the control line 81 is returned to the first voltage V _A again. Capacitive coupling via the capacitive element C1 causes the potential of the node FDa to drop from Vr to V1c. The amount of change in the potential of node FDa at this time (Vr-V1c) is equal to ΔV _FD described above.

Here, if the capacitance values C1 and _CFD are known, the variation amount ΔV _FD is _{controlled by determining the first voltage V A and the second voltage V B based on} the above equation (1). be able to. A desired ΔV _FD can be achieved by the following procedure. First, when designing a product, the capacitance ratio between the capacitive element C1 and the portion of the charge storage node other than the capacitive element C1 is determined from the overall capacitance value of the target charge storage node. Then, the amplitude of the voltage applied to the control line 81 during actual operation, that is, the specific voltage values of the first voltage _VA and the second voltage _VB are determined based on the above equation (1).

Advantageously, either the first voltage _VA or the second voltage _VB is ground (0V). This is because the ground side generally has a low impedance, so that power supply noise from the voltage supply circuit 128 connected to the control line 81 can be suppressed from entering the charge storage node. For example, when the second voltage _VB is grounded, the first voltage _VA is a negative level voltage.

In this example, the voltage supply circuit 128 supplies the first voltage V _A to the control line 81 during the exposure period during which signal charges are accumulated in the charge accumulation node including the impurity region 60a as a part thereof. On the other hand, during row selection, a second voltage _VB different from the first voltage _VA is supplied. Here, particularly, the voltage supplied to the control line 81 during the reset period during which the reset transistor 76 is turned on among the non _- exposure periods is the second voltage VB. In this way, it is also possible to employ control that differs between at least the reset period after the exposure period and other periods. According to such control, for example, the potential of the charge storage node can be temporarily lowered compared to the reset voltage Vr. By lowering the potential of the charge storage node via the capacitive element C1, the potential difference between the impurity region 60a and the second p-type semiconductor layer 62p located around it and grounded, for example, can be reduced. As a result, the depletion layer formed by the pn junction between the impurity region 60a and the second p-type semiconductor layer 62p is reduced, and the dark current is reduced. That is, by setting the potential of the charge storage node to a low potential during the exposure period, the effect of reducing the dark current can be expected.

In the operation illustrated in FIG. 4C, when a row is selected, the potential of the charge storage node rises by the potential difference between the second voltage _VB and the first voltage _VA . Therefore, by adjusting this potential difference, the source-drain voltages of the signal detection transistor 72 and the transistors in the subsequent circuit can be set within the voltage range in which these transistors can operate. Therefore, the signal detection transistor 72 and the subsequent circuit can normally read out the pixel signal or the reference signal.

(Modification of the first embodiment)
The imaging device 100 of the present disclosure is not limited to a stacked imaging device. FIG. 5 schematically shows an example of another circuit configuration of the pixel 10. As shown in FIG. Compared with the pixel 10A described with reference to FIG. 3, the pixel 10Ap shown in FIG. 5 has a photoelectric conversion section 50B instead of the photoelectric conversion section 50A. The photoelectric conversion unit 50B is an embedded photodiode formed in the semiconductor substrate 60, for example.

As shown in FIG. 5, in this example, the gate of the signal detection transistor 72 is connected to the photoelectric conversion section 50B. In the configuration illustrated in FIG. 5, it can be said that the node FDb between the photoelectric conversion unit 50B and the signal detection transistor 72 corresponds to the charge accumulation node. In other words, the pn junction, the impurity region 60a, the gate electrode 72e, and the like in the embedded photodiode as the photoelectric conversion section 50B function as a charge storage node that temporarily holds the charge generated by the photoelectric conversion section 50B. Impurity region 60a may be part of the pn junction in the embedded photodiode.

An operation similar to the operation described with reference to FIGS. 4A and 4B can also be applied to the imaging device 100 having the pixels 10Ap. For example, the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched from the first voltage V _A to the second voltage V _B higher than the first voltage V _A at the timing when the reset signal Φrst is set to low level. Thus, the potential of the node FDb can be increased through the capacitor C1. By appropriately selecting the second voltage _VB , it is possible to prevent the potential VFD of the impurity region 60a from falling below the substrate potential _Vsub , thereby suppressing the dark current. When a buried photodiode is used as the photoelectric conversion unit, a configuration in which the reset transistor 76 or the like is a p-type transistor and electrons are accumulated as signal charges is more advantageous because a wider dynamic range can be obtained.

FIG. 6 schematically shows an example of still another circuit configuration of the pixel 10. As shown in FIG. Compared to the circuit configuration of the pixel 10Ap described with reference to FIG. 5, the pixel 10Aq illustrated in FIG. 6 further includes a transfer transistor 79 connected between the gate of the signal detection transistor 72 and the photoelectric conversion section 50B. . The transfer transistor 79 transfers the signal charge obtained by the photoelectric conversion unit 50B to a node FDc between the gate of the signal detection transistor 72 and the transfer transistor 79 at a predetermined timing. The transfer transistor 79 is, for example, an n-channel MOS. Transfer transistor 79 may share impurity region 60a with reset transistor 76 as one of the source region and the drain region.

According to the circuit configuration shown in FIG. 6, similarly to the pixel 10Ap shown in FIG. 5, by switching the voltage Vc from the first voltage V _A to the second voltage V _B , the potential of the node FDc, which is a floating node, is changed to For example, the potential VFD of the impurity region 60a can be prevented from falling below the substrate potential _Vsub by raising the potential VFD via the element C1. Switching of the voltage Vc from the first voltage V _A to the second voltage V _B is performed, for example, at the timing when the reset transistor 76 is turned off after the signal charge transferred to the node FDc is discharged by turning on the reset transistor 76 . be done.

7A and 7B schematically show still another circuit configuration example of the pixel 10. FIG.

Compared to the pixel 10A described with reference to FIG. 3, the pixel 10Ar shown in FIG. 7A has a depression-type signal detection transistor 72d instead of the signal detection transistor 72. FIG. By using a depletion type transistor as the signal detection transistor 72d, a high output can be obtained from the signal detection transistor 72d even when the potential of the node FDa is at a low level. Therefore, it becomes easier to ensure a voltage range necessary for the operation of the current source composed of the load circuit and the like connected to the vertical signal line 89 .

A pixel 10As shown in FIG. 7B has a configuration in which the photoelectric conversion unit 50A of the pixel 10Ar shown in FIG. 7A is replaced with a photoelectric conversion unit 50B. As described above, the photoelectric conversion unit 50B is an embedded photodiode formed in the semiconductor substrate 60, for example. Even in a configuration using a photodiode, a depletion-type transistor can be used as the signal detection transistor 72d.

FIG. 8 is a timing chart for explaining exemplary operations of the pixel 10Ar shown in FIG. 7A or the pixel 10As shown in FIG. 7B.

Compared to the example described with reference to FIG. 4C, in this example, the waveform of voltage Vc during the non-exposure period is different from the waveform in the operation sequence shown in FIG. 4C. As shown in FIG. 8, here, in the non _- exposure period, the period during which the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is the relatively high second voltage VB is short. In the operation illustrated in FIG. 8, the voltage Vc is switched from the first voltage V _A to the relatively high second voltage V _B at time T2 when the reset signal Φrst rises, and at time T3 the reset signal Φrst goes low. After being switched to the level, it is returned to the first voltage V _A . After the reset transistor 76 is turned off, the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched to the first voltage V _A , so that all changes in the voltage Vc contribute to changes in the potential of the charge storage node. becomes possible.

In the example shown in FIG. 8, switching the voltage Vc at time T4 causes the potential of the charge storage node to drop from the reset voltage Vr by ΔV _FD represented by equation (1). As a result, the potential of the charge storage node can be lowered to potential V1d lower than Vr. A true pixel signal representing an image of an object is given as a difference between a first signal corresponding to the potential of the charge storage node at time T1 and a second signal corresponding to the potential of the charge storage node at time T4. .

The first signal is read out on the vertical signal line 89 from time T1 to time T2, and the second signal is read out on the vertical signal line 89 from time T4 to time T5. That is, in this example, when the first voltage V _A is applied to the control line 81, the pixel signal and the reference signal are read out. Similarly in this example, by using a voltage of 0 V as the first voltage _VA , it is possible to suppress noise in the voltage output from the voltage supply circuit 128 from entering the node FDa or the node FDb.

9A and 9B schematically show still another circuit configuration example of the pixel 10. FIG. A pixel 10At shown in FIG. 9A is an example in which p-type transistors are applied as the signal detection transistor 72, the address transistor 74, and the reset transistor 76 in the circuit configuration shown in FIG. A pixel 10Au shown in FIG. 9B is an example in which p-type transistors are applied as the signal detection transistor 72, the address transistor 74, and the reset transistor 76 in the circuit configuration shown in FIG.

Electrons are typically used as signal charges in the configurations illustrated in FIGS. 9A and 9B. As described above, when a p-type transistor is used as the reset transistor 76, using electrons as signal charges avoids complication of the circuit and secures a sufficient number of saturated electrons for the required dynamic range. Cheap.

FIG. 10 is a timing chart for explaining exemplary operations of the pixel 10At shown in FIG. 9A or the pixel 10Au shown in FIG. 9B. In the example shown in FIG. 10, first, at time T1, the address signal Φsel is changed from high level to low level, and the voltage Vc applied to the control line 81 is switched from the first voltage V _A to the relatively low second voltage V _B . . By setting the address signal Φsel to low level, the first signal is read out to the vertical signal line 89 from the pixels in the selected row via the signal detection transistor 72 and the address transistor 74 . Here, the address signal Φsel is maintained at low level during the non-exposure period.

As can be seen from the graph of the voltage _VFD , by switching the voltage Vc applied to the control line 81 from the first voltage V _A to the second voltage V _B , the potential of the charge storage node is changed by capacitive coupling via the capacitive element C1. decreases. The potential fluctuation amount ΔV _FD at this time is expressed by the above equation (1) based on the capacitance ratio between the capacitive element C1 and the portion of the charge storage node other than the capacitive element C1. Between time T1 and time T2, a signal corresponding to the voltage _VFD at this time is read out to the vertical signal line 89 as the first signal.

In this example, at time T2, the reset is executed by setting the reset signal Φrst to low level. That is, when the reset signal Φrst is set to low level, the reset transistor 76 is turned on, the signal charge accumulated in the node FDa or FDb is discharged through the reset transistor 76, and the potential of the charge accumulation node becomes the voltage Vr. reset.

Next, at time T3, the reset signal Φrst is set to high level to turn off the reset transistor 76 . Here, the second signal corresponding to the reset voltage Vr is read out to the vertical signal line 89 from time T3 to time T4. As schematically shown in FIG. 10, the difference between the first signal read from time T1 to time T2 and the second signal read from time T3 to time T4. is output as a true pixel signal.

Thereafter, at time T4, the voltage Vc applied to the control line 81 is returned from the second voltage _VB to the first voltage _VA . As a result, the potential of the charge storage node rises from Vr to V1e due to capacitive coupling via the capacitive element C1. |Vr-V1e|, which is the amount of variation at this time, is equal to ΔV _FD when the voltage Vc applied to the control line 81 is lowered from the first voltage V _A to the second voltage V _B .

When electrons are used as signal charges as in this example, it is beneficial to use an n-type silicon substrate as the support substrate 60S and set the conductivity type of the impurity regions 60a to 60e to be p-type, as described above. That is, it is desirable that the signal detection transistor 72, the address transistor 74 and the reset transistor 76 are p-type transistors.

If a p-type silicon substrate is used as the support substrate 60S and the reset transistor 76 is an n-channel MOS, 0 V, for example, is used as the substrate potential Vsub. Here, it is assumed that the reset transistor 76 is a p-channel MOS and 0V is adopted as the substrate potential Vsub. At this time, as schematically shown in FIG. 10, the voltage _VFD decreases as electrons, which are signal charges, are accumulated in the charge accumulation node. In order to prevent the applied voltage from becoming a forward bias, it is necessary to reset the potential of the charge storage node to a potential higher than the substrate potential Vsub before accumulating the signal charge.

As already explained, when the signal charges are electrons, a voltage of 3.3 V, for example, can be used as the reset voltage Vr. In this case, as the signal charge is accumulated, the potential of the charge accumulation node drops from 3.3 V at the start of exposure, for example, and the potential difference with the substrate potential Vsub is reduced. Therefore, the width of the depletion layer is reduced, and the effect of reducing dark current can be expected.

From the viewpoint of reducing dark current, it is advantageous to use n-channel MOS for each transistor when holes are used as signal charges. This is for the following reasons.

For example, when a p-type transistor is used as the reset transistor 76, a voltage of about 3.3 V, for example, is used as the substrate potential Vsub. When an n-type silicon substrate is used as the support substrate 60S and the conductivity type of the impurity regions 60a to 60e is p-type, the potential VFD of the impurity region 60a is set to the substrate potential _Vsub in order to prevent the applied voltage from becoming a forward bias. cannot be raised higher than Further, the potential _VFD of the impurity region 60a rises as holes are accumulated in the charge accumulation node. Therefore, prior to accumulation of signal charges, the potential of the charge accumulation node is reset to, for example, 0 V, which is lower than the substrate potential Vsub. This is because, in this case, the difference between the potential of the charge storage node at the start of exposure and the substrate potential Vsub increases compared to when an n-channel MOS is used as the reset transistor 76 .

11A and 11B schematically show still another circuit configuration example of the pixel 10. FIG.

Compared to the pixel 10A shown in FIG. 3, the pixel 10Av shown in FIG. 11A further has a transistor 71 connected between the capacitive element C and the control line 81. The pixel 10Av shown in FIG. A difference between the pixel 10Av shown in FIG. 11A and the pixel 10Aw shown in FIG. 11B is that in the pixel 10Aw, the transistor 71 is connected between the node FDa and the capacitive element C1.

A transistor 71 in the pixel 10Av shown in FIG. 11A functions as a switching element that switches connection and disconnection between the capacitive element C1 and the voltage supply circuit 128 . A transistor 71 in the pixel 10Aw shown in FIG. 11B functions as a switching element that switches connection and disconnection between the node FDa and the capacitive element C1. According to the circuit configuration illustrated in FIG. 11A, by turning off the transistor 71 by controlling the potential of the control signal Φs applied to the gate of the transistor 71, the capacitance value of the entire charge storage node can be reduced. According to the circuit configuration illustrated in FIG. 11B, the capacitive element C1 can be electrically disconnected from the node FDa.

As described in each of the examples so far, the potential of the charge storage node is controlled via the capacitive element C1 by connecting the capacitive element C1 to the node FDa or the node FDb and switching the voltage supplied to the control line 81. becomes possible. However, as a result of connecting the capacitive element C1, the capacitance value of the entire charge storage node increases, so the conversion gain when converting the signal charge into voltage may decrease.

As illustrated in FIGS. 11A and 11B, transistor 71 may be interposed between capacitive element C1 and voltage supply circuit 128, or between node FDa or node FDb and capacitive element C1. Thus, switching the transistor 71 on and off can change the capacitance value of the entire charge storage node. In other words, by switching on and off of the transistor 71, the FD potential control mode for controlling the potential of the charge storage node via the capacitive element C1 and the high gain mode for efficiently converting the signal charge into a voltage signal are selected. It becomes possible to use them properly. The FD potential control mode is a mode in which the transistor 71 is turned on to electrically couple the voltage supply circuit 128 to the charge storage node via the capacitive element C1. This is a mode in which the capacitance value of is reduced.

Mode switching may be performed automatically using an exposure time or operating temperature that increases the effect on dark current as a criterion, or may be performed based on a user's instruction. For example, the FD potential control mode can be selected for long-time exposure exceeding 1 second or photographing under a high-temperature environment exceeding 80 degrees. The operation sequence in the FD potential control mode can be the same as the operation sequence described with reference to FIGS. 4A, 4B, 4C, 8, or 10, so description of the operation will be omitted.

FIG. 11C schematically shows still another circuit configuration example of the pixel 10 . In the configuration illustrated in FIG. 11C, the imaging device 100 has a load transistor 73 connected to the vertical signal line 89 . The load transistor 73 is, for example, an n-channel MOS and functions as a current source 94 .

In addition, in the example shown in FIG. 11C, the imaging device 100 has a feedback circuit 90x. Feedback circuit 90 x includes an inverting amplifier 92 having an inverting input terminal connected to vertical signal line 89 . The inverting amplifier 92 is provided for each column of the pixels 10Ax corresponding to the vertical signal line 89, and the reset voltage line 85 is connected to its output terminal. In the illustrated example, the signal detection transistor 72, the address transistor 74, the inverting amplifier 92, and the reset transistor 76 form a feedback loop that negatively feeds back the electrical signal generated by the photoelectric conversion section 50A.

During operation of the imaging device 100, the non-inverting input terminal of the inverting amplifier 92 is supplied with a voltage Vref of 1 V or around 1 V, for example. Voltage Vref can be any voltage within the range of power supply voltage Vdd and ground. When the feedback loop is formed, the voltage of the vertical signal line 89 converges to the voltage Vref input to the non-inverting input terminal of the inverting amplifier 92 . In other words, by forming a feedback loop, the potential of the node FDa can be reset to a potential that makes the voltage of the vertical signal line 89 equal to Vref.

The first and second signals are read out onto vertical signal line 89 by a source follower formed by signal detection transistor 72 and current source 94 . If the potential of the node FDa at the time of signal readout is low, the voltage appearing on the vertical signal line 89 via the signal detection transistor 72 is also low, and the source-drain voltage required for operation in the saturation region cannot be ensured. It is possible that load transistor 73 operates in the linear region. As a result, the source follower may not operate normally and the linearity of the signal may deteriorate.

If the current value obtained by the current source 94 is set small, the load transistor 73 can be operated in the saturation region. Also, due to the voltage drop of the vertical signal line 89, the input signal to the inverting amplifier 92 may deviate from the operating range, and the feedback circuit 90x may not operate normally. That is, there is a possibility that the potential of the node FDa cannot be reset to a potential that makes the voltage of the vertical signal line 89 equal to Vref.

For example, the operation sequence described with reference to FIG. 4C, FIG. 8 or FIG. 10 can be applied to an imaging device having pixels 10Ax. That is, by switching the voltage supplied to the control line 81 between the first voltage V _A and the second voltage V _B , the potential of the charge storage node is changed through the capacitive element C1 during at least part of the non-exposure period. to temporarily increase or decrease. For example, when holes are used as signal charges, the voltage applied from the voltage supply circuit 128 to the control line 81 is switched to selectively raise the potential of the charge storage node during the non-exposure period other than the exposure period.

By selectively setting the potential of the charge storage node to a high potential during the non-exposure period, the load transistor 73 is suppressed from operating in the linear region, and the first signal and the second signal are normally transmitted from the pixel. It is possible to read. Since the signal readout operation and feedback operation are performed during the non-exposure period, there is no problem even if the potential of the charge storage node is low such that the load transistor 73 operates in the linear region during the exposure period. do not have. By setting the potential of the charge storage node to a low potential during the exposure period, it is also possible to suppress the dark current without deteriorating the circuit characteristics.

(Second embodiment)
FIG. 12 schematically shows an example of the circuit configuration of pixels 10B included in the imaging device according to the second embodiment of the present disclosure. Similar to the pixel 10A shown in FIG. 3, the pixel 10B shown in FIG. 12 is an example of the pixel 10 described above. The main difference between the pixel 10B shown in FIG. 12 and the pixel 10A described with reference to FIG. It also has a connected transistor 78 . Another difference is that voltage supply circuit 128 is electrically connected to node RD between reset transistor 76 and transistor 78 . In this example, the voltage supply circuit 128 is electrically connected through the reset transistor 76 to the impurity region 60a.

As illustrated in FIG. 12, each pixel 10 of imaging device 100 may have a circuit configuration that further includes transistor 78 connected to reset transistor 76 . The transistor 78 is, for example, an n-channel MOS, and can include the impurity region 60b as the source region or the drain region of the reset transistor 76 as the drain region or the source region. In the configuration illustrated in FIG. 12, a reset voltage line 85 is connected to the side of the source and drain of the transistor 78 that is not connected to the reset transistor 76, and during operation of the imaging device 100, for example, a predetermined reset is performed. Voltage Vr is applied to transistor 78 . A gate of the transistor 78 is connected to a signal line 88 for supplying the transistor 78 with a signal Φfb for controlling on and off of the transistor 78 . Signal line 88 has a connection with, for example, vertical scanning circuit 122 , which may be configured to control the potential of signal line 88 .

In this example, the voltage supply circuit 128 is connected to the node RD between the reset transistor 76 and the transistor 78 via the capacitive element C2. That is, in this example, the voltage supply circuit 128 is connected not to the impurity region 60a side of the reset transistor 76 but to the impurity region 60b side via the capacitive element C2. Capacitive element C2 connected between control line 81 and impurity region 60b may have the same configuration as capacitive element C1 described above. Of course, it is not essential that the capacitive element C2 and the above-described capacitive element C1 have the same configuration.

FIG. 13 shows a more specific example to which the circuit configuration shown in FIG. 12 is applied. A pixel 10Bf shown in FIG. 13 is an example of the pixel 10B shown in FIG. In the configuration illustrated in FIG. 13, the feedback circuit 90 includes an inverting amplifier 92 whose inverting input terminal is connected to the vertical signal line 89, similar to the example described with reference to FIG. 11C.

In the configuration illustrated in FIG. 13, the pixel 10Bf has a capacitive element C3 connected in parallel to the reset transistor 76. In the configuration illustrated in FIG. When the address transistor 74 and at least the transistor 78 are on, the feedback circuit 90 forms a feedback loop that negatively feeds back the electrical signal generated by the photoelectric conversion section 50A. This feedback loop includes transistor 78 as part of it.

As is well known, thermal noise called kTC noise is generated when a transistor is turned on or off. If the reset transistor 76 is simply turned off after the potential of the node FDa is reset, the kTC noise generated by turning off the reset transistor 76 remains in the charge accumulation node before the signal charge is accumulated. However, the kTC noise that occurs when the reset transistor turns off can be reduced by using negative feedback, as described in WO2012/147302. For reference, the entire disclosure content of WO2012/147302 is incorporated herein.

In the circuit configurations shown in FIGS. 12 and 13, node RD between reset transistor 76 and transistor 78 is a floating node. As noted above, transistor 78 may include impurity region 60b as, for example, a drain region. Therefore, when the transistor 78 is turned off, the potential of the impurity region 60b may become lower than the substrate potential due to electrical coupling caused by the parasitic capacitance of the transistor 78 . If the potential of the impurity region 60b falls below the substrate potential, the impurity region 60b may unintentionally fluctuate in potential due to the influx of extra holes from the p-well, and the SN ratio may decrease. However, here, the voltage supply circuit 128 is electrically connected to the impurity region 60b. As described below, by switching the voltage Vc applied from the voltage supply circuit 128 to the control line 81 between the first voltage V _A and the second voltage V _B , the potential of the impurity region 60b becomes lower than the substrate potential. It is possible to prevent it from being put away.

FIG. 14A is a timing chart for explaining exemplary operations of the pixel 10Bf having the circuit configuration shown in FIG. In FIG. 14A, the second chart from the bottom shows temporal changes in the potential of the node _RD , that is, the potential VRD of the impurity region 60b. As can be seen from the chart showing the temporal change of the voltage Vc, here, as in the first example described with reference to FIGS. 4A and 4B, the control line 81 has the first A voltage _VA is applied.

After accumulation of signal charges by exposure, first, the address signal Φsel is set to high level at time T1. At this time, the first signal having a voltage level corresponding to the signal charge accumulated in the charge accumulation node is read.

Next, at time T2, the reset signal Φrst and the signal Φfb are set to high level. That is, the reset transistor 76 and the transistor 78 are turned on. A feedback loop is formed by turning on reset transistor 76 and transistor 78 . The formation of the feedback loop resets the potential of the node FDa. Here, the potential of the node FDa drops to the voltage V2a at which the voltage of the vertical signal line 89 becomes Vref. At this time, as the voltage Vref applied to the non-inverting amplification terminal of the inverting amplifier 92, a voltage that satisfies the relationship of V2a>Vsub is used. In the example shown in FIG. 14A, the potential VRD of the node _RD rises to V3 as the reset transistor 76 and the transistor 78 are turned on. As shown in FIG. 14A, the voltage V3 satisfies the relationship of V3>Vsub.

Next, at time T3, the reset signal Φrst is set to low level to turn off the reset transistor 76 . Here, due to electrical coupling caused by the parasitic capacitance of the reset transistor 76, the potential VFD of the impurity region 60a is lowered from _V2a to V4a as the reset transistor 76 is turned off. As described above, when the potential VFD falls below the substrate potential _Vsub , excess holes flow into the impurity region 60a. However, by appropriately selecting the voltage Vref applied to the non-inverting amplification terminal of the inverting amplifier 92, it is possible to prevent the potential VFD from falling below the substrate potential _Vsub . In this example, the relationship V4a>Vsub is satisfied by appropriately choosing the voltage Vref. From the viewpoint of reducing the depletion layer as much as possible, it is beneficial if V4a is a voltage as close as possible to Vsub as long as the relationship of V4a>Vsub is satisfied.

As described above, turning off the reset transistor 76 causes kTC noise. However, in the circuit configuration illustrated in FIG. 13, the capacitive element C3 is interposed between the node FDa and the node RD, and a feedback loop including the capacitive element C3 in its path is formed while the transistor 78 is not off. state continues. Therefore, the signal output from the transistor 78 is attenuated by the attenuation circuit formed by the capacitive element C3 and the parasitic capacitance of the node FDa itself.

After the reset transistor 76 is turned off, the signal Φfb is set to low level to turn off the transistor 78 . Here, not only is the reset transistor 76 turned off at time T4, but also the voltage Vc applied from the voltage supply circuit 128 to the control line 81 is switched to the second voltage _VB .

As schematically shown in FIG. 14A, when the transistor 78 is turned off, the electrical coupling caused by the parasitic capacitance of the transistor 78 reduces the potential V _RD of the impurity region 60b. In this example, the potential VRD drops from V3 to _V5a as the transistor 78 turns off. At this time, if V5a<Vsub, extra holes causing noise flow into the impurity region 60b.

As can be seen from the chart of the voltage Vc in FIG. 14A, here, the voltage supply circuit 128 changes the voltage Vc from the first voltage V _A to the voltage higher than the first voltage V _A at the timing when the transistor 78 is switched from ON to OFF. It is configured to switch to a higher second voltage _VB . By switching the voltage Vc from the first voltage V _A to the second voltage V _B , the potential V _RD of the node RD can be raised via the capacitive element C2, preventing the potential V _RD from falling below the substrate potential. can be prevented. As a specific value of the second voltage V _B , the potential V _RD satisfies the relationship of V5a>Vsub when the transistor 78 is turned off, considering the magnitude of the parasitic capacitance between the source and the drain of the transistor 78. The voltage should be selected such that

Note that when the transistor 78 is turned off, the potential of the signal line 88 may be gradually lowered from high level to low level so as to straddle the threshold voltage of the transistor 78 . When the potential of the signal line 88 is gradually lowered from high level to low level, the resistance of the transistor 78 is gradually increased. As the resistance of transistor 78 increases, the operating band of transistor 78 narrows and the frequency range of the feedback signal narrows.

When the voltage on signal line 88 reaches a low level, transistor 78 is turned off, eliminating the formation of a feedback loop. At this time, if the operating band of the transistor 78 is sufficiently lower than the operating band of the signal detection transistor 72, the thermal noise generated by the transistor 78 is suppressed to 1/(1+AB) ^1/2 times by the feedback circuit 90. be done. Here, A in the equation is the gain of the feedback circuit 90 and B is the attenuation factor of the attenuation circuit formed by the capacitive element C3 and the parasitic capacitance of the node FDa. Attenuation rate B is expressed as B=Cc/(Cc+Cf), where Cc and Cf are the capacitance values of the parasitic capacitances of capacitive element C3 and node FDa, respectively. Therefore, it is advantageous to reduce the influence of thermal noise when the capacitance value Cc of the capacitance element C3 is as small as possible as compared with the capacitance value of the capacitance element C2. Thus, by turning off the transistor 78 while the operating band of the transistor 78 is lower than that of the signal detection transistor 72, it is possible to reduce the kTC noise remaining at the node FDa. Note that in this specification, “the transistor 78 is off” means that the voltage of the signal line 88 is at a low level lower than the threshold voltage of the transistor 78 when the transistor 78 is an n-type transistor. , and indicates that the voltage of the signal line 88 is at a high level higher than the threshold voltage of the transistor 78 when the transistor 78 is a p-type transistor.

After the transistor 78 is turned off, the second signal corresponding to the voltage level of the charge storage node is read out during the period up to time T5 when the next pulse of the horizontal synchronizing signal HD rises. As in the first example described with reference to FIGS. 4A and 4B, the difference Δ between the first signal and the second signal is output to horizontal scanning circuit 124 as an image signal.

As described above, in this example, the voltage supply circuit 128 applies the first voltage V _A to the impurity region 60b during the first period in which the reset transistor 76 is on. Furthermore, the voltage supply circuit 128 applies the second voltage V _B to the impurity region 60b during the second period in which the transistor 78 is turned off after the reset transistor 76 is turned off.

According to the second embodiment, the potential V2a of the impurity region 60a when the reset transistor 76 and the transistor 78 are turned on and the potential V4a of the impurity region 60a when the transistor 78 is further turned off are set to the substrate potential Vsub. It is possible to make the potential as low as possible as close to the substrate potential Vsub as possible while preventing it from falling below. Further, with respect to the impurity region 60b, the potential V3 when the transistor 78 is turned on and the potential V5a when the transistor 78 is turned off after that are kept from falling below the substrate potential Vsub, and are kept at the substrate potential Vsub. It is possible to set the potential as low as possible. Therefore, it is possible to suppress the generation of dark current due to variations in the potential _VRD due to electrical coupling via the transistor 78, and to obtain an image signal in which deterioration of image quality due to the dark current is suppressed. .

It is also possible to apply p-type transistors instead of n-type transistors to reset transistor 76 and transistor 78 . FIG. 14B is a timing chart for explaining exemplary operations when p-type transistors are applied to the reset transistor 76 and the transistor 78 of the pixel 10Bf. Similar to the example described with reference to FIG. 4B, here, an example using electrons as signal charges will be described. In this case, signal detection transistor 72 and address transistor 74 are also typically p-type transistors.

After accumulation of signal charges by exposure, first, at time T1, the address signal Φsel is set to low level to read out the first signal. Next, at time T2, reset transistor 76 and transistor 78 are turned on to form a feedback loop. Formation of the feedback loop resets the potential of the node FDa to a voltage V2b that makes the voltage of the vertical signal line 89 equal to Vref. At this time, a voltage that satisfies the relationship of V2b<Vsub is used as the voltage Vref. Also, in this example, the potential VRD at the node _RD rises to V3 as the reset transistor 76 and the transistor 78 are turned on. The voltage V3 satisfies the relationship of V3<Vsub.

Next, at time T3, the reset transistor 76 is turned off. Here, as the reset transistor 76 is turned off, the potential VFD of the impurity region 60a rises from V2b to _V4b . If the potential VFD exceeds the substrate potential _Vsub , a dark current is generated. Therefore, the voltage Vref applied to the non-inverting amplification terminal of the inverting amplifier 92 is appropriately selected so that the potential VFD does not exceed the substrate potential _Vsub . do. From the viewpoint of reducing the depletion layer as much as possible, it is beneficial if V4b is a voltage as close as possible to Vsub as long as the relationship of V4b<Vsub is satisfied.

After the reset transistor 76 is turned off, the transistor 78 is turned off at time T4. At this time, the transistor 78 may be turned off by gradually increasing the potential of the signal line 88 from the low level to the high level so as to straddle the threshold voltage of the transistor 78 . When the transistor 78 is turned off, the electrical coupling caused by the parasitic capacitance of the transistor 78 can raise the potential V _RD of the impurity region 60b. In this example, the potential VRD rises from V3 to _V5b as the transistor 78 turns off.

At this time, if V5b>Vsub, the impurity region 60b will be contaminated with extra charges that cause noise. As shown in FIG. _14B , by not only turning off the transistor 78 but also switching the voltage Vc applied from the voltage supply circuit 128 to the control line 81 to the second voltage VB lower than the first voltage _VA , , the potential V _RD of the node RD can be lowered via the capacitive element C2, and the potential V _RD can be prevented from exceeding the substrate potential.

After the transistor 78 is turned off, the second signal corresponding to the voltage level of the charge storage node is read out during the period up to time T5 when the next pulse of the horizontal synchronizing signal HD rises. A difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.

Thus, by switching the voltage Vc from the first voltage V _A to the second voltage V _B lower than the first voltage V _A at the timing when the transistor 78 is turned off, the reset transistor 76 and the transistor 78 are p-type transistors. Even if it is applied, it is possible to suppress the occurrence of dark current due to variations in the potential _VRD due to electrical coupling via the transistor 78 .

(Modification of Second Embodiment)
FIG. 15 shows a modification of the imaging device according to the second embodiment of the present disclosure. A pixel 10Bp shown in FIG. 15 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10B shown in FIG. 12 is replaced with a photoelectric conversion unit 50B.

The operation of imaging device 100 having pixels 10Bp may be similar to the operation described with reference to FIG. 14A or 14B, for example. That is, a first voltage V A is applied to the impurity region 60b during a first period in which the reset transistor 76 is on, and a second voltage V _A is applied to the impurity region 60b after the reset transistor 76 is turned off and in which the transistor 78 is turned off. During this period, the second voltage V _B may be applied to the impurity region 60b.

According to the circuit configuration shown in FIG. 15, similarly to the pixel 10B shown in FIG. 12, by switching the voltage Vc from the first voltage V _A to the second voltage V _B , the potential of the node RD, which is a floating node, is changed to For example, it can be lifted via element C2. Therefore, it is possible to prevent the potential VRD of the impurity region 60b from falling below the substrate potential _Vsub due to turning off of the transistor 78, thereby suppressing the dark current. A transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion unit 50B, as in the pixel 10Aq shown in FIG.

FIG. 16 shows another modification of the imaging device according to the second embodiment of the present disclosure. A pixel 10Br shown in FIG. 16 is also an example of the pixel 10 described above. The main difference between pixel 10Br shown in FIG. 16 and pixel 10B described with reference to FIG. and the voltage supply circuit 128 is electrically connected to the side of the drain which is not connected to the reset transistor 76 . That is, in the example shown in FIG. 16 , the control line 81 connected to the voltage supply circuit 128 is connected to the side of the source and drain of the transistor 78 that is not connected to the reset transistor 76 .

(Third example of operation of imaging device 100)
FIG. 17A is a timing chart for explaining exemplary operations of the pixel 10Br having the circuit configuration shown in FIG. Compared to the operation example described with _reference to FIG. _14A , the operation example shown in FIG. there is

After accumulating signal charges by exposure, first, at time T1, the address signal Φsel is set to a high level, and the first signal having a voltage level corresponding to the signal charges accumulated in the charge accumulation node is read out.

Next, at time T2, the reset signal Φrst and the signal Φfb are set to high level to turn on the reset transistor 76 and the transistor 78 . As can be seen from the voltage Vc chart, the voltage supply circuit 128 applies the first voltage V _A to the control line 81 at time T2. Therefore, when the reset transistor 76 and the transistor 78 are turned on, the potential VFD of the impurity region 60a and the potential _VRD of the impurity region _60b change to _VA . By applying a voltage higher than the voltage applied to the substrate contact to give the substrate potential Vsub as the first voltage V _A , the potential V _FD of the impurity region 60 a and the potential V _RD of the impurity region 60 b are equal to the substrate of the semiconductor substrate 60 . It is possible to avoid falling below the potential Vsub.

Next, at time T3, the reset transistor 76 is turned off. When the reset transistor 76 is turned off, electrical coupling caused by the parasitic capacitance of the reset transistor 76 can cause the potential _{VFD of the impurity region 60a to drop from VA .} At this time, if the potential VFD of the impurity region 60a falls below the substrate potential _Vsub due to the reset transistor 76 being turned off, unnecessary holes flow into the impurity region 60a.

However, in the example shown in FIG. 17A, the voltage supply circuit 128 switches the voltage applied to the control line 81 from the first voltage V _A to the second voltage V _B at the timing when the reset transistor 76 is turned off. At this time, the transistor 78 is on, and the potential V _RD of the impurity region 60b changes to V _B as shown in FIG. 17A.

As described above, the field effect transistor has a parasitic capacitance between the source and the drain, and functions as a capacitance when turned off. Therefore, by increasing the voltage applied to the control line 81 from the first voltage V _A to the second voltage V _B , the potential V _FD of the impurity region 60a can be increased through the reset transistor 76 in the OFF state. is. By appropriately selecting the specific values of the first voltage V _A and the second voltage V _B , it is possible to reduce or cancel the decrease in the potential V _FD due to the turning off of the reset transistor 76. As a result, the impurity region 60a becomes It is possible to avoid the potential VFD falling below the substrate potential _Vsub . In this example, the potential VFD of the impurity region 60a is changed to _V6a satisfying the relationship of V6a>Vsub.

Next, at time T4, the transistor 78 is turned off. In this example, the voltage applied to the control line 81 is returned from the second voltage _VB to the first voltage _VA at the timing when the transistor 78 is turned off. At this time, due to electrical coupling via the transistor 78, the potential _VRD of the impurity region 60b can be lowered due to the transistor 78 being turned off. In this example, the potential V _RD of the impurity region 60b is lowered from V _B to V7a.

Here, however, the potential _VRD of the impurity region 60b immediately before the transistor 78 is turned off is _VB . Since the transistor 78 is turned off while the second voltage VB higher than the first voltage _VA close to the substrate potential _Vsub is applied, the potential _VRD can be prevented from falling below the substrate potential Vsub. . As shown in FIG. 17A, a relationship of V7a>Vsub is established here. A voltage that satisfies the relationship of _V7a >Vsub may be used as the second voltage VB. As long as the relationship _V7a >Vsub is satisfied, using a voltage as low as possible as the second voltage VB is advantageous for reducing the depletion layer. The voltage applied to the control line 81 may not be switched at the timing when the transistor 78 is turned off, and the second voltage V _B may continue to be applied to the control line 81 after time T4. Note that the parasitic capacitance between the source and the drain of the reset transistor 76 is relatively small, so even if the potential V _RD of the impurity region 60b drops from V _B to V7a, the potential V _FD of the impurity region 60a is hardly affected. does not occur.

After the transistor 78 is turned off, the second signal corresponding to the voltage level of the charge storage node is read out during the period up to time T5 when the next pulse of the horizontal synchronizing signal HD rises. A difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.

In the third example shown in FIG. 17A, the point that the voltage supply circuit 128 applies the first voltage V _A to the impurity region 60b during the first period in which the reset transistor 76 is on will be described with reference to FIG. 14A. This is common with the example given. However, in this example, the voltage supply circuit 128 applies the second voltage V _B to the impurity region 60b during the period during which the transistor 78 is turned on, excluding the first period. Such control can also prevent the potential VRD of the impurity region 60b from falling below the substrate potential _Vsub . In addition, it is possible to suppress the occurrence of dark current due to variations in the potential _VFD of the impurity region 60a due to electrical coupling via the reset transistor 76 in the off state.

It is also possible to apply control similar to the example described with reference to FIG. 14A to the circuit configuration illustrated in FIG. Refer again to FIG. 14A. In the example shown in FIG. 14A, transistor 78 is turned off at time T4. This point is common to the third example described here. When transistor 78 is turned off, electrical coupling through transistor 78 can reduce the potential V _RD of impurity region 60b, as described above. However, as shown in FIG. 14A, by switching the voltage applied to the control line 81 to the second voltage V _B at the timing when the transistor 78 is turned off, the potential drop due to electrical coupling via the transistor 78 minutes can be reduced. This is because after time T4, the transistor 78 is in an off state and the source-drain is in a non-conducting state, but the transistor 78 functions as a capacitor because it has a parasitic capacitance between the source and the drain. That is, the electrical coupling due to the parasitic capacitance of transistor 78 can be used to control the potential _VRD of impurity region 60b. By controlling the potential _VRD via the transistor 78, the potential VRD is prevented from falling below the substrate potential _Vsub when the transistor 78 is turned off, thereby preventing unnecessary holes from flowing into the impurity region 60b. obtain.

Thus, the transistor 78 after being turned off can exhibit the same function as the capacitive element C2 shown in FIG. However, the capacitance value of the source-drain parasitic capacitance is generally relatively small. Therefore, as in the circuit configuration illustrated in FIG. 12, it is preferable to _connect the voltage supply circuit 128 to the node RD via the capacitive element _C2 having a larger capacitance value. While applying a voltage with a smaller voltage difference, the potential V _RD of the impurity region 60b can be changed to a greater extent. In other words, the circuit configuration shown in FIG. 12 can more effectively reduce the drop in potential _VRD due to turning off of transistor 78 than the circuit configuration shown in FIG. can be used as the first voltage _VA .

FIG. 17B shows an exemplary operation when p-type transistors are applied to reset transistor 76, transistor 78, signal detection transistor 72 and address transistor 74 of pixel 10Br and electrons are used as signal charges. As described below, in the operation example shown in FIG. 17B, the timing of switching the voltage applied to the control line 81 between the first voltage V _A and the second voltage V _B is the operation described with reference to FIG. 17A. Common with the example. However, here, a voltage lower than the first voltage _VA is used as the second voltage _VB .

In the example shown in FIG. 17B, after signal charges are accumulated by exposure, the address transistor 74 is first turned on at time T1 to read out the first signal having a voltage level corresponding to the signal charges accumulated in the charge accumulation node. Next, at time T2, the reset signal Φrst and the signal Φfb are set to low level to turn on the reset transistor 76 and the transistor 78 . Here, since the voltage supply circuit 128 applies the first voltage V _A to the control line 81 at time T2, the potential V _FD of the impurity region 60a and the potential V _RD of the impurity region 60b are equal to V _A. Change. As the first voltage _VA , a voltage lower than the voltage that gives the substrate potential _Vsub is used so that the potential _VFD and the potential VRD do not exceed the substrate potential Vsub.

Next, at time T3, the reset transistor 76 is turned off. When the reset transistor 76 is turned off, electrical coupling caused by the parasitic capacitance of the reset transistor 76 can cause the potential VFD of the impurity region _60a to rise from _VA . At this time, as shown in FIG. 17B, by switching the voltage applied to the control line 81 from the first voltage V _A to the second voltage V _B lower than the first voltage V _A at the timing when the reset transistor 76 is turned off, Potential V _RD of impurity region 60b changes to V _B . By switching the voltage applied to the control line 81 from the first voltage _VA to the second voltage _VB , the potential _VFD of the impurity region 60a can be lowered via the reset transistor 76 in the OFF state. This can prevent the potential VFD of the impurity region 60a from exceeding the substrate potential _Vsub when the reset transistor 76 is turned off. In this example, the potential VFD of the impurity region 60a is changed to _V6b , which satisfies the relationship of V6b<Vsub.

Next, at time T4, the transistor 78 is turned off, and at the timing when the transistor 78 is turned off, the voltage applied to the control line 81 is returned from the second voltage _VB to the first voltage _VA . At this time, electrical coupling via the transistor 78 can increase the potential _VRD of the impurity region 60b. However, here, the transistor 78 is turned off with the second voltage V _B lower than the first voltage V _A close to the substrate potential Vsub applied to the control line 81, and the impurity region immediately after the transistor 78 is turned off. Assuming that the potential VRD of 60b is _V7b , the relationship V7b<Vsub is established. That is, the potential _VRD is prevented from exceeding the substrate potential Vsub.

After the transistor 78 is turned off, the second signal corresponding to the voltage level of the charge storage node is read out during the period up to time T5 when the next pulse of the horizontal synchronizing signal HD rises. A difference Δ between the first signal and the second signal is output to the horizontal scanning circuit 124 as an image signal.

Such control can prevent the potential VRD of the impurity region 60b from exceeding the substrate potential _Vsub . In addition, it is possible to suppress the occurrence of dark current due to variations in the potential _VFD of the impurity region 60a due to electrical coupling via the reset transistor 76 in the off state. Note that when p-type transistors are applied to the reset transistor 76, the transistor 78, the signal detection transistor 72, and the address transistor 74 of the pixel 10Br shown in FIG. 16, and electrons are used as the signal charge, the description will be made with reference to FIG. 14B. Controls similar to the examples given above can also be applied.

FIG. 18 shows still another modification of the imaging device according to the second embodiment of the present disclosure. A pixel 10Bq shown in FIG. 18 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10Br shown in FIG. 16 is replaced with a photoelectric conversion unit 50B. The operation of imaging device 100 having pixels 10Bq may be similar to the operation described with reference to FIG. 17A or 17B. That is, it is possible to apply the second voltage V _B to the impurity region 60b during the period during which the transistor 78 is turned on, excluding the first period during which the reset transistor 76 is turned on. Such control can prevent the potential VRD of the impurity region 60b from falling below the substrate potential _Vsub , for example.

Note that operations similar to those described with reference to FIGS. 14A and 14B may be applied to the circuit configuration illustrated in FIG. Similarly to the pixel 10Aq shown in FIG. 6, a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion section 50B.

(Third embodiment)
19A and 19B schematically show an example of a circuit configuration of pixels included in an imaging device according to the third embodiment of the present disclosure. The imaging device 140 shown in FIG. 19A has pixels 10D. Similar to the circuit configuration described with reference to FIG. 3, the pixel 10D has three transistors, a signal detection transistor 72, an address transistor 74 and a reset transistor 76, within the pixel 10D. A pixel 10Dp shown in FIG. 19B has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10D shown in FIG. 19A is replaced with a photoelectric conversion unit 50B.

The main difference between the pixel 10D shown in FIG. 19A and the pixel 10A described with reference to FIG. The difference is that it is electrically coupled to the signal line 84 via the capacitive element C1. Pixel 10D may have a device structure similar to the device structure described with reference to FIG. In the pixel 10Dp shown in FIG. 19B, similarly to the pixel 10D shown in FIG. 19A, among the terminals of the capacitive element C1, the terminal not connected to the node FDb is connected to the address signal line 84.

The address signal Φsel is input to the terminal connected to the address signal line 84 among the terminals of the capacitive element C1. Therefore, these exemplary circuits have configurations capable of controlling the potential of the node FDa or the node FDb by controlling the address signal Φsel. However, it is not essential that the address signal line 84 is connected to one terminal of the capacitive element C1. For example, when holes are used as signal charges, the terminal of the capacitive element C1 on the side opposite to the side connected to the node FDa or the node FDb is at high level during the reset period, and at the time of row selection. It suffices if a control signal that is at a low level is input during a period in which it is not. For example, a configuration is possible in which the reset signal Φrst or another control signal is input to the terminal of the capacitive element C1 opposite to the side connected to the node FDa or the node FDb.

FIG. 20 is a timing chart for explaining exemplary operations of the pixel 10D having the circuit configuration shown in FIG. 19A. Compared to the operation sequence described with reference to FIG. 4C, in the operation sequence illustrated in FIG. 20, the address signal _Φsel also serves as the voltage Vc shown in FIG. 4C. A signal Φ _H is represented, and Φ _L represents a low level signal Φ _L . Here, the low level signal Φ _L corresponds to the first voltage _VA , and the high level signal Φ _H corresponds to the second voltage V _B .

In the pixel 10D, the node FDa is capacitively coupled with the address signal line 84 via the capacitive element C1. Therefore, by setting the address signal Φsel to a high level at time T1, the potential of the node FDa can be increased. The potential fluctuation amount ΔV _FD at this time is represented by the following equation (2).

ΔV _FD =(Φ _H −Φ _L )(C ₁ /(C ₁ +C _FD )) (2)
By setting the address signal Φsel to the low level _ΦL at time T4, the potential of the node FDa is lowered by ΔV _FD represented by the above equation (2). In this way, it is possible to control the potential of the charge accumulation node using the address signal _Φsel . As shown in FIG. The potential can be set to a potential V1f lower than the reset voltage Vr. Note that the potential VFD of the impurity region 60a at the time of row selection and after execution of the reset is in a state of being raised to the reset voltage _Vr , so that the second circuit normally operates within the voltage range in which the circuit subsequent to the signal detection transistor 72 can operate. It is possible to perform signal readout.

According to the third embodiment, for example, the address signal Φsel is used to control the potential of the charge storage node through capacitive coupling, so the number of signal lines can be reduced. Accordingly, it is possible to reduce the size of pixels. Note that the capacitive element C1 is not limited to the element having the MIS structure, MIM structure, or the like described above. For example, the capacitive element C1 may be realized by a parasitic capacitance between wirings. For example, the capacitive element C1 may be realized by a parasitic capacitance between the gate of the signal detection transistor 72 and wiring such as a signal line.

(Fourth embodiment)
FIG. 21 schematically shows an example of a circuit configuration of pixels included in an imaging device according to the fourth embodiment of the present disclosure. The imaging device 150 shown in FIG. 21 has pixels 10C. Similar to the circuit configuration described with reference to FIG. 3, the pixel 10C has three transistors, a signal detection transistor 72, an address transistor 74 and a reset transistor 76, within the pixel 10C. These three transistors, the signal detection transistor 72, the address transistor 74 and the reset transistor 76, constitute a detection circuit 95 for detecting signal charges accumulated in the node FDa electrically connected to the photoelectric conversion section 50A. However, unlike the pixel 10A shown in FIG. 3, the voltage supply circuit 128 is not connected to the node FDa of the pixel 10C shown in FIG. Pixel 10C may have a device structure similar to the device structure described with reference to FIG.

(Example of operation of imaging device 150)
FIG. 22A is a timing chart for explaining exemplary operations of the pixel 10C having the circuit configuration shown in FIG.

After accumulation of the signal charge by exposure, the address transistor 74 is turned on at time T1 to read out the first signal having the voltage level corresponding to the signal charge accumulated in the charge accumulation node, which is the same as the typical example described above. . After that, as in the first example, at time T2, the reset signal Φrst is set to high level to turn on the reset transistor 76 to discharge the signal charge from the charge accumulation node via the reset transistor 76 . At this time, the potential _VFD of the impurity region 60a changes to Vr. Note that Vr>Vsub here.

Next, at time T3, the reset signal Φrst is set to low level to turn off the reset transistor 76 . When the reset transistor 76 is turned off, the electrical coupling caused by the parasitic capacitance of the reset transistor 76 causes the potential _VFD of the impurity region 60a to drop from Vr. Here, for example, if Vr is a voltage close to the substrate potential _Vsub , the potential VFD after the reset transistor 76 is turned off may fall below the substrate potential Vsub. In this example, by turning off the reset transistor 76, the potential VFD of the impurity region 60a is lowered from Vr to _V8a where V8a<Vsub.

However, in the example shown in FIG. 22A, at time T4, the reset signal Φrst applied to the gate of the reset transistor 76 is set to an intermediate value lower than the high level signal ΦH and higher than the low _level signal _ΦL . The voltage level signal Φ _M is switched. However, as the intermediate voltage level, a voltage level that keeps the reset transistor 76 in the off state is used.

By raising the reset signal Φrst from the low level to the intermediate voltage level signal Φ _M while the reset transistor 76 is kept off, the electrical coupling due to the parasitic capacitance between the gate and the drain of the reset transistor 76 is eliminated. Using the ring, the potential VFD of the impurity region 60a can be raised to a potential higher than the substrate potential _Vsub . In this example, by increasing the reset signal Φrst from the low level signal Φ _L to the intermediate voltage level signal Φ _M , the potential V _FD of the impurity region 60a is increased to V9a, which satisfies V9a>Vsub. .

After the reset signal _Φrst is raised from the low-level signal _ΦL to the intermediate voltage-level signal ΦM, during the period up to time T5 when the next pulse of the horizontal synchronizing signal HD rises, after the signal charge is discharged, that is, , to read out a second signal corresponding to the voltage level of the charge storage node after reset. That is, in this example, the readout of the second signal is executed while the potential VFD of the impurity region 60a is higher than the substrate potential _Vsub .

In this manner, the potential VFD of the impurity region 60a may temporarily fall below the substrate potential _Vsub between reading the first signal and reading the second signal. However, the intermediate voltage applied to the reset signal line 86 is such that the potential _VFD exceeds the substrate potential Vsub when the reset signal _Φrst is raised from the low level signal _ΦL to the intermediate voltage level signal ΦM. Determine voltage levels. If the period in which the potential VFD of the impurity region 60a is lower than the substrate potential _Vsub is very short, and the potential VFD of the impurity region 60a after reset is higher than the substrate potential _Vsub , the voltage level of the charge storage node after reset will be equal to the voltage level of the charge storage node. The influence of dark current on the corresponding second signal can be suppressed.

FIG. 22B is a timing chart for explaining exemplary operations when a p-type transistor is applied to the reset transistor 76 of the pixel 10C shown in FIG. 21 and electrons are used as signal charges. When p-type transistors are used for the signal detection transistor 72, the address transistor 74, and the reset transistor 76 instead of the n-type transistors, and electrons are used as signal charges, for example, the following operation can be applied.

After signal charges are accumulated by exposure, first, the address transistor 74 is turned on at time T1 to read out the first signal having a voltage level corresponding to the signal charges accumulated in the charge accumulation node. Next, at time T2, the reset signal Φrst is set to a low level to turn on the reset transistor 76, thereby discharging the signal charge from the charge accumulation node. At this time, the potential _VFD of the impurity region 60a is Vr, and in this example, Vr<Vsub.

Next, at time T3, the reset signal _Φrst is set to a high level signal ΦH to turn off the reset transistor 76 . In this example, by turning off the reset transistor 76, the potential VFD of the impurity region 60a rises from Vr to _V8b where V8b>Vsub. After that, at time T4, the reset signal _Φrst applied to the gate of the reset transistor 76 is switched to the signal ΦM at an intermediate voltage _level between the low level signal _ΦL and the high level signal ΦH. In this example, the intermediate voltage level signal Φ _M is higher than the low level signal Φ _L and lower than the high level signal Φ _H . Again, as the intermediate voltage level, a voltage level that keeps the reset transistor 76 off is used.

By lowering the reset signal _Φrst from the high level to the intermediate voltage level signal ΦM while keeping the reset transistor 76 off, electrical coupling via the reset transistor 76 is utilized to The potential VFD of the impurity region 60a can be lowered to a potential lower than the substrate potential _Vsub . In this example, by lowering the reset signal _Φrst from the high level signal ΦH to the intermediate voltage level signal ΦM, the potential VFD of the impurity region 60a is decreased to _V9b , which satisfies _V9b <Vsub. . After that, during the period up to time T5, the second signal corresponding to the voltage level of the charge storage node after discharging the signal charge is read.

In this example, the potential VFD of the impurity region 60a is set lower than the substrate potential _Vsub at the time of reading the second signal. If the potential V _FD of the impurity region 60a is lower than the substrate potential Vsub at the time of reading the second signal, the potential V FD of the impurity region 60a is lower than the potential V _FD of the impurity region 60a between the reading of the first signal and the reading of the second signal. may temporarily exceed the substrate potential Vsub. If the period in which the potential VFD of the impurity region 60a exceeds the substrate potential _Vsub is very short, and the potential VFD of the impurity region 60a after reset is lower than the substrate potential _Vsub , the voltage level of the charge storage node after reset will remain unchanged. The influence of dark current on the corresponding second signal can be suppressed.

In the fourth embodiment, the vertical scanning circuit 122 outputs a first level signal that turns on the reset transistor 76, a second level signal that turns off the reset transistor 76, and an intermediate level signal to the reset transistor 76. By sequentially applying to the gates, the potential of the impurity region 60a is reset. Here, the voltage corresponding to the intermediate level signal Φ _M is between the voltage corresponding to the first level signal and the voltage corresponding to the second level signal and is such that the reset transistor 76 can maintain the off state. voltage. In the circuit configuration illustrated in FIG. 21, if the potential VFD of the impurity region 60a is higher than the substrate potential _Vsub when the intermediate level signal _ΦM is applied to the gate of the reset transistor 76, as described with reference to FIG. In addition, deterioration of image quality can be avoided by suppressing the influence of dark current on the second signal corresponding to the voltage level of the charge storage node after reset. At this time, the potential VFD of the impurity region 60a may temporarily fall below the substrate potential _Vsub when the second level signal is applied to the gate of the reset transistor 76. FIG.

According to the fourth embodiment, deterioration of image quality due to dark current can be prevented while avoiding excessively complicated circuits. In addition, since the potential VFD of the impurity region 60a at the time of reading the second signal corresponding to the voltage level of the charge storage node after reset can be set to a potential as low as possible, for example, close to the substrate potential _Vsub , dark current is generated. can be effectively suppressed.

(Modified example of the fourth embodiment)
FIG. 23 shows a modification of the imaging device according to the fourth embodiment of the present disclosure. A pixel 10Cp shown in FIG. 23 has a circuit configuration in which the photoelectric conversion unit 50A of the pixel 10C shown in FIG. 21 is replaced with a photoelectric conversion unit 50B.

The operation of imaging device 100 having pixel 10Cp may be similar to the operation described with reference to FIGS. 22A and 22B. According to the circuit configuration shown in FIG. 23, like the pixel 10C shown in FIG. 21, it is possible to prevent deterioration of image quality due to dark current while avoiding excessively complicated circuits. Similarly to the pixel 10Aq shown in FIG. 6, a transfer transistor 79 may be further connected between the gate of the signal detection transistor 72 and the photoelectric conversion section 50B.

As described above, according to the embodiments of the present disclosure, for example, the potential of the impurity region included in the floating node can be controlled via the capacitance, and the potential between the impurity region and its periphery can be controlled. The depletion layer formed can be shrunk to reduce the number of lattice defects located within the depletion layer. Alternatively, it is possible to suppress noise from entering due to the generation of a forward current in the pn junction between the impurity region included in the floating node and its periphery. Therefore, an imaging device is provided in which the deterioration of the SN ratio due to dark current is suppressed.

The imaging device according to the embodiment of the present disclosure is not limited to the above examples, and various modifications are possible. The operation of peripheral circuit 120 including voltage supply circuit 128 may be performed based on instructions from a control circuit mounted on semiconductor substrate 60 or another substrate different from semiconductor substrate 60 . Each circuit included in the imaging device may be realized by an integrated circuit such as an LSI, or part or all of them may be integrated on one chip as a single circuit. Each circuit included in the imaging device may be implemented as an FPGA (field-programmable gate array), or may be a reconfigurable processor or the like. Each circuit included in the imaging device may be implemented as a circuit directed to specific processing, or may be realized by combining a general-purpose processing circuit with a program describing processing as exemplified in the above embodiments. may be implemented. This program can be stored in a memory or the like formed on the semiconductor substrate 60 or another substrate.

(Fifth embodiment)
FIG. 24 schematically shows functional blocks of a camera system according to the fifth embodiment of the present disclosure. A camera system 200 shown in FIG. 24 has an optical system 201 , an imaging device 100 , a signal processing circuit 203 , a system controller 204 and a display device 205 . Camera system 200 can be, for example, a smart phone, a digital camera, a video camera, and the like.

The optical system 201 has, for example, lens groups including lenses for optical zoom and autofocus, and an aperture. Any of the imaging devices described in the first to fourth embodiments can be applied as the imaging device 100 .

The signal processing circuit 203 is, for example, a DSP (Digital Signal Processor). A signal processing circuit 203 receives output data from the imaging apparatus 100 and performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance. The imaging device 100 and the signal processing circuit 203 may be implemented as a single semiconductor device. A semiconductor device can be, for example, a so-called SoC (System on a Chip). According to such a configuration, it is possible to further miniaturize an electronic device including the imaging device 100 as a part thereof.

A system controller 204 controls the entire camera system 200 . The system controller 204 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

The display device 205 is, for example, a liquid crystal display or an organic EL display. The display device 205 may have an input interface such as a touch panel. Thereby, the user can use the touch pen to select and control the processing content of the signal processing circuit 203 and set the imaging conditions via the input interface.

Each of the signal detection transistor 72, address transistor 74, reset transistor 76, transistor 71, transistor 78, load transistor 73 and transfer transistor 79 described above may be a p-channel MOS. As mentioned above, if these transistors are p-channel MOS, the second voltage may be lower than the first voltage. The signal detection transistor 72, the address transistor 74, the reset transistor 76, the transistor 71, the transistor 78, the load transistor 73 and the transfer transistor 79 need not all be unified to either n-channel MOS or p-channel MOS. Field effect transistors as well as bipolar transistors can be used as these transistors.

According to the embodiments of the present disclosure, there is provided an imaging apparatus capable of imaging with high image quality while suppressing the influence of dark current. The imaging device of the present disclosure is useful for, for example, image sensors, digital cameras, and the like. The imaging device of the present disclosure can be used for mobile device cameras, medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like.

10, 10A to 10C, 10Ap to 10Ax Pixel 10Bf, 10Br, 10Bp, 10Bq Pixel 10C, 10Cp, 10D, 10Dp Pixel 42 Connection portion 50A, 50B Photoelectric conversion portion 52 Pixel electrode 54 Photoelectric conversion layer 56 Counter electrode 60 Semiconductor substrate 60S Support substrate 60a to 60e impurity region 61p first p-type semiconductor layer 62p second p-type semiconductor layer 71 transistor 72, 72d signal detection transistor 72e gate electrode of signal detection transistor 73 load transistor 74 address transistor 76 reset transistor 78 transistor 79 transfer transistor 81 control line 84 address signal line 86 reset signal line 88 signal line 89 vertical signal line 90, 90x feedback circuit 94 current source 95 detection circuit 100, 140, 150 imaging device 110 pixel array 120 peripheral circuit 122 vertical scanning circuit 128 voltage supply circuit 200 camera system C1 to C3 capacitive element

Claims (12)

a semiconductor substrate having a first impurity region;
a photoelectric conversion unit that is electrically connected to the first impurity region and converts light into charge;
a capacitive element having a first terminal and a second terminal, the first terminal being connected to the first impurity region;
a voltage supply circuit electrically connected to the second terminal;
a first transistor including the first impurity region as one of a source and a drain;
The voltage supply circuit is
supplying a first voltage to the second terminal during a first period in which the first transistor is on;
The imaging device, wherein a second voltage different from the first voltage is supplied to the second terminal during a second period included in the non-exposure period after the first transistor is turned off. a semiconductor substrate having a first impurity region;
a photoelectric conversion unit that is electrically connected to the first impurity region and converts light into charge;
a capacitive element having a first terminal and a second terminal, the first terminal being connected to the first impurity region;
a voltage supply circuit electrically connected to the second terminal;
a first transistor including the first impurity region as one of a source and a drain;
with
The voltage supply circuit is
supplying a first voltage to the second terminal during an exposure period ;
An imaging device, wherein a second voltage different from the first voltage is supplied to the second terminal while the first transistor is on. the first impurity region is n-type,
3. The imaging device according to claim 1, wherein said first impurity region accumulates positive charges among charges generated in said photoelectric conversion unit. 4. The imaging device according to claim 3, wherein said second voltage is higher than said first voltage. the first impurity region is p-type,
3. The imaging device according to claim 1, wherein said first impurity region accumulates negative charges among charges generated in said photoelectric conversion unit. The imaging device according to claim 5, wherein said second voltage is lower than said first voltage. the capacitive element and the first impurity region are at least part of a charge storage node that stores one polarity of charge generated in the photoelectric conversion unit;
7. The imaging device according to claim 1, wherein the capacitance value of said capacitive element is smaller than the capacitance value of a portion of said charge storage node other than said capacitive element. The photoelectric conversion unit is
a first electrode;
a second electrode facing the first electrode;
a photoelectric conversion layer positioned between the first electrode and the second electrode;
8. The imaging device according to claim 1, wherein said first electrode is electrically connected to said first impurity region. 6. The imaging device according to any one of claims 1 to 3 and 5, wherein said photoelectric conversion unit is a buried photodiode. a second transistor having a gate electrically connected to the first impurity region;
a third transistor electrically connected to the second transistor for selectively outputting a signal amplified by the second transistor;
further comprising
2. The imaging device according to claim 1, wherein said non-exposure period is a period during which said third transistor is on. a second transistor having a gate electrically connected to the first impurity region;
a third transistor electrically connected to the second transistor for selectively outputting a signal amplified by the second transistor;
further comprising
3. The imaging device according to claim 2, wherein said exposure period is a period during which said third transistor is off. a semiconductor substrate having a first impurity region;
a photoelectric conversion unit that is electrically connected to the first impurity region and converts light into charge;
a capacitive element having a first terminal and a second terminal, the first terminal being connected to the first impurity region;
a voltage supply circuit electrically connected to the second terminal;
a first transistor including the first impurity region as one of a source and a drain;
with
The voltage supply circuit is
supplying a first voltage to the second terminal during a first period in which the first transistor is on;
An imaging device, wherein a second voltage different from the first voltage is supplied to the second terminal during a second period in which the first transistor is off.

Images