JP7156330B2 - Imaging element and imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device and an imaging device using the same.

Patent Document 1 below discloses a plurality of pixels, at least two of which each include (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitor, and (c) an input to an amplifier. and a connection switch for selectively connecting the charge-voltage conversion regions to each other.

Japanese Patent Publication No. 2008-546313

In the conventional solid-state imaging device, by turning on the connection switch to connect the charge-voltage conversion regions, the number of saturated electrons in the entire connected charge-voltage conversion regions is expanded, so that the dynamic range is increased. can be expanded.

In the conventional solid-state imaging device, the charge-voltage conversion capacity is reduced and the charge-voltage conversion coefficient is increased by turning off the connection switch to separate the charge-voltage conversion region from the other charge-voltage conversion regions. Therefore, the SN ratio becomes high during high-sensitivity readout.

However, in the conventional solid-state imaging device, even if the connection switch is turned off, the SN ratio during high-sensitivity readout cannot be increased so much.

The present invention has been made in view of such circumstances, and provides a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio during high-sensitivity readout, and imaging using the same. The purpose is to provide an apparatus.

The following aspects are presented as means for solving the above problems. A solid-state imaging device according to a first aspect includes one photoelectric conversion unit, a node, and one transfer switch provided corresponding to the one photoelectric conversion unit and transferring charge from the photoelectric conversion unit to the node. a plurality of pixel blocks; an electrical connection provided between the node of one pixel block and the node of another pixel block; and the pixel block provided in the connection. and a plurality of connection switches each.

The pixel block may have only one photoelectric conversion unit and may be composed of one pixel, or may have two or more photoelectric conversion units and may be composed of a plurality of pixels. good. This point is the same for each aspect described later.

A solid-state imaging device according to a second aspect, in the first aspect, further includes a control section for controlling the connection switch, wherein the control section controls the node of the pixel block in the first operation mode. The connection switch is controlled so that the connection section is electrically disconnected, and the control section electrically connects the connection section to the node of the pixel block in the second operation mode. The connection switch is controlled so as to be in a connected state.

In the solid-state imaging device according to the third aspect, in the second aspect, the control unit is configured such that, in the second operation mode, one or more predetermined number of the connection switches in the ON state among the connection switches are: , the connection switch is controlled so as to be electrically connected to the node of the pixel block.

A solid-state imaging device according to a fourth aspect is the solid-state imaging device according to the first aspect, wherein the nodes of three or more pixel blocks among the plurality of pixel blocks are connected in a daisy chain by a plurality of the connection portions. be.

A solid-state imaging device according to a fifth aspect is, in the fourth aspect, further comprising a controller for controlling the connection switch, wherein the controller controls, in the first operation mode, one of the three or more pixel blocks The control unit controls the connection switch so that the connection unit is electrically disconnected from the node of one pixel block, and the control unit controls the three or more nodes in the second operation mode. The connection switch is controlled such that the connection portion is electrically connected to the node of the one pixel block among the pixel blocks.

In the solid-state imaging device according to the sixth aspect, in the fifth aspect, in the second operation mode, the controller controls that, in the second operation mode, one or more predetermined number of the connection switches in the ON state among the connection switches are: , the connection switch is controlled so as to be electrically connected to the node of the one pixel block among the three or more pixel blocks.

A solid-state imaging device according to a seventh aspect is the solid-state imaging device according to any one of the first to sixth aspects, wherein each of the pixel blocks has a plurality of the photoelectric conversion units and the transfer switches.

A solid-state imaging device according to an eighth aspect comprises a plurality of photoelectric conversion units, a node, and a plurality of transfer devices provided corresponding to the plurality of photoelectric conversion units and transferring charges from the plurality of photoelectric conversion units to the nodes. A plurality of pixel blocks having switches, and a plurality of connecting switches provided between the nodes of two adjacent pixel blocks.

A solid-state imaging device according to a ninth aspect is, in the eighth aspect, further comprising a control section for controlling the connection switches, wherein the control section controls, in the first operation mode, whether or not the connection switches are turned on. The control unit controls the connection switch so that the connection switch is not electrically connected to the node of one of the two pixel blocks, and performing a second operation. In a mode, one or more predetermined number of ON state connection switches among the connection switches are electrically connected to the node of the one pixel block. is to control

A solid-state imaging device according to a tenth aspect is the solid-state imaging device according to the eighth aspect, wherein the nodes of three or more pixel blocks among the plurality of pixel blocks are connected in a daisy chain by two or more sets of the plurality of connection switches. It is what was done.

A solid-state imaging device according to an eleventh aspect is, in the tenth aspect, further comprising a control section for controlling the connection switches, wherein the control section controls, in the first operation mode, whether or not the connection switches are turned on. controlling the connection switch so that the connection switch is not electrically connected to the node of one of the three or more pixel blocks; , the connection switches are arranged such that one or more predetermined number of connection switches in the ON state among the connection switches are electrically connected to the node of the one pixel block. control.

A solid-state imaging device according to a twelfth aspect is the solid-state imaging device according to any one of the seventh to eleventh aspects, wherein the transfer switch is made of a transistor, and in each pixel block, the source of one transfer switch among the transfer switches Alternatively, a diffusion region serving as a drain and a diffusion region serving as the source or drain of another transfer switch among the transfer switches are connected to one photoelectric conversion unit among the photoelectric conversion units and each photoelectric conversion unit. one diffusion region provided between one photoelectric conversion portion and another one of the photoelectric conversion portions, and in each of the pixel blocks, the gate electrode of the one transfer switch serves as the gate electrode of the one diffusion region, the arranged on the one photoelectric conversion unit side, and in each of the pixel blocks, the gate electrode of the other transfer switch is arranged on the one diffusion region on the other photoelectric conversion unit side; It is.

A solid-state imaging device according to a thirteenth aspect is the solid-state imaging device according to any one of the seventh to twelfth aspects, wherein the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are two each.

A solid-state imaging device according to a fourteenth aspect is the solid-state imaging device according to the thirteenth aspect, wherein the number of the plurality of connection switches is two, one of the plurality of connection switches and one of the plurality of connection switches is larger than the pitch of the plurality of photoelectric conversion units in the predetermined direction and smaller than twice the pitch.

A solid-state imaging device according to a fifteenth aspect is the solid-state imaging device according to any one of the first to fourteenth aspects, wherein the number of the plurality of connection switches is two, and when the plurality of connection switches are off, the plurality of The value of the capacitance between the connection between the coupling switches and the reference potential is in the range of ±20% with respect to the value of the capacitance between the node and the reference potential when the plurality of coupling switches are off. is a value within

A solid-state imaging device according to a sixteenth aspect is the solid-state imaging device according to any one of the first to fifteenth aspects, wherein the number of the plurality of connection switches is two, and when the plurality of connection switches are off, the plurality of Width of at least part of a wiring forming a connection between connection switches is wider than width of other wiring in the pixel block, a MOS capacitor is connected to the connection, and each of the connections. a diffusion capacitor that does not constitute a switch is connected to the connecting portion.

A solid-state imaging device according to a seventeenth aspect includes one photoelectric conversion unit, a first node, and a charge transfer device provided corresponding to the one photoelectric conversion unit from the photoelectric conversion unit to the first node. a plurality of pixel blocks having one transfer switch; two second nodes respectively corresponding to the first node of one pixel block and the first node of another pixel block; two first nodes for electrically connecting and disconnecting the first node of one pixel block and the first node and the two second nodes of the other pixel block, respectively; and a second switch for electrically connecting and disconnecting the two second nodes.

A solid-state imaging device according to an eighteenth aspect is, in the seventeenth aspect, further comprising a control unit for controlling each of the first switch units and the second switch units, wherein the control unit, in the first operation mode, , the first switch section for electrically connecting and disconnecting the first node of the one pixel block and the corresponding second node is turned off; wherein, in a second operation mode, a predetermined number of one or more of the first switch units and the second switch units in the ON state are in the one switch unit; The first switch section and the second switch section are controlled so as to be electrically connected to the first node of one pixel block.

The solid-state imaging device according to the nineteenth aspect, in the seventeenth aspect, is characterized in that the first nodes of three or more pixel blocks among the plurality of pixel blocks, and the three or more first nodes of these pixel blocks three or more of the first switch units for electrically connecting and disconnecting with the three or more of the second nodes respectively corresponding to the three or more second nodes, It is connected in a daisy chain by a plurality of the second switch units.

A solid-state imaging device according to a twentieth aspect, in the nineteenth aspect, further comprises a control unit for controlling each of the first switch units and the second switch units, wherein the control unit operates in a first operation mode wherein the first switch section electrically connects and disconnects the first node of one pixel block among the three or more pixel blocks and the corresponding second node. controlling the first switch units of the one pixel block out of the three or more pixel blocks to turn off, the control unit turning off each of the first switch units in a second operation mode; and one or more predetermined number of ON-state switch portions of each of the second switch portions are electrically connected to the first node of the one pixel block of the three or more pixel blocks. Each of the first switch units and each of the second switch units are controlled so as to be in a state of being effectively connected.

A solid-state imaging device according to a twenty-first aspect is the solid-state imaging device according to any one of the seventeenth to twentieth aspects, wherein each of the pixel blocks has a plurality of the photoelectric conversion units and the transfer switches.

A solid-state imaging device according to a twenty-second aspect is the solid-state imaging device according to the twenty-first aspect, wherein the transfer switches are transistors, and in each pixel block, a diffusion region serving as a source or a drain of one of the transfer switches , and a diffusion region serving as a source or a drain of another transfer switch among the transfer switches is divided between one photoelectric conversion unit and the other photoelectric conversion unit among the photoelectric conversion units. One diffusion region provided between one photoelectric conversion unit and one photoelectric conversion unit is also used. In each pixel block, the gate electrode of the other transfer switch is arranged on the other photoelectric conversion unit side of the one diffusion region.

A solid-state imaging device according to a twenty-third aspect is the solid-state imaging device according to the twenty-first or twenty-second aspect, wherein the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are two each.

A solid-state imaging device according to a twenty-fourth aspect is the solid-state imaging device according to any one of the seventeenth to twenty-third aspects, wherein the second node when the first switch units and the second switch units are in an off state and the reference potential is within a range of ±20% of the value of the capacitance between the first node and the reference potential when the first switch section is in the OFF state. is the value of

A solid-state imaging device according to a twenty-fifth aspect is the solid-state imaging device according to any one of the seventeenth to twenty-fourth aspects, wherein the width of at least part of the wiring connected to the second node is wider than that of other wirings in the pixel block. a MOS capacitor is connected to the second node; and a diffusion capacitor forming neither the first switch section nor the second switch section is connected to the second gate. being connected.

An imaging device according to a twenty-sixth aspect comprises the solid-state imaging device according to any one of the first to twenty-fifth aspects.

An imaging device according to a twenty-seventh aspect comprises a solid-state imaging device according to any one of the second, third, fifth, sixth, ninth, eleventh, eighteenth and twentieth aspects, and an ISO sensitivity set value and control means for switching between the first operation mode and the second operation mode accordingly.
The following aspects are also presented as means for solving the above problems. The imaging element by the first surface is an imaging element having a plurality of pixel blocks arranged side by side in a row direction and a column direction, wherein the pixel blocks include a plurality of photoelectric conversion units that convert light into electric charges. a node having a first diffusion portion to which charges converted by the plurality of photoelectric conversion portions are transferred; a reset transistor for controlling connection between the node and a power supply line to which a predetermined voltage is supplied; a connection transistor for controlling connection between the node and the node of another pixel block arranged adjacently in the column direction , wherein the reset transistor and the connection transistor are: A second diffusion portion electrically connected to the node is shared , and the first diffusion portion and the second diffusion portion are electrically connected by wiring .
In the imaging device according to the second surface, in the first surface, the reset transistor is formed using the first diffusion portion as a source.
The imaging device according to the third surface is such that, in the first or second surface, the connecting transistor is formed using the first diffusion portion as a source.
The image pickup device according to the fourth surface is an image pickup device including a plurality of pixel blocks arranged side by side in the row direction and the column direction, wherein the pixel blocks include a plurality of photoelectric conversion units that convert light into electric charges. a node having a first diffusion portion to which charges converted by the plurality of photoelectric conversion portions are transferred; a reset transistor for controlling connection between the node and a power supply line to which a predetermined voltage is supplied; a connection transistor for controlling connection between the node and the node of another pixel block arranged adjacently in the column direction, the source of the reset transistor being electrically connected to the node; the source of the connecting transistor is formed by the second diffusion portion; and the first diffusion portion and the second diffusion portion are electrically connected by a wiring. It is what is done.
A fifth aspect of the imaging device according to any one of the first to fourth aspects, wherein the second diffusion portion is arranged between the gate of the reset transistor and the gate of the coupling transistor in the row direction. It is a thing.
The imaging device according to the sixth aspect includes an amplifying transistor having a gate connected to the wiring in any one of the first to fifth aspects .
In the imaging device according to the seventh aspect, in the sixth aspect, the gate width of the amplifying transistor is larger than the gate width of the reset transistor.
In the imaging device according to the eighth aspect, in the sixth or seventh aspect, the gate width of the amplifying transistor is larger than the gate width of the connecting transistor.
A ninth aspect of the imaging device according to any one of the sixth to eighth aspects is such that the drain of the amplifying transistor is electrically connected to the power supply line.
The imaging device according to the tenth aspect, in any one of the sixth to ninth aspects, further includes a selection transistor for controlling connection between the amplification transistor and a signal line through which a signal from the amplification transistor is output. The source of the amplifying transistor is formed by a third diffusion arranged at a position different from that of the second diffusion, and the drain of the selection transistor is formed by the third diffusion.
The imaging device according to the eleventh aspect is the tenth aspect, wherein the third diffusion portion is arranged between the gate of the amplification transistor and the gate of the selection transistor in the row direction.
In the imaging device according to the twelfth aspect, in the tenth or eleventh aspect, the gate width of the amplification transistor is larger than the gate width of the selection transistor.
The thirteenth surface of the imaging element is such that the plurality of photoelectric conversion units are arranged side by side in the column direction on any one of the first to twelfth surfaces .
an imaging device having a fourteenth surface, a plurality of nodes arranged side by side in a row direction and a column direction and having a first diffusion portion to which photoelectrically converted charges are transferred; and a first node among the plurality of nodes. and a power supply line to which a predetermined voltage is supplied; a connection transistor for controlling connection between the first node and a second node among the plurality of nodes; wherein the first node and the second node are arranged next to each other in the column direction, and the first diffusion portion receives charges converted by the plurality of photoelectric conversion portions and is transferred to the reset node. The transistor and the connecting transistor share a second diffusion portion electrically connected to the first node, and the first diffusion portion and the second diffusion portion are electrically connected by a wiring. is.
A fifteenth aspect of the imaging device according to the fourteenth aspect is characterized in that the reset transistor is formed using the second diffusion portion as a source.
The sixteenth aspect of the imaging device is such that, in the fourteenth or fifteenth aspect, the coupling transistor is formed with the second diffusion portion as a source.
an imaging element having a seventeenth surface, a plurality of nodes arranged side by side in a row direction and a column direction and having a first diffusion portion to which photoelectrically converted charges are transferred; and a first node among the plurality of nodes. and a power supply line to which a predetermined voltage is supplied; a connection transistor for controlling connection between the first node and a second node among the plurality of nodes; wherein the first node and the second node are arranged next to each other in the column direction, and the first diffusion portion receives charges converted by the plurality of photoelectric conversion portions and is transferred to the reset node. A source of the transistor is formed by a second diffusion electrically connected to the node, a source of the connecting transistor is formed by the second diffusion , the first diffusion and the second diffusion. are electrically connected by wiring .
The image sensor according to the eighteenth aspect is any one of the fourteenth to seventeenth aspects, wherein the second diffusion portion is arranged between the gate of the reset transistor and the gate of the connection transistor in the row direction. It is a thing.
The image pickup device according to the nineteenth aspect, in any one of the fourteenth to eighteenth aspects , includes an amplification transistor having a gate connected to the wiring.
In the imaging device according to the twentieth aspect, in the nineteenth aspect, the gate width of the amplifying transistor is larger than the gate width of the reset transistor.
A twenty -first aspect of the imaging device is, in the nineteenth or twentieth aspect, wherein the gate width of the amplifying transistor is larger than the gate width of the connecting transistor.
The imaging device according to the 22nd aspect is, in any one of the 22nd to 24th aspects, wherein the drain of the amplifying transistor is electrically connected to the power supply line.
The imaging device according to the 23rd aspect, in any one of the 19th to 22nd aspects, further includes a selection transistor for controlling connection between the amplification transistor and a signal line through which a signal from the amplification transistor is output. The source of the amplifying transistor is formed by a third diffusion arranged at a position different from that of the second diffusion, and the drain of the selection transistor is formed by the third diffusion.
The imaging device according to the twenty -fourth aspect is such that, in the twenty -third aspect, the third diffusion portion is arranged between the gate of the amplification transistor and the gate of the selection transistor in the row direction.
In the twenty -fifth aspect of the imaging device according to the twenty -third or twenty -fourth aspect, the gate width of the amplification transistor is larger than the gate width of the selection transistor.
In the imaging element of the twenty-sixth surface, the plurality of photoelectric conversion units are arranged in the column direction on any one of the fourteenth to twenty-fifth surfaces .
The image pickup device according to the twenty -seventh aspect comprises an image pickup device according to any one of the first to twenty -sixth aspects.

According to the present invention, it is possible to provide a solid-state imaging device capable of expanding the dynamic range and improving the SN ratio during high-sensitivity readout, and an imaging apparatus using the same.

1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the invention; FIG. 2 is a circuit diagram showing a schematic configuration of a solid-state imaging device in FIG. 1; FIG. 3 is an enlarged circuit diagram showing the vicinity of three pixel blocks in FIG. 2; FIG. 4 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 3; FIG. 5 is a schematic plan view showing an enlarged vicinity of one pixel block in FIG. 4; FIG. 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2; 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2; 3 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2; FIG. 5 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device according to a comparative example; FIG. 10 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 9; FIG. 10 is a circuit diagram showing the vicinity of three pixel blocks of the solid-state imaging device of the electronic camera according to the second embodiment of the present invention; FIG. 12 is a schematic plan view schematically showing the vicinity of three pixel blocks shown in FIG. 11; FIG. 11 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a third embodiment of the present invention; FIG. 11 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a fourth embodiment of the present invention; 15 is an enlarged circuit diagram showing the vicinity of four pixel blocks in FIG. 14; FIG. 15 is a timing chart showing predetermined operation modes of the solid-state imaging device shown in FIG. 14; 15 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 14; 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 14; 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 14; 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 14; FIG. 12 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a fifth embodiment of the present invention;

A solid-state imaging device and an imaging device according to the present invention will be described below with reference to the drawings.

[First embodiment]
FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 according to the first embodiment of the invention.

The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera, but the image pickup apparatus according to the present invention is not limited to this, and may be other electronic cameras such as a compact camera or a camera installed in a mobile phone. It can be applied to various imaging devices such as an electronic camera and an electronic camera such as a video camera that captures moving images.

A photographing lens 2 is attached to the electronic camera 1. - 特許庁The lens controller 3 drives the focus and aperture of the photographing lens 2 . An imaging surface of a solid-state imaging device 4 is arranged in the image space of the taking lens 2 .

The solid-state imaging device 4 is driven by a command from the imaging control section 5 and outputs a digital image signal. During normal actual photography (still image photography), for example, the imaging control unit 5 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after a so-called global reset that simultaneously resets all pixels. It controls the solid-state imaging device 4 . Further, in the electronic viewfinder mode or during moving image shooting, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a predetermined readout operation while performing a so-called rolling electronic shutter, for example. At these times, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform the readout operation of each operation mode, which will be described later, according to the set value of the ISO sensitivity, as will be described later. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4 . The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7 . A memory 7 is connected to the bus 8 . Also connected to the bus 8 are the lens control unit 3, the imaging control unit 5, the CPU 9, the display unit 10 such as a liquid crystal display panel, the recording unit 11, the image compression unit 12, the image processing unit 13, and the like. An operation unit 14 such as a release button is connected to the CPU 9 . ISO sensitivity can be set by the operation unit 14 . A recording medium 11 a is detachably attached to the recording unit 11 .

The CPU 9 in the electronic camera 1 drives the image pickup control section 5 in response to an electronic viewfinder mode, moving image shooting, normal main shooting (still image shooting), or the like by operating the operation section 14 . At this time, the lens control unit 3 appropriately adjusts the focus and the aperture. The solid-state imaging device 4 is driven by a command from the imaging control section 5 and outputs a digital image signal. A digital image signal from the solid-state imaging device 4 is stored in the memory 7 after being processed by the digital signal processing unit 6 . The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a in moving image shooting. In the case of normal actual photography (during still image photography), the CPU 9 processes the digital image signal from the solid-state imaging device 4 in the digital signal processing section 6 and stores it in the memory 7, and then outputs it to the operation section 14. , the image processing unit 13 and the image compression unit 12 perform desired processing as necessary, and the recording unit 11 outputs the processed signal to record it on the recording medium 11a.

FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 shown in FIG. FIG. 3 is an enlarged circuit diagram showing the vicinity of three pixel blocks BL sequentially arranged in the column direction in FIG. 4 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 3. FIG. FIG. 5 is a schematic plan view showing an enlarged vicinity of one pixel block BL in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS-type solid-state imaging device, but is not limited to this, and may be configured as another XY address type solid-state imaging device, for example.

As shown in FIGS. 2 to 4, the solid-state imaging device 4 includes a pixel block BL arranged in a two-dimensional matrix with N rows and M columns and each having two pixels PX (PXA, PXB), and one pixel block BL. Each of the connection transistors SWa and SWb as a plurality of connection switches, the vertical scanning circuit 21, the control lines 22 to 27 provided for each row of the pixel block BL, and each column of the pixel PX (column of the pixel block BL) a plurality of (M) vertical signal lines 28 provided to receive signals from pixels PX (pixel blocks BL) in corresponding columns; a constant current source 29 provided to each vertical signal line 28; It has a column amplifier 30 , a CDS circuit (correlated double sampling circuit) 31 , an A/D converter 32 and a horizontal reading circuit 33 provided corresponding to the vertical signal line 28 .

As the column amplifier 30, an analog amplifier or a so-called switched capacitor amplifier may be used. Also, the column amplifier 30 may not necessarily be provided.

For the sake of drawing notation, M=2 is shown in FIG. 2, but the number of columns M is actually a larger arbitrary number. Also, the number of lines N is not limited. When the pixel blocks BL are distinguished row by row, the pixel block BL of the j-th row is indicated by the symbol BL(j). This point also applies to other elements and control signals to be described later. FIGS. 2 and 3 show pixel blocks BL(n−1) to BL(n+1) on the n−1th to n+1th rows over three rows.

In the drawings, the pixels on the lower side in FIGS. 2 and 3 of the pixel block BL are denoted by PXA, and the pixels on the upper side in FIGS. 2 and 3 are denoted by PXB. When the explanation is made without distinguishing between them, the reference numeral PX may be attached to both. In the drawings, the photodiode of the pixel PXA is denoted by PDA, and the photodiode of the pixel PXB is denoted by PDB. may explain. Similarly, the transfer transistor of the pixel PXA is denoted by TXA, and the transfer transistor of the pixel PXB is denoted by TXB. Sometimes. In this embodiment, the photodiodes PD of the pixel PX are arranged in a two-dimensional matrix with 2N rows and M columns.

In the present embodiment, each pixel PX includes a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges according to incident light, and a transfer transistor as a transfer switch that transfers charges from the photodiode PD to the node P. TX.

In the present embodiment, the plurality of pixels PX form a pixel block BL for every two pixels PX (PXA, PXB) in which the photodiodes PD are arranged sequentially in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, two pixels PX (PXA, PXB) belonging to the pixel block BL are connected to one set of nodes P, amplification transistor AMP, reset transistor RST, and selection transistor RST. They share the transistor SEL. A capacitor (charge-voltage conversion capacitor) is formed between the node P and a reference potential, and the charge transferred to the node P is converted into a voltage by the capacitor. The amplification transistor AMP constitutes an amplification section that outputs a signal corresponding to the potential of the node P. FIG. The reset transistor RST constitutes a reset switch that resets the potential of the node P. The selection transistor SEL constitutes a selection section for selecting the pixel block BL. A photodiode PD and a transfer transistor TX are provided for each pixel PX without being shared by two pixels PX (PXA, PXB). In FIGS. 2 and 3, n indicates the row of the pixel block BL. For example, the pixels PX (PXA) of the first row and the pixels PX (PXB) of the second row constitute the pixel block BL of the first row, and the pixels PX (PXA) of the third row and the pixels PX of the fourth row are formed. (PXB) constitute the pixel block BL of the second row.

Note that, in the present invention, for example, the pixel block BL may be configured for each of three or more pixels PX in which the photodiodes PD are arranged sequentially in the column direction.

Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light of different color components are arranged in a predetermined color arrangement on the light incident side of the photodiode PD of each pixel PX. (for example, Bayer array). The pixel PX outputs an electric signal corresponding to each color through color separation by a color filter.

An electrical connection path provided between a node P of one pixel block BL and a node P of the other pixel block BL for each two pixel blocks BL that are adjacent to each other in the column direction of each pixel block BL. Two connection transistors SWa, SWb as two connection switches are provided in series in a connection path (connection) which is a (connection) between them. Thus, in the present embodiment, the nodes P of three or more pixel blocks BL are connected in a daisy chain by the plurality of connection paths (connection portions). Of these two connecting transistors SWa and SWb, the connecting transistor SWa is arranged on the node P side of the pixel block BL on the lower side in FIGS. and the node P side of the upper pixel block BL in FIG.

For example, an electrical connection path between the node P(n) of the n-th pixel block BL(n) and the node P(n+1) of the n+1-th pixel block BL, and a unique connection path therebetween. Two connecting transistors SWa(n) and SWb(n) are provided in series therein. As shown in FIG. 4, the connection transistor SWa(n) is formed within the region of the pixel block BL(n), while the connection transistor SWb(n) is formed within the region of the pixel block BL(n+1). However, these connecting transistors SWa(n) and SWb(n) are given the same (n) at the end of their reference numerals to indicate that they are provided in series in the same unique connection path. . In the present invention, three or more connecting switches may be provided in series in each specific connection path. Preferably, two coupling transistors SWa, SWb are provided in series in the path.

2 and 3, VDD is the power supply potential. In this embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWa, and SWb are all nMOS transistors.

Gates of the transfer transistors TXA are commonly connected to the control line 26 for each row, and the control signal φTXA is supplied thereto from the vertical scanning circuit 21 . Gates of the transfer transistors TXB are commonly connected to the control line 25 for each row, and a control signal φTXB is supplied thereto from the vertical scanning circuit 21 . Gates of the reset transistors RST are commonly connected to the control line 24 for each row, and the control signal φRST is supplied thereto from the vertical scanning circuit 21 . The gates of the select transistors SEL are connected in common to the control line 23 for each row, to which the control signal φSEL is supplied from the vertical scanning circuit 21 . The gates of the connection transistors SWa are commonly connected to the control line 22 for each row, to which the control signal φSWa is supplied from the vertical scanning circuit 21 . The gates of the connection transistors SWb are commonly connected to the control line 27 for each row, to which the control signal φSWb is supplied from the vertical scanning circuit 21 . For example, a control signal φTXA(n) is supplied to the gate of the transfer transistor TXA(n), a control signal φTXB(n) is supplied to the gate of the transfer transistor TXB(n), and a gate of the reset transistor RST(n) is supplied. is supplied with the control signal φRST(n), the gate of the selection transistor SEL(n) is supplied with the control signal φSEL(n), and the gate of the connection transistor SWa(n) is supplied with the control signal φSWa(n). A control signal φSWb(n) is supplied to the gate of the connection transistor SWb(n).

Each of the transistors TXA, TXB, RST, SEL, SWa, and SWb turns on when the corresponding control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb are at high level (H), and turns on when they are at low level (L). turn off.

The vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb for each row of the pixel block BL under the control of the imaging control unit 5 shown in FIG. It controls the transistors SWa and SWb to realize a still image reading operation, a moving image reading operation, and the like. In this control, a readout operation in each operation mode, which will be described later, is performed according to, for example, the set value of the ISO sensitivity. By this control, each vertical signal line 28 is supplied with the signal (analog signal) of the pixel PX in the corresponding column.

In the present embodiment, the vertical scanning circuit 21 constitutes a control section that switches operation modes, which will be described later, according to commands (control signals) from the imaging control section 5 in FIG.

A signal read out to the vertical signal line 28 is amplified by the column amplifier 30 for each column and further converted into a light signal (a signal containing light information photoelectrically converted by the pixel PX) and a dark signal (a light signal) by the CDS circuit 31 . After being subjected to processing to obtain a difference from the difference signal containing noise components to be subtracted from the signal), it is converted into a digital signal by the A/D converter 32, and the digital signal is held in the A/D converter 32. be done. The digital image signal held in each A/D converter 32 is horizontally scanned by a horizontal reading circuit 33, converted into a predetermined signal format as necessary, and sent to an external device (the digital signal processing unit 6 in FIG. 1). ).

The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 shown in FIG. The output signal is sampled as a dark signal, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 shown in FIG. sample as Then, the CDS circuit 31 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clocks and pulses from the timing generation circuit. A known configuration can be adopted as the configuration of such a CDS circuit 31 .

Here, the structure of the pixel block BL will be described with reference to FIGS. 4 and 5. FIG. In practice, a color filter, a microlens, and the like are arranged above the photodiode PD, but they are omitted in FIGS. 4 and 5, layouts of power supply lines, ground lines, control lines 22 to 27, etc. are omitted.

In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and each element in the pixel block BL such as the photodiode PD is arranged in the P-type well. there is In FIG. 5, reference numerals 41 to 49 denote N-type impurity diffusion regions that are part of each transistor described above. Numerals 61 to 67 are gate electrodes of respective transistors made of polysilicon. The diffusion regions 42 and 45 are regions to which a power supply voltage VDD is applied by a power supply line (not shown).

The photodiodes PDA(n) and PDB(n) are composed of an N-type charge accumulation layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) arranged on the surface side thereof. not shown). The photodiodes PDA(n) and PDB(n) photoelectrically convert incident light and store the generated charges in their charge storage layers.

The transfer transistor TXA(n) is an nMOS transistor having the charge storage layer of the photodiode PDA(n) as the source, the diffusion region 41 as the drain, and the gate electrode 61 as the gate. The transfer transistor TXB(n) is an nMOS transistor having the charge storage layer of the photodiode PDB(n) as the source, the diffusion region 41 as the drain, and the gate electrode 62 as the gate. Diffusion region 41 is provided between photodiode PDA(n) and photodiode PDB(n). The diffusion region 41 is also used as a diffusion region serving as the drain of the transfer transistor TXA(n) and as a diffusion region serving as the drain of the transfer transistor TXB(n). The gate electrode 61 of the transfer transistor TXA(n) is arranged on the photodiode PDA(n) side of the diffusion region 41 . The gate electrode 62 of the transfer transistor TXB(n) is arranged on the photodiode PDB(n) side of the diffusion region 41 .

The amplification transistor AMP(n) is an nMOS transistor having the diffusion region 42 as the drain, the diffusion region 43 as the source, and the gate electrode 63 as the gate. The selection transistor SEL(n) is an nMOS transistor having the diffusion region 43 as the drain, the diffusion region 44 as the source, and the gate electrode 64 as the gate. Diffusion region 44 is connected to vertical signal line 28 . The reset transistor RST(n) is an nMOS transistor having the diffusion region 45 as the drain, the diffusion region 46 as the source, and the gate electrode 65 as the gate.

The connection transistor SWa(n) is an nMOS transistor having the diffusion region 46 as the source, the diffusion region 47 as the drain, and the gate electrode 66 as the gate. The connection transistor SWb(n−1) is an nMOS transistor having the diffusion region 48 as the drain, the diffusion region 49 as the source, and the gate electrode 67 as the gate.

The gate electrode 63 and the diffusion regions 41 and 46 of the pixel block BL(n) and the diffusion region 48 of the connection transistor SWb(n-1) are electrically connected to each other by a wiring 71(n) to be conductive. In this embodiment, the node P(n) corresponds to the wiring 71(n) and the entire portion that is electrically connected to and conducts with it.

The structure of the pixel blocks BL other than the n-th row is also the same as the structure of the n-th pixel block BL(n) described above. The structure of the connection transistor SWa other than the connection transistor SWa(n) is also the same as the structure of the connection transistor SWa(n) described above. The structure of the connection transistor SWb other than the connection transistor SWb(n) is also the same as the structure of the connection transistor SWb(n) described above.

For the two connection transistors SWa and SWb provided in series in each unique connection path, a wiring 72 connects between the diffusion region 47 of the connection transistor SWa and the diffusion region 49 of the connection transistor SWb. It is For example, the diffusion region 47 of the coupling transistor SWa(n-1) and the diffusion region 49 of the coupling transistor SWb(n-1) are electrically connected by the wiring 72(n-1). A wiring 72(n-1) serves as a connection portion between the connection transistors SWa(n-1) and SWb(n-1) when the connection transistors SWa(n-1) and SWb(n-1) are off. Configure. A wiring 72(n) electrically connects the diffusion region 47 of the coupling transistor SWa(n) and the diffusion region 49 of the coupling transistor SWb(n). The wiring 72(n) constitutes a connection portion between the connection transistors SWa(n) and SWb(n) when the connection transistors SWa(n) and SWb(n) are off.

Here, as shown in FIG. 4, the positional deviation amount in the column direction between the two connecting transistors SWa and SWb provided in series in each unique connection path is Ls, and the column direction of the photodiode PD is Ls. Let Pg be the pitch of . Although the relationship between the pitch Pg and the positional deviation Ls is not limited in the present invention, it is preferable that pg<Ls<2×Pg in order to reduce the capacitance value Cfd1 of the capacitor CA, which will be described later. In the present embodiment, for example, the connection transistor SWb(n−1) is arranged in the vicinity of the connection transistor SWa(n), and the positional deviation amount Ls is set to be slightly less than 2×Pg. (n) is made as short as possible, and a capacitance value Cfd1 of a capacitor CA(n), which will be described later, is made as small as possible.

2 to 5, CA(n) is the capacitance between the node P(n) and the reference potential when the coupling transistors SWa(n) and SWb(n-1) are off. Let Cfd1 be the capacitance value of the capacitor CA(n). CB(n) represents the capacitance between the wiring 72(n) and the reference potential when the coupling transistors SWa(n) and SWb(n) are off. Let Cfd2 be the capacitance value of the capacitor CB(n). These points are the same for rows of other pixel blocks BL.

The capacitance CA(n) is the capacitance of the drain diffusion regions 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region 46 of the reset transistor RST(n), and the source of the connection transistor SWa(n). It is composed of the capacitance of the diffusion region 46, the capacitance of the drain diffusion region 48 of the coupling transistor SWb(n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n). , is the capacitance value Cfd1 of the capacitance CA(n). This point is the same for the rows of other pixel blocks BL.

Here, let Csw be both the value of the channel capacitance when the coupling transistor SWa is on and the value of the channel capacitance when the coupling transistor SWb is on. Normally, the capacitance value Csw is a value smaller than the capacitance values Cfd1 and Cfd2.

Now, focusing on the pixel block BL(n), both the connection transistors SWa(n) and SWb(n−1) are turned off (that is, the connection transistors SWa and SWb that are in the ON state are the nodes). P(n) is not electrically connected to the node P(n), and the connection path provided with the coupling transistors SWa and SWb is not electrically connected to the node P(n). , the capacitance (charge-voltage conversion capacitance) between the node P(n) and the reference potential is the capacitance CA(n). Therefore, the capacitance value of the charge-voltage conversion capacitor of node P(n) is Cfd1. This state corresponds to the state of period T2 in FIG. 6 showing the first operation mode described later.

Focusing on the pixel block BL(n), when the connection transistor SWa(n) is turned on, the ON-state connection transistors of the connection transistors SWa and SWb other than the connection transistor SWa(n) are connected to the node P(n). (here, specifically, if coupling transistors SWb(n−1) and SWb(n) are off), node P(n) and reference The capacitance (charge-voltage conversion capacitance) between the potential and the potential is the capacitance CA(n) plus the capacitance CB(n) and the channel capacitance when the coupling transistor SWa(n) is on. Therefore, the capacitance value of the charge-voltage conversion capacitor at node P(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2. This state corresponds to the state of period T2 in FIG. 7 showing the 2A operation mode described later.

Further, focusing on the pixel block BL(n), when both the connection transistors SWa(n) and SWb(n) are turned on, the connection transistors SWa and SWb other than the connection transistors SWa(n) and SWb(n) are turned on. are electrically connected to the node P(n) (here, specifically, the connection transistors SWb(n−1) and SWa(n+1) are turned off). ), the charge-voltage conversion capacitance of the node P(n) is the capacitance CA(n), the capacitance CB(n), the on-channel capacitances of the coupling transistors SWa(n) and SWb(n), and It is obtained by adding a capacitance CA(n+1). Therefore, the capacitance value of the charge-voltage conversion capacitor of the node P(n) is 2*Cfd1+Cfd2+2*Csw≈2*Cfd1+Cfd2. This state corresponds to the state of period T2 in FIG. 8 showing the 2B operation mode described later.

Thus, if there is no ON-state connecting transistor electrically connected to the node P(n) among the connecting transistors SWa and SWb, the capacitance value of the charge-voltage conversion capacitor at the node P(n) is the minimum. As a result, the charge-voltage conversion coefficient becomes large due to the charge-voltage conversion capacity, so that reading with the highest SN ratio becomes possible.

On the other hand, if the number of ON-state connecting transistors electrically connected to the node P(n) among the connecting transistors SWa and SWb is increased to a desired number of one or more, the node P(n) Since the capacitance value of the charge-voltage conversion capacitor can be increased to a desired value and a large amount of signal charge can be handled, the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

Although the node P(n) of the pixel block BL(n) has been described above, the same applies to the node P of the other pixel blocks BL.

FIG. 6 is a timing chart showing the first operation mode of the solid-state imaging device 4 shown in FIG. In this first operation mode, each pixel block BL is sequentially selected row by row, and the ON state in which the pixel block BL is electrically connected to the node P of the pixel block BL selected from among the connecting transistors SWa and SWb is selected. , the transfer transistors TXA and TXB of the selected pixel block BL are sequentially selectively turned on in a state in which there is no connecting transistor (a state in which the charge-voltage conversion capacity of the node P is minimum), and the selected pixel block BL This is an example of the operation of sequentially reading the signals of the photodiodes PDA and PDB in each row. In the example shown in FIG. 6, the signals of all the pixels PXA and PXB are read, but the present invention is not limited to this. This point is the same for each example shown in FIGS. 7 and 8, which will be described later.

In FIG. 6, the pixel block BL(n-1) on the n-1th row is selected during the period T1, the pixel block BL(n) on the n-th row is selected during the period T2, and the pixels on the n+1th row are selected during the period T3. A situation is shown in which the block BL(n+1) is being selected. Since the operation is the same when the pixel block BL of any row is selected, only the operation when the pixel block BL(n) of the n-th row is selected will be described here.

The exposure of the photodiodes PDA(n) and PDB(n) is already completed in the predetermined exposure period before the period T2 starts. This exposure is performed by a mechanical shutter (not shown) after a so-called global reset that simultaneously resets all pixels during normal shooting (still image shooting). , a so-called rolling electronic shutter operation. All the transistors SEL, RST, TXA, TXB, SWa, and SWb are off immediately before the start of the period T2.

In the period T2, φSEL(n) of the n-th row is set to H, the selection transistor SEL(n) of the pixel block BL(n) of the n-th row is turned on, and the pixel block BL(n) of the n-th row is turned on. selected.

Also, in the period T2, φSWa(n) and φSWb(n−1) are set to L, and the coupling transistors SWa(n) and SWb(n−1) are turned off. As a result, in the period T2, there is no ON-state connecting transistor electrically connected to the node P(n) of the selected pixel block BL(n) among the connecting transistors SWa and SWb. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor at node P(n) is Cfd1, which is the minimum.

Immediately after the start of the period T2, φRST(n) is set to H for a certain period of time, the reset transistor RST(n) of the n-th row is once turned on, and the potential of the node P(n) is once reset to the power supply potential VDD. be.

During the period T2, the dark signal sampling signal φDARKC is set to H for a certain period from time t1, and the potential appearing at the node P(n) is amplified by the amplification transistor AMP(n) of the n-th row, and then the selection transistor A signal amplified by the column amplifier 30 via SEL(n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

φTXA(n) is set to H and the n-th row transfer transistor TXA(n) is turned on for a certain period from time t2 after that during the period T2. As a result, the signal charge accumulated in the photodiode PDA(n) of the n-th pixel block BL(n) is transferred to the charge-voltage conversion capacitor of the node P(n). Excluding noise components, the potential of node P(n) has a value proportional to the amount of signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of node P(n).

At time t3 after that during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P(n) is amplified by the amplification transistor AMP(n) of the n-th row and then the selection transistor SEL(n). ) and the vertical signal line 28 and further amplified by the column amplifier 30 are sampled by the CDS circuit 31 as optical signals.

After that, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled for a certain period from time t1 and the light signal sampled for a certain period from time t3. . The A/D converter 32 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A/D converter 32 is horizontally scanned by a horizontal reading circuit 33 and output as a digital image signal to the outside (the digital signal processing unit 6 in FIG. 1).

Then, φRST(n) is set to H for a certain period from time t4 in period T2, the reset transistor RST(n) of the n-th row is once turned on, and the potential of the node P(n) is temporarily changed to the power supply potential VDD. reset to

The dark signal sampling signal φDARKC is set to H for a certain period from time t5 after that during the period T2, and the potential appearing at the node P(n) is amplified by the amplification transistor AMP(n) of the n-th row, and then the selection transistor A signal amplified by the column amplifier 30 via SEL(n) and the vertical signal line 28 is sampled by the CDS circuit 31 as a dark signal.

φTXB(n) is set to H and the n-th row transfer transistor TXB(n) is turned on for a certain period from time t6 after that during the period T2. As a result, the signal charge accumulated in the photodiode PDB(n) of the n-th pixel block BL(n) is transferred to the charge-voltage conversion capacitor of the node P(n). Excluding noise components, the potential of node P(n) has a value proportional to the amount of signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitor of node P(n).

At time t7 after that during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P(n) is amplified by the amplification transistor AMP(n) of the n-th row and then selected by the selection transistor SEL(n). ) and the vertical signal line 28 and further amplified by the column amplifier 30 are sampled by the CDS circuit 31 as optical signals.

After that, after φSIGC becomes L, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled for a certain period from time t5 and the light signal sampled for a certain period from time t7. . The A/D converter 32 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A/D converter 32 is horizontally scanned by a horizontal reading circuit 33 and output as a digital image signal to the outside (the digital signal processing unit 6 in FIG. 1).

As described above, in the first operation mode, there is no ON-state connecting transistor electrically connected to the node P of the selected pixel block BL among the connecting transistors SWa and SWb. Since the capacitance value of the charge-voltage conversion capacitor of the node P of the pixel block BL is minimized and the charge-voltage conversion coefficient of the charge-voltage conversion capacitor is increased, reading with the highest SN ratio is possible. For example, when the set value of the ISO sensitivity is the highest, the imaging control section 5 instructs to perform the first operation mode.

FIG. 7 is a timing chart showing the 2A operation mode of the solid-state imaging device 4 shown in FIG. A second A mode of operation is one of the second modes of operation. In this second operation mode, each pixel block BL is sequentially selected row by row, and one or more predetermined number of ON-state connection transistors among the connection transistors SWa and SWb are connected to the selected pixel block. While being electrically connected to the node P of BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence to turn on the photodiodes PDA and PDB of the selected pixel block BL. This is an example of the operation of sequentially reading out the signals of . The 2A operation mode is an example of operation in which the predetermined number is set to 1 in the second operation mode.

In FIG. 7, similarly to FIG. 6, the pixel block BL(n-1) in the n-1 row is selected in the period T1, the pixel block BL(n) in the n-th row is selected in the period T2, and the pixel block BL(n) in the n-th row is selected in the period T3. , the pixel block BL(n+1) on the n+1-th row is being selected. The difference between the 2A operation mode shown in FIG. 7 and the first operation mode shown in FIG. 6 is described below.

In the 2A operation mode shown in FIG. 7, φSWa(n) is set to H and φSWb(n−1) is set to L during the period T2 in which the n-th pixel block BL(n) is selected. The connection transistor SWa(n) is turned on and the connection transistor SWb(n-1) is turned off. As a result, in the period T2, one of the connection transistors SWa and SWb in the ON state (here, the connection transistor SWa(n)) is connected to the node P(n) of the selected pixel block BL(n). ) are electrically connected to each other. Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor at node P(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is one step higher than in the first operation mode shown in FIG.

Although the period T2 in which the n-th pixel block BL(n) is selected has been described here, the same applies to the periods in which other pixel blocks BL are selected.

Thus, in the 2A operation mode, one of the connecting transistors SWa and SWb, which is in the ON state, is electrically connected to the node P of the selected pixel block BL. The capacitance value of the charge-voltage conversion capacitor at the node P of the selected pixel block BL is increased by one step, and the number of saturated electrons at the charge-voltage conversion capacitor at the node P can be increased by one step. As a result, the dynamic range can be expanded by one step. For example, when the set value of the ISO sensitivity is one step lower than the highest value, the imaging control section 5 instructs to perform the 2A operation mode.

FIG. 8 is a timing chart showing the 2B operation mode of the solid-state imaging device 4 shown in FIG. The 2B operation mode is another one of the second operation modes, and is an operation example in which the predetermined number is two.

In FIG. 8, similarly to FIGS. 6 and 7, the pixel block BL(n-1) on the n-1th row is selected during the period T1, and the pixel block BL(n) on the n-th row is selected during the period T2. , the n+1-th row pixel block BL(n+1) is being selected in the period T3. 8 differs from the first operation mode shown in FIG. 6 and the operation mode 2A shown in FIG. 7 in the following points.

In the 2B operation mode shown in FIG. 8, φSWa(n) and φSWb(n) are set to H and φSWb(n−1) is set to H during the period T2 in which the n-th pixel block BL(n) is selected. , φSWa(n+1) are set to L, the coupling transistors SWa(n) and SWb(n) are turned on, and the coupling transistors SWb(n−1) and SWa(n+1) are turned off. As a result, in the period T2, two of the connection transistors SWa and SWb in the ON state (here, the connection transistors SWa(n) and SWb(n)) are connected to the selected pixel block BL(n). are electrically connected to the node P(n) of . Therefore, as described above, the capacitance value of the charge-voltage conversion capacitor at node P(n) is 2*Cfd1+Cfd2+2Csw≈2*Cfd1+Cfd2, which is two steps higher than in the first operation mode shown in FIG.

Although the period T2 in which the n-th pixel block BL(n) is selected has been described here, the same applies to the periods in which other pixel blocks BL are selected.

As described above, in the 2B operation mode, two of the connection transistors SWa and SWb in the ON state are electrically connected to the node P of the selected pixel block BL. The capacitance value of the charge-voltage conversion capacitor at the node P of the selected pixel block BL is increased by two steps, and the number of saturated electrons at the charge-voltage conversion capacitor at the node P can be increased by two steps. Thereby, the dynamic range can be expanded by two steps. For example, when the set value of the ISO sensitivity is two steps smaller than the highest value, the imaging control unit 5 instructs to perform the second B operation mode.

In addition, in the second operation mode, the predetermined number may be three or more.

Here, a solid-state imaging device according to a comparative example to be compared with the solid-state imaging device 4 in the present embodiment will be described. FIG. 9 is a circuit diagram showing the vicinity of three pixel blocks BL of the solid-state imaging device according to this comparative example, and corresponds to FIG. 10 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 9, and corresponds to FIGS. 4 and 5. FIG. In FIGS. 9 and 10, elements that are the same as or correspond to elements in FIGS. 3, 4 and 5 are denoted by the same reference numerals, and overlapping descriptions thereof will be omitted. In FIG. 10, diffusion regions and gate electrodes are not denoted by reference numerals, but the reference numerals thereof are the same as in FIG. 5, so please refer to FIG.

The difference between this comparative example and the present embodiment is that each connecting transistor SWb is removed, and the removed connecting transistor SWb is short-circuited by a wire 171 including the wires 71 and 72. . For example, in the present embodiment, the connection transistor SWb(n-1) is removed, and the gate electrode of the pixel block BL(n) is connected to the gate electrode of the pixel block BL(n) by the wiring 171(n) including the wirings 71(n) and 72(n-1). 63, the diffusion regions 41 and 46, and the diffusion region 47 of the connecting transistor SWa(n-1) are electrically connected to each other to conduct.

9 and 10, CAB(n) is the capacitance between the node P(n) and the reference potential when the coupling transistors SWa(n) and SWa(n-1) are off. Let Cfd be the capacitance value of the capacitor CAB(n). These points are the same for rows of other pixel blocks BL.

The capacitance CAB(n) is the capacitance of the drain diffusion regions 41 of the transfer transistors TXA(n) and TXB(n), the source diffusion region 46 of the reset transistor RST(n), and the source diffusion region of the connection transistor SWa(n). 46, the capacitance of the drain diffusion region 47 of the coupling transistor SWa(n−1), the capacitance of the gate electrode 63 of the amplification transistor AMP(n), and the wiring capacitance of the wiring 171(n). The sum of the values becomes the capacitance value Cfd of the capacitance CAB(n). This point is the same for the rows of other pixel blocks BL.

The wiring capacitance of the wiring 171(n) is substantially equal to the sum of the wiring capacitance (stray capacitance) of the wiring 71(n) and the wiring capacitance of the wiring 171(n). Therefore, the capacitance value Cfd of the capacitance CAB(n) is approximately equal to the sum of the capacitance value Cfd1 of the capacitance CA(n) and the capacitance value Cfd2 of the capacitance CB(n) described above in this embodiment, and Cfd≈Cfd1+Cfd2 becomes.

In this comparative example, focusing on the pixel block BL(n), when both the connection transistors SWa(n) and SWa(n−1) are turned off, the charge-voltage conversion capacitance of the node P(n) is changed to the capacitance CAB( n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the node P(n) becomes Cfd, which is the minimum in the comparative example, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitance increases. can be read out.

In this comparative example, focusing on the pixel block BL(n), one or more predetermined number of ON-state connecting transistors among the connecting transistors SWa are electrically connected to the node P(n). In this state, the capacitance value of the charge-voltage conversion capacitor of the node P(n) increases according to the number of the connecting transistors in the ON state, and the number of saturated electrons can be increased. Thereby, the dynamic range can be expanded.

However, in this comparative example, the capacitance value of the charge-voltage conversion capacitor at node P(n) cannot be made smaller than Cfd≈Cfd1+Cfd2. Therefore, according to this comparative example, the charge-to-voltage conversion coefficient cannot be increased so much, and reading with a very high SN ratio is not possible.

In contrast, according to the present embodiment, since the coupling transistor SWb is added, the minimum capacitance value of the charge-voltage conversion capacitance of the node P(n) is set to Cfd1≈Cfd−Cfd2, as described above. and can be made smaller than the comparative example.

Therefore, according to the present embodiment, it is possible to expand the dynamic range and improve the SN ratio during high-sensitivity readout as compared with the comparative example.

In this embodiment, the connection transistors SWa and SWb are provided between all two nodes P that are adjacent in the column direction, but the present invention is not necessarily limited to this. For example, between every q (q is an integer equal to or greater than 2) nodes P arranged in the column direction and the node P adjacent to the node P on the lower side in the drawing, the connection transistors SWa and SWb are not provided. You may leave the space open all the time. In this case, the smaller the number of q, the smaller the maximum number of the predetermined number in the second operation mode. ratio can be improved.

Note that each operation example described with reference to FIGS. 6 to 8 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing it with the signal charge of the photodiode PD of another pixel PX. Met. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed with the signal charge of the photodiode PD of another pixel PX of the same color and read out.

For example, connecting transistors SWa(n-1), SWb(n-1), SWa(n), SWb(n) are turned on to connect nodes P(n-1), P(n), P(n+1) to each other. When connected and TXA(n−1), TXA(n), TXA(n+1) are turned on at the same time, three pixels PXA(n−1), PXA(n) of the same color assuming a Bayer array, etc. , PXA(n-1) of photodiodes PDA(n-1), PDA(n), PDA(n-1) are connected to nodes P(n-1), P(n), P It is averaged by (n+1), and the same-color 3-pixel mixed readout function can be realized. At this time, the connection transistors SWb(n-2) and SWa(n+1) are turned off, and the on-state connection electrically connected to the nodes P(n-1), P(n) and P(n+1). By minimizing the number of transistors, the charge-to-voltage conversion capacitance value at the connected nodes P(n-1), P(n), P(n+1) is minimized, and the same-color 3-pixel mixture is achieved with the highest signal-to-noise ratio. Reads can be performed. On the other hand, in addition to the connection transistors SWa(n−1), SWb(n−1), SWa(n), and SWb(n), one or more ON-state connection transistors are connected to the nodes P(n−1), P (n), P(n+1), the charge at the connected nodes P(n-1), P(n), P(n+1) The voltage conversion capacitance value is increased, and the dynamic range of same-color three-pixel mixed readout can be expanded.

[Second embodiment]
FIG. 11 is a circuit diagram showing the vicinity of three pixel blocks BL of the solid-state imaging device of the electronic camera according to the second embodiment of the invention, and corresponds to FIG. 12 is a schematic plan view schematically showing the vicinity of the three pixel blocks BL shown in FIG. 9, and corresponds to FIGS. 4 and 5. FIG. 11 and 12, elements that are the same as or correspond to elements in FIGS. 3, 4 and 5 are denoted by the same reference numerals, and redundant description thereof will be omitted.

This embodiment differs from the first embodiment in that each wiring 72 is added with an adjustment capacitor CB' having a capacitance value Cfd3. Since the capacitance CB(n) is the capacitance between the wiring 72(n) and the reference potential when the coupling transistors SWa(n) and SWb(n) are off, the adjustment capacitance CB'(n) is is also included in the capacitance CB(n), the adjustment capacitance CB' has a capacitance value Cfd3 added to the capacitance value Cfd2 of the capacitance CB(n) in the first embodiment. 11 and 12 show the adjustment capacitor CB' separately from the capacitor CB(n) in order to clarify that it is a component. While the capacitance value of the capacitor CB(n) is Cfd2 in the first embodiment, the capacitance value of the capacitor CB(n) is Cfd2+Cfd3 in the present embodiment. These points are the same for the other capacitor CB, the wiring 72, and the adjustment capacitor CB'.

According to the present embodiment, the same advantages as those of the first embodiment can be obtained. In addition, by providing the adjustment capacitor CB′, the capacitance value of the capacitor CB can be set to any desired capacitance value. can.

Specifically, for example, (i) the width of at least a part of the wiring width of the wiring 72 is made wider than the wiring width of other wirings in the pixel block BL, so that the area of the wiring 72 is reduced. (ii) connecting a MOS capacitor to the wiring 72; (iii) connecting a diffusion capacitor that does not constitute the connecting transistors SWa and SWb; (iv) making the area of the drain diffusion region 47 of the coupling transistor SWa larger than the area of the drain diffusion region 47 in the first embodiment; It can be configured by one or a combination of two or more of: making the area larger than the area of the source diffusion region 49 in one embodiment.

An example of setting the capacitance value Cfd3 of the adjustment capacitor CB' will now be described. It is desirable that the capacitance value of the charge-voltage conversion capacitor at node P be an integral multiple of the reference capacitance value. However, in the structure of the first embodiment described above, when the adjustment capacitor CB' is not added, the capacitance value Cfd2 of the capacitor CB is generally smaller than the capacitance value Cfd1 of the capacitor CA. Therefore, for example, in order to make the capacitance value of the charge-voltage conversion capacitance of the node P(n) twice the reference capacitance value, the connection transistors SWa(n) and SWb(n) are turned on to turn on the node P(n). ) is set to 2*Cfd1+Cfd2+2*Csw, and two pixel blocks BL(n) and BL(n+1) are used.

On the other hand, in the present embodiment, if the adjustment capacitor CB' is formed so that the capacitance value Cfd3 of the adjustment capacitor CB' is Cfd1-Cfd2, the capacitance value of the capacitor CB is cfd2+Cfd3=Cfd1. Therefore, in order to make the capacitance value of the charge-voltage conversion capacitance of the node P(n) twice the reference capacitance value, it is enough to turn on the connection transistor SWa(n), and one pixel block BL(n) just use . Also, when dealing with a larger saturated charge amount, the number of connected pixel blocks BL can be greatly reduced.

This setting example of the capacitance value Cfd3 of the adjustment capacitor CB' is merely an example, and is not limited to this.

In order to bring the capacitance value of the charge-voltage conversion capacitor at the node P closer to an integral multiple of the reference dose value, the capacitance value of the capacitance CB should be within a range of ±20% of the capacitance value of the capacitance CA. is preferable, and a value within a range of ±10% with respect to the capacitance value of the capacitor CA is more preferable.

[Third embodiment]
FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device 84 of an electronic camera according to the third embodiment of the invention, and corresponds to FIG. In FIG. 13, elements that are the same as or correspond to elements in FIG. 2 are denoted by the same reference numerals, and overlapping descriptions thereof will be omitted.

This embodiment differs from the first embodiment in that the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL in the first embodiment. The point is that the pixel block BL is the pixel PXA. However, in this embodiment, the density in the column direction of the photodiodes PDA is double the density in the column direction of the photodiodes PDA in the first embodiment. The density in the column direction of the entire PDA and PDB is the same. In this embodiment, n indicates the row of the pixel block BL and the row of the pixel PXA.

In other words, each pixel block BL is composed of two pixels PX (PXA, PXB) in the first embodiment, whereas each pixel block BL is composed of one pixel block BL in the present embodiment. of pixels PX (PXA). In the first embodiment, two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of nodes P, amplification transistor AMP, reset transistor RST, and selection transistor SEL. In contrast, in the present embodiment, each pixel PX (only PXA in the present embodiment) has a set of nodes P, amplification transistor AMP, reset transistor RST, and selection transistor SEL.

Basically, the description of the first embodiment is compatible with the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment is omitted here.

This embodiment also provides advantages similar to those of the first embodiment.

In addition, in the present invention, the same modification as the present embodiment obtained by modifying the first embodiment may be applied to the second embodiment.

[Fourth embodiment]
FIG. 14 is a circuit diagram showing a schematic configuration of a solid-state imaging device 94 of an electronic camera according to the fourth embodiment of the invention, and corresponds to FIG. FIG. 15 is an enlarged circuit diagram showing the vicinity of four pixel blocks BL sequentially arranged in the column direction in FIG. 14, and corresponds to FIG. In FIGS. 14 and 15, elements that are the same as or correspond to elements in FIGS. 2 and 3 are denoted by the same reference numerals, and overlapping descriptions thereof will be omitted. This embodiment differs from the first embodiment in the following points.

In this embodiment, the first connection transistor SWa, the second connection transistor SWb, and the wirings 71 and 72 in the first embodiment are removed, and instead, the first node Pa and the corresponding node Pa are provided. a first transistor SWA as a first switch unit for electrically connecting and disconnecting between two second nodes Pb, and a second switch for electrically connecting and disconnecting between two second nodes Pb. A second transistor SWB as a unit and wirings 97 and 98 are provided.

The first node Pa(n) of the pixel block BL(n) corresponds to the node P(n) in the first embodiment. Transfer transistor TXA(n) transfers charge from photodiode PDA(n) to first node Pa(n), and transfer transistor TXB(n) transfers charge from photodiode PDB(n) to first node Pa(n). ). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa(n) and a reference potential, and the capacitance converts the charge transferred to the first node Pa(n) into a voltage. be. The amplification transistor AMP(n) outputs a signal corresponding to the potential of the first node Pa(n). The reset transistor RST(n) resets the potential of the first node Pa(n). These points are the same for rows of other pixel blocks BL.

The first transistor SWA(n) constitutes a first switch section that electrically connects and disconnects the first node Pa(n) and the corresponding second node Pb(n). ing. Such a first switch section can be configured by combining switches such as a plurality of transistors. (n) is preferable. These points are the same for other first transistors SWA.

Each second transistor SWB connects a second node Pb corresponding to the first node Pa of one pixel block BL and the other pixel block BL for each two pixel blocks BL adjacent to each other in the column direction. A second switch section is provided to electrically connect and disconnect the second node Pb corresponding to the first node Pa of the pixel block BL. Thus, in the present embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy chain by the plurality of second switch units. The second switch section as described above can be configured by combining switches such as a plurality of transistors. It is preferable to configure with SWB.

For example, the second transistor SWB(n) connects the second node Pb(n) corresponding to the first node Pa(n) of the n-th pixel block BL(n) and the n-1-th pixel block BL(n). It is provided to electrically connect and disconnect the second node Pb(n-1) corresponding to the first node Pa(n-1) of the block BL(n-1). This point is the same for the other second transistor SWB.

The gate electrode of the amplification transistor AMP(n) of the pixel block BL(n), the source region of the reset transistor RST(n), the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), and the first transistor SWA The source diffusion regions of (n) are electrically connected to each other by a wiring 97(n) for conduction. The first node Pa(n) corresponds to the wiring 97(n) and the entire portion electrically connected to it and conducting. These points are the same for rows of other pixel blocks BL.

A wiring 98(n) electrically connects the drain diffusion region of the first transistor SWA(n), the drain diffusion region of the second transistor SWB(n), and the source diffusion region of the second transistor SWB(n+1). are connected and conducting. The second node Pb(n) corresponds to the wiring 98(n) and the entire portion electrically connected to it and conducting. These points are the same for the other first transistor SWA and the other second transistor SWB.

Gates of the first transistors SWA are commonly connected to the control line 95 for each row, and the control signal φSWA is supplied thereto from the vertical scanning circuit 21 . The gates of the second transistors SWB are commonly connected to the control line 96 for each row, to which the control signal φSWB is supplied from the vertical scanning circuit 21 .

14 and 15, CC(n) is the capacitance between the first node Pa(n) and the reference potential when the first transistor SWA(n) is off. Let Cfd1' be the capacitance value of the capacitor CC(n). CD(n) is the capacitance between the wiring 98(n) and the reference potential when the first transistor SWA(n) and the second transistors SWB(n) and SWB(n+1) are off. be. Let Cfd2' be the capacitance value of the capacitance CD(n). These points are the same for the other first transistor SWA and the other second transistor SWB.

The capacitance CC(n) is the capacitance of the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the reset transistor RST(n), and the source of the first transistor SWA(n). It is composed of the capacitance of the diffusion region, the capacitance of the gate electrode of the amplification transistor AMP(n), and the wiring capacitance of the wiring 97(n). Become. This point is the same for the rows of other pixel blocks BL.

Since the capacitance of the source diffusion region of the second transistor SWB(n) is not a component of the capacitance CC(n), the capacitance value Cfd1' of the capacitance CC(n) is reduced accordingly. In this regard, in the first embodiment, not only the capacitance of the source diffusion region 46 of the coupling transistor SWa(n) but also the capacitance of the drain diffusion region 48 of the coupling transistor SWb(n-1) are components of the capacitance CB. Therefore, the capacitance value Cfd1 of the capacitor CB is increased accordingly. That is, the capacitance value Cfd1' in the present embodiment is smaller than the capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance.

Here, the value of the channel capacitance when the first transistor SWA is on and the value of the channel capacitance when the second transistor SWB is on are both Csw. Normally, the capacitance value Csw is a value smaller than the capacitance values Cfd1' and Cfd2'.

Now, focusing on the pixel block BL(n), the first transistor SWA(n) is turned off (that is, the on-state transistor of each of the first transistors SWA and each of the second transistors SWB is the first transistor). is not electrically connected to the node Pa(n) of the first node Pa(n), and the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the capacitance CC(n) becomes. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1'. This state corresponds to the state of period T2 in FIG. 16 showing the first operation mode described later.

Focusing on the pixel block BL(n), when the first transistor SWA(n) is turned on, the first transistor SWA and the second transistor SWB other than the first transistor SWA(n) are turned on. are electrically connected to the first node Pa(n) (here, specifically, the second transistors SWB(n) and SWB(n+1) is off), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the capacitance CD(n) and the first transistor It is obtained by adding the channel capacity when SWA(n) is on. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1'+Cfd2'+Csw≈Cfd1'+Cfd2'. This state corresponds to the state of period T2 in FIG. 17 showing the 2A operation mode described later.

Further, focusing on the pixel block BL(n), when the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, among the first transistor SWA and the second transistor SWB, Unless the transistors in the ON state other than the transistors SWA(n) and SWB(n+1) are electrically connected to the first node Pa(n) (here, specifically, the transistor SWB (n), SWA(n+1), and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) is the capacitance CD(n), It is obtained by adding the capacitance CD(n+1) and the channel capacitance when the transistors SWA(n) and SWB(n+1) are on. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1'+2*Cfd2'+2*Csw≈Cfd1'+2*Cfd2'. This state corresponds to the state of period T2 in FIG. 18 showing the 2B operation mode described later.

Furthermore, focusing on the pixel block BL(n), when the first transistors SWA(n) and SWA(n+1) and the second transistor SWB(n+1) are turned on, each first transistor SWA and each second transistor SWA(n+1) turn on. of the transistors SWB, the transistors other than the transistors SWA(n), SWA(n+1), and SWB(n+1) must be electrically connected to the first node Pa(n). (Here, specifically, if the transistors SWB(n) and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) is, with respect to the capacitance CC(n), It is obtained by adding the capacitance CD(n), the capacitance CD(n+1), the capacitance CC(n+1), and the channel capacitances of the transistors SWA(n), SWA(n+1), and SWB(n+1) when they are on. Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is 2*Cfd1'+2*Cfd2'+3*Csw≈2*Cfd1'+2*Cfd2'. This state corresponds to the state of period T2 in FIG. 19 showing the 2C operation mode described later.

Focusing on the pixel block BL(n), when the first transistor SWA(n) and the second transistors SWB(n+1) and SWB(n+2) are turned on, each first transistor SWA and each second transistor SWA are turned on. Of the transistors SWB, if the transistors other than the transistors SWA(n), SWB(n+1), and SWB(n+2) in the ON state are electrically connected to the first node Pa(n) ( Here, specifically, if the transistors SWA(n+1), SWA(n+2), SWB(n), and SWB(n+3) are off), the charge-voltage conversion capacity of the first node Pa(n) is Add the capacitance CD(n), the capacitance CD(n+1), the capacitance CD(n+2), and the channel capacitances of the transistors SWA(n), SWB(n+1), and SWB(n+2) when they are on to the capacitance CC(n). It will be Therefore, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) is Cfd1'+3*Cfd2'+3*Csw≈Cfd1'+3*Cfd2'. This state corresponds to the state of period T2 in FIG. 20 showing the 2C operation mode described later.

In this way, if there is no ON-state transistor electrically connected to the first node Pa(n) among the first transistors SWA and the second transistors SWB, the first node Pa(n) The capacitance value of the charge-voltage conversion capacitor n) becomes the minimum capacitance value Cfd1′, and the charge-voltage conversion coefficient of the charge-voltage conversion capacitor becomes large, so that reading with the highest SN ratio is possible. As described above, the capacitance value Cfd1′ is smaller than the minimum capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance. Compared to the embodiment, the charge-to-voltage conversion coefficient is further increased, enabling readout with a higher SN ratio.

On the other hand, among each of the first transistors SWA and each of the second transistors SWB, the number of ON-state transistors electrically connected to the first node Pa(n) is increased to a desired number of one or more. As a result, the capacitance value of the charge-voltage conversion capacitor of the first node Pa(n) can be increased to a desired value, and a large amount of signal charge can be handled, so that the number of saturated electrons can be increased. can. Thereby, the dynamic range can be expanded.

Although the first node Pa(n) of the pixel block BL(n) has been described above, the same applies to the first nodes Pa of the other pixel blocks BL.

FIG. 16 is a timing chart showing the first operation mode of solid-state imaging device 94 shown in FIG. In this first operation mode, each pixel block BL is sequentially selected row by row, and each of the first transistor SWA and the second transistor SWB is connected to the first node Pa of the pixel block BL selected. The transfer transistors TXA and TXB of the selected pixel block BL are sequentially selected in a state in which there is no ON-state transistor electrically connected to the pixel block BL (a state in which the charge-voltage conversion capacitance of the first node Pa is minimum). This is an example of the operation of sequentially turning on the photodiodes PDA and PDB of the selected pixel block BL and sequentially reading out the signals of the photodiodes PDA and PDB for each row. In the example shown in FIG. 16, the signals of all pixels PXA and PXB are read out, but the present invention is not limited to this. This point is the same for each example shown in FIGS. 17 to 20, which will be described later.

Since the operation in the first operation mode shown in FIG. 16 is clear from the above description, detailed description thereof will be omitted.

FIG. 17 is a timing chart showing the 2A operation mode of the solid-state imaging device 94 shown in FIG. A second A mode of operation is one of the second modes of operation. In this second operation mode, each pixel block BL is sequentially selected row by row, and a predetermined number of ON-state transistors, which are one or more of each first transistor SWA and each second transistor SWB, are turned on. , in a state of being electrically connected to the first node Pa of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are sequentially selectively turned on, and the selected pixel This is an example of the operation of sequentially reading the signals of the photodiodes PDA and PDB of the block BL row by row. The 2A operation mode is an operation example in which the predetermined number is one (one of the first transistors SWA) in the second operation mode.

Since the operation of the 2A operation mode shown in FIG. 17 is clear from the explanation so far, the detailed explanation thereof is omitted.

FIG. 18 is a timing chart showing the 2B operation mode of the solid-state imaging device 94 shown in FIG. A 2B operation mode is another one of the second operation modes, and the predetermined number is two (one for the first transistor SWA and one for the second transistor SWB). This is an example of operation. Since the operation of the 2B operation mode shown in FIG. 18 is clear from the explanation so far, the detailed explanation thereof is omitted.

FIG. 19 is a timing chart showing the 2C operation mode of the solid-state imaging device 94 shown in FIG. A 2C operation mode is still another one of the second operation modes, and the predetermined number is three (two of the first transistor SWA and one of the second transistor SWB). This is an example of operation. Since the operation in the 2C operation mode shown in FIG. 19 is clear from the above description, detailed description thereof will be omitted.

FIG. 20 is a timing chart showing the 2D operation mode of the solid-state imaging device 94 shown in FIG. A second D operation mode is still another one of the second operation modes, and the predetermined number is three (one of the first transistor SWA and two of the second transistor SWB). This is an example of operation. Since the operation of the 2D operation mode shown in FIG. 20 is clear from the explanation so far, the detailed explanation thereof is omitted.

According to the present embodiment, as in the first embodiment, the dynamic range can be expanded, and the SN ratio during high-sensitivity readout can be improved as compared with the comparative example. Moreover, according to the present embodiment, the charge-voltage conversion coefficient is even greater than in the first embodiment, and high-sensitivity readout at a higher SN ratio is possible.

In the present embodiment, the second transistor SWB is provided between every two second nodes Pb that are sequentially adjacent in the column direction, but the present invention is not necessarily limited to this. For example, between every second node Pb (r is an integer equal to or greater than 2) arranged in the column direction and the second node Pb adjacent to the second node Pb on the lower side in the figure, The gap between them may always be left open without providing the second transistor SWB. In this case, the smaller the number of r, the smaller the maximum number of the predetermined number in the second operation mode. ratio can be improved. Further, for example, between every s (s is an integer equal to or greater than 1) second nodes Pb arranged in the column direction and the second node Pb adjacent to the second node Pb on the lower side in the figure may be electrically shorted without providing the second transistor SWB. Further, for example, between every second node Pb (u is an integer equal to or greater than 1) arranged in the column direction and the second node Pb adjacent to the second node Pb on the lower side in the figure While only the second transistor SWB is provided, between the second nodes Pb other than the second nodes Pb arranged in the column direction and the second nodes Pb adjacent to the second nodes Pb on the lower side in the drawing, It may be electrically shorted.

As in the second embodiment, the wiring 98 may be provided with an adjustment capacitor in the present embodiment. Also in the present embodiment, the capacitance value of the capacitance CD may be a value within a range of ±20% with respect to the capacitance value of the capacitance CC, or a value within a range of ±10% with respect to the capacitance value of the capacitance CC. It can be a value within the range. These points also apply to the fifth embodiment, which will be described later.

Note that each operation example shown in FIGS. 16 to 20 is an example of an operation of reading the signal charge of the photodiode PD of each pixel PX without mixing it with the signal charge of the photodiode PD of another pixel PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be mixed with the signal charge of the photodiode PD of another pixel PX of the same color and read out.

For example, by turning on the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1), the first node Pa(n-1) , Pa(n), and Pa(n+1) are connected to each other, and TXA(n-1), TXA(n), and TXA(n+1) are turned on at the same time. Signal charges of photodiodes PDA(n-1), PDA(n), PDA(n-1) of pixels PXA(n-1), PXA(n), PXA(n-1) are connected to each other. are averaged at the nodes Pa(n−1), Pa(n), and Pa(n+1) of , and the function of same-color three-pixel mixed readout can be realized. At this time, the second transistors SWB(n−2) and SWB(n+2) are turned off and electrically connected to the first nodes Pa(n−1), Pa(n) and Pa(n+1). By minimizing the number of first or second transistors in the ON state, the charge-to-voltage conversion capacitance value at the coupled first node Pa(n-1), Pa(n), Pa(n+1) is minimized, and same-color three-pixel mixed readout can be performed with the highest SN ratio. On the other hand, in addition to the first transistors SWA(n−1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1), each first transistor SWA and each second transistor If one or more of the transistors SWB in the ON state are electrically connected to the first nodes Pa(n−1), Pa(n), Pa(n+1), then the According to the number, the charge-to-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) increases, and the dynamic range of same-color three-pixel mixed readout is expanded. can be done.

[Fifth embodiment]
FIG. 21 is a circuit diagram showing a schematic configuration of a solid-state imaging device 104 of an electronic camera according to the fifth embodiment of the invention, and corresponds to FIG. In FIG. 21, elements that are the same as or correspond to elements in FIG. 14 are denoted by the same reference numerals, and overlapping descriptions thereof will be omitted.

This embodiment differs from the fourth embodiment in that the photodiode PDB and the transfer transistor TXB are removed from each pixel block BL in the fourth embodiment. The point is that the pixel block BL is the pixel PXA. However, in this embodiment, the density in the column direction of the photodiodes PDA is double the density in the column direction of the photodiodes PDA in the fourth embodiment. The density in the column direction of the entire PDA and PDB is the same. In this embodiment, n indicates the row of the pixel block BL and the row of the pixel PXA.

In other words, each pixel block BL is composed of two pixels PX (PXA, PXB) in the fourth embodiment, whereas each pixel block BL is composed of one pixel block BL in the present embodiment. of pixels PX (PXA). In the fourth embodiment, two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of first node Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL. In contrast, in the present embodiment, each pixel PX (only PXA in the present embodiment) has a set of first node Pa, amplification transistor AMP, reset transistor RST, and selection transistor SEL. is doing.

Basically, the description of the fourth embodiment is compatible with the description of the present embodiment by replacing the pixel block BL with the pixel PXA. Therefore, detailed description of this embodiment is omitted here.

This embodiment also provides advantages similar to those of the fourth embodiment.

Although the embodiments and modifications of the present invention have been described above, the present invention is not limited to these.

4 solid-state imaging device BL pixel block PX pixel PD photodiode TXA, TXB transfer transistor P node AMP amplification transistor SWa, SWb connection transistor

Claims (27)

An imaging device comprising a plurality of pixel blocks arranged side by side in a row direction and a column direction,
The pixel block is
a plurality of photoelectric conversion units that convert light into electric charges;
a node having a first diffusion portion to which charges converted by the plurality of photoelectric conversion portions are transferred;
a reset transistor for controlling connection between the node and a power supply line to which a predetermined voltage is supplied;
a connection transistor for controlling connection between the node and the node of another pixel block arranged adjacently in the column direction ;
the reset transistor and the connection transistor share a second diffusion electrically connected to the node ;
The first diffusion section and the second diffusion section are electrically connected to each other by wiring . In the imaging device according to claim 1,
The reset transistor is an imaging device formed with the first diffusion portion as a source. In the imaging device according to claim 1 or claim 2,
The connection transistor is an imaging device having the first diffusion portion as a source. An imaging device comprising a plurality of pixel blocks arranged side by side in a row direction and a column direction,
The pixel block is
a plurality of photoelectric conversion units that convert light into electric charges;
a node having a first diffusion portion to which charges converted by the plurality of photoelectric conversion portions are transferred;
a reset transistor for controlling connection between the node and a power supply line to which a predetermined voltage is supplied;
a connection transistor for controlling connection between the node and the node of another pixel block arranged adjacently in the column direction ;
the source of the reset transistor is formed by a second diffusion electrically connected to the node;
a source of the coupling transistor is formed by the second diffusion ;
The first diffusion section and the second diffusion section are electrically connected to each other by wiring . In the imaging device according to any one of claims 1 to 4,
The second diffusion portion is arranged between the gate of the reset transistor and the gate of the connection transistor in the row direction. In the imaging device according to any one of claims 1 to 5 ,
An imaging device comprising an amplification transistor having a gate connected to the wiring. In the imaging device according to claim 6 ,
The imaging device, wherein the gate width of the amplification transistor is larger than the gate width of the reset transistor. In the imaging device according to claim 6 or claim 7 ,
The imaging device, wherein the gate width of the amplification transistor is larger than the gate width of the connection transistor. In the imaging device according to any one of claims 6 to 8 ,
The imaging device, wherein the drain of the amplification transistor is electrically connected to the power supply line. In the imaging device according to any one of claims 6 to 9 ,
a selection transistor for controlling connection between the amplification transistor and a signal line through which a signal from the amplification transistor is output;
the source of the amplifying transistor is formed by a third diffusion located at a position different from that of the second diffusion;
The imaging device, wherein the drain of the selection transistor is formed by the third diffusion portion. In the imaging device according to claim 10 ,
The imaging element, wherein the third diffusion portion is arranged between the gate of the amplification transistor and the gate of the selection transistor in the row direction. In the imaging device according to claim 10 or claim 11 ,
The imaging device, wherein the gate width of the amplification transistor is larger than the gate width of the selection transistor. In the imaging device according to any one of claims 1 to 12 ,
The plurality of photoelectric conversion units are imaging elements arranged side by side in the column direction. a plurality of nodes arranged side by side in a row direction and a column direction and having first diffusion portions to which photoelectrically converted charges are transferred;
a reset transistor for controlling connection between a first node among the plurality of nodes and a power supply line to which a predetermined voltage is supplied;
a connection transistor that controls connection between the first node and a second node among the plurality of nodes;
the first node and the second node are arranged next to each other in the column direction;
the first diffusion portion transfers charges converted by the plurality of photoelectric conversion portions, and
the reset transistor and the connection transistor share a second diffusion electrically connected to the first node ;
The first diffusion section and the second diffusion section are electrically connected to each other by wiring . In the imaging device according to claim 14 ,
The reset transistor is an imaging device formed with the second diffusion portion as a source. In the imaging device according to claim 14 or 15 ,
The connection transistor is an imaging device having the second diffusion portion as a source. a plurality of nodes arranged side by side in a row direction and a column direction and having first diffusion portions to which photoelectrically converted charges are transferred;
a reset transistor for controlling connection between a first node among the plurality of nodes and a power supply line to which a predetermined voltage is supplied;
a connection transistor that controls connection between the first node and a second node among the plurality of nodes;
the first node and the second node are arranged next to each other in the column direction;
the first diffusion portion transfers charges converted by the plurality of photoelectric conversion portions, and
the source of the reset transistor is formed by a second diffusion electrically connected to the node;
a source of the coupling transistor is formed by the second diffusion ;
The first diffusion section and the second diffusion section are electrically connected to each other by wiring . In the imaging device according to any one of claims 14 to 17 ,
The second diffusion portion is arranged between the gate of the reset transistor and the gate of the connection transistor in the row direction. In the imaging device according to any one of claims 14 to 18 ,
An imaging device comprising an amplification transistor having a gate connected to the wiring. In the imaging device according to claim 19 ,
The imaging device, wherein the gate width of the amplification transistor is larger than the gate width of the reset transistor. In the imaging device according to claim 19 or claim 20 ,
The imaging device, wherein the gate width of the amplification transistor is larger than the gate width of the connection transistor. In the imaging device according to any one of claims 19 to 21 ,
The imaging device, wherein the drain of the amplification transistor is electrically connected to the power supply line. In the imaging device according to any one of claims 19 to 22 ,
a selection transistor for controlling connection between the amplification transistor and a signal line through which a signal from the amplification transistor is output;
the source of the amplifying transistor is formed by a third diffusion located at a position different from that of the second diffusion;
The imaging device, wherein the drain of the selection transistor is formed by the third diffusion portion. 24. The imaging device according to claim 23 ,
The imaging element, wherein the third diffusion portion is arranged between the gate of the amplification transistor and the gate of the selection transistor in the row direction. In the imaging device according to claim 23 or 24 ,
The imaging device, wherein the gate width of the amplification transistor is larger than the gate width of the selection transistor. In the imaging device according to any one of claims 14 to 25 ,
The plurality of photoelectric conversion units are imaging elements arranged side by side in the column direction. An imaging device comprising the imaging device according to any one of claims 1 to 26 .

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