JP7156160B2 - Semiconductor device inspection method - Google Patents

Description

The technology disclosed in the present specification relates to an inspection method for inspecting the short-circuit resistance of a semiconductor element.

Before shipping a semiconductor device, an inspection is performed to determine whether the short-circuit resistance of the semiconductor device satisfies the required specifications. In such pre-collection inspection, a short-circuit energy within the inspection standard range is applied to the semiconductor element to confirm that there is no problem in the state of the semiconductor element. It is desirable that all semiconductor devices be inspected before shipment. Patent Literature 1 discloses an example of a method for testing the short circuit withstand capability of all semiconductor devices.

JP 2015-198218 A

In general, in the short-circuit resistance inspection method, in order to apply short-circuit energy within the inspection standard range to the semiconductor element, the semiconductor element is turned on while a predetermined voltage (V) is applied between the main terminals of the semiconductor element. A short-circuit current (I) is passed through the semiconductor element for a predetermined period of time. As a result, a short-circuit energy (time integral of I.times.V) within the inspection standard range should be applied to the semiconductor device.

However, due to manufacturing variations, there are also variations in the saturation current of the semiconductor device, that is, the short-circuit current. For this reason, for example, a large short-circuit current flows through a semiconductor element having a large saturation current, and there is a possibility that a large short-circuit energy exceeding the inspection standard range is applied. For example, a small short-circuit current flows through a semiconductor element with a small saturation current, and there is a possibility that short-circuit energy smaller than the inspection standard range is applied.

As described above, the short-circuit energy applied to the semiconductor element fluctuates depending on the variation in the saturation current of the semiconductor element, and the short-circuit energy applied to the semiconductor element may deviate from the inspection standard range. If the short-circuit energy applied to the semiconductor device is out of the test specification range, the test will fail and the test must be re-performed.

The present specification provides a technique for making the short-circuit energy applied to a semiconductor element fall within the inspection standard range in the inspection method for inspecting the short-circuit resistance of the semiconductor element.

This specification can disclose an inspection method for inspecting the short-circuit resistance of a semiconductor element by passing a short-circuit current through the semiconductor element. This inspection method comprises the steps of: applying a predetermined voltage across main terminals of the semiconductor element; turning on the semiconductor element to allow the short-circuit current to flow through the semiconductor element; and performing a predetermined period of time after the semiconductor element is turned on. and adjusting the timing of turning off the semiconductor element based on the current value of the short-circuit current flowing through the semiconductor element after a lapse of time.

In the inspection method, the timing for turning off the semiconductor element is adjusted based on the current value of the short-circuit current flowing through the semiconductor element. In other words, in the inspection method, the time during which the semiconductor element is turned on, that is, the time during which the short-circuit energy is applied is adjusted based on the current value of the short-circuit current flowing through the semiconductor element. According to the inspection method described above, by adjusting the turn-on time of the semiconductor element, it is possible to compensate for variations in the short-circuit current and keep the short-circuit energy applied to the semiconductor element within the inspection standard range.

1 shows a circuit diagram of an inspection device; FIG. In the inspection method of the comparative example, it is a timing chart of the waveforms of the gate voltage, the current and the voltage between the drain and the source of the semiconductor device when the short-circuit withstand capability is being inspected, and the inductance on the circuit is relatively small. 4 shows a timing chart for the case. In the inspection method of the comparative example, it is a timing chart of the waveforms of the gate voltage, current, and drain-source voltage of the semiconductor element when the short-circuit withstand capability is being inspected, and is a timing chart when the inductance on the circuit is relatively large. A timing chart is shown. It is a flowchart of the first inspection method of the present embodiment, and is a flowchart of the inspection method when the inductance on the circuit is relatively small. FIG. 5 is a timing chart of waveforms of the gate voltage, current, and drain-source voltage of the semiconductor device when the short-circuit withstand capability is being inspected in the first inspection method of FIG. 4 ; FIG. It is a flowchart of a modified example of the first inspection method of the present embodiment, and is a flowchart of the inspection method when the inductance on the circuit is relatively small. FIG. 10 is a flowchart of another modified example of the first inspection method of the embodiment, and is a flowchart of the inspection method when the inductance on the circuit is relatively small. FIG. It is a flowchart of the second inspection method of the present embodiment, and is a flowchart of the inspection method when the inductance on the circuit is relatively large. FIG. 9 is a timing chart of waveforms of the gate voltage, current, and drain-source voltage of the semiconductor device when the short-circuit withstand capability is being inspected in the second inspection method of FIG. 8 ; FIG.

FIG. 1 shows a circuit diagram of an inspection apparatus 1 for inspecting the short-circuit resistance of all semiconductor devices 10 before shipment. The inspection device 1 includes a DC power supply 20 , an inductor 30 , a voltmeter 40 and an ammeter 50 . The drain terminal D of the semiconductor element 10 is connected to the positive terminal of the DC power supply 20 via the inductor 30, and the source terminal S of the semiconductor element 10 is connected to the negative terminal of the DC power supply 20 via the ammeter 50. . A voltmeter 40 is connected between the drain terminal D and the source terminal S of the semiconductor element 10 . Inductor 30 is provided to suppress abrupt changes in current. The inductance L of the inductor 30 also includes parasitic inductance on the circuit wiring. Further, when the parasitic inductance on the circuit wiring is sufficiently large, the inductance L may be only the parasitic inductance. Hereinafter, the inductance L will be referred to as "the inductance L on the circuit". A voltmeter 40 is provided to measure the drain-source voltage Vds of the semiconductor element 10 . Ammeter 50 is provided to measure current Id flowing through semiconductor device 10 .

(Inspection method of comparative example)
Here, before explaining the short-circuit withstand capability inspection method of the present embodiment, an inspection method of a comparative example corresponding to the conventional inspection method will be explained. The circuit configuration of the inspection apparatus of the comparative example is the same as the circuit configuration of the inspection apparatus 1 of this embodiment. Therefore, in the following description, the inspection apparatus of the comparative example will be described with reference to the same reference numerals.

FIG. 2 is a timing chart of the waveforms of the gate voltage Vg, the current Id, and the drain-source voltage Vds of the semiconductor device 10 when the short-circuit withstand capability is being inspected in the inspection method of the comparative example. It is a timing chart when the inductance L is relatively small. FIG. 2A is a timing chart of the semiconductor device 10 having a large saturation current due to manufacturing variations, and FIG. 2B is a timing chart of the semiconductor device 10 having a small saturation current due to manufacturing variations.

In the inspection method of the comparative example, in a state in which the fixed voltage VH of the DC power supply 20 is applied between the drain and source terminals of the semiconductor element 10, the semiconductor element 10 is turned on at the timing Ton, and is turned on at a predetermined time from the timing Ton to the timing Toff. This is carried out by causing a current Id to flow through the semiconductor element 10 over the entire length. Since the fixed voltage VH of the DC power supply 20 is large, the drain-source voltage Vds applied to the semiconductor element 10 is large. Therefore, the current Id flowing through the semiconductor device 10 is also called a short-circuit current.

As shown in FIG. 2A, the current Id of the semiconductor element 10, which has a large saturation current, does not reach the saturation current during the predetermined time (timing Ton to timing Toff) during which the semiconductor element 10 is on. is increasing all the time. On the other hand, as shown in FIG. 2B, the current Id of the semiconductor element 10 with a small saturation current reaches the saturation current at timing Tm. In this example, since the inductance L on the circuit is relatively small, the voltage drop (ΔV=L× di/dt) is small. Therefore, at the timing Tm, the voltage drop in the drain-source voltage Vds of the semiconductor element 10 in FIG. Although there is a difference, the difference is practically negligible. Therefore, the short-circuit energy (E=Id×Vds time integral) applied to the semiconductor element 10 is large in the semiconductor element 10 having a large saturation current in FIG. The element 10 becomes smaller.

FIG. 3 is a timing chart of the waveforms of the gate voltage Vg, the current Id, and the drain-source voltage Vds of the semiconductor device 10 when the short-circuit withstand capability is being inspected in the inspection method of the comparative example. It is a timing chart when the inductance L is relatively large. FIG. 3A is a timing chart of the semiconductor device 10 having a large saturation current due to manufacturing variations, and FIG. 3B is a timing chart of the semiconductor device 10 having a small saturation current due to manufacturing variations.

In this example, since the inductance L on the circuit is relatively large, the voltage drop (ΔV=L× di/dt) is large. Therefore, at the timing Tm, the voltage drop in the drain-source voltage Vds of the semiconductor element 10 in FIG. There is a difference that cannot be ignored. Therefore, the short-circuit energy (E=Id×Vds time integral) applied to the semiconductor element 10 is small in the semiconductor element 10 having a large saturation current in FIG. The element 10 becomes large.

The relationship between FIGS. 2 and 3 is shown in Table 1 below.

Thus, in the inspection method of the comparative example, the short-circuit energy applied to the semiconductor element 10 fluctuates depending on the variation in the saturation current of the semiconductor element 10 regardless of whether the inductance L on the circuit is small or large. do. As a result, the short circuit energy applied to the semiconductor device 10 may deviate from the inspection standard range. For example, in the examples of FIGS. 2(A) and 3(B), the short-circuit energy may be applied beyond the inspection standard range. In the examples of FIGS. 2B and 3A, the short-circuit energy may be applied below the inspection standard range. Thus, if the short-circuit energy applied to the semiconductor device 10 is out of the inspection standard range, the inspection fails and the inspection must be performed again. Therefore, the inspection method of the comparative example has a problem that the number of times of re-executing the inspection increases and the cost of the inspection process increases.

(Inspection method of this embodiment)
Several inspection methods of this embodiment will be described below. All of the inspection methods of this embodiment are characterized in that the short-circuit energy applied to the semiconductor element 10 is adjusted so as to fall within the inspection standard range, as will be specifically described below.

(First inspection method)
FIG. 4 is a flowchart of an example of the inspection method of this embodiment, and is a flowchart of the inspection method when the inductance L on the circuit is relatively small. FIG. 5 is a timing chart of waveforms of the gate voltage Vg, the current Id, and the drain-source voltage Vds of the semiconductor device 10 during the inspection of FIG. FIG. 5A is a timing chart of a semiconductor device 10 with a large saturation current due to manufacturing variations, and FIG. 5B is a timing chart of a semiconductor device 10 having a small saturation current due to manufacturing variations.

First, as shown in FIG. 4, a fixed voltage VH of the DC power supply 20 (see FIG. 1) is applied between the drain and source terminals of the semiconductor element 10 (step S11). Next, with the fixed voltage VH applied, the gate voltage Vg applied to the gate terminal G of the semiconductor element 10 is increased to turn on the semiconductor element 10 (step S12). This step S2 corresponds to the timing Ton in FIG. When the semiconductor device 10 turns on, a current Id begins to flow through the semiconductor device 10 . Since the fixed voltage VH of the DC power supply 20 is large, the drain-source voltage Vds applied to the semiconductor element 10 is large. Therefore, the current Id flowing through the semiconductor device 10 is also called a short-circuit current.

At the determination timing t after a predetermined time has elapsed since the semiconductor element 10 was turned on, the current value of the current Id flowing through the semiconductor element 10 is compared with the determination current value Ith (step S13). As shown in FIG. 5A, in the semiconductor element 10 with a large saturation current, the current Id does not reach the saturation current at the determination timing t, and the relationship of Id>Ith is established. In this case, as shown in FIG. 4, the semiconductor element 10 is turned off at a timing Toff1 after a predetermined time Δt1 has elapsed from the determination timing t (step S14). On the other hand, as shown in FIG. 5B, in the semiconductor element 10 with a small saturation current, the current Id reaches the saturation current at the determination timing t, and the relationship of Id<Ith is established. In this case, as shown in FIG. 4, the semiconductor element 10 is turned off at a timing Toff2 after a predetermined time Δt2 has elapsed from the determination timing t (step S15). Here, predetermined time Δt1<predetermined time Δt2. Alternatively, the predetermined time Δt1=0 may be satisfied.

In the example of FIG. 5, since the inductance L on the circuit is relatively small, the voltage drop (ΔV=L×di/dt) based on the inductance L on the circuit is small. ) can be ignored. Therefore, in the example of FIG. 5, the short circuit energy generated in the semiconductor element 10 having a large saturation current in FIG. Short-circuit energy tends to be small. In the inspection method of the present embodiment, the semiconductor element 10 determined to have a large saturation current based on the comparison result in step S13 is turned off at a timing Toff1 after a relatively short predetermined time Δt1 has elapsed, and if the saturation current is small, the semiconductor element 10 is turned off. The determined semiconductor element 10 is turned off at timing Toff2 after a relatively long predetermined time Δt2 has elapsed. As a result, in both cases of FIGS. 5A and 5B, the generated short-circuit energy is adjusted to be within the inspection standard range.

Next, as shown in FIG. 4, the product of the drain-source voltage Vds measured by the voltmeter 40 and the current Id measured by the ammeter 50 is time-integrated to calculate the generated short-circuit energy (E). Then, confirm whether the short-circuit energy (E) is within the inspection standard range. In addition, in the inspection method of the present embodiment, since the generated short-circuit energy is adjusted so as to be within the inspection standard range, this confirmation step may be omitted. The lower limit of the inspection specification is Emin, and the upper limit of the inspection specification is Emax. If the short circuit energy (E) is out of the test specification range (E<Emin or Emax<E), the test fails and a retest is performed. If the short-circuit energy (E) is within the test specification range (Emin<E<Emax), the test is successful and other electrical properties are confirmed (step S17). If other electrical characteristics are normal, the inspection of the semiconductor device 10 is completed. If other electrical characteristics are abnormal, the semiconductor device 10 is determined to be defective.

(First modification of the first inspection method)
FIG. 6 shows a flowchart of a modification of the first inspection method. This modification is characterized in that the current value of the current Id flowing through the semiconductor element 10 is compared using a plurality of determination current values Ith1 and Ith2 at the determination timing t. In this example, two determination current values Ith1 and Ith2 are used, and the first determination current value Ith1>the second determination current value Ith2 is set. Note that three or more determination current values may be used. Further, steps S11, S12, S16, and S17 are the same as the inspection method described above, and description thereof will be omitted.

In this inspection method, the current value of the current Id flowing through the semiconductor element 10 is compared with the first determination current value Ith1 at the determination timing t when a predetermined time has passed since the semiconductor element 10 was turned on (step S101). As for the semiconductor element 10 where Id>Ith1, the semiconductor element 10 is turned off at the timing when the predetermined time Δt11 has passed from the judgment timing t (step 102). If Id<Ith1, the current value of the current Id is compared with the second determination current value Ith2 (step S103). As for the semiconductor element 10 where Id>Ith2, the semiconductor element 10 is turned off at the timing when the predetermined time Δt12 has passed from the judgment timing t (step 104). As for the semiconductor element 10 where Id<Ith2, the semiconductor element 10 is turned off at the timing when the predetermined time Δt13 has passed from the judgment timing t (step 105). Here, predetermined time Δt11<predetermined time Δt12<predetermined time Δt13. Alternatively, the predetermined time Δt11=0 may be satisfied.

By finely controlling the turn-off timing of the semiconductor element 10 using a plurality of judgment current values Ith1 and Ith2, it is possible to more accurately adjust the generated short-circuit energy to be within the inspection standard range.

(Second modification of the first inspection method)
FIG. 7 shows a flowchart of another modification of the first inspection method. This modification is characterized in that the current values of the current Id flowing through the semiconductor element 10 are compared using the corresponding determination current values Ith11 and Ith12 at each of a plurality of determination timings t1 and t2. In this example, corresponding determination current values Ith11 and Ith12 are used at two determination timings t1 and t2, respectively, and determination timing t1<determination timing t2. Further, the first determination current value Ith11 and the second determination current value Ith12 may be the same value or different values. It should be noted that the determination may be made at three or more determination timings. Further, steps S11, S12, S16, and S17 are the same as the inspection method described above, and description thereof will be omitted.

In this inspection method, the current value of the current Id flowing through the semiconductor element 10 is compared with the first determination current value Ith11 at the determination timing t1 when a predetermined time has elapsed since the semiconductor element 10 was turned on (step S201). As for the semiconductor element 10 satisfying Id>Ith11, the semiconductor element 10 is turned off at the timing when the predetermined time Δt21 has passed from the judgment timing t1 (step 202). If Id<Ith11, the current value of the current Id flowing through the semiconductor device 10 is compared with the second determination current value Ith12 at the determination timing t2 when a predetermined time has elapsed since the semiconductor device 10 was turned on (step S203). As for the semiconductor element 10 satisfying Id>Ith12, the semiconductor element 10 is turned off at the timing when the predetermined time Δt22 has passed from the judgment timing t (step 204). As for the semiconductor element 10 where Id<Ith12, the semiconductor element 10 is turned off at the timing when the predetermined time Δt23 has passed from the judgment timing t (step 205). Here, predetermined time Δt21<predetermined time Δt22<predetermined time Δt23. Alternatively, the predetermined time Δt21=0 may be satisfied.

By finely controlling the timing of turning off the semiconductor element 10 using a plurality of judgment timings t1 and t2 in this way, it is possible to more accurately adjust the generated short-circuit energy to be within the inspection standard range.

(Second inspection method)
FIG. 8 is a flowchart of an example of the inspection method of this embodiment, and is a flowchart of the inspection method when the inductance L on the circuit is relatively large. FIG. 9 is a timing chart of waveforms of the gate voltage Vg, the current Id, and the drain-source voltage Vds of the semiconductor device 10 during the inspection of FIG. FIG. 9A is a timing chart of the semiconductor device 10 having a large saturation current due to manufacturing variations, and FIG. 9B is a timing chart of the semiconductor device 10 having a small saturation current due to manufacturing variations.

First, as shown in FIG. 8, a fixed voltage VH of DC power supply 20 (see FIG. 1) is applied between the drain and source terminals of semiconductor element 10 (step S21). Next, with the fixed voltage VH applied, the gate voltage Vg applied to the gate terminal G of the semiconductor element 10 is increased to turn on the semiconductor element 10 (step S22). This step S2 corresponds to the timing Ton in FIG. When the semiconductor device 10 turns on, the current Id of the semiconductor device 10 begins to flow. Since the fixed voltage VH of the DC power supply 20 is large, the drain-source voltage Vds applied to the semiconductor element 10 is large. Therefore, the current Id flowing through the semiconductor device 10 is also called a short-circuit current.

At the determination timing t after a predetermined time has elapsed since the semiconductor element 10 was turned on, the current value of the current Id flowing through the semiconductor element 10 is compared with the determination current value Ith (step S23). As shown in FIG. 9A, in the semiconductor element 10 with a large saturation current, the current Id does not reach the saturation current at the determination timing t, and the relationship of Id>Ith is established. In this case, as shown in FIG. 8, the semiconductor element 10 is turned off at a timing Toff3 after a predetermined time Δt3 has elapsed from the determination timing t (step S24). On the other hand, as shown in FIG. 9B, in the semiconductor element 10 with a small saturation current, the current Id reaches the saturation current at the determination timing t, and the relationship of Id<Ith is established. In this case, as shown in FIG. 8, the semiconductor element 10 is turned off at a timing Toff4 after a predetermined time Δt4 has elapsed from the determination timing t (step S25). Here, predetermined time Δt3>predetermined time Δt4. Alternatively, the predetermined time Δt4=0 may be satisfied.

In the example of FIG. 9, since the inductance L on the circuit is relatively large, the voltage drop (ΔV=L×di/dt) based on the inductance L on the circuit is large. ) cannot be ignored. Therefore, in the example of FIG. 9, the short circuit energy generated in the semiconductor element 10 having a large saturation current in FIG. Short-circuit energy tends to increase. In the inspection method of the present embodiment, the semiconductor device 10 determined to have a large saturation current based on the comparison result in step S23 is turned off at a timing Toff3 after a relatively long predetermined time Δt3 has passed, and if the saturation current is small, the semiconductor device 10 is turned off. The determined semiconductor device 10 is turned off at timing Toff4 after a relatively short predetermined time Δt4 has elapsed. As a result, in both cases of FIGS. 9A and 9B, the generated short-circuit energy is adjusted to be within the inspection standard range.

Next, as shown in FIG. 8, the product of the drain-source voltage Vds measured by the voltmeter 40 and the current Id measured by the ammeter 50 is time-integrated to calculate the generated short circuit energy (E). Then, confirm whether the short-circuit energy (E) is within the inspection standard range. In addition, in the inspection method of the present embodiment, since the generated short-circuit energy is adjusted so as to be within the inspection standard range, this confirmation step may be omitted. The lower limit of the inspection specification is Emin, and the upper limit of the inspection specification is Emax. If the short circuit energy (E) is out of the test specification range (E<Emin or Emax<E), the test fails and a retest is performed. If the short-circuit energy (E) is within the test specification range (Emin<E<Emax), the test is successful and other electrical properties are confirmed (step S27). If other electrical characteristics are normal, the inspection of the semiconductor device 10 is completed. If other electrical characteristics are abnormal, the semiconductor device 10 is determined to be defective.

In the above-described second inspection method, as in the modification of the first inspection method, determination may be made using a plurality of determination current values, or determination may be made at a plurality of determination timings. good too.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

1: Inspection device 10: Semiconductor element 20: DC power supply 30: Inductor 40: Voltmeter 50: Ammeter

Claims (1)

An inspection method for applying a short-circuit energy within an inspection standard to the semiconductor element by passing a short-circuit current through the semiconductor element,
applying a predetermined voltage between main terminals of the semiconductor element;
turning on the semiconductor device to apply the short circuit current to the semiconductor device;
adjusting the timing of turning off the semiconductor element based on the current value of the short-circuit current flowing through the semiconductor element after a predetermined time has elapsed since the semiconductor element was turned on ;
In the step of adjusting the timing, when the current value of the short-circuit current is larger than the judgment current value, the semiconductor element is turned off when a first predetermined time elapses after the elapse of the predetermined time, and the short-circuit current is is smaller than the judgment current value, the semiconductor device is turned off when a second predetermined time elapses after the elapse of the predetermined time, and the first predetermined time is equal to the second predetermined time. Shorter than the test method.

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