JP7038588B2 - Open / ground fault detection circuit - Google Patents

Description

The present invention relates to an open / ground fault detection circuit for opening an output terminal of a power supply circuit and detecting a ground fault, and more particularly to a circuit for realizing open / ground fault discrimination detection with a relatively simple configuration.

As is well known, conventionally, in a power supply circuit such as a switching power supply, circuit protection using various protection circuits or the like is attempted to protect the power supply circuit and the load in the event of an abnormal output voltage. (For example, refer to Patent Document 1 and the like).

In recent switching power supply circuits and the like, for example, various functions for circuit protection called current sense function, power good function, and OVP (Over Voltage Protection) function are appropriately selected according to the application of the power supply circuit and the like. Often provided.

The current sense function generally detects the current output from the power supply circuit to the load, and can determine the presence or absence of an abnormality in the output stage based on the detected current value. In a power supply circuit provided with such a current sense function, the current sense function can be transferred to detect the potential difference between the output terminal of the power supply circuit and the feedback terminal provided for output voltage control. It is possible to open between the output terminal and the feedback terminal and detect ground faults.

Further, in a power supply circuit provided with a power good function that can detect that the output voltage has reached a predetermined set voltage, it is possible to detect that the output voltage deviates from the set voltage, and an abnormality in the output terminal is obtained. It is possible to judge whether or not it has occurred.

Further, in the power supply circuit having the OVP function, it is possible to detect the opening of the feedback terminal by comparing the voltage of the feedback terminal with an error amplifier.

JP-A-2017-79444

However, in the case of opening / ground fault detection between the output terminal / feedback terminal using the current sense function, it is necessary to monitor both the output terminal and the feedback terminal, and the opening and the ground fault are individually discriminated. There is a problem that it is not possible to respond to the request to individually determine whether it is an open or a ground fault.

In addition, in the case of open / ground fault detection using the power good function, open / ground fault detection can be performed by monitoring the input voltage of the error amplifier, but it is the same as when the current sense function is used. There is a problem that it is not possible to distinguish between open and ground faults individually.

Further, in the open / ground fault detection using the OVP function, in addition to the need to directly monitor the voltage of the output terminal, there is a problem that the open / ground fault cannot be discriminated individually.

The present invention has been made in view of the above circumstances, and provides an open / ground fault detection circuit capable of distinguishing between open and ground faults between an output terminal and a feedback terminal with a structure as simple as possible.

In order to achieve the above object of the present invention, the open / ground fault detection circuit according to the present invention is
The output voltage obtained from the output terminal is used for feedback control via the feedback terminal to detect the opening and ground fault between the output terminal and the feedback terminal in a power supply circuit configured to be able to control the output of the output voltage. It is an open / ground fault detection circuit.
A feedback voltage monitoring circuit that monitors whether the voltage of the feedback terminal is normal and outputs a monitoring signal according to the monitoring result.
When a predetermined monitoring signal indicating that the feedback voltage is not normal is output by the feedback voltage monitoring circuit, the feedback voltage is the voltage corresponding to the opening between the output terminal and the feedback terminal, or the feedback. An open / ground fault determination circuit that determines whether the voltage is the voltage corresponding to the ground fault between the output terminal and the feedback terminal and outputs a determination signal according to the determination result.
It is provided with a delay processing circuit that delays the output of the open / ground fault determination circuit and outputs the circuit.
The open / ground fault determination circuit has a comparator in which a reference voltage is set in the inverting input terminal, and the output terminal and the feedback terminal are in an open state, and the feedback voltage is not normal due to the feedback voltage monitoring circuit. When a predetermined monitoring signal is output, an applied voltage to the non-inverting input terminal of the comparator that exceeds the reference voltage of the comparator is generated, while the output terminal and the feedback terminal are short-circuited, and the above-mentioned When a predetermined monitoring signal indicating that the feedback voltage is not normal is output by the feedback voltage monitoring circuit, an applied voltage to the non-inverting input terminal of the comparator, which is lower than the reference voltage of the comparator, is generated, and the output terminal is used. When the feedback terminal is open, the comparator determines the output voltage corresponding to the logical value High, and when the output terminal and the feedback terminal are short-circuited, the comparator determines the output voltage as the determination signal. The output voltage corresponding to the value Low is configured so that it can be output .

According to the present invention, unlike the conventional case, by monitoring only the voltage of the feedback terminal with a relatively simple configuration, it is possible to distinguish whether the output terminal and the feedback terminal are open or a ground fault, and it is possible to detect a failure. Since it is possible to accurately grasp the situation of the power supply circuit, it is possible to take appropriate measures according to the situation of the failure, which has the effect of contributing to the improvement of the reliability and safety of the power supply circuit. be.

It is a circuit diagram which shows the 1st circuit configuration example of the open / ground fault detection circuit in embodiment of this invention. It is an equivalent circuit diagram explaining the operation state of the opening / ground fault determination circuit when the output terminal and the feedback terminal are in the open state in the opening / ground fault detection circuit in embodiment of this invention. It is an equivalent circuit diagram explaining the operation state of the opening / ground fault determination circuit when the output terminal and the feedback terminal are in the ground fault state in the opening / ground fault detection circuit in embodiment of this invention. It is a circuit diagram which shows the 2nd circuit configuration example of the open / ground fault detection circuit in embodiment of this invention. It is a circuit diagram which shows the 3rd circuit configuration example of the open / ground fault detection circuit in embodiment of this invention. FIG. 6A is a timing chart showing a signal change of the main part when the opening between the output terminal and the feedback terminal is detected by the opening / ground fault detection circuit according to the embodiment of the present invention, and FIG. 6A is a switching power supply circuit. 6 (b) is a timing chart showing the voltage change of the feedback terminal, FIG. 6 (c) is a timing chart showing the voltage change of the inverting input terminal of the error amplifier, and FIG. 6 (d). ) Is a timing chart showing a change in the output of the first comparator, FIG. 6 (e) is a timing chart showing a change in the start signal, FIG. 6 (f) is a timing chart showing a change in the soft start end signal, and FIG. 6 (g). ) Is a timing chart showing the output change of the first NOR circuit, FIG. 6 (h) is a timing chart showing the voltage change of the non-inverting input terminal of the second comparator, and FIG. 6 (i) is the output of the second comparator. FIG. 6 (j) is a timing chart showing a change, FIG. 6 (j) is a timing chart showing a change in the output of the second NOR circuit, FIG. 6 (k) is a timing chart showing a change in the output of the first delay circuit, and FIG. 6 (l) is a timing chart. A timing chart showing an output change of the first AND circuit, FIG. 6 (m) is a timing chart showing an output change of the third NOR circuit, and FIG. 6 (n) is a timing chart showing an output change of the second delay circuit. , FIG. 6 (o) is a timing chart showing the output change of the second AND circuit. FIG. 7A is a timing chart showing a signal change of a main part when a ground fault between an output terminal and a feedback terminal is detected by the open / ground fault detection circuit according to the embodiment of the present invention, and FIG. 7A is a switching power supply. FIG. 7 (b) is a timing chart showing a change in the output voltage of the circuit, FIG. 7 (b) is a timing chart showing a change in the voltage of the feedback terminal, and FIG. 7 (c) is a timing chart showing a change in the voltage of the inverting input terminal of the error amplifier. d) is a timing chart showing a change in the output of the first comparator, FIG. 7 (e) is a timing chart showing a change in the start signal, FIG. 7 (f) is a timing chart showing a change in the soft start end signal, and FIG. 7 (f). g) is a timing chart showing the output change of the first NOR circuit, FIG. 7 (h) is a timing chart showing the voltage change of the non-inverting input terminal of the second comparator, and FIG. 7 (i) is the timing chart of the second comparator. A timing chart showing an output change, FIG. 7 (j) is a timing chart showing an output change of the second NOR circuit, FIG. 7 (k) is a timing chart showing an output change of the first delay circuit, and FIG. 7 (l). Is a timing chart showing the output change of the first AND circuit, FIG. 7 (m) is a timing chart showing the output change of the third NOR circuit, and FIG. 7 (n) is a timing showing the output change of the second delay circuit. The chart, FIG. 7 (o) is a timing chart showing the output change of the second AND circuit. It is explanatory drawing explaining the truth value of the main part of the open / ground fault detection circuit in embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 8.
The members, arrangements, etc. described below are not limited to the present invention, and can be variously modified within the scope of the purpose of the present invention.
First, a first circuit configuration example of the open / ground fault detection circuit according to the embodiment of the present invention will be described with reference to FIG.
The configuration example shown in FIG. 1 is a configuration example in which the open / ground fault detection circuit 201 according to the embodiment of the present invention is built in the switching power supply circuit 301.

First, the switching power supply circuit 301 will be described.
The switching power supply circuit 301 is roughly divided into a switching control circuit (denoted as "CONTROL" in FIG. 1) 302, a driver circuit 303, and a feedback circuit 304. The configuration of the switching power supply circuit 301 is not unique to the present invention, but is basically the same as that of the conventional circuit.

The switching control circuit 302 is an integrated circuit in which a main circuit such as a switching circuit required for a switching power supply circuit is integrated.
The output stage of the switching control circuit 302 is connected to the driver circuit 303, and a desired voltage can be output via the driver circuit 303.

The driver circuit 303 buffer-amplifies and outputs the voltage generated by the switching control circuit 302.
The output stage of the driver circuit 303 is connected to the output terminal 31.
A load 315 is connected to the output terminal 31 via the smoothing coil 313, and a smoothing capacitor 314 is connected between the connection point between the smoothing coil 313 and the load 315 and the ground.

Further, between the feedback terminal 32 and the ground, first and second resistors 316 and 317 are provided, and the first resistor (denoted as "R1" in FIG. 1) 316 and the second resistor from the ground side. Resistors (denoted as "R2" in FIG. 1) 317 are connected in series in this order.
The voltage of the feedback terminal 32 is divided by the first and second resistors 316 and 317, and the voltage at the mutual connection point of the first and second resistors 316 and 317 is the error described below as the feedback voltage. It is designed to be input to the amplifier 318.

The mutual connection points of the first and second resistors 316 and 317 are connected to the inverting input terminal of the error amplifier (denoted as "ERRAMP" in FIG. 1) 318 using an operational amplifier.
The first reference voltage Vref1 is applied to the non-inverting input terminal of the error amplifier 318. From this error amplifier 318, the difference between the input voltage of the inverting input terminal and the first reference voltage Vref1 is amplified and output, input to the switching control circuit 302 as a feedback signal, and used for feedback control of the output voltage. It has become.

The switching power supply circuit 301 having such a configuration includes an open / ground fault detection circuit 200 having a feedback terminal voltage monitoring circuit 201, an open / ground fault determination circuit 202, and a delay processing circuit 203. ing.
Hereinafter, the open / ground fault detection circuit 200 will be described.

First, a specific configuration of each circuit will be described.
First, the feedback terminal voltage monitoring circuit 201 monitors the feedback voltage at the inverting input terminal of the error amplifier 318, determines whether the voltage at the output terminal 31 is normal with respect to the set value, and determines whether the determination result is normal or not, and determines the determination result in the subsequent stage. It is output to the open / ground fault determination circuit 202.

The feedback terminal voltage monitoring circuit 201 according to the embodiment of the present invention mainly comprises a first comparator 1 and a first NOR circuit (denoted as "NOR1" in FIG. 1) 3 having three input terminals. It is composed.
The non-inverting input terminal of the first comparator 1 is connected to the mutual connection points of the first and second resistors 316 and 317, and the voltage of the inverting input terminal of the error amplifier 318 is applied. It has become.

Further, a second reference voltage Vref2 is applied to the inverting input terminal of the first comparator 1.
The output terminal of the first comparator 1 is connected to one input terminal of the first NOR circuit 3.

A soft start end signal is input to one of the remaining two input terminals of the first NOR circuit 3, and a start signal is input to the other one.
The output terminal of the first NOR circuit 3 is connected to the subsequent open / ground fault determination circuit 202 as described below.

The open / ground fault determination circuit 202 includes first to fourth MOS transistors (denoted as "M1", "M2", "M3", and "M4" in FIG. 1, respectively) 6 to 9, and second. The comparator 2 and the third and fourth resistors (denoted as "R3" and "R4" in FIG. 1, respectively) 11 and 12 are configured as main components.

In this first configuration example, p-channel MOSFETs are used in the first to third MOS transistors 6 to 8, and n-channel MOSFETs are used in the fourth MOS transistor 9.
The sources of the first to third MOS transistors 6 to 8 are connected to each other so that a required internal power supply voltage is applied.
The output terminal of the first NOR circuit 3 is connected to the gate of the first MOS transistor 6, and the drain is connected to the drain of the second MOS transistor 7 to each other. A constant current source 13 is provided between the connection point between the drains of the first and second MOS transistors 6 and 7 and the ground.

The second and third MOS transistors 7 and 8 are connected as described below to form a current mirror circuit.
That is, the gates of the second and third MOS transistors 7 and 8 are connected to each other and connected to the drain of the second MOS transistor 7, and the second MOS transistor 7 is in a diode-connected state. ing.
The drain of the third MOS transistor 8 is connected to the mutual connection points of the third and fourth resistors 11 and 12 described below.

The output terminal of the first NOR circuit 3 is connected to the gate of the fourth MOS transistor 9.
The source of the fourth MOS transistor 9 is connected to the ground, while one end of the third resistor 11 is connected to the drain.

The third and fourth resistors 11 and 12 are connected in series, and the other end of the fourth resistor 12 is connected to the feedback terminal 32.
Further, the mutual connection points of the third and fourth resistors 11 and 12 are connected to the non-inverting input terminal of the second comparator 2.

A third reference voltage Vref3 is applied to the inverting input terminal of the second comparator 2.
The output terminal of the second comparator 2 is connected to the input stage of the delay processing circuit 203 as described below.

The delay processing circuit 203 includes a second and a third NOR circuit (denoted as “NOR2” and “NOR3” in FIG. 1, respectively) 4 and 5, and a first and second delay circuits (in FIG. 1, respectively, they are referred to as “NOR2” and “NOR3”). 14 and 15 (denoted as "DELAY1" and "DELAY2", respectively) and 16 and 17 of the first and second AND circuits (denoted as "AND1" and "AND2" in FIG. 1, respectively), the first and the first. It is configured to have two output control circuits (indicated as "CONT1" and "CONT2" in FIG. 1, respectively) 18 and 19.

The second and third NOR circuits 4 and 5 both have two input terminals, but the second NOR circuit 4 has one input terminal as a negative logic input.
The negative logic input input terminal of the second NOR circuit 4 and one input terminal of the third NOR circuit 5 are both connected to the output terminal of the second comparator 2 of the open / ground fault determination circuit 202. ing.
Further, the other input terminal of the second NOR circuit 4 and the other input terminal of the third NOR circuit 5 are both connected to the output terminal of the first comparator 1 of the previous feedback terminal voltage monitoring circuit 201. ..

The output terminal of the second NOR circuit 4 is connected to the input terminal EN of the first delay circuit 14, and the output terminal of the third NOR circuit 5 is connected to the input terminal EN of the second delay circuit 15. There is.
The first and second AND circuits 16 and 17 both have two input terminals, and one input terminal of the first AND circuit 16 has an output terminal of the first delay circuit 14 as a second. The output terminal of the second delay circuit 15 is connected to one input terminal of the AND circuit 17 of the above.

Then, the other input terminals of the first and second AND circuits 16 and 17 are connected to each other, and the output terminal of the second comparator 2 of the previous open / ground fault determination circuit 202 is connected. There is.
Further, the output terminal of the first AND circuit 16 is connected to the input terminal of the first output control circuit 18, and the output terminal of the second AND circuit 17 is connected to the input terminal of the second output control circuit 19. Has been done.

An open detection signal corresponding to the detection that the output terminal 31 and the feedback terminal 32 are in an open state is output from the first output control circuit 18 from the second output control circuit 19. A ground fault detection signal corresponding to the detection that a ground fault state is detected between the terminal 31 and the feedback terminal 32 is output (details will be described later).

Next, the operation in the above configuration will be described with reference to FIGS. 6 and 7.
First, a normal operation in which the required voltage is normally output from the output terminal 31 will be described.
When the switching power supply circuit 301 is started by turning on a power supply switch or the like (not shown), the start signal generated in the switching control circuit 302 is input to the first NOR circuit 3 of the feedback terminal voltage monitoring circuit 201. (See FIG. 6 (e)). In the embodiment of the present invention, the start signal has a voltage level corresponding to the logic value Low at the start of circuit operation.

In the switching control circuit 302, the soft start is started when the start signal is generated, and the output voltage VOUT at the output terminal 31 rises toward the set value (FIGS. 6 (a), 6 (e), and FIG. See FIG. 6 (f)). In the embodiment of the present invention, a soft start end signal for so-called soft start at the time of circuit start is generated in the switching control circuit 302 and input to the first NOR circuit 3 to be input to the first NOR. A signal to be described later is output from the circuit 3.

In the embodiment of the present invention, this soft start end signal is a voltage level corresponding to the logical value High from the circuit start current event to the time when the soft start period ends, and the voltage corresponding to the logical value Low at the end of the soft start. It is considered to be a level (see FIG. 6 (f)).

While the output voltage VOUT is rising, the magnitude relationship between the ERRRAMP inverting input applied to the non-inverting input terminal of the first comparator 1 of the feedback terminal voltage monitoring circuit 201 and the second reference voltage Vref2 is that the ERRRAMP inverting input <second. The reference voltage is Vref2 (see time t1 to t2 in FIG. 6C).

Due to the ERRRAMP inverting input <second reference voltage Vref2, the first comparator 1 becomes a voltage output corresponding to the logic value Low.
On the other hand, since the soft start end signal has a voltage level corresponding to the logical value High until the end of the soft start, the output VO_ERR of the first NOR circuit 3 at times t1 to t2 has a voltage level corresponding to the logical value Low. (See FIG. 6 (g)).

When the output VO_ERR of the first NOR circuit 3 has a voltage level corresponding to the logic value Low, the fourth MOS transistor 9 is turned off in the open / ground fault determination circuit 202. Therefore, the feedback monitor voltage FB_MONITOR at the non-inverting input terminal of the second comparator 2 is larger than the third reference voltage Vref3 (see FIG. 6 (h)). As a result, the output of the second comparator 2 becomes a voltage level corresponding to the logical value High (see FIG. 6 (i)).

Until the time t2 when the ERRRAMP inverting input exceeds the second reference voltage Vref2, the logic value from the above-mentioned second comparator 2 is connected to the input terminal of the negative logic input of the second NOR circuit 4 of the delay processing circuit 203. A signal with a voltage level corresponding to High is applied.

On the other hand, a voltage level signal corresponding to the logic value Low from the first comparator 1 is applied to the other input terminal (positive logic input terminal) of the second NOR circuit 4.
As a result, the output of the second NOR circuit 4 has a voltage level corresponding to the logical value Low (see FIG. 6J).

Further, in the third NOR circuit 5, a voltage level signal corresponding to the logic value High from the second comparator 2 and a voltage level signal corresponding to the logic value Low from the first comparator 1 are applied. As a result, the output signal has a voltage level corresponding to the logical value Low as in the second NOR circuit 4 (see FIG. 6 (m)).

In the first and second delay circuits 14 and 15, when a signal having a voltage level corresponding to the logical value High is input to the input terminal EN, the voltage level corresponding to the logical value High is obtained after a predetermined delay time. It is configured to output the signal of.
Therefore, as described above, when both the second and third NOR circuits 4 and 5 are in the output state of the voltage level corresponding to the logic value Low, any of the first and second delay circuits 14 and 15. However, the output is in a state corresponding to the logical value Low (see FIGS. 6 (k) and 6 (n)).

Since the outputs of the first and second delay circuits 14 and 15 correspond to the logical value Low, the output signals of the first and second delay circuits 14 and 15 are input to the first and second delay circuits 14 and 15. In the AND circuits 16 and 17, the AND condition is not satisfied regardless of the state of the other input signals, and all the outputs are in the state corresponding to the logical value Low (FIGS. 6 (l) and 6 (FIG. 6) and 6 (FIG. 6). o) See).

As a result, the open detection signal is not output from the first output control circuit 18 until the time t2, and the ground fault detection signal is output from the second output control circuit 19. There is no.

Next, the ERRRAMP inverting input exceeds the second reference voltage Vref2 as the output voltage VOUT rises, and then the ERRRAMP inverting input also reaches the corresponding voltage level in response to the voltage VOUT reaching the required voltage. The circuit operation in the period from the state to the end of the soft start period, that is, the period from the time t2 to the time t3 in FIG. 6 will be described.

When the ERRRAMP inverting input exceeds the second reference voltage Vref2, the output of the first comparator 1 changes from the logical value Low to the voltage level corresponding to the logical value High (at the time point of time t2 in FIG. 6D). reference).
Even if the output of the first comparator 1 has a voltage level corresponding to the logic value High, the output state of the first NOR circuit 3 changes because the soft start end signal has a voltage level corresponding to the logic value High. The voltage level corresponding to the logical value Low remains without any problem (see the time point at time t2 in FIG. 6 (g)).

Therefore, there is no change in the operation of the open / ground fault determination circuit 202 to which the output signal of the first NOR circuit 3 is input, and the output of the second comparator 2 remains at the voltage level corresponding to the logic value High. (See FIG. 6 (i)).
Therefore, there is no change in the circuit operation even in the delay processing circuit 203, and the state in which the detection signal is not output from the first output control circuit 18 and the second output control circuit 19 is maintained.

Next, the circuit operation from the end of the soft start time to the open state between the output terminal 31 and the feedback terminal 32, that is, the circuit operation during the period from time t3 to t4 in FIG. 6 will be described.
First, the soft start period ends when the soft start end signal changes from the logical value High to the voltage level corresponding to the logical value Low (see the time point at time t3 in FIG. 6 (f)).

At the end of the soft start period, the rotation path becomes a normal operating state.
When the soft start period ends and the normal operating state is entered, only the soft start end signal among the above-mentioned main signals changes from the logical value High to the voltage level corresponding to the logical value Low as described above. (Refer to the time point at time t3 in FIG. 6 (f)), the other signals are in the same state as before if the connection between the output terminal 31 and the feedback terminal 32 is normal (FIG. 6). See the period from time t3 to t4).
Therefore, there is no change in the circuit operation in the delay processing circuit 203, and the state in which the detection signal is not output from the first output control circuit 18 and the second output control circuit 19 is maintained.

Next, it is assumed that the output terminal 31 and the feedback terminal are in an open state at time t4 in FIG.
The ERRRAMP inverting input is lowered to the ground potential by the first resistor 316 (see time t4 in FIG. 6 (c)).
As a result, the ERRRAMP inverting input <the second reference voltage Vref2, so that the output of the first comparator 1 becomes the voltage level corresponding to the logical value Low from the logical value High (at time t4 in FIG. 6D). See time point).

Since the output of the first comparator 1 has a voltage level corresponding to the logical value Low, all three inputs of the first NOR circuit 3 have a voltage level corresponding to the logical value Low. Therefore, the first NOR circuit 3 The output VO_ERR (monitoring signal) of is a voltage level corresponding to the logical value High (see the time point at time t4 in FIG. 6 (g)).

When the output VO_ERR of the first NOR circuit 3 reaches a voltage level corresponding to the logical value High, the first MOS transistor 6 is turned off, while the fourth MOS transistor 9 is turned on.
FIG. 2 shows an open / ground fault determination circuit 202 in the case where the first MOS transistor 6 in this case is equivalent to a switch in an open state and the fourth MOS transistor 9 is equivalent to a switch in a closed state. The equivalent circuit diagram of the above is shown, and the change of the signal of the main part will be described below with reference to the figure.

First, when the first MOS transistor 6 is turned off, the second and third MOS transistors 7 and 8 are put into an operating state.
Further, when the fourth MOS transistor 9 is turned on, one end of the third resistor 11 connected to the drain of the fourth MOS transistor 9 is connected to the ground.

After all, the third resistor 11 is in a state of being connected in series between the connection point between the drain of the third MOS transistor 8 and the non-inverting input terminal of the second comparator 2 and the ground. (See FIG. 2).
Further, between the connection point between the drain of the third MOS transistor 8 and the non-inverting input terminal of the second comparator 2 and the ground, a fourth is ordered from the non-inverting input terminal side of the second comparator 2. The resistor 12, the second resistor 317, and the first resistor 316 are connected in series (see FIG. 2).

Therefore, between the connection point between the drain of the third MOS transistor 8 and the non-inverting input terminal of the second comparator 2 and the ground, a third resistor 11 and a fourth resistor in a series connection state are connected. 12, the second resistor 317, and the first resistor 316 are connected in parallel.
In FIG. 2, the notation of "FB = HIZ" at the mutual connection point between the second resistor 317 and the fourth resistor 12 means that this connection point is the connection point with the feedback terminal 32 in the open state. It means that it is in a high impedance state because it is there.

In such a connection state, the current IMONITOR from the third MOS transistor 8 is connected to the third resistor 11 in series by the operation of the current mirror circuit by the second and third MOS transistors 7 and 8. The voltage of the non-inverting input terminal of the second comparator 2 that flows into the resistor 12, the second resistor 317, and the first resistor 316 becomes the voltage level represented by the following equation 1.

VFBMONITOR (OPEN) = IMONITOR × {R3 // (R4 + R2 + R1)} ... Equation 1

R1 is the resistance value of the first resistor 316, R2 is the resistance value of the second resistor 317, R3 is the resistance value of the third resistor 11, and R4 is the resistance value of the fourth resistor 12. Suppose there is.
Further, {R3 // (R4 + R2 + R1)} means the parallel connection resistance value of the third resistor 11 and the series resistors of the first and second resistors 316 and 317 and the fourth resistor 12. do.

When setting the constants of each element, the output of the second comparator 2 can be output by appropriately setting the current value of the current IMONITOR and the resistance values of R1 to R4 so that VFBMONITOR (OPEN)> Vref3 is established. The determination signal) is a voltage corresponding to the logical value High (see the time point at time t4 in FIGS. 6 (h) and 6 (i)).

Then, at the time t4, in the delay processing circuit 203, the negative logic input terminal of the second NOR circuit 4 has a voltage level signal corresponding to the logic value High of the second comparator 2 described above. On the other hand, a signal having a voltage level corresponding to the logical value Low from the first comparator 1 is input to the other input end of the second NOR circuit 4. As a result, the second NOR circuit 4 outputs a signal having a voltage level corresponding to the logical value High (see the time point at time t4 in FIG. 6J), and serves as a trigger signal to the first delay circuit 14. It will be input.

As a result, the first delay circuit 14 has a voltage level corresponding to the logical value High after a predetermined delay time has elapsed from the time when the signal of the voltage level corresponding to the logical value High from the second NOR circuit 4 is input. The signal will be output (see the time point at time t5 in FIG. 6 (k).

On the other hand, at the time t4, in the third NOR circuit 5, a signal having a voltage level corresponding to the logic value High of the second comparator 2 is input, so that the output of the third NOR circuit 5 is logical. The state corresponds to the value Low (see FIG. 6 (m)). Therefore, unlike the first delay circuit 14, the output of the second delay circuit 15 remains at the voltage level corresponding to the logic value Low (see FIG. 6 (n)).

The voltage level signal corresponding to the logical value High from the first delay circuit 14 is input to one input terminal of the first AND circuit 16, while at this time, the other input terminal is connected to the previous first. A signal with a voltage level corresponding to the logical value High of the comparator 2 of 2 is input. As a result, the opening detection signal OPEN of the voltage level corresponding to the logical value High corresponding to the detection of the opening of the feedback terminal 32 is output from the first AND circuit 16 (FIG. 6 (l). ) Time t5).
From the first output control circuit 18, a signal of a required voltage level is output according to the open detection signal from the first AND circuit 16.

On the other hand, in this case, since the output of the second delay circuit 15 is in a state corresponding to the logical value Low as described above, the output of the second AND circuit 17 is also in a state corresponding to the logical value Low. Is. Therefore, no signal is output from the second output circuit 19.

Next, the circuit operation when a ground fault occurs between the output terminal 31 and the feedback terminal 32 will be described with reference to FIG. 7.
First, the circuit operation from the switching power supply circuit 301 being activated by turning on a power supply switch or the like (not shown) to start normal operation until the output terminal 31 and the feedback terminal 32 are in a ground fault state is shown in FIG. Since the circuit operation until the output terminal 31 and the feedback terminal 32 are opened is basically the same as the circuit operation described with reference to the above, detailed description here will be omitted.

Next, it is assumed that the output terminal 31 and the feedback terminal 32 are in a ground fault state at the time t4 in FIG. 7.
When the output terminal 31 and the feedback terminal 32 are in a ground fault state, the connection point between the second resistor 317 and the fourth resistor 12 is connected to the ground.
Therefore, the non-inverting input terminal of the first comparator 1 becomes the ground potential, and the output of the first comparator 1 becomes a state corresponding to the logical value Low (see the time point at time t4 in FIG. 7D).

As a result, all three inputs of the first NOR circuit 3 are in a state corresponding to the logical value Low, so that the output VO_ERR of the first NOR circuit 3 has a voltage level corresponding to the logical value High (FIG. 7). (Refer to the time point at time t4 in g)).
When the output VO_ERR (monitoring signal) of the first NOR circuit 3 reaches a voltage level corresponding to the logic value High, the first MOS transistor 6 is turned off, while the fourth MOS transistor 9 is turned on. ..

FIG. 3 shows an open / ground fault determination circuit 202 in the case where the first MOS transistor 6 in this case is equivalent to a switch in an open state and the fourth MOS transistor 9 is equivalent to a switch in a closed state. The equivalent circuit diagram of the above is shown, and the change of the signal of the main part will be described below with reference to the figure.
First, when the first MOS transistor 6 is turned off, the second and third MOS transistors 7 and 8 are put into an operating state.

When the fourth MOS transistor 9 is turned on, one end of the third resistor 11 connected to the drain of the fourth MOS transistor 9 is connected to the ground.
As a result, the third resistor 11 and the fourth resistor 12 are connected in parallel between the non-inverting input terminal of the second comparator 2 and the ground (see FIG. 3).

In such a connection state, the current IMONITOR flows from the third MOS transistor 8 into the parallel connection portion of the third resistor 11 and the fourth resistor 12, and the voltage of the non-inverting input terminal of the second comparator 2 is set. It is the voltage level represented by the following equation 2.

VFBMONITOR (SHORT) = IMONITOR × (R3 // R4) ・ ・ ・ Equation 2

Here, (R3 // R4) means the parallel connection resistance value of the third resistor 11 and the fourth resistor 12.
The voltage represented by the formula 2 is lower than the voltage represented by the formula 1 because there is no (R2 + R3) unlike the voltage of the formula 1.
Therefore, when setting the constants of each element, the current value of the current IMONITOR and the resistance values of R3 and R4 are appropriately set so that VFBMONITOR (SHORT) <Vref3 is satisfied. The output (determination signal) has a voltage corresponding to the logical value Low (see the time point of time t4 in FIGS. 7 (h) and 7 (i)).

When the output of the second comparator 2 is in the state of the logical value Low, the output of the second NOR circuit 4 is in the state corresponding to the logical value Low (see the time point at time t4 in FIG. 7 (j)). On the other hand, the output of the third NOR circuit 5 is in a state corresponding to the logical value High (see the time point at time t4 in FIG. 7 (m)).

The voltage level signal corresponding to the logic value High of the third NOR circuit 5 is input to the second delay circuit 15 as a trigger signal.
As a result, the second delay circuit 15 has a voltage level corresponding to the logical value High after a predetermined delay time has elapsed from the time when the signal of the voltage level corresponding to the logical value High from the third NOR circuit 5 is input. A signal will be output (see the time point at time t5 in FIG. 7 (n)).

On the other hand, since the output of the second NOR circuit 4 is in the state of the logical value Low (see the time point at time t4 in FIG. 7 (j)), there is no input of the trigger signal to the first delay circuit 14, and the second is No signal is output from the delay circuit 14 of 1.
Therefore, since the AND of the input signal of the first AND circuit 16 is not established, there is no output of the signal from the first AND circuit 16 and no output of the signal from the first output control circuit 18.

On the other hand, since the AND condition of the input signal is satisfied in the second AND circuit 17, the logical value High corresponding to the detection of the ground fault between the output terminal 31 and the feedback terminal 32 from the second AND circuit 17 A ground fault detection signal SHORT having a voltage level corresponding to is output (see the time point at time t5 in FIG. 7 (o)).
From the second output control circuit 19, a signal of a required voltage level is output according to the ground fault detection signal from the second AND circuit 17.

Here, a setting example of specific circuit constants of the first and second resistors 316 and 317, the third and fourth resistors 11 and 12, and IMONITOR will be described.
For example, it is assumed that IMONITOR = 30 μA, R1 = 30 kΩ, R2 = 120 kΩ, R3 = 360 kΩ, R4 = 40 kΩ, and the third reference voltage Vref3 = 2 V. Further, it is preferable that the ON resistance of the fourth MOS transistor 9 is set sufficiently smaller than that of R3 and R4.
Under these conditions, the voltages VFBMONITOR (OPEN) and VFBMONITOR (SHORT) of the non-inverting input terminal of the second comparator 2 are as follows.

First, VFBMONITOR (OPEN) becomes VFBMONITOR (OPEN) = 30 μA × {360 kΩ // (40 kΩ + 120 kΩ + 30 kΩ)} = 30 μA × 124.36 kΩ = 3.73 V, and VFBMONITOR (OPEN)> Vref3 is established.

On the other hand, for VFBMONITOR (SHORT), VFBMONITOR (SHORT) = 30 μA × (360 kΩ // 40 kΩ) = 30 μA × 36 kΩ = 1.08 V, and VFBMONITOR (SHORT) <Vref3 is established.

As described above, in the opening / opening / ground fault determination circuit 202 of the embodiment of the present invention, the second comparator 2 is opened according to the opening / ground fault between the output terminal 31 and the feedback terminal 32. Different voltages are generated at each of the non-inverting input terminals, and detection signals can be output according to the open and ground faults.

Basically, the output signal of the open / ground fault determination circuit 202 can be used as the open / ground fault detection result, but in reality, the load 315 suddenly fluctuates due to the load transient response characteristics and the like. In that case, there is a risk of false detection. Therefore, in the embodiment of the present invention, the delay processing circuit 203 is provided and a delay time is provided for the determination result of the open / ground fault determination circuit 202 to prevent erroneous detection.

FIG. 8 shows a truth table listing the signal states of the main parts in the above-mentioned open / ground fault detection, and the figure will be described below.
In the figure, four circuit operating states, that is, "from the start of the switching power supply circuit 301 to the end of the soft start", "normal operation", "opening between the output terminal 31 and the feedback terminal 32", "output terminal 31 and feedback". The output of the first NOR circuit 3 of the feedback terminal voltage monitoring circuit 201, the output of the second comparator 2 of the open / ground fault determination circuit 202, the first of the delay processing circuit 203, and the output of the second comparator 2 of the feedback terminal voltage monitoring circuit 201 in each of the "ground faults between terminals 32". The truth values of the outputs of the second AND circuits 16 and 17 are shown.
In FIG. 8, the notation "HiZ" as the output of the second comparator 2 of the open / ground fault determination circuit 202 means that the impedance is high.

The truth values shown in FIG. 8 summarize the states of the corresponding output signals in the circuit operation described above with reference to FIGS. 6 and 7. Therefore, the individual truth values are described here. The detailed explanation of the above will be omitted.

Next, a second configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This second configuration example is configured to perform only open detection.

That is, the delay processing circuit 203A in the second configuration example has a second NOR circuit 4, a first delay circuit 14, a first AND circuit 16, and a first output control circuit 18. It is composed of.
Unlike the delay processing circuit 203 in FIG. 1, the delay processing circuit 203A has a third NOR circuit 5, a second delay circuit 15, a second AND circuit 17, and a second AND circuit 17, which are necessary for generating a ground fault detection signal. , The second output control circuit 19 is omitted.
Since the circuit operation in the open detection is the same as that of the first configuration example shown in FIG. 1, detailed description here will be omitted.

Next, a third configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
This third configuration example is configured to perform only ground fault detection.

That is, the delay processing circuit 203B in the third configuration example has a third NOR circuit 5, a second delay circuit 15, a second AND circuit 17, and a second output control circuit 19. It is composed of.
Unlike the delay processing circuit 203 in FIG. 1, the delay processing circuit 203B has a second NOR circuit 4, a first delay circuit 14, a first AND circuit 16, and a second NOR circuit required for generating an open detection signal. The configuration is such that the first output control circuit 18 is omitted.
Since the circuit operation in ground fault detection is the same as that of the first configuration example shown in FIG. 1, detailed description here will be omitted.

It can be applied to a power supply circuit in which detection that distinguishes between openness between the output terminal and the feedback terminal and ground fault is desired with a configuration as simple as possible.

201 ... Feedback terminal Voltage monitoring circuit 202 ... Open / ground fault determination circuit 203, 203A, 203B ... Delay processing circuit 301 ... Switching power supply circuit

Claims (1)

The output voltage obtained from the output terminal is used for feedback control via the feedback terminal to detect the opening and ground fault between the output terminal and the feedback terminal in a power supply circuit configured to be able to control the output of the output voltage. It is an open / ground fault detection circuit.
A feedback voltage monitoring circuit that monitors whether the voltage of the feedback terminal is normal and outputs a monitoring signal according to the monitoring result.
When a predetermined monitoring signal indicating that the feedback voltage is not normal is output by the feedback voltage monitoring circuit, the feedback voltage is the voltage corresponding to the opening between the output terminal and the feedback terminal, or the feedback. An open / ground fault determination circuit that determines whether the voltage is the voltage corresponding to the ground fault between the output terminal and the feedback terminal and outputs a determination signal according to the determination result.
It is provided with a delay processing circuit that delays the output of the open / ground fault determination circuit and outputs the circuit.
The open / ground fault determination circuit has a comparator in which a reference voltage is set in the inverting input terminal, and the output terminal and the feedback terminal are in an open state, and the feedback voltage is not normal due to the feedback voltage monitoring circuit. When a predetermined monitoring signal is output, an applied voltage to the non-inverting input terminal of the comparator that exceeds the reference voltage of the comparator is generated, while the output terminal and the feedback terminal are short-circuited, and the above-mentioned When a predetermined monitoring signal indicating that the feedback voltage is not normal is output by the feedback voltage monitoring circuit, an applied voltage to the non-inverting input terminal of the comparator, which is lower than the reference voltage of the comparator, is generated, and the output terminal is used. When the feedback terminal is open, the comparator determines the output voltage corresponding to the logical value High, and when the output terminal and the feedback terminal are short-circuited, the comparator determines the output voltage as the determination signal. An open / ground fault detection circuit characterized in that the output voltage corresponding to the value Low is configured so that each can be output .

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