JP7013839B2 - Domain wall analog memory, non-volatile logic circuit and magnetic neuro element - Google Patents

Description

The present invention relates to a domain wall -based analog memory, a non-volatile logic circuit, and a magnetic neuro element.

As a next-generation non-volatile memory that replaces flash memory, which has reached its limit in miniaturization, resistance-change memory that records data using resistance-change elements, for example, MRAM (Magnetroresistive Random Access Memory), ReRAM (Resistancne) Random Access Memory), PCRAM (Phase Change Random Access Memory), etc. are attracting attention.

As a method of increasing the density (large capacity) of the memory, there are various methods of increasing the recording bit per element constituting the memory, in addition to the method of reducing the size of the element itself constituting the memory. Various multi-valued methods have been proposed (for example, Patent Documents 1 to 3).

Further, Patent Document 4 and Patent Document 5 describe multi-value recording and analog recording using a domain wall-based MRAM. The domain wall-based MRAM writes data by passing a current in the in-plane direction of the domain wall drive layer (magnetization free layer) and reversing the magnetization of the ferromagnetic film in a direction corresponding to the direction of the write current. The domain wall of the domain wall drive layer moves due to the spin transfer effect due to the spin-polarized electrons.

On the other hand, at the time of reading, the domain wall-based MRAM data the resistance value change of the magnetoresistive effect element that changes according to the relative relationship between the magnetization direction of the magnetization fixed layer and the average magnetization direction of the central region of the magnetization recording layer. Read as. The average magnetization direction of the central region of the magnetization recording layer changes according to the magnetization state (position of the domain wall) of the central region of the magnetization recording layer. Further, Patent Document 5 describes an example in which a domain wall-based MRAM is used in a current reading circuit of a memory array. One end of the domain wall drive layer is grounded, and the current from the memory array is input to the other fixed magnetization region. Depending on the direction of the current, the magnetization direction of the domain wall layer becomes parallel to or antiparallel to the magnetization fixed layer, and thus functions as a current mode comparator.

Japanese Unexamined Patent Publication No. 2015-88669 International Publication No. 2009/072213 Japanese Unexamined Patent Publication No. 2016-4924 International Publication No. 2009/101827 U.S. Pat. No. 9,489,618

However, Patent Document 4 only describes reading data by changing the resistance value of the magnetoresistive element, and does not describe how the read current should be applied. Therefore, the resistance value change that changes according to the magnetization state (position of the domain wall) is not linear, and there is a case that the information written in multiple values cannot be read out stably. In Patent Document 5, the purpose is not to store information but to detect a bit line current, and only to provide a function equivalent to reading a conventional binary memory.

The present invention has been made in view of the above circumstances, and provides a domain wall-based analog memory element, a domain wall-based analog memory, a non-volatile logic circuit, and a magnetic neuro element capable of stably reading analog recorded data. The purpose is.

The present invention provides the following means for solving the above problems.

(1) The magnetic wall-based analog memory element according to the first aspect includes a magnetization-fixed layer in which magnetization is oriented in the first direction, a non-magnetic layer provided on one surface of the magnetization-fixed layer, and the first. It has a first region in which magnetization is oriented in a direction, a second region in which magnetization is oriented in a second direction opposite to the first direction, and a magnetic wall forming an interface between these regions, and the magnetization is fixed. A magnetic wall drive layer provided with the non-magnetic layer interposed therebetween, and a current control means for passing a current between the magnetization fixing layer and the second region at the time of readout are provided.

(2) In the domain wall utilization type analog memory element according to the above aspect, the first magnetization supply means for supplying the magnetization oriented in the first direction and the magnetization oriented in the second direction are supplied to the domain wall drive layer. Further having a second magnetization supply means, at least one of the first magnetization supply means and the second magnetization supply means is in contact with the domain wall drive layer and is oriented in the first direction or the second direction. It may be a magnetization supply layer having a magnetized state.

(3) In the domain wall utilization type analog memory element according to the above aspect, the first magnetization supply means for supplying the magnetization oriented in the first direction and the magnetization oriented in the second direction are supplied to the domain wall drive layer. Further having a second magnetization supply means, at least one of the first magnetization supply means and the second magnetization supply means is electrically insulated from the domain wall drive layer and intersects with the domain wall drive layer. The wiring may extend in the direction.

(4) In the domain wall utilization type analog memory element according to the above aspect, the first magnetization supply means for supplying the magnetization oriented in the first direction and the magnetization oriented in the second direction are supplied to the domain wall drive layer. Further having a second magnetization supply means, at least one of the first magnetization supply means and the second magnetization supply means is in contact with the domain wall drive layer and extends in a direction intersecting with the domain wall drive layer. It may be a spin orbit torque wiring to be magnetized.

(5) In the domain wall utilization type analog memory element according to the above aspect, the first magnetization supply means for supplying the magnetization oriented in the first direction and the magnetization oriented in the second direction are supplied to the domain wall drive layer. Further having a second magnetization supply means, even if at least one of the first magnetization supply means and the second magnetization supply means is a voltage application means connected to the domain wall drive layer via an insulating layer. good.

(6) In the domain wall-based analog memory element according to the above aspect, the current control means may be a potential control means that sets the potential of the second region lower than the potential of the magnetization fixed layer at the time of reading.

(7) In the domain wall-based alog memory element according to the above aspect, the current control means may be a rectifying element that controls the current flow direction.

(8) The domain wall-based analog memory according to the second aspect includes a plurality of domain wall-based analog memory elements according to the above aspect.

(9) In the non-volatile logic circuit according to the third aspect, the domain wall-based analog memory according to the above aspect is arranged in an array, and the STT-MRAM is provided in or in the array or in a storage function. The domain wall-based analog memory and the STT-MRAM are provided as storage functions.

(10) The magnetic neuro element according to the fourth aspect includes the magnetic domain wall utilization type analog memory element according to the above aspect, and the domain wall drive layer includes a first storage unit arranged in the longitudinal direction and the first storage unit. It has a second storage unit and a third storage unit to be sandwiched, and the domain wall is moved in order so as to stay in all the storage units of the first storage unit, the second storage unit, and the third storage unit at least once. It comprises a current source having a control circuit for controlling the write current obtained.

According to the domain wall-based analog memory element of the present invention, data can be recorded in multiple values or analog, and these data can be stably read out.

It is sectional drawing of an example of the domain wall use type analog memory element which concerns on 1st Embodiment. It is a figure which shows the writing operation of the domain wall use type analog memory element which concerns on 1st Embodiment. It is a figure which shows the reading operation of the domain wall use type analog memory element which concerns on 1st Embodiment. It is a figure which shows a part of the circuit at the time of reading a data schematically, and (a) is the magnetization which the magnetization of the magnetization fixed layer and the orientation direction are opposite to each other like the magnetic wall utilization type analog memory element which concerns on this embodiment. It is a circuit diagram in the case where the read-out current is passed in the existing direction, and (b) is the circuit diagram in the case where the readout current is passed in the direction in which the magnetization and the orientation direction of the magnetization fixed layer are the same. It is a perspective schematic diagram of the domain wall utilization type analog memory element which concerns on 2nd Embodiment. It is a perspective schematic diagram of another example of the domain wall utilization type analog memory element which concerns on 2nd Embodiment. It is a perspective schematic diagram of the domain wall utilization type analog memory element which concerns on 3rd Embodiment. It is a perspective schematic diagram of the domain wall utilization type analog memory element which concerns on 4th Embodiment. It is a perspective schematic diagram of another example of the domain wall utilization type analog memory element which concerns on 4th Embodiment. It is a figure which showed typically an example of the circuit structure of the domain wall use type analog memory which concerns on this embodiment. It is sectional drawing of an example of the magnetic neuro element which concerns on this embodiment. It is a figure which shows the concept of the artificial brain using the magnetic neuro element which concerns on this embodiment. This is a product-sum calculation circuit in which magnetic neuroelements according to the present embodiment are arranged in an array.

Hereinafter, the configuration of this embodiment will be described with reference to the drawings. In the drawings used in the following description, the featured portion may be enlarged for convenience in order to make the feature easy to understand, and the dimensional ratio of each component may not be the same as the actual one. Further, the materials, dimensions, etc. exemplified in the following description are examples, and the present invention is not limited thereto.

"First embodiment"
(Analog memory element using domain wall)
FIG. 1 is a schematic cross-sectional view of an example of a domain wall-based analog memory element according to the first embodiment. The domain wall-based analog memory element shown in FIG. 1 includes a magnetization fixing layer 1, a non-magnetic layer 2, a domain wall drive layer 3, a first magnetization supply layer 4, a second magnetization supply layer 5, and a current control means ( (Not shown).

In FIG. 1, the stacking direction of each layer, that is, the direction orthogonal to the main surface of each layer (direct plane direction) is defined as the Z direction. Each layer is formed parallel to the XY plane orthogonal to the Z direction.

"Magnetized fixed layer"
The magnetization fixed layer 1 is a layer in which the magnetization M1 is oriented and fixed in the first direction. Here, the fact that the magnetization is fixed means that the magnetization direction does not change (the magnetization is fixed) before and after writing using the write current.

In the example shown in FIG. 1, the magnetization fixed layer 1 is an in-plane magnetization film in which the magnetization M1 has in-plane magnetic anisotropy (in-plane magnetization easy axis). The magnetization fixing layer 1 is not limited to the in-plane magnetization film, and may be a perpendicular magnetization film having perpendicular magnetic anisotropy (perpendicular magnetization easy axis).

When the magnetization fixing layer 1 is an in-plane magnetizing film, it has a high MR ratio, is not easily affected by the spin transfer torque (STT) at the time of reading, and can increase the reading voltage. On the other hand, when it is desired to miniaturize the device, it is preferable to use a perpendicular magnetization film having a large magnetic anisotropy and a small demagnetizing field. Perpendicular magnetized films are highly resistant to thermal disturbance, so data is difficult to erase.

A known material can be used for the magnetization fixing layer 1. For example, a metal selected from the group consisting of Cr, Mn, Co, Fe and Ni and an alloy containing one or more of these metals and exhibiting ferromagnetism can be used. Also, alloys containing these metals and at least one or more elements of B, C, and N can be used. Specific examples thereof include Co-Fe and Co-Fe-B.

Further, a Whistler alloy such as Co ₂ FeSi can be used for the magnetization fixing layer 1. The Whisler alloy contains an intermetallic compound with a chemical composition of X ₂ YZ, where X is a Co, Fe, Ni or Cu group transition metal element or noble metal element on the periodic table, where Y is Mn, V. , Cr or Ti is a transition metal and can take the elemental species of X, and Z is a typical element of groups III to V. For example, Co ₂ FeSi, Co ₂ MnSi, Co ₂ Mn _1-a Fe _a Al _b Si _1-b and the like can be mentioned.

Further, the magnetization fixing layer 1 may have a synthetic structure composed of an antiferromagnetic layer, a ferromagnetic layer, and a non-magnetic layer. In the synthetic structure, the magnetization direction of the magnetization fixed layer 1 is strongly held by the antiferromagnetic layer. Therefore, the magnetization of the magnetization fixed layer 1 is less likely to be affected from the outside.

When the magnetization of the magnetization fixing layer 1 is oriented in the XY plane (the magnetization fixing layer 1 is made into an in-plane magnetization film), for example, NiFe is preferably used. On the other hand, when the magnetization of the magnetization fixing layer 1 is oriented in the Z direction (the magnetization fixing layer 1 is made a perpendicular magnetization film), for example, it is preferable to use a Co / Ni laminated film, a Co / Pt laminated film, or the like. For example, the magnetization fixing layer 1 is [Co (0.24 nm) / Pt (0.16 nm)] ₆ / Ru (0.9 nm) / [Pt (0.16 nm) / Co (0.16 nm)] ₄ / Ta ( When 0.2 nm) / FeB (1.0 nm), a perpendicular magnetization film is obtained.

"Non-magnetic layer"
The non-magnetic layer 2 is provided on one surface of the magnetization fixing layer 1. The domain wall-based analog memory element 100 reads out a change in the magnetization state of the domain wall drive layer 3 with respect to the magnetization fixed layer 1 via the non-magnetic layer 2 as a resistance value change. That is, the magnetization fixing layer 1, the non-magnetic layer 2 and the magnetic wall drive layer 3 function as a magnetoresistive effect element, and when the non-magnetic layer 2 is made of an insulator, the configuration is similar to that of a tunnel magnetoresistive (TMR) element. When the non-magnetic layer 2 is made of metal, it has a configuration similar to that of a giant magnetoresistive (GMR) element.

As the material of the non-magnetic layer 2, a known material that can be used for the non-magnetic layer of the magnetoresistive sensor can be used. When the non-magnetic layer 2 is made of an insulator (when it is a tunnel barrier layer), the materials thereof are Al ₂ O ₃ , SiO ₂ , MgO, MgAl ₂ O ₄ , ZnAl ₂ O ₄ , MgGa ₂ O ₄ , ZnGa ₂ O. ₄ , MgIn ₂ O ₄ , ZnIn ₂ O ₄ , and a multilayer film or a mixed composition film of these materials can be used. In addition to these, a material in which a part of Al, Si, and Mg is replaced with Zn, Be, or the like can also be used. Among these, _MgO and _MgAl2O4 are materials that can realize a coherent tunnel, so that spin can be efficiently injected. On the other hand, when the non-magnetic layer 2 is made of metal, Cu, Al, Ag or the like can be used as the material.

"Domain wall drive layer 3"
The domain wall drive layer 3 is a magnetization free layer made of a ferromagnetic material, and the direction of magnetization inside the magnetic wall drive layer 3 can be reversed. The domain wall drive layer 3 includes a first region 3a in which the magnetization M3a is oriented in the same first direction as the magnetization fixing layer 1, and a second region 3b in which the magnetization M3b is oriented in the second direction opposite to the first direction. It has a domain wall DW forming an interface between these regions. The directions of magnetization of the first region 3a and the second region 3b are opposite to each other across the domain wall DW. The domain wall DW moves as the composition ratio of the first region 3a and the second region 3b in the domain wall drive layer 3 changes.

As the material of the domain wall drive layer 3, a known material that can be used for the magnetization free layer of the magnetoresistive element can be used, and a soft magnetic material can be particularly applied. For example, a metal selected from the group consisting of Cr, Mn, Co, Fe and Ni, an alloy containing one or more of these metals, these metals and at least one or more elements of B, C and N are contained. It is possible to use an alloy or the like. Specifically, Co—Fe, Co—Fe—B, and Ni—Fe are mentioned as materials for the domain wall drive layer 3.

As the material of the domain wall drive layer 3, a material having a small saturation magnetization can also be used. For example, if a material having a small saturation magnetization such as MnGaAs or InFeAs is used, the domain wall DW of the domain wall drive layer 3 can be driven with a small current density. Further, when these materials are used, the driving speed of the domain wall DW becomes slow, and the magnetic wall DW can be suitably used as an analog memory.

In a material having a weak magnetic anisotropy such as NiFe, the drive speed of the domain wall DW is high, and the domain wall DW operates at a speed of 100 m / sec or more. That is, the domain wall DW travels a distance of 1 μm with a pulse of 10 nsec. Therefore, when the domain wall drive layer 3 is moved in an analog manner in the element, it is possible to apply a minute pulse by using an expensive semiconductor circuit or to make the domain wall drive layer sufficiently long at the expense of the degree of integration. You will need it. On the other hand, in the case of a material having a slow drive speed of the domain wall DW, it is possible to form an analog memory even when a sufficiently long pulse current is applied or the length of the domain wall drive layer 3 is short.

For the domain wall drive layer 3, it is preferable to use a perpendicular magnetization film of Mn ₃ X (X = Ga, Ge) or a perpendicular magnetization film made of a multilayer film such as Co / Ni, Co / Pt. These materials can drive the domain wall DW even if the current density for driving the domain wall is small.

The length of the domain wall drive layer 3 extending in the X direction is preferably 60 nm or more. If it is less than 60 nm, it tends to be a single magnetic domain, and it is difficult for the domain wall DW to be formed in the domain wall drive layer 3.

The thickness of the domain wall drive layer 3 is not particularly limited as long as it functions as the domain wall drive layer, but can be, for example, 2 to 60 nm. When the thickness of the domain wall drive layer 3 is 60 nm or more, the possibility that the domain wall is formed in the stacking direction increases. However, whether or not the domain wall is formed in the stacking direction depends on the balance with the shape anisotropy of the domain wall drive layer 3. If the thickness of the domain wall drive layer 3 is less than 60 nm, it is unlikely that the domain wall DW can be formed.

The domain wall drive layer 3 may have a domain wall pinning portion on the side surface of the layer to stop the movement of the domain wall DW. For example, if an unevenness, a groove, a bulge, a constriction, a notch, or the like is provided at a position where the movement of the domain wall DW of the domain wall drive layer 3 is desired to be stopped, the movement of the domain wall can be stopped (pinned). If the domain wall pinning portion is provided, the domain wall can be configured so that the domain wall does not move any more unless a current equal to or higher than the threshold value is passed, and the output signal is not analog and tends to be multi-valued.

For example, by forming the domain wall pinning portion at predetermined distances, the domain wall DW can be held more stably, stable multi-value recording is possible, and more stable multi-valued output is possible. Allows the signal to be read.

"1st magnetization supply layer, 2nd magnetization supply layer"
The first magnetization supply layer 4 and the second magnetization supply layer 5 are one aspect of the magnetization supply means for supplying magnetization to the domain wall drive layer 3. When a write current flows between the magnetization fixing layer 1 and the first magnetization supply layer 4 or the second magnetization supply layer 5, magnetization is generated from the first magnetization supply layer 4 or the second magnetization supply layer 5 to the domain wall drive layer 3. Be supplied.

The first magnetization supply layer 4 and the second magnetization supply layer 5 are both layers (ferromagnetic layers) made of a ferromagnetic material having fixed magnetization. The magnetization M4 of the first magnetization supply layer 4 is oriented in the same direction as the magnetization M3a of the first region 3a of the domain wall drive layer 3 in contact with the first magnetization supply layer 4. That is, the magnetization M4 of the first magnetization supply layer 4 is oriented in the same direction as the magnetization M1 of the magnetization fixing layer 1. On the other hand, the magnetization M5 of the second magnetization supply layer 5 is oriented in the same direction as the magnetization M3b of the second region 3b of the domain wall drive layer 3 in contact with the second magnetization supply layer 5. That is, the magnetization M5 of the second magnetization supply layer 5 is oriented in the direction opposite to the magnetization M1 of the magnetization fixed layer 1.

In FIG. 1, the first magnetization supply layer 4 and the second magnetization supply layer 5 are arranged on the opposite side to the magnetization fixing layer 1 with reference to the domain wall drive layer 3. The first magnetization supply layer 4 and the second magnetization supply layer 5 may be arranged on the same surface side as the magnetization fixing layer 1 with reference to the domain wall drive layer 3.

When the first magnetization supply layer 4 and the second magnetization supply layer 5 are arranged on the opposite side of the magnetization fixing layer 1 with respect to the domain wall drive layer 3, the magnetization M1 of the magnetization fixation layer 1 is the first magnetization supply layer. The influence of the magnetization M4 of 4 and the magnetization M5 of the second magnetization supply layer 5 can be reduced. On the other hand, when the first magnetization supply layer 4 and the second magnetization supply layer 5 are arranged on the same surface side as the magnetization fixing layer 1 with reference to the domain wall drive layer 3, the first magnetization supply layer 4 and the second magnetization supply layer 5 are arranged. 2 It is not necessary to match the heights of the surfaces of the magnetization supply layer 5 on which the domain wall drive layer 3 is formed, which facilitates the manufacture of the domain wall-based analog memory element 100.

Further, in principle, the direction of magnetization of the portion of the domain wall drive layer 3 in contact with the first magnetization supply layer 4 and the second magnetization supply layer 5 is not rewritten. This is because the first magnetization supply layer 4 and the second magnetization supply layer 5 and the domain wall drive layer 3 are magnetically coupled and stabilized. Therefore, when the first magnetization supply layer 4 and the second magnetization supply layer 5 are used as the magnetization supply means, even if the domain wall DW is moved, the domain wall DW is in contact with the first magnetization supply layer 4 and the second magnetization supply layer 5. In principle, it does not move to the outside (X direction). By limiting the movable range of the domain wall DW, it is possible to prevent the domain wall DW from disappearing and becoming a single magnetic domain during operation.

The same material as the magnetization fixing layer 1 can be used for the first magnetization supply layer 4 and the second magnetization supply layer 5. The orientation direction of the magnetization M4 of the first magnetization supply layer 4 and the magnetization M5 of the second magnetization supply layer 5 is set in advance by an external magnetic field or the like.

"Current control means"
The current control means is a control means for controlling the current to flow from the magnetization fixed layer 1 to the second region 3b side of the domain wall drive layer 3 at the time of reading.

As one of the current control means, there is a potential control means that adjusts the potentials of the magnetization fixed layer 1, the first region 3a, and the second region 3b at the time of reading. For example, the magnetization-fixed layer 1 and the first region 3a are set to equipotential, and the potential of the second region 3b is set lower than the potential of the magnetization-fixed layer 1. With this setting, a current flows from the magnetization fixed layer 1 toward the second region 3b at the time of reading.

In addition to this, a rectifying element such as a diode may be used as the current control means. A diode or the like may be used to control the current to flow from the magnetization fixed layer 1 toward the second region 3b at the time of reading.

(Operation of analog memory element using domain wall)
Next, the operating principle of writing and reading data of the domain wall-based analog memory element according to the present embodiment will be described.

"Write operation"
First, the writing operation will be described. In the domain wall-based analog memory element, writing is performed using a magnetoresistive effect such as a GMR (Giant Magneto Resistance) effect or a TMR (Tunnel Magneto Resistance) effect. For the magnetoresistive effect, for example, the resistance value state caused by the directions of magnetization of two ferromagnetic layers laminated via a non-magnetic layer being parallel or antiparallel is associated as "0" or "1". Record with. Since the direction of magnetization does not change unless an external force is applied, the data is recorded non-volatilely.

At the time of writing, data is recorded by changing the orientation direction of the magnetizations M3a and M3b of the domain wall drive layer 3 with respect to the magnetization M1 of the magnetization fixed layer 1. Therefore, at the time of writing, the state of magnetization of the domain wall drive layer 3 is rewritten. The state of magnetization of the domain wall drive layer 3 is also rewritten by passing a writing current from one end to the other end of the domain wall drive layer 3. When a current exceeding the threshold value is passed in the direction (X direction) penetrating the domain wall DW, a spin polarization current is generated in the domain (magnetic domain) of the domain wall drive layer 3, and conduction electrons are transmitted to the domain wall DW in the domain wall drive layer 3. Move in the direction of flow.

FIG. 2 is a diagram showing a writing operation of the domain wall-based analog memory element 100 according to the present embodiment.
For example, when the current I _W1 is passed from the first magnetization supply layer 4 to the second magnetization supply layer 5 via the domain wall drive layer 3 in the direction shown by the dotted line in FIG. 2 (a), the conduction electron e ₁ is the current I. The current flows in the direction indicated by the solid line, which is opposite to the direction of _W1 . When the conduction electron e ₁ enters the domain wall drive layer 3 from the second magnetization supply layer 5, the conduction electron e ₁ magnetizes the domain magnetically coupled to the second magnetization supply layer 5 and the second magnetization supply layer 5 of the domain wall drive layer 3. It becomes a spin-polarized electron corresponding to the direction of M3b. When the spin-polarized electrons reach the domain wall DW, the spins of the spin-polarized electrons cause spin transfer to the domain wall DW, and the domain wall DW moves in the same direction as the conduction electron _e1 flows. That is, the domain wall DW moves from the left to the right in FIG. 2A.

Similarly, when a current I _W2 is passed from the second magnetization supply layer 5 to the first magnetization supply layer 4 via the domain wall drive layer 3 in the direction shown by the dotted line in FIG. 2 (b), the conduction electron e ₂ becomes a current. The current flows in the direction indicated by the solid line, which is opposite to the direction of I _W2 . When the conduction electron e ₂ enters the domain wall drive layer 3 from the first magnetization supply layer 4, the conduction electron e ₂ magnetizes the domain magnetically coupled to the first magnetization supply layer 4 and the first magnetization supply layer 4 of the domain wall drive layer 3. The spin polarization current corresponds to the direction of M3a. When the spin-polarized electrons reach the domain wall DW, the spins of the spin-polarized electrons in the domain wall DW cause spin transfer to the domain wall DW, and the domain wall DW moves in the same direction as the conduction electron _e2 flows. That is, the domain wall DW moves from right to left in FIG. 2 (b).

When the position of the domain wall DW fluctuates, the magnetization state of the portion of the domain wall drive layer 3 in contact with the magnetization fixing layer 1 changes. For example, as shown in FIG. 2A, the case where the magnetization state of the portion of the domain wall drive layer 3 in contact with the magnetization fixed layer 1 is antiparallel to the magnetization M1 of the magnetization fixed layer 1 is “0”, FIG. 2 (a). ), The data can be recorded in binary by setting the case where the magnetization state of the portion of the domain wall drive layer 3 in contact with the magnetization fixing layer 1 is parallel to the magnetization M1 of the magnetization fixing layer 1 as “1”. Further, when the domain wall DW is present at the portion of the domain wall drive layer 3 in contact with the magnetization fixed layer 1, a plurality of threshold values are set for the resistance value that fluctuates due to the change in the composition ratio of the magnetization M3a and the magnetization M3b in the domain wall drive layer 3. Therefore, the data can be recorded in multiple values.

Further, the moving amount (moving distance) of the domain wall DW can be variably controlled by adjusting the magnitude and time of the writing current. For the magnitude and time of the write current, for example, the movement amount (movement distance) of the domain wall DW may be set according to the number of pulses or the pulse width.

"Read operation"
Next, the data reading operation will be described. FIG. 3 is a diagram showing a read operation of the domain wall-based analog memory element 100 according to the present embodiment.

As shown in FIG. 3, when reading data, a current IR is passed between the _{magnetization} fixing layer 1 and the second region 3b of the domain wall drive layer 3. The flow direction of the current _IR is controlled by the current control means. By passing a current IR in the direction in which the magnetization _M3b whose orientation direction is opposite to that of the magnetization M1 of the magnetization fixed layer 1 exists, the resistance value change of the domain wall-based analog memory element 100 becomes linear, and more accurate data can be obtained. It can be read by value.

The magnetization M3a of the first region 3a of the domain wall drive layer 3 is oriented in parallel with the magnetization M1 of the magnetization fixed layer 1. On the other hand, the magnetization M3b of the second region 3b of the domain wall drive layer 3 is oriented antiparallel to the magnetization M1 of the magnetization fixed layer 1. That is, the interface between the magnetization fixing layer 1 and the first region 3a has low resistance, and the interface between the magnetization fixing layer 1 and the second region 3b has high resistance.

FIG. 4 is a diagram schematically showing a part of a circuit at the time of reading data, and FIG. 4A is an orientation with the magnetization M1 of the magnetization fixed layer 1 like the magnetic wall utilization type analog memory element according to the present embodiment. It is a circuit diagram when the readout current IR is passed in the direction in which the magnetization _M3b having the opposite direction exists, and (b) is the readout in the direction in which the magnetization M3a having the same orientation direction as the magnetization M1 of the magnetization fixed layer 1 exists. It is a circuit diagram when the current _IR is passed.

When the readout current IR is passed to the second region 3b side where the magnetization _M3b whose orientation direction is opposite to that of the magnetization M1 of the magnetization fixed layer 1 exists, the magnetization fixed layer 1 and the first region are as shown in FIG. 4A. A parallel circuit is formed having a current path I _3a having a resistance R _3a at the interface with 3a and a current path I _3b having a resistance R _3b at the interface between the magnetization fixing layer 1 and the second region 3b. The resistance R 3a at the interface between the magnetization fixing layer 1 and the first region _3a and the resistance R _3b at the interface between the magnetization fixing layer 1 and the second region 3b depend on the position of the domain wall DW in the domain wall drive layer 3 in contact with the magnetization fixing layer 1. It can be regarded as a variable resistance that changes.

Further, since the read current _IR finally flows to the second region 3b side, the current flowing at the interface between the magnetization fixed layer 1 and the first region 3a passes through the domain wall DW between the first region 3a and the second region 3b. pass. That is, the resistance RDW at the domain wall _DW interface is superimposed on the current path I _3a . Since the resistance state of the domain wall _DW only fluctuates but the resistance state does not fluctuate significantly, the resistance RDW can be regarded as a fixed resistance.

On the other hand, even when the read current IR is passed to the first region 3a side where the magnetization _M3a having the same orientation direction as the magnetization M1 of the magnetization fixing layer 1 exists, as shown in FIG. 4B, the magnetization fixing layer A parallel circuit is formed having a current path I _3a having a resistance R _3a at the interface between 1 and the first region 3a and a current path I _3b having a resistance R _3b at the interface between the magnetization fixing layer 1 and the second region 3b. Will be done. On the other hand, since the read current IR finally flows to the first region 3a side, the current flowing at the interface between the magnetized fixed layer 1 and the second region _3b is between the first region 3a and the second region 3b. It is necessary to pass through the domain wall DW. That is, the resistance RDW at the domain wall _DW interface is superimposed on the current path I _3b .

Here, as described above, the resistance R _3a at the interface between the magnetization fixing layer 1 and the first region 3a has a lower resistance than the resistance R _3b at the interface between the magnetization fixing layer 1 and the second region 3b. As shown in FIG. 4 (b), when the resistance RDW at the interface of the domain wall _DW is present in the current path I _3b in which the resistance R _3b having a high resistance exists, the total resistance of the current path I _3b becomes large and the read current Most flow through the current path I _3a . Therefore, when the readout current IR is passed to the first region 3a side where the magnetization _M3a having the same orientation direction as the magnetization M1 of the magnetization fixed layer 1 exists, it is mainly read out as the resistance value change of the magnetic wall utilization type analog memory element 100. Is the change in the resistance value of the resistance R _3a at the interface between the magnetization fixing layer 1 and the first region 3a, and the change in the resistance value of the resistance R _3b at the interface between the magnetization fixing layer 1 and the second region 3b does not make a large contribution.

On the other hand, as shown in FIG. 4A, when the resistance RDW at the interface of the magnetic wall _DW exists in the current path I _3a in which the low resistance resistance R _3a exists, the total resistance of the current path I _3a becomes large. , The distribution ratio of the read current flowing in the current path I _3a and the reading current flowing in the current path I _3b is averaged. Therefore, when the read-out current IR is passed to the second region 3b side where the magnetization _M3b whose orientation direction is opposite to that of the magnetization M1 of the magnetization fixed layer 1 exists, the read-out current is applied to both the current path I _3a and the current path I _3b . The magnetic wall is used by superimposing the change in the resistance value of the resistance R _3a between the magnetization fixing layer 1 and the first region 3a and the resistance value change of the resistance R _3b between the magnetization fixing layer 1 and the second region 3b. It is read out as a change in the resistance value of the type analog memory element 100.

By controlling the flow direction of the current IR at the time of reading by the current control means in this way, the resistance value change of the two resistors _{R 3a} and R _3b (variable resistance) on the circuit can be changed by the resistance of the magnetic wall-based analog memory element 100. It can be read as a value change, and the data can be read more precisely.

It is necessary to consider the spatial distribution of current when reading data. In FIG. 3, the resistance between the magnetizing fixed layer 1 and the domain wall driving layer 3 differs depending on the magnetization directions of the magnetization fixing layer 1 and the domain wall driving layer 3. In FIG. 3, the orientations of the first region 3a and the magnetization fixing layer 1 are parallel, and the resistance is low. The orientations of the second region 3b and the magnetization fixing layer 1 are antiparallel, and the resistance is high. That is, the current easily flows into the first region 3a. The current flowing in the first region 3a flows to the second magnetization supply layer 5 via the second region 3b. However, when the current flows from the magnetization fixed layer 1 to the first magnetization supply layer 4, the current flowing in the first region 3a flows to the first magnetization supply layer 4 as it is, so that the magnetization fixed layer 1 has a high resistance. The current flowing through the second magnetization supply layer 5 decreases, and the region of high resistance cannot be fully utilized as the resistance of the path. Therefore, the reading resistance is more linear with respect to the movement of the domain wall when the current flows from the magnetization fixing layer 1 to the second magnetization supply layer 5 than when the current flows from the magnetization fixing layer 1 to the first magnetization supply layer 4. The sex improves.

A _part of the current IR at the time of reading flows in the direction (X direction) penetrating the domain wall DW. At this time, it is assumed that the domain wall DW moves and the writing state changes at the time of reading, but the current _{IR applied at the time of reading is smaller than the currents I W1 and} I _W2 applied at the time of writing. Therefore, the movement of the domain wall DW can be suppressed by adjusting the current _IR applied at the time of reading.

As described above, the domain wall utilization type analog memory element 100 according to the first embodiment adjusts the composition ratio of the first region 3a and the second region 3b in the portion of the domain wall drive layer 3 in contact with the magnetization fixing layer 1 at the time of writing. However, by moving the domain wall DW, data can be recorded at multiple values. Further, by controlling the flow direction of the current _IR at the time of reading by the current control means, the change in the resistance value of the domain wall-based analog memory element 100 changes linearly by the domain wall drive, and the analog value can be measured more accurately.

(Other configurations)
A magnetic coupling layer may be installed between the domain wall drive layer 3 and the non-magnetic layer 2. The magnetic coupling layer is a layer that transfers the magnetization state of the domain wall driving layer 3. The main function of the domain wall drive layer 3 is a layer for driving the domain wall, and it is not always possible to select a material suitable for the magnetoresistive effect generated via the magnetization fixing layer 1 and the non-magnetic layer 2. In general, it is known that a ferromagnetic material having a BCC structure is good for the magnetization fixing layer 1 and the magnetic coupling layer in order to generate a coherent tunneling effect using the non-magnetic layer 2. In particular, as a material for the magnetization fixing layer 1 and the magnetic coupling layer, it is known that a large output can be obtained when a material having a Co—Fe—B composition is produced by sputtering.

Further, the thickness of the portion of the domain wall drive layer 3 that overlaps with the magnetization fixing layer 1 in a plan view may be thicker than the other portions. When the domain wall DW moves under the non-magnetic layer 2, the cross-sectional area of the domain wall DW increases, so that the current density decreases and the moving speed of the domain wall DW slows down. When the moving speed of the domain wall DW becomes slow, it becomes easy to control the composition ratio of the first region 3a and the second region 3b in the portion of the domain wall drive layer 3 in contact with the magnetization fixing layer 1, and it becomes easy to read the output data as an analog value.

Such a structure can be produced by forming a film of the domain wall driving layer 3, the non-magnetic layer 2 and the magnetization fixing layer 1 by continuous film formation, and scraping off unnecessary portions. When continuous film formation is performed, the bond between the layers to be bonded becomes stronger, and more efficient magnetic coupling and output can be obtained.

In addition, a configuration equivalent to that used for the magnetoresistive effect element can be used. For example, each layer may be composed of a plurality of layers, or may be provided with another layer such as an antiferromagnetic layer for fixing the magnetization direction of the magnetization fixing layer 1.

"Second embodiment"
FIG. 5 is a perspective schematic view of the domain wall-based analog memory element 101 according to the second embodiment. The domain wall-based analog memory element 101 according to the second embodiment is different from the domain wall-based analog memory element 100 according to the first embodiment in that the magnetization supplying means is different. Other configurations are the same as those of the domain wall-based analog memory element 100 according to the first embodiment, and the same configurations are designated by the same reference numerals.

Second Embodiment In the domain wall utilization type analog memory element 101, the magnetization supply means is electrically insulated from the domain wall drive layer 3 and extends in a direction intersecting the domain wall drive layer 3 with the first wiring 14 and the second. Wiring 15.

Since the magnetic domain wall-based analog memory element 101 according to the second embodiment has different magnetization supplying means, the operation at the time of writing is different. When writing the domain wall-based analog memory element 101, currents I _{14 and} I ₁₅ are passed through at least one of the first wiring 14 and the second wiring 15. In the first wiring 14 and the second wiring 15, when the currents I _{14 and} I ₁₅ flow, the magnetic fields M ₁₄ and M ₁₅ are generated according to Ampere's law.

The directions of the current I ₁₄ flowing through the first wiring 14 and the current I ₁₅ flowing through the second wiring 15 are opposite to each other. By reversing the directions of the currents, the directions of the magnetic fields M ₁₄ and M ₁₅ generated around the respective wirings are opposite. The magnetic field M ₁₄ generated by the first wiring 14 imparts a + X magnetic field M ₁₄ to the domain wall drive layer 3, and the magnetic field M ₁₅ generated by the second wiring 15 imparts an −X magnetic field M ₁₅ to the domain wall drive layer 3. That is, by flowing the data through the first wiring 14 and the second wiring 15, the composition ratio of the first region 3a and the second region 3b of the domain wall drive layer 3 can be changed, and the position of the domain wall DW can move the data. Can be recorded in multiple values.

At the time of reading data, the current flow direction is controlled between the magnetization fixing layer 1 and the second region 3b of the domain wall drive layer 3 as in the case of the domain wall utilization type analog memory element 100 according to the first embodiment. , Data can be read out accurately.

The material used for the first wiring 14 and the second wiring 15 is not particularly limited as long as it has excellent conductivity. For example, gold, silver, copper, aluminum and the like can be used.

Further, when the magnetization directions of the domain wall fixing layer 1 and the domain wall drive layer 3 are oriented in the Z direction as in the domain wall utilization type analog memory element 102 shown in FIG. 6, the first wiring 14 and the second wiring 15 The position of the domain wall DW can be moved by adjusting the positional relationship and the directions in which the currents I _{14 and} I ₁₅ flow.

"Third embodiment"
FIG. 7 is a perspective schematic view of the domain wall-based analog memory element 103 according to the third embodiment. The domain wall-based analog memory element 103 according to the third embodiment is different from the domain wall-based analog memory element 100 according to the first embodiment in that the magnetization supplying means is different. Other configurations are the same as those of the domain wall-based analog memory element 100 according to the first embodiment, and the same configurations are designated by the same reference numerals.

Third Embodiment In the domain wall utilization type analog memory element 103, the magnetization supply means is in contact with the domain wall drive layer 3 and extends in a direction intersecting the domain wall drive layer 3 with a first spin orbit torque wiring 24 and a second spin. The track torque wiring 25. Hereinafter, the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25 may be collectively referred to as a spin orbit torque.

Since the magnetic domain wall-based analog memory element 103 according to the third embodiment has different magnetization supplying means, the operation at the time of writing is different. When writing the magnetic wall-based analog memory element 103, currents I _{24 and} I ₂₅ are passed through at least one of the first spin-orbit torque wiring 24 and the second spin-orbit torque wiring 25.

When the currents I _{24 and} I ₂₅ flow through the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25, the spin derived from the spin-orbit interaction is supplied to the magnetic wall drive layer 3. The spin derived from the spin-orbit interaction is generated by the spin Hall effect caused by the current flowing through the spin-orbit torque wiring and the interface Rashba effect between dissimilar element interfaces.

The spin Hall effect is a phenomenon in which a pure spin current is induced in a direction orthogonal to the direction of the current based on the spin-orbit interaction when a current is passed through the material. When a current is passed in the extending direction of the spin-orbit torque wiring, the first spin oriented in one direction and the second spin oriented in the opposite direction are bent in the directions orthogonal to the current, respectively. The normal Hall effect and the spin Hall effect are common in that the moving (moving) charge (electrons) can bend the moving (moving) direction, but in the normal Hall effect, the charged particles moving in a magnetic field exert Lorentz force. In contrast to the spin Hall effect, which receives and bends the direction of motion, the spin Hall effect is significantly different in that the direction of movement is bent only by the movement of electrons (only the flow of electric current) even though there is no magnetic field.

In a non-magnetic material (a material that is not a ferromagnet), the number of electrons in the first spin and the number of electrons in the second spin are equal. Therefore, for example, in the figure, the number of electrons in the first spin going up is equal to the number of electrons in the second spin going down. When the electron flow of the first spin is J _↑ , the electron flow of the second spin is J _↓ , and the spin flow is J _S , it is defined as J _S = J _↑ -J _↓ . _JS is a flow of electrons with a polarizability of 100%. That is, in the spin-orbit torque wiring, the current as a net flow of electric charge is zero, and the spin current without this current is particularly called a pure spin current.

When the spin-orbit torque wiring in which the pure spin current is generated is joined to the domain wall drive layer 3, spins oriented in a predetermined direction are diffused and flow into the domain wall drive layer 3.

The interface Rashba effect is a phenomenon in which spins are easily oriented in a predetermined direction due to the influence of the interface between different elements, and spins oriented in a predetermined direction are accumulated in the vicinity of the interface.

For example, in FIG. 7, the interface between the spin-orbit torque wiring and the domain wall drive layer 3 corresponds to the interface between different elements. Therefore, spins oriented in a predetermined direction are accumulated on the surface of the spin-orbit torque wiring on the domain wall drive layer 3 side. The accumulated spin diffuses and flows into the domain wall drive layer 3 in order to obtain energy stability.

The direction of the spin that diffuses and flows into the magnetic wall drive layer 3 can be changed by the direction of the current flowing through the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25. A spin in the same direction as the magnetization M _3a is supplied to the first region 3a of the domain wall drive layer 3, and a spin in the same direction as the magnetization M _3b is supplied to the second region 3b of the domain wall drive layer 3.

In this way, by passing the currents I _{24 and} I ₂₅ through at least one of the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25, it is possible to supply spin in a predetermined direction to the magnetic wall drive layer 3. .. As a result, the composition ratio of the first region 3a and the second region 3b of the domain wall drive layer 3 is changed, and the position of the domain wall DW is moved, so that data can be recorded at multiple values.

At the time of reading data, the current flow direction is controlled between the magnetization fixing layer 1 and the second region 3b of the domain wall drive layer 3 as in the case of the domain wall utilization type analog memory element 100 according to the first embodiment. , Data can be read out accurately.

The spin-orbit torque wiring is made of a material in which a pure spin current is generated by the spin Hall effect when a current flows. The material constituting the spin-orbit torque wiring is not limited to a material composed of a single element, but is composed of a part composed of a material in which a pure spin current is generated and a part composed of a material in which a pure spin current is not generated. And so on.

The spin-orbit torque wiring may contain non-magnetic heavy metals. Here, the heavy metal is used to mean a metal having a specific density equal to or higher than that of yttrium. The spin-orbit torque wiring may consist only of non-magnetic heavy metals.

In this case, the non-magnetic heavy metal is preferably a non-magnetic metal having a d-electron or an f-electron in the outermost shell and having an atomic number of 39 or more and a large atomic number. This is because such a non-magnetic metal has a large spin-orbit interaction that causes the spin Hall effect. The spin-orbit torque wiring may consist only of a non-magnetic metal having an atomic number of 39 or more and having a d-electron or an f-electron in the outermost shell and having a large atomic number.

Normally, when a current is passed through a metal, all the electrons move in the opposite direction to the current regardless of the direction of their spin, whereas the outermost shell is a non-magnetic metal with a large atomic number and d-electrons or f-electrons. Since the spin orbital interaction is large, the direction of electron movement depends on the direction of the electron spin due to the spin hole effect, and a pure spin current is likely to occur. Further, the spin-orbit torque wiring is preferably a metal alloy. Since different metal elements are present in one structure in an alloy, the symmetry of the crystal structure is lowered and a pure spin current is likely to occur. Further, it is more preferable that the atomic numbers of the metal elements constituting the alloy are sufficiently different. In this case, the orbit of the metal element perceived by the electron changes significantly, so that a pure spin current is more likely to occur.

Further, the spin-orbit torque wiring may include magnetic metal. The magnetic metal refers to a ferromagnetic metal or an antiferromagnetic metal. This is because when the non-magnetic metal contains a small amount of magnetic metal, the spin-orbit interaction is enhanced, and the spin-orbit generation efficiency with respect to the current flowing through the spin-orbit torque wiring can be increased. The spin-orbit torque wiring may consist only of antiferromagnetic metal.

Since the spin-orbit interaction is caused by the inherent infield of the material of the spin-orbit torque wiring material, a pure spin current is also generated in the non-magnetic material. When a small amount of magnetic metal is added to the spin-orbit torque wiring material, the spin current generation efficiency is improved because the magnetic metal itself scatters the flowing electron spins. However, if the amount of the magnetic metal added is too large, the generated pure spin current is scattered by the added magnetic metal, and as a result, the effect of reducing the spin current becomes stronger. Therefore, it is preferable that the molar ratio of the added magnetic metal is sufficiently smaller than the molar ratio of the main component of the spin-orbit torque wiring. As a guide, the molar ratio of the added magnetic metal is preferably 3% or less.

Further, the spin-orbit torque wiring may include a topological insulator. The spin-orbit torque wiring may consist only of topological insulators. The topological insulator is a substance in which the inside of the substance is an insulator or a high resistance substance, but a metal state in which spin polarization occurs on the surface thereof. Matter has something like an internal magnetic field called spin-orbit interaction. Therefore, a new topological phase appears due to the effect of spin-orbit interaction even in the absence of an external magnetic field. This is a topological insulator, and a pure spin current can be generated with high efficiency due to strong spin-orbit interaction and breaking of inversion symmetry at the edge.

As the topological insulator, for example, SnTe, Bi _1.5 Sb _0.5 Te _1.7 Se _1.3 , TlBiSe ₂ , Bi ₂ Te ₃ , (Bi _1-x Sb _x ) ₂ Te ₃ and the like are preferable. These topological insulators can generate spin currents with high efficiency.

"Fourth Embodiment"
FIG. 8 is a perspective schematic view of the domain wall-based analog memory element 104 according to the fourth embodiment. The domain wall-based analog memory element 104 according to the fourth embodiment is different from the domain wall-based analog memory element 100 according to the first embodiment in that the magnetization supplying means is different. Other configurations are the same as those of the domain wall-based analog memory element 100 according to the first embodiment, and the same configurations are designated by the same reference numerals.

Fourth Embodiment In the domain wall utilization type analog memory element 104, the magnetization supply means is a first voltage application terminal 34 and a second voltage application terminal 35 connected to the domain wall drive layer 3 via insulating layers 36 and 37. Hereinafter, the first voltage application terminal 34 and the second voltage application terminal 35 may be collectively referred to as a voltage application terminal.

Fourth Embodiment Since the magnetic domain wall-based analog memory element 104 has different magnetization supplying means, the operation at the time of writing is different. When writing the domain wall-based analog memory element 104, a voltage is applied between the magnetization fixing layer 1 and the first voltage application terminal 34 or the second voltage application terminal 35.

For example, when a voltage is applied between the magnetization fixing layer 1 and the first voltage application terminal 34, a part of the magnetization M _3a in the first region 3a is affected by the voltage. When a voltage is applied as a pulse, a part of the magnetization _M3a is oriented in the Z direction when the voltage is applied, and is oriented in the easy magnetization direction + X direction or −X direction at the timing when the voltage application is stopped. It is an equal probability whether the magnetization oriented in the Z direction collapses in the + X direction or the −X direction, and by adjusting the timing, the number of times, and the period in which the pulse voltage is applied, a part of the magnetization _M3a is partially from the + X direction to-. It can be oriented in the X direction.

In this way, by applying a voltage to the domain wall drive layer 3 as a pulse, it is possible to supply spin in a predetermined direction to the domain wall drive layer 3. As a result, the composition ratio of the first region 3a and the second region 3b of the domain wall drive layer 3 is changed, and the position of the domain wall DW is moved, so that data can be recorded at multiple values.

On the other hand, the insulating layers 36 and 37 obstruct the flow of current at the time of reading. Therefore, the presence of the insulating layers 36 and 37 may reduce the output characteristics of the domain wall-based analog memory element 104. In this case, a read wiring 38 through which a read current flows may be provided as in the domain wall-based analog memory element 104 shown in FIG.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the configurations and combinations thereof in each embodiment are examples, and the configurations may be added or omitted within a range not deviating from the gist of the present invention. , Replacements, and other changes are possible.

The magnetization supplying means may be different from the means for supplying the magnetization to the first region 3a and the means for supplying the magnetization to the second region 3b. For example, the means for supplying the magnetization to the first region 3a may be the first magnetization supply layer 4, and the means for supplying the magnetization to the second region 3b may be the second wiring 15. In this way, the magnetization supply means according to the first to fourth embodiments may be arranged in combination. Further, as the magnetization supplying means, the write current itself flowing through the domain wall drive layer 3 may be used as a spin polarization current.

(Analog memory using domain wall)
The domain wall-based analog memory according to the present embodiment includes a plurality of domain wall-based analog memory elements according to the above-described embodiment.

FIG. 10 is a diagram schematically showing an example of the circuit structure of the domain wall-based analog memory 200 according to the present embodiment. The domain wall-based analog memory 200 includes a plurality of domain-wall-based analog memory elements 100, a first wiring 201, a first control element 202, a second wiring 203, a second control element 204, and a third wiring 205. , And a cell selection control element 206.

The first wiring 201 is connected to the magnetization fixing layer 1 of each domain wall utilization type analog memory element 100, and connects each magnetization fixing layer 1 and the first control element 202. The second wiring 203 is connected to the first magnetization supply layer 4 of each domain wall-based analog memory element 100, and connects the first magnetization supply layer 4 and the second control element 204, respectively. The third wiring 205 is connected to the second magnetization supply layer 5 of each domain wall-based analog memory element 100, and connects each first magnetization supply layer 4 and the cell selection control element 206.

For the first wiring 201, the second wiring 203, and the third wiring 205, materials used as materials for ordinary wiring can be used. For example, aluminum, silver, copper, gold and the like can be used.

The first control element 202 controls the current flowing through the first wiring 201. The second control element 204 controls the current flowing through the second wiring 203. The cell selection control element 206 controls which magnetic domain wall-based analog memory element 100 a current flows during writing and reading.

Known switching elements can be used for the first control element 202, the second control element 204, and the cell selection control element 206. For example, a transistor element or the like represented by a field effect transistor or the like can be used.

When writing data to the domain wall-based analog memory 200, the cell selection control element 206 connected to the second control element 204 and the domain wall-based analog memory element 100 to which data is to be written is opened. As a result, the domain wall DW of the domain wall drive layer 3 of the predetermined domain wall utilization type analog memory element 100 moves, and data is written.

When reading data from the domain wall-based analog memory 200, the cell selection control element 206 connected to the first control element 202 and the domain wall-based analog memory element 100 to which data is to be written is opened. As a result, the data of the predetermined domain wall-based analog memory element 100 is read out.

(Non-volatile logic circuit)
In the non-volatile logic circuit according to the present embodiment, the domain wall-based analog memory elements according to the present embodiment are arranged in an array, and STT-MRAM is provided either in the array or in a non-array, and the storage function and the logic function are provided. It has a magnetic domain wall-based analog memory element and an STT-MRAM as a storage function.
Since the domain wall-based analog memory element and the STT-MRAM can be manufactured in the same process, the cost can be reduced. In addition, by installing the digital STT-MRAM in the same circuit as the domain wall-based analog memory elements arranged in an array, the input and output can be digitized and the logic that can be processed internally by analog is provided. Can be formed.

(Magnetic neuro element)
FIG. 11 is a schematic cross-sectional view of an example of the magnetic neuroelement according to the present embodiment. The magnetic neuro element 300 according to the present embodiment includes the above-mentioned domain wall-based analog memory element and a current source (not shown) having a control circuit. In the longitudinal direction of the domain wall drive layer 3 of the domain wall utilization type analog memory element, there are a first storage unit 301, a second storage unit 302 and a third storage unit 303 sandwiching the first storage unit 301. The control circuit sends a write current capable of moving the domain wall in order so as to stay at least once in all the storage units of the first storage unit 301, the second storage unit 302, and the third storage unit 303.

The first storage unit 301 is a portion of the domain wall drive layer 3 that overlaps with the magnetization fixing layer 1 in a plan view. The second storage unit 302 is a portion between the portions overlapping the magnetization fixing layer 1 and the second magnetization supply layer 5 in a plan view (a portion not overlapping with either the magnetization fixing layer 1 or the second magnetization supply layer 5). .. Further, the third storage unit 303 is a portion between the magnetization fixing layer 1 and the first magnetization supply layer 4 (a portion that does not overlap with either the magnetization fixing layer 1 or the first magnetization supply layer 4) in a plan view. ..

The magnetic neuro element is an element that simulates the operation of synapses, and can be used as a magnetic neuro element by providing a control circuit in the magnetic domain wall-based analog memory element according to the present embodiment.

Synapses have a linear output in response to external stimuli, and when a load in the opposite direction is applied, they output reversibly without hysteresis. When the area of the portion where the magnetization directions of the magnetized fixed layer 1 and the domain wall drive layer 3 are parallel to each other continuously changes due to the drive (movement) of the domain wall DW, the magnetization directions of the magnetized fixed layer 1 and the domain wall drive layer 3 are changed. A parallel circuit is formed by the current path formed in the parallel portion and the current path formed in the antiparallel portion.

When the domain wall DW of the domain wall drive layer 3 moves, the ratio of the area ratio of the portion where the magnetization directions are parallel to the area ratio of the portion where the magnetization directions are antiparallel changes, and a relatively linear resistance change can be obtained. The movement of the domain wall DW also depends on the magnitude of the current and the time of the applied current pulse. Therefore, the magnitude and direction of the current and the time of the applied current pulse can be regarded as an external load.

(Early stage of memory)
For example, when the domain wall of the domain wall drive layer 3 moves to the maximum in the −X direction, the domain wall DW is stabilized at the end portion 302a on the magnetization fixed layer 1 side of the second magnetization supply layer 5. When a current is passed from the first magnetization supply layer 4 to the second magnetization supply layer 5, electrons flow from the second magnetization supply layer 5 to the first magnetization supply layer 4, and the inside of the second magnetization supply layer 5 and the domain wall drive layer 3 The spin-polarized electrons cause spin transfer, and the domain wall DW moves in the + X direction. Even if the domain wall DW moves until the domain wall DW reaches the end 302b on the second magnetization supply layer 5 side of the magnetization fixing layer 1, the read resistance does not change. This state (when the domain wall DW is arranged in the second storage unit 302) is called an initial stage of storage. Although it is not recorded as data in the initial stage of memory, it is in a state where it is ready to record data.

(Main memory stage)
While the domain wall DW passes through the lower part of the magnetization fixed layer 1 (the portion overlapping in a plan view, the first storage unit 301), the resistance at the time of reading changes. The flow of a current from the first magnetization supply layer 4 to the second magnetization supply layer 5 is regarded as an external load, and a linear resistance value change proportional to the load can be read out. This is the main memory stage. That is, the case where the domain wall DW is arranged in the first storage unit 301 is called the main storage stage of storage. The state in which the domain wall DW is outside one end of the magnetized fixed layer 1 in the X direction is defined as memory or non-memory, and the state in which the domain wall DW is outside the other end of the magnetized fixed layer 1 is nothing. Defined as memory or memory. If the direction of the current flowing through the domain wall drive layer 3 is reversed, the opposite effect is obtained.

(Deepening stage of memory)
When the domain wall DW reaches the end 303b on the first magnetization supply layer 4 side of the magnetization fixing layer 1 and the domain wall DW moves away from the magnetization fixing layer 1, the read output does not change. However, after the domain wall DW is sufficiently separated from the magnetization fixing layer 1, even if a load in the opposite direction is applied, the output at the time of reading does not change until the domain wall DW reaches the end portion 303b of the magnetization fixing layer 1. That is, when the domain wall DW is present in the third storage unit 303, the memory is not lost even when an external load is applied, and the memory is deepened. That is, the case where the domain wall DW is arranged in the third storage unit 303 is called a storage deepening stage.

When the direction of the current flowing through the domain wall drive layer 3 is reversed, the correspondence between the initial stage of memory, the main storage stage, and the deepening stage of memory and each storage unit is reversed.

In order to use the domain wall-based analog memory as a magnetic neuro element that simulates the operation of synapses, it is necessary to move the domain wall DW through the initial stage of memory, the main memory stage, and the deepening stage of memory in order. The movement of the domain wall DW is controlled by a current source that carries a write current. That is, the domain wall-based analog memory is controlled to pass a write current that can move the domain wall in order so as to stay at least once in all the storage units of the first storage unit, the second storage unit, and the third storage unit. By providing a current source (not shown) having a control circuit, it functions as a magnetic domain wall element. How many times the magnetic domain wall passes through each of the first storage unit 301, the second storage unit 302, and the third storage unit 303 is determined by the condition of the write current.

(Memory forgetting stage)
By moving the domain wall of the domain wall drive layer 3 to a non-memory state, the memory can be forgotten. The domain wall can also be driven or extinguished by applying an external magnetic field, heat, and physical strain. Domain wall analog memory has constant low resistance and high resistance values, so memory and non-memory are determined by definition. Further, when the domain wall is moved or disappears by a method other than passing a current through the domain wall drive layer 3, it becomes random, so that the correlation of information between a plurality of domain wall-based analog memories is lost. These are called the forgetting stages of memory.

(Artificial brain using magnetic neuro element)
The magnetic neuroelement according to the present embodiment is a memory capable of simulating the movement of synapses and undergoing an initial stage of memory, a main memory stage, and a deepening stage of memory. That is, it is possible to simulate the brain by installing the domain wall-based analog memory on a plurality of circuits. It is possible to form a highly integrated brain by arranging them evenly in the vertical and horizontal directions as in general memory.

As shown in FIG. 12, by arranging a plurality of magnetic neuroelements having a specific circuit as one block and arranging them in an array, it is possible to form a brain having a different degree of recognition from an external load. FIG. 13 is a product-sum calculation circuit in which magnetic neuro elements are arranged in an array. In FIG. 13, data is simultaneously input to each wiring from the left direction in the figure. The input data outputs data based on the weights (initial stage of memory, main memory stage, and deepening stage of memory) recorded by the magnetic neuroelement. Each data output from each magnetic neuro element is bundled and output in the column direction. The neuromorphic computer provided with the product-sum calculation circuit shown in FIG. 13 can produce individuality such as a brain having a high sensitivity to color and a brain having a high degree of understanding of language, such as a brain. In other words, the information obtained from the external sensor is processed in the five senses area optimized for visual, taste, tactile, olfactory and auditory recognition, and further judged in the logical thinking area. It is possible to form the process of deciding what to do. Further, when the material of the domain wall drive layer 3 is changed, the domain wall drive speed with respect to the load and the method of forming the domain wall are changed, so that it is possible to form an artificial brain with the changes as individuality.

1 ... Magnetized fixed layer, 2 ... Non-magnetic layer, 3 ... Magnetic wall drive layer, 3a ... First region, 3b ... Second region, 4 ... First magnetized supply layer, 5 ... Second magnetized supply layer, 14 ... First Wiring, 15 ... 2nd wiring, 24 ... 1st spin orbit torque wiring, 25 ... 2nd spin orbit torque wiring, 34 ... 1st voltage application terminal, 35 ... 2nd voltage application terminal, 36, 37 ... Insulation layer, 38 ... Reading wiring, 100, 101, 102 ... Magnetic wall utilization type analog memory element, 200 ... Magnetic wall utilization type analog memory, 201 ... First wiring, 202 ... First control element, 203 ... Second wiring, 204 ... Second control Element, 205 ... 3rd wiring, 206 ... Cell selection control element, 300 ... Magnetic neuro element, 301 ... 1st storage unit, 302 ... 2nd storage unit, 303 ... 3rd storage unit, M1, M3a, M3b, M4 M5 ... Magnetization, I _W1 , I _W2 , IR, I ₁₄ , I ₁₅ , I ₂₄ , I ₂₅ ... Current, e ₁ , e ₂ ... Conduction electrons, _{R 3a} , R _3b , RDW ... Resistance, _DW ... Domain wall

Claims (9)

A plurality of domain wall-based analog memory elements, a first control element, a second control element, a plurality of cell selection control elements, a first wiring, a second wiring, a plurality of third wirings, and a control circuit. Equipped with a current source
Each of the plurality of domain wall-based analog memory elements
A magnetization fixed layer whose magnetization is oriented in the first direction,
The non-magnetic layer provided on one surface of the magnetization fixing layer and
It has a first region in which the magnetization is oriented in the first direction, a second region in which the magnetization is oriented in the second direction opposite to the first direction, and a domain wall forming an interface between these regions. A magnetic domain wall driving layer provided with the non-magnetic layer interposed therebetween with respect to the magnetization fixing layer.
The first wiring connects the magnetization fixed layer of each of the plurality of domain wall-based analog memory elements to the first control element.
The second wiring is a part of a configuration for electrically connecting the first region of each of the plurality of domain wall-based analog memory elements and the second control element.
Each of the third wirings is a part of a configuration for electrically connecting the second region of each of the plurality of domain wall-based analog memory elements and each of the cell selection control elements.
The first control element and the cell selection control element are a part of the current control means, and a current is passed between the magnetization fixing layer and the second region at the time of reading.
The domain wall drive layer has a first storage unit arranged in the longitudinal direction, and a second storage unit and a third storage unit sandwiching the first storage unit.
The first storage unit is a portion of the domain wall drive layer that overlaps with the magnetization fixing layer in a plan view.
The second storage unit and the third storage unit are portions that do not overlap with the magnetization fixing layer in a plan view.
The control circuit controls a writing current that can move the domain wall in order so as to stay in all the storage units of the first storage unit, the second storage unit, and the third storage unit at least once. Analog memory. The domain wall-based analog memory element comprises a first magnetization supplying means for supplying the magnetization wall driven layer with the magnetization oriented in the first direction and a second magnetization supplying means for supplying the magnetization oriented in the second direction. Have more
At least one of the first magnetization supply means and the second magnetization supply means is a magnetization supply layer having magnetization that is in contact with the domain wall drive layer and is oriented in the first direction or the second direction. The domain wall-based analog memory according to claim 1. The domain wall-based analog memory element comprises a first magnetization supplying means for supplying the magnetization wall driven layer with the magnetization oriented in the first direction and a second magnetization supplying means for supplying the magnetization oriented in the second direction. Have more
Claimed that at least one of the first magnetization supply means and the second magnetization supply means is wiring that is electrically insulated from the domain wall drive layer and extends in a direction intersecting with the domain wall drive layer. Item 1. The domain wall-based analog memory according to Item 1. The domain wall-based analog memory element comprises a first magnetization supplying means for supplying the magnetization wall driven layer with the magnetization oriented in the first direction and a second magnetization supplying means for supplying the magnetization oriented in the second direction. Have more
The claim is that at least one of the first magnetization supply means and the second magnetization supply means is a spin-orbit torque wiring that is in contact with the domain wall drive layer and extends in a direction intersecting the domain wall drive layer. The domain wall utilization type analog memory according to 1. The domain wall-based analog memory element comprises a first magnetization supplying means for supplying the magnetization wall driven layer with the magnetization oriented in the first direction and a second magnetization supplying means for supplying the magnetization oriented in the second direction. Have more
The magnetic wall utilization type analog memory according to claim 1, wherein at least one of the first magnetization supplying means and the second magnetization supplying means is a voltage applying means connected to the magnetic wall driving layer via an insulating layer. .. The domain wall-based analog memory according to any one of claims 1 to 5, wherein the current control means is a potential control means that sets the potential of the second region lower than the potential of the magnetization fixed layer at the time of reading. The domain wall-based analog memory according to any one of claims 1 to 5, wherein the current control means further includes a rectifying element that controls a current flow direction. The domain wall-based analog memory according to any one of claims 1 to 7 is provided.
In the domain wall-based analog memory, the domain wall-based analog memory elements are arranged in an array.
The STT-MRAM is provided either in the array or in a non-array.
A non-volatile logic circuit having a storage function and a logic function, and comprising the domain wall-based analog memory element and the STT-MRAM as storage functions. The magnetic neuro element provided with the domain wall-based analog memory according to any one of claims 1 to 7.

Images