JP7008410B2 - Memory controller and method - Google Patents

Description

The present invention relates to a memory controller and a method.

In recent years, the manufacturing process of DRAM (Dynamic Random Access Memory) has been miniaturized. When the DRAM manufacturing process is less than 40 nm and the density is increased, the influence of the leakage current on the memory cell connected to the adjacent word line becomes remarkable due to the electric influence such as crosstalk on the adjacent word line. As a result, when the activation commands are centrally issued by the memory controller to a specific ROW, the data inside the memory cell of the DRAM may be damaged. This is called the ROW HAMMER problem.

As a countermeasure to the ROW HAMMER problem, the Target Row Refresh command (hereinafter referred to as TRR) is defined in the LPDDR4 standard. TRR is an operation of executing a specific sequence from the memory controller for a ROW of a DRAM when the number of active commands issued to the ROW reaches the upper limit within a certain period of time. This upper limit is called MAC (Maximum Activate Count). By implementing TRR, it is possible to avoid data corruption inside the memory cell.

However, when implementing the TRR function in the memory controller, the number of Activate commands issued to each ROW must be counted. In the case of LPDDR4, the maximum MAC value is 700,000 (a counter having a length of 20 bits is required), and the number of ROWs of the DRAM is 131 K per channel even in the case of 4 Gbit, which is the minimum capacity. Therefore, if a simple implementation is performed, the circuit scale will increase. Correspondingly, Patent Document 1 proposes a method of measuring the number of Activate commands issued and executing TRR while suppressing the circuit scale.

U.S. Patent Application Publication No. 2014/0006704

In the method shown in Patent Document 1, the memory controller has a table that holds the ROW address and the number of Activate commands issued to each ROW address in association with each other. The number of entries in this table is based on the number of ROWs that can reach the MAC within a given period of time, which can reduce the circuit scale as compared to the simple implementation described above.

However, the method shown in Patent Document 1 sacrifices the accuracy of the number of issues at the cost of reducing the number of entries in the table. Therefore, there may be a discrepancy between the number of actual Activate commands issued to the ROW address and the number of issues held in the table. This divergence causes unnecessary TRR, which may lead to deterioration of performance.

The present invention has been made in view of these problems, and an object of the present invention is to provide a technique capable of suppressing the generation of unnecessary TRR while suppressing the circuit scale in a memory controller in which TRR is mounted.

One aspect of the invention relates to a memory controller. This memory controller is a memory controller that controls a DRAM whose ROW address is divided into a plurality of groups, and associates a ROW address with a count value that is updated when an Activate command is issued for the ROW address. The first holding means, in which the number of entries that can hold the ROW address is smaller than the total number of ROW addresses, and the count value held by the first holding means satisfy predetermined conditions. A control means for issuing a Target Row Refresh command for a corresponding ROW address when satisfied, and a second holding means for holding a plurality of count values corresponding to each of a plurality of groups of ROW addresses are provided, and the control means is the first. If the Activate command is issued for the first ROW address, which is a ROW address that is not held by the holding means, and there is no free entry in the first holding means, the ROW address held by the first holding means If the second ROW address, which is the ROW address selected according to a predetermined criterion for the count value, is replaced with the first ROW address, and the group to which the second ROW address belongs and the group to which the first ROW address belongs are different, the second ROW address is used. Among the plurality of count values held in the holding means, the count value corresponding to the first ROW address is set by referring to the count value corresponding to the group to which the first ROW address belongs, and the group to which the second ROW address belongs and the first ROW are set. When the group to which the address belongs is the same, the count value held in the first holding means is updated corresponding to the second ROW address, and the updated count value is set as the count value corresponding to the first ROW address. do.

According to the present invention, in a memory controller equipped with TRR, it is possible to suppress the generation of unnecessary TRR while suppressing the circuit scale.

The block diagram which shows the function and the structure of the memory controller which concerns on embodiment. The data structure diagram which shows an example of the address holding part, the count value holding part, and the maximum value holding part for each bank of FIG. An explanatory diagram showing a correspondence relationship between an address group and a bank / ROW address in the present embodiment. The flowchart which shows the flow of a series of processing in the memory controller of FIG. The figure for demonstrating the operation of the control part in a certain scenario. The figure for demonstrating the operation of the control part in a certain scenario. The figure for demonstrating the operation of the control part in a certain scenario. The figure for demonstrating the operation of the control part in a certain scenario. 9 (a) and 9 (b) are diagrams showing an example of how to divide the ROW address.

Hereinafter, the same or equivalent components, members, processes, and signals shown in the drawings shall be designated by the same reference numerals, and duplicate description thereof will be omitted as appropriate. In addition, some of the members that are not important for explanation in each drawing are omitted.

In the method described in Patent Document 1, when the memory controller issues an Activate command, it operates as follows. First, if the ROW address to which the Activate command is issued does not exist in the table and the table is full, the management unit of the table replaces the entry of the ROW address having the smallest number of Activate commands issued. At this time, the management unit of the table copies the number of Activate commands issued associated with the entry before replacement to the number of Activate commands issued associated with the entry after replacement, and subsequently increments the number of Activate commands issued. That is, regardless of the number of Activate commands issued to the ROW address after replacement up to the time of replacement, the value obtained by adding 1 to the number of Activate commands issued to the ROW address before replacement. Is associated with the replaced ROW address.

The problem with this mechanism is that the table management unit focuses only on the number of Activate commands issued at the time of replacement. For example, consider a situation in which access to the ROW address of Bank0 of DRAM occurs frequently, the table is full, and the ROW address of Bank0 is occupied. At this time, when the ROW address of Bank1 is accessed for the first time, the management unit of the table replaces the entry of the ROW address of Bank0 associated with the minimum number of Activate commands issued in the table with the ROW address of Bank1. Although it is the first time that an Activate command has been issued to the ROW address of Bank1, the ROW address of Bank1 stored in the table by replacement is associated with a larger number of Activate commands issued than the actual number. In this way, there is a discrepancy between the actual state of access to the ROW address of Bank1 and the number of commands issued. When the dissociation occurs, useless TRR occurs and performance deterioration may occur.

In the technique described in Patent Document 1, when an Activate command (hereinafter referred to as ACT) is issued for a certain ROW address, if there is no space in the table and there is no entry of the same ROW address in the table, the table The entry (consisting of the ROW address and the ACT issuance count) is expelled to the outside. On the other hand, in the memory controller according to the embodiment, a holding unit for holding an ACT issuance number count among the expelled entries is provided. This holding unit is prepared for each bank or address range, and the ACT issuance count of the expelled entry is registered in the holding unit corresponding to the bank / address range of the ROW address of the expelled entry. Further, when an ACT is issued to a ROW address of a certain bank / address range, the ACT issuance number count held in the holding unit corresponding to the bank / address range is written back to the table and incremented. As a result, as compared with the technique described in Patent Document 1, it is possible to suppress the discrepancy between the number of accesses to the actual ROW address and the number of ACTs issued, and it is possible to suppress the occurrence of unnecessary TRR.

FIG. 1 is a block diagram showing the functions and configurations of the memory controller 100 according to the embodiment. The memory controller 100 includes an issuing unit 101, a control unit 102, a table 106, and a bank-specific maximum value holding unit 105. The memory controller 100 is connected to the DRAM 110 and controls the DRAM 110 by transmitting a DRAM command CMD to the DRAM 110. The DRAM 110 operates according to the DRAM command CMD received from the memory controller 100. The DRAM 110 conforms to LPDDR4. The DRAM 110 has a plurality of banks, and the ROW address of the DRAM 110 is divided into a plurality of address groups corresponding to the plurality of banks.

The issuing unit 101 issues a DRAM command CMD in response to the memory access request MAR received by the memory controller 100. When the issuing unit 101 receives the memory access request MAR from, for example, an external CPU, it generates a DRAM command CMD related to the ROW address included in the received memory access request MAR and transmits it to the DRAM 110.
The control unit 102 monitors to which ROW address the ACT is issued among the DRAM command CMDs issued by the issuing unit 101.

The table 106 holds the ROW address, the bank ID that identifies the bank to which the ROW address belongs, and the count value that is updated when the ACT is issued for the ROW address in association with each other. Since there is a one-to-one correspondence between a bank and an address group, the bank ID is also an ID that identifies the corresponding address group. For table 106, the number of entries that can hold ROW addresses is less than the total number of ROW addresses in DRAM 110.

The table 106 includes an address holding unit 103 and a count value holding unit 104. The address holding unit 103 is controlled by the control unit 102. The control unit 102 registers or stores in the address holding unit 103 a set of a bank to which the ACT issued by the issuing unit 101 is issued and a ROW address. Hereinafter, the pair of the bank and the ROW address will be referred to as a bank / ROW address. In the present embodiment, the bank ROW address is represented as "bank 0, ROW address 0x000", but as another example, the third digit from the left of the ROW address 0x000 may be used as the bank ID. That is, 0x000 may be expressed as the ROW address of bank 0, and 0x100 may be expressed as the ROW address of bank 1.

The count value holding unit 104 is controlled by the control unit 102. When an ACT is issued for each ROW address held in the address holding unit 103, the control unit 102 increments the corresponding count value held in the count value holding unit 104.
The maximum value holding unit 105 for each bank is controlled by the control unit 102, and holds the maximum count value for each address group (that is, bank).

FIG. 2 is a data structure diagram showing an example of an address holding unit 103, a count value holding unit 104, and a bank-by-bank maximum value holding unit 105. The address holding unit 103 and the count value holding unit 104 each have an MVC (Maximum Victim Count) (see Patent Document 1) or less. The MVC is the number of ROW addresses that can reach the MAC when the memory controller 100 issues the ACT as much as possible within the refresh cycle of the DRAM 110. This value is calculated based on the values of tREFW, tRC and MAC. For example, when tREFW is 32 ms, tRC is 42 ns, and MAC is 200 K times, the ACT to the ROW address is 32 ms / 42 ns = about 762 K times. The memory controller 100 can issue about 762K ACTs in one refresh cycle. In this case, the number of ROW addresses that can reach the MAC within one refresh cycle is 762K / 100K = about 7.62. Therefore, in this case, eight entries of the address holding unit 103 and the count value holding unit 104 are required. The maximum value holding unit 105 for each bank has the number of address groups = several entries in the bank.

FIG. 3 is an explanatory diagram showing a correspondence relationship between the address group 301 and the bank / ROW address 302 in the present embodiment. As shown in FIG. 3, one bank is assigned to one address group.

The operation of the memory controller 100 with the above configuration will be described.
FIG. 4 is a flowchart showing a flow of a series of processes in the memory controller 100. When the issuing unit 101 issues an ACT, the control unit 102 executes the process shown in FIG. 4 depending on the respective states of the address holding unit 103 and the count value holding unit 104. In S401, the control unit 102 monitors the DRAM command CMD issued by the issuing unit 101, and determines whether or not the ACT has been issued. If the ACT is not issued, the control unit 102 repeats S401. When the ACT is issued, the control unit 102 refers to the address holding unit 103 in S402, and determines whether or not the bank / ROW address of the issuing destination of the issued ACT exists in the address holding unit 103.

When it is determined in S402 that it exists, the control unit 102 refers to the count value holding unit 104 in S403 and holds it in the count value holding unit 104 corresponding to the entry of the address holding unit 103 which is the same as the bank / ROW address of the issuing destination. Read the count value that has been set. The control unit 102 determines whether or not the read count value is equal to the threshold value, in this case MAC / 2-1. If it is determined in S403 that they are not equal, that is, less than the threshold value, the control unit 102 increments (for example, +1) the read count value in S404. The control unit 102 updates the count value holding unit 104 by registering the incremented count value in the count value holding unit 104. After that, the process returns to S401.

If it is determined in S403 that they are equal, the issuing unit 101 issues a TRR targeting the bank / ROW address of the issuing destination of the ACT in S405. In S406, the control unit 102 resets or initializes the maximum count value held in the maximum value holding unit 105 for each bank corresponding to the bank to which the TRR is issued. For example, the maximum count value is an initial value such as 0 or 1. After that, the process returns to S401.

When it is determined in S402 that it does not exist, the control unit 102 in S407 determines whether or not there is a vacant entry (hereinafter referred to as a vacant entry) in the address holding unit 103. If it is determined to be S407, the control unit 102 newly registers the bank / ROW address of the issue destination of the ACT in the empty entry of the address holding unit 103 in S408. In S409, the control unit 102 reads out the maximum count value held in the maximum value holding unit 105 for each bank corresponding to the bank to which the ACT is issued. In S410 and S411, the control unit 102 sets the count value corresponding to the bank / ROW address of the issue destination of the ACT with reference to the read maximum count value. In S410, the control unit 102 increments the read maximum count value. In S411, the control unit 102 registers the incremented value in the count value holding unit 104 as a count value corresponding to the bank / ROW address of the issue destination of the ACT. After that, the process returns to S401.

When it is determined in S407 that there is no empty entry, the control unit 102 in S412 specifies the minimum count value from the count values held in the count value holding unit 104. In S413, the control unit 102 selects the bank / ROW address corresponding to the specified minimum count value from the bank / ROW addresses held in the address holding unit 103. In S414, the control unit 102 replaces the selected bank ROW address with the bank ROW address to which the ACT is issued.

In S415, the control unit 102 determines whether or not the banks are different before and after the replacement. That is, the control unit 102 determines the difference between the bank selected in S413 (the bank before the replacement) and the bank to which the ACT is issued (the bank after the replacement). If it is determined in S415 that they are the same, the control unit 102 in S416 increments the minimum count value specified in S412. The control unit 102 updates the count value holding unit 104 by registering the incremented count value in the count value holding unit 104 in association with the bank / ROW address of the issue destination of the ACT. After that, the process returns to S401.

If it is determined in S415 that they are different, the control unit 102 in S417 reads out the maximum count value held in the maximum value holding unit 105 for each bank corresponding to the bank selected in S413. Since the minimum count value specified in S412 corresponds to the bank ROW address selected in S413 and is overwritten (excluded) in the subsequent processing of S411, it is hereinafter referred to as an expelled count value. In S418, the control unit 102 determines whether or not the expelled count value is larger than the maximum count value read in S417. When it is determined in S418 that it is large, the control unit 102 updates the maximum value holding unit 105 for each bank by overwriting the maximum count value corresponding to the bank selected in S413 with the expelled count value in S419. When it is determined in S418 that it is not large, or after S419, the control unit 102 registers the count value corresponding to the issue destination bank / ROW address of the ACT by performing S409, S410, and S411. After that, the process returns to S401.

Hereinafter, with reference to FIGS. 5 to 8, details of the operation of the control unit 102 under each condition described with reference to FIG. 4 will be described. These examples show the operation of the control unit 102 when the issuing unit 101 issues the ACT 501 to the bank 0 and the ROW address 0x100. The control unit 102 confirms the states of the address holding unit 103 and the count value holding unit 104, and performs processing according to the states.

When the control unit 102 detects the issuance of the ACT 501 from the issuing unit 101, the control unit 102 determines whether or not the bank ROW address to which the ACT 501 is issued exists in the address holding unit 103 (S402 in FIG. 4). Depending on this state, the control unit 102 determines the subsequent processing.

FIG. 5 is a diagram for explaining the operation of the control unit 102 in a certain scenario. In the example of FIG. 5, as a result of the control unit 102 searching in the address holding unit 103 (reference numeral 502), a pair of bank 0 and ROW address 0x100 is found in the entry of the address holding unit 103. The control unit 102 confirms the entry of the count value holding unit 104 corresponding to the found set of the bank 0 and the ROW address 0x100 (reference numeral 503). As a result, the control unit 102 finds that the count value corresponding to the set of bank 0 and ROW address 0x100 is "999999" (= MAC / 2-1) (S403 in FIG. 4).

Under this condition, the control unit 102 deletes the entry of the set of bank 0 and ROW address 0x100 from the address holding unit 103 (reference numeral 504), and deletes the entry of the count value holding unit 104 corresponding to the entry (reference numeral 505). ). Subsequently, the control unit 102 instructs the issuing unit 101 to issue a TRR (reference numeral 506). The issuing unit 101 issues a TRR to the DRAM 110 in response to an instruction from the control unit 102 (S405 in FIG. 4).

FIG. 6 is a diagram for explaining the operation of the control unit 102 in a certain scenario. In the example of FIG. 6, as a result of the control unit 102 searching in the address holding unit 103 (reference numeral 601), a pair of bank 0 and ROW address 0x100 is found in the entry of the address holding unit 103. The control unit 102 confirms the entry of the count value holding unit 104 corresponding to the found set of the bank 0 and the ROW address 0x100 (reference numeral 602). As a result, the control unit 102 finds that the count value corresponding to the set of bank 0 and ROW address 0x100 is less than MAC / 2-1 (S403 in FIG. 4).

Under this condition, the control unit 102 increments the count value held in the count value holding unit 104 corresponding to the bank 0 and the ROW address 0x100 of the address holding unit 103 (S404 in FIG. 4). The control unit 102 writes “80001”, which is the result of the increment, in the entry of the count value holding unit 104 corresponding to the set of the bank 0 and the ROW address 0x100 (reference numeral 603). As a result of this increment, the count value of the count value holding unit 104 does not reach MAC / 2, so no other processing is performed.

FIG. 7 is a diagram for explaining the operation of the control unit 102 in a certain scenario. In the example of FIG. 7, as a result of the control unit 102 searching in the address holding unit 103 (reference numeral 701), the pair of bank 0 and ROW address 0x100 is not found in the entry of the address holding unit 103. Further, the control unit 102 determines that there is a free entry in the address holding unit 103 (S407 in FIG. 4).

Under this condition, the control unit 102 newly creates an entry for the bank 0 and the ROW address 0x100 in the empty entry of the address holding unit 103 (reference numeral 702, S408 in FIG. 4). The control unit 102 reads out the maximum count value (“0”) held in the maximum value holding unit 105 for each bank corresponding to the bank 0 (address group 0) (reference numeral 703, S409 in FIG. 4). The control unit 102 increments the read maximum count value (0 + 1 = 1). The control unit 102 registers the value (“1”) obtained as a result of the increment in the count value holding unit 104 as the count value corresponding to the bank 0 and the ROW address 0x100 (reference numeral 704, S411 in FIG. 4).

FIG. 8 is a diagram for explaining the operation of the control unit 102 in a certain scenario. In the example of FIG. 8, as a result of the control unit 102 searching in the address holding unit 103 (reference numeral 801), the pair of bank 0 and ROW address 0x100 is not found in the entry of the address holding unit 103. Further, the control unit 102 determines that there is no free entry in the address holding unit 103 (S407 in FIG. 4).

Under this condition, the control unit 102 refers to the count value holding unit 104 to specify the minimum count value, and identifies the entry held in the address holding unit 103 corresponding to the specified minimum count value. The control unit 102 replaces the specified entry with a set of bank row addresses to which the ACT 501 is issued (S414 in FIG. 4). In FIG. 8, the entries of bank 1 and ROW address 0x98 are replaced by the pair of bank 0 and ROW address 0x100 (reference numeral 802). The control unit 102 reads out the maximum count value (“100”) held in the maximum value holding unit 105 for each bank corresponding to the set of bank / ROW addresses after replacement (bank 0, ROW address 0x100) (reference numeral 803). ). The control unit 102 increments the read value (100 + 1 = 101). The control unit 102 writes the value (“101”) obtained as a result of the increment in the entry of the count value holding unit 104 corresponding to the set of bank / ROW addresses after replacement (S411 in FIG. 4). In FIG. 8, "100" is read from the entry of the address group 0 of the maximum value holding unit 105 for each bank, and is incremented to "101", and the minimum count value "15000" of the count value holding unit 104 is the minimum count value "15000". It is overwritten with the value "101" (reference numeral 804).

The control unit 102 has a count value "15000" of the expelled bank 1 and a maximum count value ("14500") held in the maximum value holding unit 105 for each bank corresponding to the bank 1 (address group 1). , Are compared (S418 in FIG. 4). Since 15000> 14500, the control unit 102 replaces the maximum count value corresponding to the bank 1 with 15000 (reference numeral 805).

According to the memory controller 100 according to the present embodiment, the control unit 102 controls the address holding unit 103, the count value holding unit 104, and the bank-by-bank maximum value holding unit 105 as described above to obtain an actual ROW address. It is possible to suppress the discrepancy between the number of accesses and the number of issued ACTs. As a result, it is possible to suppress the generation of useless TRR.

The configuration and operation of the memory controller 100 according to the embodiment have been described above. It is understood by those skilled in the art that this embodiment is an example, and that various modifications are possible for each component and a combination of each process, and that such modifications are also within the scope of the present invention.

In the embodiment, the case where the address group of the ROW address corresponds to the bank of the DRAM 110 has been described, but the present invention is not limited to this. The ROW address may be divided into a plurality of groups, and the method of division may be arbitrary. 9 (a) and 9 (b) are diagrams showing an example of how to divide the ROW address. As shown by reference numeral 1001 in FIG. 9A, classification by ROW address may be used. Alternatively, as shown by reference numeral 1002 in FIG. 9B, a division for each master (when the access destination address is fixed by the master) may be used. In this way, any allocation method can be adopted.

In the embodiment, the case where the count value is incremented has been described, but the present invention is not limited to this, and other embodiments may be used as long as the count value is updated when the ACT is issued to the ROW address. good. For example, the count value may be decremented for the issuance of ACT. In this case, the determination criteria in S403 and S418 in FIG. 4 may also be changed.

In the embodiment, the case where the TRR is issued when the count value reaches the threshold value = MAC / 2-1 has been described, but the present invention is not limited to this, and other threshold values may be used. Conditions other than the threshold value may be used.

In the embodiment, the case where the minimum count value is specified in S412 of FIG. 4 and the bank ROW address corresponding to the count value specified in S413 is selected is not limited thereto. From the bank / ROW addresses held in the address holding unit 103, the bank / ROW address may be selected according to a predetermined reference regarding the count value. For example, a minimum count value may be specified. Alternatively, three count values are selected from the count value holding unit 104 from the smaller one, and the bank ROW address held in the address holding unit 103 corresponding to one randomly selected from the three count values is selected. You may choose.

The minimum count value in S412 is the count value in which the number of increments required to satisfy the condition of reaching MAC / 2-1 is the largest among the count values held in the count value holding unit 104. I can say. That is, it can be said that S412 specifies the count value having the largest number of updates required to satisfy the condition of TRR issuance among the count values held in the count value holding unit 104.

In the embodiment, the case where the maximum count value of the corresponding bank is reset when the TRR is issued in S406 of FIG. 4 has been described, but the present invention is not limited to this. For example, the maximum count value held in the maximum value holding unit 105 for each bank may be automatically decreased with time, or the maximum count value may be read out from the maximum value holding unit 105 for each bank. The maximum count value may be reset.

In the embodiment, the case where the DRAM 110 conforms to LPDDR4 has been described, but the present invention is not limited to this, and the technical idea according to the present embodiment can be applied to any DRAM whose ROW address is divided into a plurality of groups.

100 memory controller, 101 issuing unit, 102 control unit, 103 address holding unit, 104 count value holding unit, 105 maximum value holding unit for each bank, 110 DRAM.

Claims (11)

A memory controller that controls DRAMs whose ROW addresses are divided into multiple groups.
It is the first holding means that holds the ROW address in association with the count value that is updated when the Activate command is issued for the ROW address, and the number of entries that can hold the ROW address is the total number of ROW addresses. Smaller than the first holding means,
When the count value held in the first holding means satisfies a predetermined condition, a control means for issuing a Target Row Refresh command regarding the corresponding ROW address, and a control means.
A second holding means for holding a plurality of count values corresponding to each of a plurality of groups of ROW addresses is provided.
When the Activate command is issued to the first ROW address, which is a ROW address that is not held by the first holding means, and there is no vacant entry in the first holding means, the first holding means said. The second ROW address, which is the ROW address selected according to a predetermined criterion for the count value from the ROW addresses held in the holding means, is replaced with the first ROW address, and the group to which the second ROW address belongs and the first ROW are described. When the group to which the address belongs is different, the count value corresponding to the group to which the first ROW address belongs is referred to among the plurality of count values held in the second holding means to correspond to the first ROW address. When the group to which the second ROW address belongs and the group to which the first ROW address belongs are the same, the count value held in the first holding means corresponding to the second ROW address is set. Is updated and the updated count value is set as the count value corresponding to the first ROW address. The control means has a count value held in the first holding means corresponding to the second ROW address and a count value held in the second holding means corresponding to the group to which the second ROW address belongs. The memory controller according to claim 1, wherein the second holding means is updated by comparing the above. The control means has a count value held in the second holding means corresponding to the group to which the second ROW address belongs, and a count value held in the first holding means corresponding to the second ROW address. The memory controller according to claim 2, which is updated in. When the first holding means has an empty entry, the control means registers the first ROW address in the entry and is held in the second holding means corresponding to the group to which the first ROW address belongs. The memory controller according to any one of claims 1 to 3, wherein the count value corresponding to the first ROW address is set with reference to the count value. From claim 1, the second ROW address is a ROW address corresponding to the count value having the largest number of updates required to satisfy the predetermined condition among the count values held in the first holding means. The memory controller according to any one of 4. A memory controller that controls DRAMs whose ROW addresses are divided into multiple groups.
It is the first holding means that holds the ROW address in association with the count value that is updated when the Activate command is issued for the ROW address, and the number of entries that can hold the ROW address is the total number of ROW addresses. Smaller than the first holding means,
When the count value held in the first holding means satisfies a predetermined condition, a control means for issuing a Target Row Refresh command regarding the corresponding ROW address, and a control means.
A second holding means for holding a plurality of count values corresponding to each of a plurality of groups of ROW addresses is provided.
When the Activate command is issued to the first ROW address, which is a ROW address that is not held by the first holding means, and the first holding means has an empty entry, the control means said the first ROW. The address is registered in the entry, and among the plurality of count values held in the second holding means, the count corresponding to the first ROW address is referred to by referring to the count value corresponding to the group to which the first ROW address belongs. A memory controller that sets the value. The first holding means holds the ROW address, the ID that identifies the group to which the ROW address belongs, and the count value that is updated when the Activate command is issued for the ROW address in association with each other.
The memory controller according to any one of claims 1 to 6, wherein the control means refers to an ID held by the first holding means to specify a group to which the first ROW address belongs. The memory controller according to any one of claims 1 to 7, wherein the group of ROW addresses corresponds to a bank. The memory controller according to any one of claims 1 to 8, wherein the DRAM conforms to LPDDR4. A method executed by a memory controller that controls a DRAM whose ROW address is divided into multiple groups.
The ROW address is associated with the count value updated when the Activate command is issued for the ROW address and held in the first holding means, and the number of entries that can hold the ROW address is the ROW address. To keep, less than the total number of
When the count value held in the first holding means satisfies a predetermined condition, the Target Row Refresh command for the corresponding ROW address is issued.
Holding a plurality of count values corresponding to each of a plurality of groups of ROW addresses in the second holding means, and
If the Activate command is issued to the first ROW address, which is a ROW address that is not held by the first holding means, and there is no free entry in the first holding means, the first holding means holds the command. The second ROW address, which is the ROW address selected according to a predetermined criterion for the count value, is replaced with the first ROW address, and the group to which the second ROW address belongs and the group to which the first ROW address belongs When is different, among the plurality of count values held in the second holding means, the count value corresponding to the first ROW address is set with reference to the count value corresponding to the group to which the first ROW address belongs. When the group to which the second ROW address belongs and the group to which the first ROW address belongs are the same, the count value held in the first holding means is updated corresponding to the second ROW address. A method including setting the updated count value as a count value corresponding to the first ROW address. A method executed by a memory controller that controls a DRAM whose ROW address is divided into multiple groups.
The ROW address is associated with the count value updated when the Activate command is issued for the ROW address and held in the first holding means, and the number of entries that can hold the ROW address is the ROW address. To keep, less than the total number of
When the count value held in the first holding means satisfies a predetermined condition, the Target Row Refresh command for the corresponding ROW address is issued.
Holding a plurality of count values corresponding to each of a plurality of groups of ROW addresses in the second holding means, and
If an Activate command is issued for the first ROW address, which is a ROW address that is not held by the first holding means, and there is an empty entry in the first holding means, the first ROW address is used as the entry. At the same time as registering, among the plurality of count values held in the second holding means, the count value corresponding to the first ROW address is set by referring to the count value corresponding to the group to which the first ROW address belongs. And how to include.

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