JP6938344B2 - Time digital conversion circuit - Google Patents

Description

The present invention relates to a time digital conversion circuit.

Conventionally, voltage / current signals are generally used for analog digital signal processing. Further, an AD conversion circuit, a DA conversion circuit, an analog filter, or the like can be mentioned as a signal processing circuit. On the other hand, in the ultrafine CMOS process, it is difficult to secure the dynamic range of the voltage / current signal due to the low power supply voltage, and it is difficult to realize a high-performance AD conversion circuit, DA conversion circuit, and analog filter. However, since the digital circuit benefits from miniaturization, it can operate at high speed even under a low power supply voltage, and the time resolution of the digital circuit is improved. By using the time signal for signal processing, it is possible to perform high-precision signal processing in an ultrafine CMOS process, but when using the time signal for analog-digital signal processing, a time-digital conversion circuit is required. Further, in order to secure the dynamic range, it is indispensable to improve the accuracy of the time-digital conversion circuit.

There are various circuit methods for the time-digital conversion circuit, but the time-digital conversion circuit using the oscillation circuit is a circuit method that can realize a high dynamic range with a simple configuration.

In the following Patent Document 1 and Non-Patent Document 1, a time-digital conversion circuit for avoiding the problem of metastability is proposed. In Non-Patent Documents 2 and 3, in a time digital conversion circuit using an oscillator circuit, the phase output signal of the oscillator circuit is not treated as a binary digital signal of 0,1 but as an analog signal having a subdivided voltage level. A technique that enables high accuracy by handling and interpreting the phase more precisely has been presented.

U.S. Pat. No. 2015/0077279A1 (published March 19, 2015)

Matthias Fugger, Attila Kinali, Christoph Lenzen, and Thomas Polzer, “Metastability-Aware Memory-Efficient Time-to-Digital Converters”, In IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2017 Shingo Mandai, “A 780x800 um2 Multichannel Digital Silicon Photomultiplier With Column-Parallel Time-to-Digital Converter and Basic characterization”, IEEE Trans. On Nuclear Science vol. 61, Browse Journals & Magazines, no. 1, Feb., 2014, page 44-52 Singo Mandai, “Multichannel Digital Silicon Photomultipliers for Time-of-Flight PET”, TU Delft Library, the Netherlands, 1, July, 2014, page 74-80, 87-92

However, in the high precision technology described in Non-Patent Document 2 and Non-Patent Document 3 as described above,
-Metastability of the latch circuit due to a violation of the setup time-Metastability of the latch circuit due to a violation of the hold time-Clock skew-There is a problem with accuracy deterioration due to timing deviation of the digital circuit due to individual differences between elements.

In the time digital conversion circuit described in Non-Patent Documents 2 and 3, a method for avoiding the above-mentioned deterioration in accuracy has not been proposed.

One aspect of the present invention has been made in view of the above problems, and an object of the present invention is to realize a time-digital conversion circuit in which accuracy deterioration is suppressed.

In order to solve the above problems, the time digital conversion circuit according to one aspect of the present invention includes an oscillation circuit that outputs a plurality of phase signals and a stop that is input after the plurality of phase signals are input and is input after the start signal is input. Due to the signal input, a phase sampling circuit that samples each of a plurality of phase signals and outputs an output signal according to the sampled result, and one of the plurality of phase signals are input, and the stop signal is input. The output of the clock generation circuit that latches and outputs the one phase signal, the counter circuit that counts the output of the clock generation circuit and counts the period of the oscillation circuit, and the output of the phase sampling circuit. comprising a signal, and the counter value of the counter circuit, with reference to the output of the clock generating circuit, a decode circuit that outputs a digital signal indicating the time from the start signal input to the stop signal input.

According to one aspect of the present invention, it is possible to realize a time-digital conversion circuit in which accuracy deterioration is suppressed.

This is an example of a conventional time-digital conversion circuit. It is a conventional figure which shows the lookup table for obtaining the value which concerns on the calculation of the output signal of a time digital conversion circuit from the digital output of a phase sampling circuit. It is a timing diagram which shows an example of the output signal in each element or a circuit. It is a timing diagram which shows an example when the problem of metastability or the timing shift occurs. It is the schematic which shows the time digital conversion circuit. It is a figure which shows the lookup table. It is a timing diagram which shows an example of the output signal in each element or a circuit. It is a timing diagram which shows an example when the problem of metastability or the timing shift occurs. This is a configuration example of the first to fourth phase sampling circuits.

[Embodiment 1]
First, the time-digital conversion circuit, which is the premise configuration of the present invention, will be described with reference to FIG.

FIG. 1 is a schematic view showing a time digital conversion circuit 1 which is a prerequisite configuration of the present invention.

As shown in FIG. 1, the time-digital conversion circuit 1 includes an oscillation circuit 2, phase sampling circuits 3a to 3d, a clock generation circuit 4, a counter circuit 5, and a decoding circuit 6.

The START signal from the START terminal 8 and the STOP signal from the STOP terminal 9 are input to the time digital conversion circuit 1, and the STOP signal is transmitted from the time when the START signal changes from Low (0) to High (1). Measure the time between the points of change from Low to High.

The oscillation circuit 2 is a ring-type oscillation circuit including non-inverting delay elements 21 to 24 and an inverting element 25 that inverts the output PHI3 of the delay element 24 and feeds it back to the delay element 21.

The delay elements 21 to 24 have a digital signal input terminal, a digital signal output terminal, and an enable control terminal, and delay the digital signal input to the digital signal input terminal from the digital signal output terminal for a predetermined fixed time to delay the phase. Output as an output signal (PHI0 to 3). The delay elements 21 to 24 start oscillating due to the input of the START signal, and when the input from the enable control terminal is Low, the delay elements 21 to 24 do not perform the delay operation, output a predetermined digital value set in advance, and enable. When the input from the control terminal is High, the delay operation is performed. The enable control terminal is connected to the START terminal, which is a time measurement start signal of the time digital conversion circuit 1.

The oscillation circuit included in the time digital conversion circuit 1 may be an oscillation circuit that is not a ring type and can realize the same function or an equivalent function.

The phase sampling circuit (group) 3 includes a first phase sampling circuit 3a, a second phase sampling circuit 3b, a third phase sampling circuit 3c, and a fourth phase sampling circuit 3d.

The first to fourth phase sampling circuits 3a to 3d sample the phase output signals (PHI0 to 3) from the oscillation circuit 2 as analog signals, compare them with a predetermined voltage level, and output digital values (DPHI0 to 3). do.

The phase sampling circuit 3a compares the buffer circuit 31a that amplifies the output signal of the oscillation circuit 2, the capacitor (capacitor) 32a for sampling the output signal, and the sampled output signal with a certain reference voltage level, and compares the sampled output signal with a reference voltage level. It includes a comparator circuit 33a that outputs a comparison result as a digital signal, and a delay circuit 34a for operating the comparator circuit 33a after a certain period of time has elapsed immediately after sampling. The phase signal means a signal having the same waveform periodically.

Further, as shown in FIG. 1, the second to fourth phase sampling circuits 3b to 3d also include members corresponding to the members included in the phase sampling circuit 3a.

The first to fourth phase sampling circuits 3a to 3d sample the voltage level of the phase signal (PHI0 to 3) at the time when the STOP signal, which is the time measurement stop signal, changes from Low to High.

The clock generation circuit 4 includes a latch circuit 41 and a Schmitt trigger circuit 42.

The latch circuit 41 is a circuit capable of holding a value corresponding to 1 bit of High or Low. The phase output signal PHI3 of the oscillation circuit 2 and the STOP signal are input to the latch circuit 41, and while the STOP signal is Low, the value of the phase output signal PHI3 is output to the Schmitt trigger circuit 42 as it is, but the STOP signal is output. During High, the value of the output signal at the time when the STOP signal changes from Low to High is retained.

The Schmitt trigger circuit 42 is a circuit capable of removing noise from the input signal. The Schmitt trigger circuit 42 has two threshold values, large and small, and when the input signal has a value larger than the larger threshold value, it outputs a high signal and has a value smaller than the smaller input signal threshold value. If there is, a low signal is output. If the input signal is greater than or equal to the smaller threshold value and less than or equal to the larger threshold value, the immediately preceding output is continuously output.

The Schmitt trigger circuit 42 is preferably arranged after the latch circuit 41 in order to avoid the metastability problem due to the setup / hold time violation of the latch circuit 41.

That is, the clock generation circuit 4 includes the Schmitt trigger circuit 42, and the clock signal shaped by the Schmitt trigger circuit 42 is input to the counter circuit 5.

The counter circuit 5 can count the oscillation cycle of the oscillation circuit 2 during the period until the START signal is set to High and the STOP signal becomes High by the operation of the clock generation circuit 4.

The counter circuit 5 is a ripple counter type counter composed of a plurality of flip-flops, and counts the falling edge of the input signal from High to Low.

The decoding circuit 6 decodes from the outputs DPHI0 to 3 of the phase sampling circuits 3a to 3d and the digital outputs MSB_CNT of the counter circuit 5.

FIG. 2 is a diagram showing a look-up table for obtaining LSB_DEC, which is a value related to the calculation of the output signal DOUT of the time digital conversion circuit 1, from the digital outputs DPI0 to DPI3 of the phase sampling circuits 3a to 3d. For example, when DPHI0 = 1, DPHI1 = 1, DPHI2 = 1, and DPHI3 = 0, the value of LSB_DEC is 3 from FIG.

From the LSB_DEC and the output MSB_CNT of the counter circuit 5, the output DOUT of the decoding circuit 6 is calculated according to the following equation and used as the output signal of the time digital conversion circuit 1.
DOUT = LSB_DEC + MSB_CNT ・ 8
By performing the above decoding, a high-resolution time-digital conversion circuit 1 that outputs a value based on the count value (MSB_CNT) from the counter circuit 5 and the output signal (DPHI0 to 3) of the phase sampling circuit 3 is provided. It has the effect of being able to be realized.

However, since the time-digital conversion circuit 1 handles signals on the order of pico-second, there is a secondary problem that unexpected timing deviation and metastability problems occur.

Hereinafter, the problem of metastability will be described with reference to FIGS. 3 and 4.

FIG. 3 is a timing diagram showing an example of an output signal in each element or circuit.

In FIG. 3, the START signal is set to High at a timing T0 (not shown), the falling edge of PHI3 (input signal of the clock generation circuit 4) from High to Low is counted N times in Tn, and then PHI3 falls down. It shows the case where the STOP signal changes from Low to High immediately before the count and at almost the same timing TS2.

Since PHI0 = 0, PHI1 = 0, PHI2 = 0, PHI3 = 1 at the time of TS2 are sampled, DPHI0 = 0, DPHI1 = 0, DPHI2 = 0, DPHI3 = 1 are output from the phase sampling circuit. Further, from FIG. 2, LSB_DEC = 7. And since the value of the ripple counter is N and MSB_CNT = N, DOUT = 7 + 8N. FIG. 3 shows an ideal case where there is no timing shift or metastability problem.

FIG. 4 is a timing diagram showing an example when a metastability problem or a timing shift occurs.

In FIG. 4, as in the case shown in FIG. 3, the START signal is set to High at a timing T0 (not shown), the falling edge of PHI3 is counted N times at Tn, and then immediately before the counting of the next falling edge of PHI3. , Shows the case where the STOP signal changes from Low to High at almost the same timing TS2.

However, unlike the case shown in FIG. 3, the falling edge of PHI3 is counted by the counter circuit 5 before TS2 due to the metastability problem of the latch circuit 41 in the clock generation circuit 4 or the occurrence of timing deviation. ing.

In the above case, DPHI0 = 0, DPHI1 = 0, DPHI2 = 0, DPHI3 = 1, so LSB_DEC = 7 from Fig. 2, but since the counter circuit count value is N + 1, MSB_CNT = N + 1. , DOUT = 7 + 8 ・ (N + 1).

As described above, the measurement result (DOUT) may have different values due to the occurrence of metastability problems or timing deviations. When such a thing occurs, the accuracy of measurement deteriorates.

Next, the time digital conversion circuit 1a according to the first embodiment of the present invention will be described with reference to FIGS. 5 to 9. The time-digital conversion circuit 1a avoids the problem of metastability of the latch circuit and the deterioration of accuracy due to the timing deviation of the digital circuit.

For convenience, the same reference numerals will be added to the members having the same functions as the members in the description using the time digital conversion circuit 1 described above, and the description will be omitted.

FIG. 5 is a schematic view showing a time digital conversion circuit 1a. As shown in FIG. 5, the time-digital conversion circuit 1a includes an oscillation circuit 2, a phase sampling circuit (group) 3, a clock generation circuit 4a, a counter circuit 5, and a decoding circuit 6a.
The oscillation circuit 2 is a ring-type oscillation circuit in which delay elements are arranged in a ring shape, and is a single-ended type including delay elements having one input and one output for simplification of explanation. A differential type and ring type oscillation circuit in which a delay element having two inputs and two outputs is formed in a ring shape can also be configured.

By using the differential oscillation circuit, it is possible to realize a time digital conversion circuit that is not easily affected by the power supply and ground noise.

The first to fourth phase sampling circuits 3a to 3d included in the phase sampling circuit 3 sample the phase output signals (PHI0 to 3) from the oscillation circuit 2 as analog signals, compare them with a predetermined voltage level, and compare them with a digital value (digital value (PHI0 to 3d). Output DPHI0 to 3).

The clock generation circuit 4a includes a Schmitt trigger circuit 42, and a clock signal shaped by the Schmitt trigger circuit 42 is input to the counter circuit 5.

Due to metastability issues, very short parasitic pulses can occur from the latch circuit 41. At this time, even when the correction method shown in the present invention is used, the problem of metastability cannot be avoided. By providing the Schmitt trigger circuit 42, the metastability problem can be avoided more reliably.

In the decoding circuit 6a, in addition to the digital outputs DPHI0, DPHI1, DPHI2, and DPHI3 of the phase sampling circuits 3a to 3d and the digital output MSB_CNT of the counter circuit 5, the output signal CLK3 of the latch circuit 41 included in the clock generation circuit 4a is provided. The configuration is different from that of the time digital conversion circuit 1 shown in FIG. 1 in that it is input.

The above configuration is an example, and does not necessarily mean that the configuration must be the same as that of the time-digital conversion circuit 1a when the present invention is implemented.

FIG. 6 is a diagram showing a look-up table.

LSB_DEC which is a value related to the calculation of the output signal DOUT of the time digital conversion circuit 1a from the digital outputs DPI0 to DPI3 of the phase sampling circuits 3a to 3d and the output signal of the clock generation circuit 4a according to the lookup table shown in FIG. And MSB_CAL. For example, when DPHI0 = 1, DPHI1 = 1, DPHI2 = 0, DPHI3 = 0, and CLK3 = 0, LSB_DEC = 2 and MSB_CAL = 0 are shown in FIG.

From the LSB_DEC, MSB_CAL, and the output signal MSB_CNT of the counter circuit 5, the output DOUT'of the decoding circuit 6a is calculated according to the following equation, and is used as the output signal of the time digital conversion circuit 1a.
DOUT'= LSB_DEC + (MSB_CAL + MSB_CNT) ・ 8
In the above description, the decoding circuit 6a generates LSB_DEC and a new reference signal MSB_CAL from the digital outputs DPI0 to DPI3 of the phase sampling circuits 3a to 3d and the output CLK3 of the clock generation circuit 4a, and the above reference signal. In other words, the digital signal DOUT'corresponding to the counter value MSB_CNT of the counter circuit 5 is output. Further, by using the value of MSB_CAL together with the reference signal LSB_DEC in the calculation of the output DOUT'of the decoding circuit 6a, it is possible to correct the inconsistency caused by the metastability problem or the timing deviation as described later. can.

By checking the value of MSB_CAL, it is possible to check whether or not inconsistency has occurred due to metastability, clock skew, or timing deviation. Specifically, if the value of MSB_CAL is 0, the above-mentioned inconsistency does not occur, but if the value of MSB_CAL is 1 or -1, the above-mentioned inconsistency occurs.

FIG. 7 is a timing diagram showing an example of an output signal in each element or circuit.

FIG. 7 is a timing diagram showing an ideal case in which a metastability problem or a timing shift does not occur. When the START signal is already at the High level (1), the STOP signal changes from Low to High. It is a timing diagram at the time of switching to.

During the period when the START signal is High, the oscillation circuit 2 oscillates, and the output waveforms of the delay elements 21 to 24 are the waveforms shown in PHI 0 to 3.

The counter circuit 5 counts the falling edge of the output signal of the clock generation circuit 4a from High to Low after the START signal becomes High, and the output is updated as 0, 1, ..., N-1, N. The phase sampling circuits 3a to 3d sample the delay element output when the STOP signal changes to 1, and output 0 or 1 by comparing with the intermediate value between the high level and the low level of the delay element. Each comparator circuit outputs a value of 0 or 1 depending on the sampled values of PHI0 to 3 at the moment when the STOP signal becomes 1 (as an example, in the present embodiment (DPHI0, DPHI1, DPHI2, DPHI3) = (0, 0, 0, 1)). Further, in the clock generation circuit 4a, the input value from the output signal PHI3 of the oscillation circuit 2 is latched (as an example, in the present embodiment, the state of CLK3 = 1 is maintained). From the above sampled or latched values DPHI0 to 3 and CLK3, according to FIG. 6, LSB_DEC = 7, MSB_CAL = 0, and DOUT'is an ideal value of 7 + 8N.

In the time-digital conversion circuit 1a of the present invention, inconsistency occurs between the output of the counter circuit 5 and the outputs of the phase sampling circuits 3a to 3d even if the problem of semi-stability of the latch circuit 41 or the timing deviation of the digital circuit occurs. Explain that it is possible to avoid problems caused by quasi-stability and timing lag.

FIG. 8 is a timing diagram showing an example of a case where a mismatch occurs in the latch circuit 41.

The description of the signal having the same phase as that of FIG. 7 will be omitted, and only the differences will be described.

FIG. 8 is a timing diagram showing an example when a metastability problem or a timing shift occurs.

As shown in FIG. 8, since the phase of the output signal CLK3 of the latch circuit 41 is slightly ahead of the phase of the output signal PHI3 of the oscillation circuit 2 due to circuit variation or the like, when the STOP signal becomes 1, it becomes PHI3. A timing difference occurs with CLK3, and the latch circuit 41 holds Low (0) instead of High (1), so that CLK3 becomes Low (0).

In the above case, when the output of the time digital conversion circuit 1a is calculated according to FIG. 2, DOUT (without correction) = 15 + 8N, and the value is settled to a value different from DOUT (ideal) due to the timing deviation. On the other hand, when calculated according to FIG. 6, DOUT'(with correction) = 7 + 8N, which is the same value as DOUT (ideal). Therefore, according to the correction method, even if the timing shift occurs, the performance of the time digital conversion circuit 1a does not deteriorate.

The decoding circuit 6a has a configuration in which the latch circuit 41 and the decoding circuit 6a are directly connected if the output signal CLK3 from the latch circuit 41, in other words, the internal state of the clock generation circuit 4a can be obtained. Not limited.

That is, the decoding circuit 6a generates LSB_DEC and the reference signal MSB_CAL corresponding to the output signal CLK3 or the internal state of the clock generation circuit 4a and the output signals DPHI0 to DPHI3 of the phase sampling circuits 3a to 3d, and a timing error occurs. Detect that it has occurred.

In this way, by using the value of the reference signal MSB_CAL together with LSB_DEC in the calculation of the output DOUT'of the decoding circuit 6a, in other words, the clock generation circuit 4a is combined with the output signals DPHI0 to DPHI3 of the phase sampling circuits 3a to 3d. By using the output signal CLK3 or the internal state of the above in the calculation of the output DOUT'of the decoding circuit 6a, it is possible to correct the inconsistency caused by the problem of quasi-stability or the timing deviation.

As described above, the time-digital conversion circuit 1a is caused by the oscillation circuit 2 that outputs a plurality of phase signals and the input of the stop signal that is input after the plurality of phase signals are input and is input after the start signal is input. Phase sampling circuits 3a to 3d that sample each of a plurality of phase signals and output an output signal according to the sampled result, and one of the plurality of phase signals are input, and due to the input of the stop signal, Outputs of a clock generation circuit 4a that latches and outputs the one phase signal, a counter circuit 5 that counts the output of the clock generation circuit 4a and counts the period of the oscillation circuit 2, and the phase sampling circuits 3a to 3d. The decoding circuit 6a that outputs a digital signal indicating the time from the start signal input to the stop signal input by referring to the signal, the counter value of the counter circuit 5, and the output or internal state of the clock generation circuit 4a. Be prepared.

According to the above configuration, the time digital conversion circuit 1a in which the deterioration of accuracy is suppressed can be realized.

Hereinafter, a configuration example of the phase sampling circuit 3 will be described.

FIG. 9 is a configuration example of the first to fourth phase sampling circuits 3a to 3d.

The phase sampling circuits 3a to 3d are arranged between an inverter circuit composed of switching elements MN1 and MP2 arranged to transmit an input signal to the capacitor 32 and the comparator input terminal, and an output terminal of the inverter circuit and the capacitor 32. The sampling switch SW1 was sampled, the capacitor 32 for holding the sampled voltage signal, the resistors R1 and R2 for generating the intermediate voltage between the power supply voltage VDD and the ground level, and the intermediate voltage level sampled. It is provided with a comparator circuit 33 that compares voltage signals and outputs a signal having a logic level of High or Low.

The switching elements MN1 and MP2 are FETs (Field effect transistors) and correspond to the components of the buffer circuits 31a to 31d in the first to fourth phase sampling circuits 3a to 3d.

When the STOP signal is Low, the capacitor 32 is connected to the output terminal of the inverter circuit, and the inverted signal of the output voltage of the oscillation circuit 2 is transmitted to the capacitor 32. At the moment when the STOP signal changes from Low to High, the sampling switch SW1 is shut off, and the voltage value at that moment is held in the capacitor 32. Waiting for the voltage held in the capacitor 32 to stabilize, the STOP signal is transmitted to the comparator circuit 33, the voltage held in the capacitor 32 is compared with the intermediate voltage level, and the comparator circuit 33 is used as the logic level. Outputs a signal that is High or Low.

As described above, the phase sampling circuits 3a to 3d include an analog signal sampling circuit composed of the capacitor 32 and the switch SW1, and each of the above sampling circuits samples the phase signal as an analog voltage signal.

Each phase signal of the oscillation circuit 2 is treated as an analog signal, and the voltage held in the capacitor 32 is compared not only with the one intermediate voltage level but also with a plurality of reference voltage levels, or each phase signal is compared in combination. Therefore, the time resolution of the phase sampling circuit can be improved.

By performing decoding as in this embodiment, the count value (MSB_CNT) in the counter circuit 5, the phase signal (DPHI0 to 3) of the oscillation circuit 2, and the output signal (CLK3) from the latch circuit 41 latched by the STOP signal. ) And a high-resolution time-digital conversion circuit 1a that outputs a value based on the above can be realized.

In the present embodiment, for the sake of simplicity, the input signals of the phase sampling circuits 3a to 3d are the corresponding output signal 1 inputs of the oscillation circuit 2, and the predetermined voltage levels compared in the comparator circuits 33a to 33d are set. Although the intermediate value between the high level and the low level of each input signal (PHI0 to 3) is set, the present invention is valid even with the configuration as described in Non-Patent Documents 2 and 3. Further, in order to simplify the explanation here, the oscillation circuit 2 is a single-ended system, but it is easier to improve the performance by using a fully differential oscillation circuit.

〔summary〕
The time digital conversion circuit 1a according to the first aspect of the present invention is caused by the oscillation circuit 2 that outputs a plurality of phase signals and the input of the stop signal that is input after the plurality of phase signals are input and is input after the start signal is input. , Phase sampling circuits 3a to 3d that sample each of a plurality of phase signals and output an output signal according to the sampled result, and one of the plurality of phase signals is input, which is caused by the input of the stop signal. A clock generation circuit 4a that latches and outputs the one phase signal, a counter circuit 5 that counts the output of the clock generation circuit 4a and counts the period of the oscillation circuit, and the phase sampling circuits 3a to 3a. With reference to the output signal of 3d, the counter value of the counter circuit 5, and the output or internal state of the clock generation circuit 4a, a digital signal indicating the time from the start signal input to the stop signal input is output. It is configured to include a decoding circuit 6a.

According to the above configuration, the time digital conversion circuit 1a in which the deterioration of accuracy is suppressed can be realized.

In the time digital conversion circuit 1a according to the second aspect of the present invention, in the above aspect 1, the decoding circuit 6a has the output or internal state of the clock generation circuit 4a and the output signals of the phase sampling circuits 3a to 3d. It may be configured to generate a corresponding reference signal and detect that a timing error has occurred.

According to the above configuration, the reference signal corresponding to the output CLK3 or the internal state of the clock generation circuit 4a and the output signals DPHI0 to DPHI3 of the phase sampling circuits 3a to 3d is used for the calculation of the output DOUT'of the decoding circuit 6a. This makes it possible to correct inconsistencies due to quasi-stability problems or timing lag.

In the time digital conversion circuit 1a according to the third aspect of the present invention, in the above aspect 1 or 2, the phase sampling circuits 3a to 3d include an analog signal sampling circuit including a capacitor 32 and a switch SW1. The sampling circuit may be configured to sample the phase signal as an analog voltage signal.

According to the above configuration, each phase signal of the oscillation circuit 2 is treated as an analog signal, and the voltage held in the capacitor 32 can be compared not only with the one intermediate voltage level but also with a plurality of reference voltage levels, or each phase can be compared. By comparing the signals in combination, the time resolution of the phase sampling circuit can be improved.

In any of the above aspects 1 to 3, the time digital conversion circuit 1a according to the fourth aspect of the present invention includes the Schmitt trigger circuit 42 in the clock generation circuit 4a, and the Schmitt trigger circuit 5 in the counter circuit 5. A clock signal shaped by the circuit 42 may be input.

According to the above configuration, the problem of metastability can be more reliably avoided by providing the Schmitt trigger circuit 42.

According to the above configuration, it is possible to prevent erroneous detection in the counter circuit 5.

In the time digital conversion circuit 1a according to the fifth aspect of the present invention, in any one of the above aspects 1 to 4, the oscillation circuit 2 is a ring type oscillation circuit, and the differential is composed of a differential delay element. It may be configured as an oscillation circuit.

According to the above configuration, by using the differential oscillation circuit, it is possible to realize a time digital conversion circuit that is not easily affected by the power supply and ground noise.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the claims.

1, 1a Time digital conversion circuit 2 Oscillation circuit 3, 3a to 3d Phase sampling circuit 4, 4a Clock generation circuit 5 Counter circuit 6, 6a Decoding circuit 8 START terminal 9 STOP terminal 21 to 24 Delay element 25 Inverting element 31a to 31d Buffer Circuit 32a to 32d Capacitor (capacitor)
33a to 33d Comparator circuit 34a to 34d Delay circuit 41 Latch circuit 42 Schmitt trigger circuit

Claims (5)

An oscillator circuit that outputs multiple phase signals and
With a phase sampling circuit in which the plurality of phase signals are input, each of the plurality of phase signals is sampled due to the input of the stop signal input after the start signal is input, and an output signal is output according to the sampled result. ,
A clock generation circuit in which one of the plurality of phase signals is input, and due to the input of the stop signal, the one phase signal is latched and output.
A counter circuit that counts the output of the clock generation circuit and counts the period of the oscillation circuit.
An output signal of the phase sampling circuit, and the counter value of the counter circuit, with reference to the output of the clock generating circuit, decoding and outputs a digital signal indicating the time from the start signal input to the stop signal input A time-digital conversion circuit characterized by including a circuit. The above decoding circuit
Output and the clock generation circuit,
A reference signal corresponding to the output signal of the phase sampling circuit is generated.
The time digital conversion circuit according to claim 1, wherein the occurrence of a timing error is detected. The phase sampling circuit includes an analog signal sampling circuit composed of a capacitor and a switch.
The time-digital conversion circuit according to claim 1 or 2, wherein each of the sampling circuits samples a phase signal as an analog voltage signal. The clock generation circuit includes a Schmitt trigger circuit.
The above counter circuit has
The time digital conversion circuit according to any one of claims 1 to 3, wherein a clock signal shaped by the Schmitt trigger circuit is input. The above oscillation circuit is a ring type oscillation circuit.
The time-digital conversion circuit according to any one of claims 1 to 4, wherein the time-digital conversion circuit is a differential oscillation circuit composed of a differential delay element.

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