JP6925729B2 - Manufacturing method of semiconductor devices - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

In the manufacturing process of semiconductor devices such as semiconductor integrated circuits, a semiconductor substrate may be irradiated with light ions such as hydrogen or helium to form a defective region for the purpose of improving performance. When a lattice defect is formed in a semiconductor substrate by ion irradiation, electrons and holes recombine and disappear through the defect, so that the local lifetime characteristics of a diode in a semiconductor device can be controlled, for example. Further, in order to form a defect region or a high resistance region at different positions in the depth direction of the semiconductor substrate, a method of performing ion irradiation a plurality of times while changing the acceleration energy has been proposed (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2015-119039

When the defect regions are formed at different positions in the depth direction based on the method of the above document, it becomes necessary to change the acceleration energy in the middle of the irradiation step. When adjusting the energy of the beam source, after changing the operating conditions of the beam source, there is a waiting time until the operation of the beam source is stabilized under the changed operating conditions. When adjusting the energy by replacing the energy reduction plate on the downstream side while keeping the output energy from the beam source constant, release the vacuum in the chamber where the reduction plate is placed, replace the reduction plate, and vacuum again. It is necessary to pull it, and there is a waiting time due to the replacement of the reduction plate. From the viewpoint of productivity of the ion irradiation process, it is preferable to reduce the waiting time required for energy change.

One of the exemplary objects of an aspect of the present invention is to improve the productivity of the process of forming defect regions at different positions in the depth direction of the semiconductor substrate.

The method for manufacturing a semiconductor device according to an aspect of the present invention is a method for manufacturing a semiconductor device including irradiating a semiconductor substrate with an ion beam through a mask, wherein the mask uses an incident ion beam as the first energy. It has a first region for deceleration and a second region for decelerating to a second energy smaller than the first energy. The first region and the second region are alternately arranged in at least one direction, and are viewed from the incident direction of the ion beam. The widths of the first region and the second region in the arrangement direction at the time are 500 μm or less, respectively.

It should be noted that any combination of the above components or components and expressions of the present invention that are mutually replaced between methods, devices, systems, and the like are also effective as aspects of the present invention.

According to the present invention, defect regions can be formed at different positions in the depth direction of the semiconductor substrate by one ion beam irradiation.

It is a figure which shows typically the structure of the ion irradiation apparatus which concerns on embodiment. It is sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is a top view which shows typically the structure of the mask which concerns on embodiment. It is sectional drawing which shows typically the beam passing through the 1st region of a mask. It is sectional drawing which shows typically the beam passing through the 2nd region of a mask. It is a graph which shows the relationship between the irradiation depth of an ion beam and the beam diffusion width. It is a graph which shows the ion irradiation amount distribution in the depth direction in the ion irradiation step which concerns on embodiment. It is a top view which shows typically the structure of the mask which concerns on the modification. It is a top view which shows typically the structure of the mask which concerns on the modification. It is sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the modification. It is a figure which shows typically the 1st ion irradiation process which concerns on a modification. It is a figure which shows typically the 2nd ion irradiation process which concerns on a modification.

Before concretely explaining the present invention, an outline will be described. The present embodiment is a method for manufacturing a semiconductor device, which includes a step of irradiating a semiconductor substrate with an ion beam to form a defect region in the semiconductor substrate. The ion beam irradiates the semiconductor substrate through the mask. The mask has a first region for decelerating the incident ion beam to the first energy and a second region for decelerating the incident ion beam to a second energy smaller than the first energy, and the first region and the second region are in at least one direction. They are arranged alternately. The beam decelerated to the first energy forms the first defect region at the first depth position, and the beam decelerated to the second energy forms the second defect region at the second depth shallower than the first depth. Form.

In the present embodiment, the mask is configured so that the width of the first region and the second region in the arrangement direction when viewed from the incident direction of the ion beam is 100 μm or less. As a result, each of the first defect region and the second defect region can be continuously formed in the horizontal direction orthogonal to the depth direction. Therefore, in the present embodiment, continuous defect regions can be simultaneously formed at different depth positions by one irradiation, and the productivity of the ion irradiation step can be improved as compared with the case of irradiating a plurality of times. can.

Hereinafter, embodiments for carrying out the present invention will be described in detail. The configuration described below is an example and does not limit the scope of the present invention. Further, in the description of the drawings, the same elements are designated by the same reference numerals, and duplicate description will be omitted as appropriate. Further, in each cross-sectional view referred to in the following description, the thickness and size of the semiconductor substrate and other layers are for convenience of explanation and do not necessarily indicate actual dimensions and ratios.

FIG. 1 is a diagram schematically showing the configuration of the ion irradiation device 50 according to the embodiment. The ion irradiation device 50 includes a beam generation device 52, a beam transport device 54, and an irradiation processing chamber 56. The beam generator 52 includes a cyclotron type or Van de Graaff type accelerator, and generates, for example, an ion beam B having an acceleration energy of about 1 MeV to 100 MeV. The beam transport device 54 transports the ion beam B generated by the beam generator 52 to the irradiation processing chamber 56.

The beam transport device 54 is provided with a deflection device 60, a beam slit 62, and an absorber 64. The deflection device 60 scans the ion beam B from the beam generation device 52 by an electric field type or a magnetic field type so that the entire semiconductor substrate 12 is sequentially scanned by the ion beam B. The scanned beam B passes through the beam slit 62 and the absorber 64. The absorber 64 is an energy reduction plate made of a material such as aluminum (Al), and the ion beam B passing through the absorber 64 is decelerated and adjusted to have a desired energy.

The irradiation processing chamber 56 is provided with a wafer holding device 66 that holds the semiconductor substrate 12 and the mask 20 to be irradiated. The mask 20 is arranged closer to the front side of the ion beam B in the traveling direction than the semiconductor substrate 12. Therefore, the scanned beam B is incident on the semiconductor substrate 12 through the mask 20. The mask 20 decelerates the incident ion beam B and adjusts the energy of the beam incident on the semiconductor substrate 12. By irradiating the ion beam B, a defect region is formed inside the semiconductor substrate 12.

As the ion beam B for forming the defect region, ^{light ions such as hydrogen (H) and helium (3} He, ⁴ He), which are elements having a small atomic number, are used. The energy of the ion beam B incident on the mask 20 is not particularly limited, but is, for example, about 0.1 MeV to 100 MeV, and typically about 1 MeV to 30 MeV.

FIG. 2 is a cross-sectional view schematically showing a manufacturing method of the semiconductor device 10 according to the embodiment, and shows in detail the configurations of the semiconductor substrate 12 and the mask 20 of FIG. The semiconductor device 10 is a semiconductor integrated circuit formed by using the semiconductor substrate 12, and is, for example, a power semiconductor device such as a system LSI or an IGBT (insulated gate bipolar transistor). The semiconductor device 10 includes an element region 14, a first defect region 16, and a second defect region 18. The element region 14 is a region in which an element such as a transistor or a diode is formed, and is provided on the first main surface 12a of the semiconductor substrate 12. The first defect region 16 and the second defect region 18 are provided at positions separated from the first main surface 12a of the semiconductor substrate 12, and are formed at different positions in the depth direction (z direction) of the semiconductor substrate 12.

In the example of FIG. 2, the beam is irradiated from the second main surface 12b on the side opposite to the first main surface 12a of the semiconductor substrate 12, and the first defect region 16 and the second defect region 18 are formed. By beam irradiation, the first defect region 16 is formed from the second main surface 12b to the position of the first depth d1, and the second defect region 18 is formed from the second main surface 12b to the position of the second depth d2. .. It is also possible to form a defect region by irradiating a beam from the first main surface 12a on which the element region 14 is provided.

The mask 20 has a first region 31 that decelerates the incident ion beam B to the first energy E1, and a second region 32 that decelerates the incident ion beam B to a second energy E2 that is smaller than the first energy E1. The beam that has passed through the first region 31 is emitted from the mask 20 as the first beam B1 having the first energy E1 and is incident on the semiconductor substrate 12. On the other hand, the beam that has passed through the second region 32 is emitted from the mask 20 as the second beam B2 having the second energy E2 and is incident on the semiconductor substrate 12.

The mask 20 has a base layer 22 and a pattern layer 24. The base layer 22 is provided over the entire incident range of the ion beam B, and is provided over both the first region 31 and the second region 32 described above. The pattern layer 24 is selectively provided in the second region 32 and is not provided in the first region 31. Therefore, the opening 26 of the pattern layer 24 is formed in the first region 31, and the upper surface of the base layer 22 is exposed. The side wall of the opening 26 is preferably formed vertically along the incident direction (z direction) of the ion beam B.

FIG. 3 is a top view schematically showing the configuration of the mask 20 according to the embodiment. FIG. 2 corresponds to the cross section taken along line AA of FIG. The mask 20 is configured such that the first region 31 and the second region 32 are alternately arranged in a predetermined direction (x direction). In the illustrated example, a strip-shaped or rectangular opening 26 extending in the y direction is provided in the first region 31. The widths W1 and W2 of the first region 31 and the second region 32 in the arrangement direction (x direction) are configured to be 100 μm or less, respectively, and are configured to be, for example, 70 μm or less or 30 μm or less. The preferable dimensions of the widths W1 and W2 in the arrangement direction of the first region 31 and the second region 32 will be described later.

Returning to FIG. 2, the beam B1 incident on the first region 31 of the mask 20 passes through the base layer 22 and reaches the semiconductor substrate 12. On the other hand, the beam incident on the second region 32 of the mask 20 passes through the base layer 22 and the pattern layer 24 and reaches the semiconductor substrate 12. The second beam B2 emitted from the second region 32 is decelerated more than the first beam B1 emitted from the first region 31 by the amount of passing through the pattern layer 24, and as a result, has lower energy than the first beam B1. ..

The relatively high-energy first beam B1 reaches a relatively deep position d1 from the second main surface 12b, and the first defect region 16 reaches a predetermined range in the depth direction centered on the first depth position d1. To form. On the other hand, the relatively low-energy second beam B2 reaches a relatively shallow position d2 from the second main surface 12b, and has a second defect in a predetermined range in the depth direction centered on the second depth position d2. Region 18 is formed. The depth positions d1 and d2 where the first defect region 16 and the second defect region 18 are formed are determined by the ion species and energy values of the irradiated beams B1 and B2.

The energies E1 and E2 of the first beam B1 and the second beam B2 can be adjusted by appropriately selecting the thicknesses t1 and t2 of the base layer 22 and the pattern layer 24 and the material. Therefore, the depth positions d1 and d2 of the first defect region 16 and the second defect region 18 can be adjusted by appropriately designing the configuration of the mask 20. Specifically, the thickness t of the mask, the depth position d of the defect region, the ion range Rs of the material of the semiconductor substrate 12 of the beam having a specific energy E0 incident on the mask 20, and the ion range of the material of the mask 20. Using Rm, it can be described as t = Rm- (Rm / Rs) d. If the materials of the base layer 22 and the pattern layer 24 are the same, it can be described as t1 = Rm- (Rm / Rs) d1 and t2 = (Rm / Rs) (d1-d2).

As the material of the mask 20, a metal material or a resin material can be used. The elements constituting the mask 20 may be ejected toward the semiconductor substrate 12 by irradiation with the ion beam B and injected into the semiconductor substrate 12, so the mask is made of a material that does not easily affect the performance of the semiconductor device 10. 20 is preferably configured. If the semiconductor substrate 12 is silicon (Si), a metal material such as aluminum (Al), silicon (Si), or titanium (Ti) can be used as the material for the mask 20. A resin material such as polyimide can also be used as the mask 20.

To give an example of the material and thickness of the mask 20, the material of the base layer 22 and the pattern layer 24 is aluminum (Al), and the thickness of the base layer 22 is t1 = 288 μm and the thickness of the pattern layer 24 is t2 = 125 μm. be. ^{When 7.9 MeV hydrogen (H +} ) ions are incident on the silicon (Si) semiconductor substrate 12 through the mask 20, the first defect region 16 is formed at the position of d1 = 150 μm, and the first defect region 16 is formed at the position of d2 = 10 μm. A second defect region 18 is formed. These values can be calculated using the ion range Rs = 473 μm of Si and the ion range Rm = 422 μm of Al in hydrogen (H ^{+) ions of 7.9 MeV.}

The base layer 22 and the pattern layer 24 may be made of different materials. For example, as the material of the pattern layer 24, a material having a smaller ion range than the material of the base layer 22, that is, a material having a large specific density may be used. For example, by using a material having a specific density higher than that of Al, the thickness t2 of the pattern layer 24 can be made smaller, and typically 100 μm or less. As such a material, iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr) or an alloy containing these (for example, stainless steel or 42 alloy) can be used. As the material of the pattern layer 24, gold (Au), silver (Ag), copper (Cu) or the like may be used.

When a high-density material such as Fe, Ni, Co, Cr, Au, Ag, or Cu is injected into the semiconductor substrate 12, the performance of the semiconductor device 10 may be affected. However, as shown in FIG. 2, by arranging the mask 20 in a direction in which the pattern layer 24 is on the upstream side and the base layer 22 is on the downstream side with respect to the incident direction of the incident ion beam B, the mask 20 is ejected from the pattern layer 24. The element can be shielded by the base layer 22. Therefore, even when a material having a high specific density is used for the pattern layer 24, the injection of the high specific density material into the semiconductor substrate 12 is suitably prevented by using the mask 20 having a two-layer structure of the base layer 22 and the pattern layer 24. can. For example, in the case of 23 MeV helium ( ³ He ²⁺ ) ions, the base layer 22 preferably shields the elements constituting the pattern layer 24 by making the thickness of the base layer 22 at least 5 μm or more, preferably 10 μm or more. can.

Next, the widths W1 and W2 in the arrangement direction of the first region 31 and the second region 32 of the mask 20 will be described. FIG. 4 is a cross-sectional view schematically showing a beam passing through the first region 31 of the mask 20, and shows a beam passing through two first regions 31a and 31b adjacent to each other with the second region 32 in between. The first beam B1 emitted from the first region 31 of the mask 20 reaches the position of the first depth d1 from the second main surface 12b of the semiconductor substrate 12. The first beam B1 collides with the atoms constituting the mask 20 and is scattered in the process of passing through the first region 31 of the mask 20. The first beam B1 that has passed through the mask 20 travels straight to the position of the first depth d1 of the semiconductor substrate 12. In such a process, the first beam B1 has a beam spread and has a predetermined beam diffusion width (also referred to as a first beam diffusion width) s1 at the position of the first depth d1. As a result, the beam width of the first beam B1 in the pattern arrangement direction (x direction) of the mask 20 is about the same as the width W1 of the first region 31 before passing through the mask 20, whereas the first depth d1 At the position of, it becomes W1 + 2 × s1 in consideration of the first beam diffusion width s1.

At this time, if the first beam diffusion width s1 is ½ or more of the width W2 of the second region 32, the first beam has passed through the two adjacent first regions 31a and 31b with the second region 32 in between. The beams B1 partially overlap at the position of the first depth d1. As a result, the first beam B1 is also irradiated to the position corresponding to the second region 32 of the mask 20, and a continuous defect region can be formed in the horizontal direction (x direction) of the semiconductor substrate 12. Therefore, in order to form the first defect region 16 continuous in the horizontal direction of the semiconductor substrate 12, the width W2 of the second region 32 should be set to a value less than twice the beam diffusion width s1 of the first beam B1. Just do it.

FIG. 5 is a cross-sectional view schematically showing a beam passing through the second region 32 of the mask 20, and shows a beam passing through two second regions 32a and 32b adjacent to each other with the first region 31 in between. The second beam B2 emitted from the second region 32 of the mask 20 reaches the position of the second depth d2 from the second main surface 12b of the semiconductor substrate 12. The second beam B2 has a predetermined beam diffusion width (also referred to as a second beam diffusion width) s2 at the position of the second depth d2, similarly to the first beam B1 shown in FIG. Therefore, in order to form the second defect region 18 continuous in the horizontal direction of the semiconductor substrate 12, the width W1 of the first region 31 should be set to a value less than twice the beam diffusion width s2 of the second beam B2. Just do it.

Since the beam diffusion widths s1 and s2 at the beam arrival position in the semiconductor substrate differ depending on the acceleration energy, ion type, and irradiation depth (arrival depth position) of the incident ion beam B, these factors are taken into consideration. Therefore, it is necessary to set the widths W1 and W2 of the first region 31 and the second region 32 of the mask 20.

FIG. 6 is a graph showing the relationship between the irradiation depth of the ion beam and the beam diffusion width. The graph shown in FIG. 6 shows the relationship between the irradiation depth and the beam diffusion width when the semiconductor substrate 12 made of silicon (Si) is irradiated with three types of beams having different ion types and acceleration energies. .. The beam diffusion width is calculated based on the half width of the horizontal ion irradiation amount distribution at a certain irradiation depth.

As shown, a 4.3 MeV hydrogen (H ⁺ ) ion has a beam diffusion width of about 10 to 12 μm, and a 23 MeV helium ( ³ He ²⁺ ) ion has a beam diffusion of about 12 to 15 μm. It has a width, and in ^{the case of 7.9 MeV hydrogen (H +} ) ions, it is shown to have a beam diffusion width of about 28 μm to 35 μm. Further, it can be seen that the deeper the irradiation depth, the larger the beam diffusion width tends to be. From the graph, it can be seen that when hydrogen ions of about 1 to 10 MeV are used, the widths W1 and W2 of the first region 31 and the second region 32 of the mask 20 may be 70 μm or less, preferably 50 μm or less. Further, when helium ions of about 10 to 30 MeV are used, it can be seen that the widths W1 and W2 of the first region 31 and the second region 32 of the mask 20 may be set to 30 μm or less, preferably 20 μm or less. Even if the energy value and ion species are not shown in the graph, when light ions such as hydrogen and helium are used, the widths W1 and W2 of the first region 31 and the second region 32 of the mask 20 are at least 100 μm or less. It can be said that it is necessary to.

FIG. 7 is a graph schematically showing the ion irradiation amount distribution in the depth direction in the ion irradiation step according to the embodiment. As described above, since the semiconductor substrate 12 is irradiated with the first beam B1 and the second beam B2 having different energies, the ion irradiation amount having a peak at the depth positions d1 and d2 corresponding to the respective energies E1 and E2. It becomes a distribution. Assuming that the standard deviation of the ion irradiation dose distribution is σ, a defect region is formed in a range of about ± 2σ to 3σ around the peak position of the irradiation dose distribution. Therefore, if the difference d1-d2 between the two peak positions is 7σ or more, the first defect region 16 and the second defect region 18 can be formed so as to be discontinuous in the depth direction. On the other hand, if the difference d1-d2 between the two peak positions is less than 7σ, preferably 6σ or less, the first defect region 16 and the second defect region 18 can be formed so as to be continuous in the depth direction. For example, when the semiconductor substrate 12 is silicon and irradiates hydrogen (H +) ions of 7.9 Mev, the standard deviation σ of the ion irradiation dose distribution is about 10 μm, so that the peak position difference d1-d2 is 70 μm or more. If so, the first defect region 16 and the second defect region 18 separated in the depth direction can be formed. In this case, the thickness t2 of the pattern layer 24 of the mask 20 may be 60 μm or more if the material of the pattern layer 24 is aluminum (Al). If a high specific density material is used as the material of the pattern layer 24, the thickness t2 of the pattern layer 24 can be set to a value smaller than 60 μm.

Next, a method of manufacturing the mask 20 will be described. The method for manufacturing the mask 20 is not particularly limited, and the base layer 22 and the pattern layer 24 may be integrally formed, or the base layer 22 and the pattern layer 24 may be formed separately and then laminated. The pattern layer 24 may be produced by preparing a flat or thin base material and selectively etching the first region 31 of the base material to form an opening 26, or the pattern layer 24 may be formed in the second region 32. It may be produced by selectively depositing materials. When the material is selectively deposited in the second region 32 to form the pattern layer 24, the pattern layer 24 may be formed on a base material such as a resin film. In this case, a base material such as a resin film may be arranged between the base layer 22 and the pattern layer 24, and the base material such as a resin film may form a part of the mask 20. In addition, the base layer 22 and the pattern layer 24 may be integrally formed by using the base layer 22 as a base material and depositing a material to be the pattern layer 24 on the base layer 22.

In the method for manufacturing the mask 20 described above, it is preferable to reduce the thickness t2 of the pattern layer 24 so that the aspect ratio (t2 / W1 or t2 / W2) of the opening 26 is 0.3 or less. By reducing the aspect ratio of the opening 26, it becomes easy to form the side wall of the opening 26 vertically, and the energies of the first beam B1 and the second beam B2 can be suitably separated. In other words, the processing accuracy of the pattern layer 24 can be improved by reducing the thickness t2 of the pattern layer 24. In order to reduce the thickness t2 of the pattern layer 24, it is preferable to use a high specific density material as the pattern layer 24 as described above.

On the other hand, the base layer 22 may be composed of a single layer or a laminated body of a plurality of layers. For example, a plurality of mask substrates having different thicknesses may be prepared, and the thickness t1 of the base layer 22 may be adjusted by changing the combination of the plurality of mask substrates. For example, by preparing a plurality of mask substrates having different thicknesses such as 10 μm, 20 μm, 50 μm, 100 μm, and 200 μm and combining them, a base layer 22 having an arbitrary thickness can be formed in the range of about 10 μm to 500 μm. It may be. Further, a plurality of pattern layers 24 having different materials and at least one thickness t2 are prepared, and any one of the plurality of pattern layers 24 is combined with the base layer 22 composed of one or more mask substrates. The mask 20 may be configured. As a result, the energies E1 and E2 of the first beam B1 and the second beam B2 emitted from the mask 20 are adjusted so that the first defect region 16 and the second defect region are formed at the desired depth positions d1 and d2. Can be adjusted to. In this case, a fixing jig for fixing the base layer 22 and the pattern layer 24 in a laminated state may be used. This fixing jig may have a function of fixing the mask 20 to the semiconductor substrate 12, or may be configured so that it can be attached to the wafer holding device 66.

With the above configuration, by executing ion irradiation using the mask 20 according to the present embodiment, defect regions 16 and 18 can be simultaneously formed at different depth positions d1 and d2 in one irradiation step. By setting the arrangement widths W1 and W2 of the first region 31 and the second region 32 of the mask 20 to 100 μm or less, the beams are at least partially overlapped at the depth positions d1 and d2 reached by the beams B1 and B2. It is possible to form continuous defect regions 16 and 18 in the horizontal direction orthogonal to the depth direction. According to the present embodiment, it is not necessary to change the energy of the ion beam B to irradiate the ion beam B a plurality of times in order to form defect regions at different depth positions, so that the productivity of the ion irradiation step can be improved. ..

The present invention has been described above based on the embodiments. It is understood by those skilled in the art that the present invention is not limited to the above-described embodiment, various design changes are possible, various modifications are possible, and such modifications are also within the scope of the present invention. It is about to be.

8 and 9 are top views schematically showing the configuration of the mask 20 according to the modified example. In the above-described embodiment, the case where the first region 31 and the second region 32 are arranged in only one direction (x direction) is shown, but in the modified example, the first region 31 and the second region 32 are two-dimensional. It may be arranged as a target. For example, as shown in FIG. 8, the rectangular openings 26 may be arranged in two directions, the x direction and the y direction. Further, the shape of the opening 26 is not limited to a rectangle, and a circular opening 26 may be provided as shown in FIG.

FIG. 10 is a cross-sectional view schematically showing a manufacturing method of the semiconductor device 10 according to the modified example. In this modification, the mask 20 is tilted with respect to the incident direction of the ion beam B, and the incident angle θ of the ion beam B with respect to the mask 20 is shifted from the vicinity of 0 degrees. In this modification, since the mask 20 is tilted, the values of the widths W1a and W2a of the first region 31 and the second region when viewed from the incident direction (z direction) of the ion beam B are arranged in the pattern of the mask 20. It can be smaller than the widths W1 and W2 in the direction (direction of arrow C). Specifically, the widths W1a and W2a of the first region 31 and the second region when viewed from the beam incident direction (z direction) can be set to 1 / cosθ of the pattern widths W1 and W2 of the pattern layer 24. As a result, the overlapping range of the beams B1 and B2 can be widened, and defect regions 16 and 18 having a more uniform distribution in the horizontal direction of the semiconductor substrate 12 can be formed.

In a further modification, the semiconductor substrate 12 may be tilted with respect to the incident direction of the ion beam B instead of tilting only the mask 20. For example, the mask 20 may be fixed to the semiconductor substrate 12 so that the inclination angles θ of the semiconductor substrate 12 and the mask 20 are the same. In this case, the wafer holding device 66 may be tilted with respect to the ion beam B traveling through the beam transporting device 54, or a beam deflecting device may be provided downstream of the beam transporting device 54 so that the beam can be directed to the wafer holding device 66. It may be obliquely incident.

11 and 12 are diagrams schematically showing an ion irradiation step according to a modified example. In a further modification, the ion beam is obliquely incident on the semiconductor substrate 12 and the mask 20, and a plurality of ion irradiation steps in which the ion beams are incident in different directions are combined. FIG. 11 schematically shows the first ion irradiation step, in which the incident angle of the ion beam B10 is inclined in the + θ direction with respect to the semiconductor substrate 12 and the mask 20. FIG. 12 schematically shows the second ion irradiation step, in which the incident angle of the ion beam B20 with respect to the semiconductor substrate 12 and the mask 20 is inclined in the −θ direction opposite to that of the first ion irradiation step. There is.

In this modification, in the first ion irradiation step of FIG. 11, the first beam B11 that has passed through each of the two adjacent first regions 31a and 31b across the second region 32 is at the position of the first depth d1. It does not overlap. Similarly, in the second ion irradiation step of FIG. 12, the first beam B21 that has passed through each of the two adjacent first regions 31a and 31b across the second region 32 overlaps at the position of the first depth d1. Not. However, since the irradiation direction is changed in the first ion irradiation step and the second ion irradiation step, the irradiation ranges W11 and W21 at the position of the first depth d1 of the first beams B11 and B21 irradiated in each step. Partially overlap. By combining beam irradiations having different irradiation directions (irradiation angles) in this way, it is possible to form defect regions that are continuously connected in the horizontal direction. The same applies to the second beam passing through the second region 32.

According to this modification, even if the opening widths W1 and W2 of the mask 20 are made larger than those of the above-described embodiment, a continuous defect region can be formed in the pattern arrangement direction of the mask 20. For example, even if the opening widths W1 and W2 of the mask 20 are doubled as compared with the above-described embodiment, a continuous defect region can be formed in the pattern arrangement direction of the mask 20. Therefore, according to this modification, the pattern size of the mask 20 can be increased to improve the workability of the mask 20. Further, even when the beam diffusion width of the ion beam to be irradiated is small, a continuous defect region can be formed in the pattern arrangement direction.

In a further modification, the incident direction of the beam may be changed to three or more. For example, the semiconductor substrate 12 and the mask 20 may be combined in the three directions of vertical direction, + θ direction, and −θ direction, or may be combined in the four directions of + 2θ, + θ, −θ, and -2θ. Further, when the masks 20 arranged two-dimensionally as shown in FIGS. 8 and 9 are used, the incident direction of the beam may be changed in each of the x direction and the y direction. For example, the incident angle of the beam in the (x, y) direction is set to (+ θ, 0), (-θ, 0), (0, + θ), (0, -θ), and a total of four ion irradiations are performed. May be executed.

In the above-described embodiment, the case where the mask 20 is arranged so that the pattern layer 24 is on the upstream side and the base layer 22 is on the downstream side with respect to the incident ion beam B is shown. In the modified example, the mask 20 may be used with the base layer 22 on the upstream side and the pattern layer 24 on the downstream side. In this case, the materials of the base layer 22 and the pattern layer 24 are preferably made of materials (for example, Al, Si, Ti) that do not easily affect the performance of the semiconductor device 10.

In the above-described embodiment, the case where the mask 20 is arranged in the vicinity of the semiconductor substrate 12 and away from the main surface of the semiconductor substrate 12 is shown. In a further modification, the mask 20 may be arranged at a position away from the semiconductor substrate 12, and for example, the mask 20 may be arranged at the position of the absorber 64 shown in FIG. By separating the mask 20 from the substrate, the beam diffusion width at the depth position where the defect region is formed can be made larger. For example, in the case of 23 MeV helium ( ³ He ²⁺ ) ions, the beam diffusion width can be increased by about 50 μm by separating the semiconductor substrate 12 and the mask 20 by about 1 mm. Further, if the distance between the semiconductor substrate 12 and the mask 20 is about 1 cm, the beam diffusion width can be made about 500 μm. In this case, the widths W1a and W2a of the first region 31 and the second region 32 of the mask 20 may be larger than 100 μm, and may be, for example, 200 μm or less, 300 μm or less, 400 μm or less, or 500 μm or less.

The mask 20 may be provided so as to be in contact with the main surface of the semiconductor substrate 12, and the mask 20 may be formed on the main surface of the semiconductor substrate 12. When the mask 20 is formed on the main surface of the semiconductor substrate 12, a resist, a wiring layer, or the like formed on the main surface of the semiconductor substrate 12 may be used.

10 ... semiconductor device, 12 ... semiconductor substrate, 16 ... first defect region, 18 ... second defect region, 20 ... mask, 22 ... base layer, 24 ... pattern layer, 31 ... first region, 32 ... second region.

Claims (11)

A method for manufacturing a semiconductor device, which comprises irradiating a semiconductor substrate with an ion beam through a mask.
The mask has a first region for decelerating an incident ion beam to a first energy and a second region for decelerating the incident ion beam to a second energy smaller than the first energy, and the first region and the second region are in at least one direction are alternately arranged, Ri said first region and said width der 500μm or less each of the arrangement direction of the second region when viewed from the incident direction of the ion beam,
The width of the first region in the arrangement direction when viewed from the traveling direction of the ion beam passes through two adjacent second regions with the first region in between and is incident on the semiconductor substrate with the second energy. A method for manufacturing a semiconductor device, characterized in that the ion beams to be generated are set so as to overlap at least partially in the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the mask is arranged away from the semiconductor substrate. The mask 1 or 2 includes a base layer provided over the first region and the second region, and a pattern layer selectively provided in the second region on the base layer. The method for manufacturing a semiconductor device according to the above. The method for manufacturing a semiconductor device according to claim 3, wherein the pattern layer contains a material having a higher specific density than the base layer. The method for manufacturing a semiconductor device according to claim 3 or 4, wherein the mask is arranged so that the pattern layer is on the upstream side and the base layer is on the downstream side with respect to the incident ion beam. The method for manufacturing a semiconductor device according to any one of claims 3 to 5, wherein the base layer is composed of a laminate of a plurality of mask substrates. By adjusting the thickness of the base layer, the thickness of the pattern layer, and at least one of the materials, the values of the first energy and the second energy of the ion beam incident on the semiconductor substrate can be adjusted. The method for manufacturing a semiconductor device according to any one of claims 3 to 6, wherein the method is characterized. The width of the second region in the arrangement direction when viewed from the traveling direction of the ion beam passes through two adjacent first regions with the second region in between and is incident on the semiconductor substrate with the first energy. the method of manufacturing a semiconductor device according to any one of claims 1 to 7, the ion beam is characterized and is configured to at least partially overlap Turkey within the semiconductor substrate. The first defect region formed at the first depth position of the semiconductor substrate by the ion beam of the first energy and the second defect region formed at the second depth position of the semiconductor substrate by the ion beam of the second energy. The semiconductor according to any one of claims 1 to 8, wherein the values of the first energy and the second energy are adjusted so that the defect region is formed discontinuously in the depth direction. How to manufacture the device. The first defect region formed at the first depth position of the semiconductor substrate by the ion beam of the first energy and the second defect region formed at the second depth position of the semiconductor substrate by the ion beam of the second energy. The semiconductor according to any one of claims 1 to 8, wherein the values of the first energy and the second energy are adjusted so that the defect region is continuously formed in the depth direction. How to manufacture the device. The semiconductor according to any one of claims 1 to 10, wherein the ion beam passes through an absorber provided on the upstream side of the mask and then enters the first region and the second region. Manufacturing method of the device.

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