JP6918302B2 - Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device - Google Patents

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Conventionally, in a power semiconductor element, in order to reduce the on-resistance of the element, a vertical MOSFET (Metal Oxided Semiconductor Field Effect Transistor) having a trench structure has been manufactured (manufactured). In a vertical MOSFET, a trench structure in which channels are formed perpendicular to the substrate surface can increase the cell density per unit area rather than a planar structure in which channels are formed parallel to the substrate surface. The current density per area can be increased, which is advantageous in terms of cost.

However, when a trench structure is formed in a vertical MOSFET, the entire inner wall of the trench is covered with a gate insulating film in order to form a channel in the vertical direction, and the bottom portion of the trench of the gate insulating film approaches the drain electrode. A high electric field is likely to be applied to the bottom of the trench. In particular, since a wide bandgap semiconductor (a semiconductor having a wider bandgap than silicon, for example, silicon carbide (SiC)) is used to produce an ultrahigh withstand voltage element, the adverse effect on the gate insulating film at the bottom of the trench greatly reduces reliability. Let me.

As a method for solving such a problem, in a vertical MOSFET having a trench structure having a striped planar pattern, a technique has been proposed in which a ^{p + type base region is provided in a striped pattern between trenches in parallel with the trench.} (For example, see Patent Document 1 below). Further, a technique has been proposed in which a ^{p +} type base region is provided in a striped pattern parallel to the trench at the bottom of the trench.

FIG. 17 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. ^{The conventional silicon carbide semiconductor device shown in FIG. 17 has a general trench on the front surface (the surface on the p +} type base layer 6 side) side of a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate) 100. A MOS gate having a gate structure is provided. The silicon carbide substrate (semiconductor chip) 100 has an ^n- type drift layer 2 and an n-type region 5 which is a current diffusion region on an n ⁺ type support substrate (hereinafter referred to as n ⁺ type silicon carbide substrate) 1 made of silicon carbide. And each silicon carbide layer to be the p ⁺ type base layer 6 is epitaxially grown in order.

^{In the n-type region 5, a first p ++} type region 3 is selectively provided so as to cover the entire bottom surface of the trench 18. The first p ⁺⁺ type region 3 is provided at a depth that does not reach the ^{n − type drift layer 2.} Further, in the n-type region 5, a second p ⁺⁺ type region 4 is selectively provided between adjacent trenches 18 (mesa portion). The second p ⁺⁺ type region 4 is provided at a depth that is in contact with the p ⁺ type base layer 6 and ^{does not reach the n − type drift layer 2.} Reference numerals 7 to 12 are an n ⁺⁺ type source region, a p ⁺⁺⁺ type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, and a source electrode, respectively.

In the vertical MOSFET having the configuration shown in FIG. 17, ^{the pn junction between the first p ++} type region 3, the second p ⁺⁺ type region 4 and the n type region 5 is located deeper than the trench 18. Therefore, the ^{electric field is concentrated at the boundary between the first p ++} type region 3, the second p ⁺⁺ type region 4 and the n type region 5, and the electric field concentration at the bottom of the trench 18 can be relaxed.

Further, in order to reduce the on-resistance, the thickness of the field plate insulating film provided on the bottom surface of the trench in the Z direction (trench depth direction) is set from the thickness of the field plate insulating film in the X direction (trench width direction). There is a semiconductor device in which the carrier concentration of the n-type base layer can be set high by making the thickness thinner (see, for example, Patent Document 2 below).

JP-A-2009-260253 Japanese Unexamined Patent Publication No. 2013-125827

In the conventional structure described above, the channel length can be shortened and the on-resistance can be further reduced by shortening the length of the portion ^{where the trench is in contact with the p + type base layer 6.} However, when the channel length is shortened, the threshold voltage of the semiconductor device drops sharply due to the short channel effect. In this case, the use of the semiconductor device as a switching device is limited.

In order to solve the above-mentioned problems caused by the prior art, the present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, which does not cause a decrease in the threshold voltage even if the channel length is shortened and the on-resistance is lowered. The purpose is to provide.

In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer is provided on the front surface of the silicon carbide substrate. A second conductive type second semiconductor layer is provided on the side of the first semiconductor layer opposite to the silicon carbide substrate side. Inside the second semiconductor layer, a first conductive type first semiconductor region having a higher impurity concentration than the first semiconductor layer is selectively provided. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. Inside the trench, a semiconductor film in contact with the second semiconductor layer and the first semiconductor layer is provided. A gate electrode is provided inside the trench and inside the semiconductor film via a gate insulating film. A first electrode in contact with the first semiconductor region and the second semiconductor layer is provided. A second electrode is provided on the back surface of the silicon carbide substrate. In the semiconductor film, the region in contact with the second semiconductor layer is a second conductive type region having a lower impurity concentration than the second semiconductor layer, and the region in contact with the first semiconductor layer is from the first semiconductor layer. Ri region der of low impurity concentration first conductivity type, having a profile in which the impurity concentration is lower the closer to the center of the trench.

Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the semiconductor film is a second conductive type in which a region in contact with the second semiconductor layer has a lower impurity concentration than the second semiconductor layer. It is characterized in that it is not provided at the bottom of the trench.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, the first step of forming the first conductive type first semiconductor layer on the front surface of the silicon carbide substrate is performed. Next, a second step of forming the second conductive type second semiconductor layer on the side of the first semiconductor layer opposite to the silicon carbide substrate side is performed. Next, a third step of selectively forming a first conductive type first semiconductor region having a higher impurity concentration than the first semiconductor layer is performed inside the second semiconductor layer. Next, a fourth step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer is performed. Next, a fifth step of forming a semiconductor film in contact with the second semiconductor layer and the first semiconductor layer is performed inside the trench. Next, a sixth step of forming a gate electrode provided inside the trench and inside the semiconductor film via a gate insulating film is performed. Next, a seventh step of forming the first electrode in contact with the first semiconductor region and the second semiconductor layer is performed. Next, the eighth step of forming the second electrode on the back surface of the silicon carbide substrate is performed. In the fifth step, a region of the semiconductor film in contact with the second semiconductor layer is formed in a second conductive type region having a lower impurity concentration than the second semiconductor layer, and the region is formed with the first semiconductor layer of the semiconductor film. The contacting region is formed in a first conductive type region having a lower impurity concentration than the first semiconductor layer , and the semiconductor film is formed so as to have a profile in which the impurity concentration becomes lower as it approaches the center of the trench .

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the fifth step, a semiconductor film is formed on the first semiconductor region, on the second semiconductor layer, and inside the trench. The step of epitaxially growing, the step of removing the semiconductor film at the bottom of the trench, and the region of the semiconductor film in contact with the second semiconductor layer are divided into a second conductive type region having a lower impurity concentration than the second semiconductor layer. It is characterized in that it is a process including the process of performing.

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the step of removing the semiconductor film at the bottom of the trench is performed on the first semiconductor region, on the second semiconductor layer, and in the trench. The semiconductor film on the side wall of the trench is thinned, and the semiconductor film on the bottom of the trench is removed.

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the fifth step is the center of the trench by the treatment of activating the first semiconductor region formed in the third step. It is characterized in that the semiconductor film having a profile in which the impurity concentration becomes lower as it approaches is formed.

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the fifth step is an annealing treatment for the trench formed in the fourth step, and the impurity concentration becomes closer to the center of the trench. It is characterized in that the semiconductor film having a low profile is formed.

Further, according to the above-described invention, a low-concentration thin film (semiconductor film ^{) having a lower impurity concentration than the p + type base layer is formed in a region in contact with the p +} type base layer (second conductive type second semiconductor layer) inside the trench. ) Can be provided to reduce the impurity concentration in the channel portion. As a result, when a voltage is applied to the gate, the channel portion is completely depleted, and the electric field entering from the drain side can be suppressed. As a result, even if the channel length is shortened, it is possible to prevent the threshold value from suddenly decreasing due to the short channel effect, and the channel length can be shortened while maintaining the threshold value, so that the on-resistance-threshold trade-off can be improved.

A low-concentration thin film having a profile in which the impurity concentration decreases toward the center of the trench can be formed by ^{annealing the trench or activating the n ++} type source region and the p ^{+++ type contact region.} can. As a result, a semiconductor device capable of forming a low-concentration thin film and reducing on-resistance can be realized at low cost by an existing process.

Further, since the low-concentration thin film is not provided at the bottom of the trench, the capacitance between the drift and the gate is reduced, and the loss during switching can be reduced. As a result, it is possible to realize a semiconductor device having less power loss and less heat generation during operation.

Further, in order to form a low-concentration thin film by epitaxial growth, it is difficult to control time, flow rate, pressure, etc. However, in the above-mentioned invention, a thick film is formed and thinned by etching, so that a low-concentration thin film can be easily formed. Can be created in.

According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, there is an effect that the threshold voltage does not decrease even if the channel length is shortened and the on-resistance is lowered.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 4). FIG. 5 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 5). FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 6). FIG. 7 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 7). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 2. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 4). FIG. 5 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment (No. 5). FIG. 6 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment (No. 6). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing which shows the structure of the conventional trench type MOSFET.

Hereinafter, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
The semiconductor device according to the present invention is configured by using a semiconductor having a bandgap wider than that of silicon (hereinafter, referred to as a wide bandgap semiconductor). Here, the structure of a semiconductor device (silicon carbide semiconductor device) using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described as an example. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 1 shows only two unit cells (functional units of elements), and other unit cells adjacent to them are not shown. The silicon carbide semiconductor device according to the first embodiment shown in FIG. 1 has a ^{MOS on the front surface (the surface on the p +} type base layer 6 side) side of a semiconductor substrate (silicon carbide substrate: semiconductor chip) 100 made of silicon carbide. It is a MOSFET with a gate.

The silicon carbide substrate 100 includes an ^n- type drift layer (first semiconductor layer) 2 and a p ⁺ type base layer (second semiconductor layer) on an ^{n +} type support substrate (n ⁺ type silicon carbide substrate) 1 made of silicon carbide. Each silicon carbide layer to be No. 6 is epitaxially grown in order. The MOS gate is composed of a p ⁺ type base layer 6, an n ⁺⁺ type source region (first semiconductor region) 7, a p ⁺⁺⁺ type contact region 8, a trench 18, a gate insulating film 9, and a gate electrode 10. .. Specifically, an n-type region 5 is provided on ^{the surface layer of the n-} type drift layer 2 on the source side (source electrode 12 side) ^{so as to be in contact with the p + type base layer 6.} The n-type region 5 is a so-called current spreading layer (CSL) that reduces the spread resistance of carriers. The n-type region 5 is uniformly provided, for example, in a direction parallel to the front surface of the substrate (the front surface of the silicon carbide substrate 100) (hereinafter, referred to as the lateral direction).

Inside the n-type region 5, a first p ⁺⁺ type region 3 and a second p ⁺⁺ type region 4 are selectively provided. The first p ⁺⁺ type region 3 is provided so as to cover the bottom surface and the bottom surface corner portion of the trench 18. The bottom corner portion of the trench 18 is a boundary between the bottom surface and the side wall of the trench 18. The first p ⁺⁺ type region 3 is ^{deeper than the interface between the p +} type base layer 6 and the n type region 5 on the drain side, and does not reach the interface between the ^{n type region 5 and the n-type drift region 2.} It is provided at the interface. By providing the first 1p ⁺⁺ type region 3, it is possible to form a pn junction between the near bottom, first 1p ⁺⁺ type region 3 and the n-type region 3 of the trench 18.

The second p ⁺⁺ type region 4 is provided between adjacent trenches 18 (mesa portion) so as to be separated from the ^{first p ++ type region 3 and in contact with the p +} type base layer 6. A part of the second p ⁺⁺ type region 4 may extend toward the trench 18 side and partially contact the first p ⁺⁺ type region 3. Further, the second p ⁺⁺ type region 4 is provided at a depth that does not reach the interface between the ^{n-type region 5 and the n- type drift region 2 from the interface between the p +} type base layer 6 and the n-type region 5. There is. By providing the first 2p ⁺⁺ type region 4, between the adjacent trenches 18, at a deep position in the drain side of the bottom surface of the trench 18, pn junction between the first 2p ⁺⁺ type region 4 and the n-type region 5 Can be formed. ^{By forming a pn junction between the first p ++} type region 3, the second p ⁺⁺ type region 4 and the n type region 5 in this way, a high electric field is applied to the bottom surface of the trench 18 of the gate insulating film 9. Can be prevented.

Inside the p ⁺ type base layer 6, an n ⁺⁺ type source region 7 and a p ⁺⁺⁺ type contact region 8 are selectively provided so as to be in contact with each other. The depth of the p ⁺⁺⁺ type contact area 8 may be the same as, for example, the n ⁺⁺ type source area 7, or may be deeper than the ^{n ++ type source area 7.}

^{The trench 18 penetrates the n ++} type source region 7 and the p ⁺ type base layer 6 from the front surface of the substrate and reaches the n type region 5 and the first p ⁺⁺ type region 3. A low-concentration thin film 14 is provided inside the trench 18. The low-concentration thin film 14 makes it possible to reduce the impurity concentration on the channel surface, increase the resistance in the channel region, and prevent a decrease in the threshold voltage.

The low-concentration thin film 14 is in contact with the n ⁺⁺ type source region 7, the p ⁺ type base layer 6, the n type region 5, and the first p ⁺⁺ type region 3, and is the same conductive type as the contacted region, and is in contact with the region. The impurity concentration is lower than the region. For example, the region S1 in contact with ^{the n ++} type source region 7 of the low-concentration thin film 14 ^{is n-} type and has a lower impurity concentration than the ^{n ++ type source region 7.} Further, the region S2 in contact with ^{the p +} type base layer 6 of the low concentration thin film 14 ^{is p-} type and has a lower impurity concentration than the ^{p + type base layer 6.} The region S3, in contact with the n-type region 5 of low density thin film 14, n ^- is the type, impurity concentration lower than the n-type region 5. Further, the region S4 in contact with ^{the first p ++} type region 3 of the low-concentration thin film 14 ^{is p-} type, and the impurity concentration is lower than that of the first p ^{++ type region 3. The region S2 in contact with the p +} type base layer 6 of the low-concentration thin film 14 can reduce the impurity concentration on the channel surface, increase the resistance in the channel region, and prevent the threshold voltage from decreasing. Further, the film thickness of the low-concentration thin film 14 preferably has an aspect ratio of 2 or more between the channel length and the film thickness of the low-concentration thin film 14. For example, when the channel length is 0.4 μm, it is preferable that the film thickness of the low-concentration thin film 14 is 0.2 μm or less and the channel length / film thickness of the low-concentration thin film 14 is ≥ 2.

Further, the low-concentration thin film 14 has a profile in which the impurity concentration decreases as it approaches the center O of the trench 18. Specifically, the low-concentration thin film 14 has the ^{highest impurity concentration in the portion in contact with the n ++} type source region 7, the p ⁺ type base layer 6, the n type region 5, and the first p ⁺⁺ type region 3, and will be described later. The impurity concentration is the lowest at the portion in contact with the gate insulating film 9. Since the ^{impurity concentration is highest in the region in contact with the p +} type base layer 6, the low concentration thin film 14 can further increase the resistance in the channel region.

A gate insulating film 9 is provided along the side wall of the trench 18 inside the trench 18 and inside the low-concentration thin film 14, and a gate electrode 10 is provided inside the gate insulating film 9. The source side end of the gate electrode 10 may or may not protrude outward from the front surface of the substrate. The gate electrode 10 is electrically connected to a gate pad (not shown) at a portion (not shown). The interlayer insulating film 11 is provided on the entire surface of the front surface of the substrate so as to cover the gate electrode 10 embedded in the trench 18.

The source electrode (first electrode) 12 is in contact with the n ⁺⁺ type source region 7 and the p ⁺⁺⁺ type contact region 8 through the contact hole opened in the interlayer insulating film 11, and the gate electrode is formed by the interlayer insulating film 11. It is electrically insulated from 10. A nickel silicide film 15 for preventing the diffusion of metal atoms from the source electrode 12 to the gate electrode 10 side is provided between the source electrode 12 and the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A drain electrode (second electrode) 13 is provided on the back surface of the silicon carbide substrate 10 (the back surface of the ^{n + type silicon carbide substrate 1 which is an n +} type drain region).

Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. 2 to 8 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. First, a n ⁺ -type silicon carbide substrate 1 made of an n ⁺ -type drain region. Then, the front surface of the n ⁺ -type silicon carbide substrate 1, n mentioned above ^- -type drift layer 2 is epitaxially grown. For example, n ^- epitaxial growth conditions for forming the type drift layer 2, n ^- impurity concentration type drift layer 2 may be set to be 8 × 10 ¹⁵ / cm ³ order.

Next, the lower n-type region 5a is epitaxially grown on ^{the n-type drift layer 2.} For example, the conditions for epitaxial growth for forming the lower n-type region 5a may be set so that ^{the impurity concentration in the lower n-type region 5a is about 1 × 10 17} / cm ^3. The lower n-type region 5a is a part of the n-type region 5. ^{Next, the first p ++} type region 3 and the lower second p ⁺⁺ type region 4a are selectively formed on the surface layer of the lower n-type region 5a by photolithography and ion implantation of p-type impurities. For example, the ^{dose amount at the time of ion implantation for forming the first p ++} type region 3 and the lower second p ⁺⁺ type region 4a is set so that the impurity concentration is about 5 × 10 ¹⁸ / cm ^3. May be good. The state up to this point is shown in FIG.

Next, the upper n-type region 5b is epitaxially grown on the lower n-type region 5a and the lower second p ^{++ type region 4a.} For example, the conditions for epitaxial growth for forming the upper n-type region 5b may be set to be about the same as the impurity concentration in the lower n-type region 5a. The upper n-type region 5b is a part of the n-type region 5, and the lower n-type region 5a and the upper n-type region 5b are combined to form the n-type region 5. ^{Next, the upper second p ++} type region 4b is selectively formed on the surface layer of the upper n type region 5b by photolithography and ion implantation of p-type impurities. For example, the dose amount at the time of ion implantation for forming the ^{upper second p ++} type region 4b may be set so ^{that the impurity concentration is about the same as that of the lower second p ++ type region 4a.} The state up to this point is shown in FIG.

^{Next, the p +} type base layer 6 is epitaxially grown on the upper n-type region 5b and the upper second p ⁺⁺ type region 4b. For example, the epitaxial growth conditions for forming the p ⁺ -type base layer 6, the impurity concentration of the p ⁺ -type base layer 6 may be set to be about 1 × 10 ¹⁸ / cm ^{3. Further, the p +} type base layer 6 may be formed by inverting the conductive type of the upper n-type region 5b by ion implantation of the p-type impurity.

^{Next, the p +++} type contact region 8 is selectively formed on ^{the surface layer of the p +} type base layer 6 by photolithography and ion implantation of p-type impurities. For example, the dose amount at the time of ion implantation for forming the ^{p +++} type contact region 8 may be set so ^{that the impurity concentration is about 1 × 10 20} / cm ^3. The state up to this point is shown in FIG.

^{Next, the n ++} type source region 7 is selectively formed on ^{the surface layer of the p +} type base layer 6 so as to be in contact ^{with the p +++} type contact region 8 by photolithography and ion implantation of n-type impurities. For example, the dose amount at the time of ion implantation for forming the ^{n ++} type source region 7 may be set so ^{that the impurity concentration is about 1 × 10 20} / cm ^3. The formation order of the n ⁺⁺ type source region 7 and the p ⁺⁺⁺ type contact region 8 may be exchanged.

Next, photolithography and etching are performed to form a trench 18 that ^{penetrates the n ++} type source region 7 and the p ⁺ type base layer 6 and reaches the n type region 5 and the lower second p ^{++ type region 4a.} An oxide film is used as a mask when forming a trench. The state up to this point is shown in FIG.

Next, a low-concentration thin film 14'which becomes a low-concentration thin film 14 is epitaxially grown to a thickness of 0.03 to 0.1 μm on ^{the n ++} type source region 7, on the p ^{+ type base layer 6, and inside the trench 18.} .. The error in the thickness of the low-concentration thin film 14'is about ± 10%. For example, the conditions for epitaxial growth for forming the low-concentration thin film 14'may be set so that ^{the impurity concentration of the low-concentration thin film 14'is about 1 × 10 14 to} 5 × 10 ¹⁶ / cm ^3. The density error of the low-concentration thin film 14'is about ± 100%. Here, the conductive type of the low-concentration thin film 14'may be n-type or p-type. Further, the low-concentration thin film 14'may be non-doped. The state up to this point is shown in FIG.

Further, after the low-concentration thin film 14'growth, isotropic etching for removing damage to the trench 18 and hydrogen annealing for rounding the corners of the bottom of the trench 18 and the opening of the trench 18 may be performed. Only one of isotropic etching and hydrogen annealing may be performed. Further, hydrogen annealing may be performed after performing isotropic etching. Hydrogen annealing is performed, for example, at 1500 ° C.

When hydrogen annealing is performed, the low-concentration thin film 14'becomes a low-concentration thin film 14 by hydrogen annealing. That is, the low-concentration thin film 14 having the same conductive type as the contacted region is formed. Specifically, a portion in contact with the n ⁺⁺ type source region 7 of low density thin film 14 'is, n-type impurities from n ⁺⁺ type source region 7, for example, phosphorus (P) is diffused in the horizontal and vertical directions , The conductive type becomes n ^- type. Here, the lateral direction is the width direction of the trench, and the portion that diffuses in the lateral direction is a portion where the low-concentration thin film 14'in the trench 18 ^{is in contact with the n ++} type source region 7. The vertical direction is the depth direction of the trench, and the portion that diffuses in the vertical direction is a portion where the low-concentration thin film ^{14'is in} contact with the n ++ type source region 7 at the upper part of the silicon carbide substrate 100. Similarly, a portion in contact with the p ⁺ -type base layer 6 of a low density thin film 14 'is diffused from the p ⁺ -type base layer 6 p-type impurity, such as aluminum (Al) is laterally conductivity type p ^- type and Become. The same applies to the portion of the low-concentration thin film ^{14'that is in contact with the p +} type base layer 6, the n type region 5, and the first p ^{++ type region 3.} Since silicon carbide is a material in which impurities are difficult to diffuse, impurities diffused in the horizontal direction are less likely to be further diffused in the vertical direction. Therefore, the low-concentration thin film 14 is the same as the conductive type in the region in contact with the low-concentration thin film 14.

Further, since the low-concentration thin film 14 diffuses p-type or n-type impurities from the region in contact with the low-concentration thin film 14, the impurity concentration of the low-concentration thin film 14 is based on the n ⁺⁺ type source region 7 and p ⁺ type. The portion in contact with the layer 6 and the like becomes higher, and ^{becomes lower as the distance from the n ++} type source region 7 and the p ⁺ type base layer 6 and the like increases. As a result, the low-concentration thin film 14 has a profile in which the impurity concentration decreases as it approaches the center O of the trench 18.

Next, activation annealing is performed on the ion-implanted region. For example, activation annealing is performed at 1700 ° C. As a result, ^{the impurities ion-implanted into the n ++} type source region 7 and the p ⁺ type base layer 6 are activated. Here, when hydrogen annealing is not performed on the trench 18, the low-concentration thin film 14'becomes a low-concentration thin film 14 by activation annealing. The processing content is the same as in the case of hydrogen annealing for the trench 18, and is therefore omitted. The state up to this point is shown in FIG. In addition, activation annealing may be performed before forming the trench 18. In this case, it is necessary to perform hydrogen annealing on the trench 18 in order to form the low-concentration thin film 14.

Next, the gate insulating film 9 is formed along the front surface of the silicon carbide substrate 100 and the inner wall of the trench 18. Next, for example, polysilicon is deposited and etched so as to be embedded in the trench 18 to leave polysilicon to be the gate electrode 10 inside the trench 18. At that time, the polysilicon may be etched back so as to remain inside the surface of the substrate, or the polysilicon may protrude outward from the surface of the substrate by performing patterning and etching. The state up to this point is shown in FIG.

Next, an interlayer insulating film 11 is formed on the entire front surface of the silicon carbide substrate 100 so as to cover the gate electrode 10. The interlayer insulating film 11 is formed by, for example, NSG (None-topped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature), or a combination of HTO (High Temperature). NS. Next, the interlayer insulating film 11 and the gate insulating film 9 are patterned to form a contact hole, and the n ⁺⁺ type source region 7 and the p ⁺⁺⁺ type contact region 8 are exposed.

Next, a nickel (Ni) film is formed on the front surface side of the semiconductor substrate 100 by, for example, a sputtering method. Next, the silicon carbide semiconductor portion (n ⁺ source region 7 and p ⁺⁺⁺ type contact region 8) is reacted with the nickel film by syntaring (heat treatment) to form the nickel silicide film 15, thereby forming the silicon carbide semiconductor. Form ohmic contact with the department. A TiN (titanium nitride) film may be formed between the interlayer insulating film 11 and the nickel film. In the process of forming the nickel silicide film 15, ^{the p- layer of the portion of the low-concentration thin film 14 in contact with the p +++} type contact region 8 disappears, so that the low-concentration thin film 14 does not affect the contact resistance. ..

Next, the source electrode 12 is formed so as to be in contact with ^{the n ++ type source region 7.} The source electrode 12 may be formed so as to cover the nickel silicide film 15, or may be left only in the contact hole.

Next, the source electrode pad is formed so as to embed the contact hole. A part of the metal layer deposited to form the source electrode pad may be used as a gate pad. On the back surface of the n ⁺ type silicon carbide substrate 1, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the drain electrode 13 by sputter vapor deposition or the like. This metal film may be laminated by combining a plurality of Ni films and Ti films. Then, annealing such as high-speed heat treatment (RTA: Rapid Thermal Annealing) is performed so that the metal film silicides to form ohmic contacts. After that, for example, a thick film such as a laminated film in which a Ti film, a Ni film, and gold (Au) are laminated in this order is formed by electron beam (EB: Electron Beam) vapor deposition or the like to form a drain electrode 13.

In the above-mentioned epitaxial growth and ion implantation, examples of n-type impurities (n-type dopants) include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), which are n-type with respect to silicon carbide. Should be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., which are p-type with respect to silicon carbide, may be used. .. In this way, the MOSFET shown in FIG. 1 is completed.

As described above, according to the first embodiment, the trench, the region in contact with p ⁺ -type base layer, by providing the low-concentration thin low impurity concentration than the p ⁺ -type base layer, the channel portion Impurity concentration can be lowered. As a result, when a voltage is applied to the gate, the channel portion is completely depleted, and the electric field entering from the drain side can be suppressed. As a result, even if the channel length is shortened, it is possible to prevent the threshold value from dropping sharply due to the short channel effect, and the channel length can be shortened while maintaining the threshold value, so that the on-resistance-threshold value trade-off can be improved. ..

Further, since the low-concentration thin film has a profile in which the impurity concentration decreases as it approaches the center of the trench, the impurity concentration in the channel portion can be further reduced. As a result, the channel length can be shortened and the on-resistance can be reduced.

Further, a low-concentration thin film having a profile in which the impurity concentration decreases toward the center of the trench is formed by an annealing treatment on the trench or a treatment for activating ^{the n ++} type source region and the p ^{+++ type contact region.} be able to. As a result, a semiconductor device capable of forming a low-concentration thin film and reducing on-resistance can be realized at low cost by an existing process.

(Embodiment 2)
Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. FIG. 9 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The difference between the silicon carbide semiconductor device according to the second embodiment and the silicon carbide semiconductor device according to the first embodiment is that, as shown in FIG. 9, in the second embodiment, the low-concentration thin film 14 is provided at the bottom of the trench 18. It is a point that has not been done.

The low-concentration thin film 14 is in contact with the n ⁺⁺ type source region 7, the p ⁺ type base layer 6 and the n-type region 5, and is of the same conductive type as the contacting region, and the impurity concentration is lower than that of the contacting region. There is. For example, the region S1 in contact with ^{the n ++} type source region 7 of the low-concentration thin film 14 ^{is n-} type and has a lower impurity concentration than the ^{n ++ type source region 7.} Further, the region S2 in contact with ^{the p +} type base layer 6 of the low concentration thin film 14 ^{is p-} type and has a lower impurity concentration than the ^{p + type base layer 6.} The region S3, in contact with the n-type region 5 of low density thin film 14, n ^- is the type, impurity concentration lower than the n-type region 5. Further, the low-concentration thin film 14 is not in contact with the first p ⁺⁺ type region 3. That is, the low-concentration thin film 14 is not provided at the bottom of the trench 18, and the trench 18 and the first p ⁺⁺ type region 3 are in contact with each other at the bottom of the trench 18. As a result, the capacitance between the drift and the gate is reduced, and the loss during switching can be reduced. Further, the film thickness of the low-concentration thin film 14 preferably has an aspect ratio of 2 or more between the channel length and the film thickness of the low-concentration thin film 14. For example, when the channel length is 0.4 μm, it is preferable that the film thickness of the low-concentration thin film 14 is 0.2 μm or less and the channel length / film thickness of the low-concentration thin film 14 is ≥ 2.

Further, the low-concentration thin film 14 has a profile in which the impurity concentration decreases as it approaches the center O of the trench 18. Specifically, the low-concentration thin film 14 has the ^{highest impurity concentration in the portion in contact with the n ++} type source region 7, the p ⁺ type base layer 6 and the n-type region 5, and is in contact with the gate insulating film 9 described later. The impurity concentration is the lowest. Since the ^{impurity concentration is highest in the region in contact with the p +} type base layer 6, the low concentration thin film 14 can further increase the resistance in the channel region.

Further, as shown in FIG. 9, in the second embodiment, the p ⁺⁺⁺ type contact region 8 does not have to be in contact with the second p ^{++ type region 4.}

Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described. 10 to 15 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the second embodiment. First, as in the first embodiment, the n ⁺ type silicon carbide substrate 1 is prepared ^{, and the steps up to the step of selectively forming the upper second p ++} type region 4b are sequentially performed (see FIGS. 2 and 3). ..

^{Next, the p +} type base layer 6 is epitaxially grown on the upper n-type region 5b and the upper second p ⁺ type region 4b. For example, the epitaxial growth conditions for forming the p ⁺ -type base layer 6, the impurity concentration of the p ⁺ -type base layer 6 may be set to be 1.7 × 10 ¹⁷ / cm ³ order. ^{Further, the p +} type base layer 6 may be formed by inverting the conductive type of the upper n-type region 5b by ion implantation of the p-type impurity.

^{Next, a p +++} type contact region 8 that ^{does not contact the second p ++} type region 4 ^{is selectively formed on the surface layer of the p +} type base layer 6 by photolithography and ion implantation of p-type impurities. For example, the dose amount at the time of ion implantation for forming the ^{p +++} type contact region 8 may be set so ^{that the impurity concentration is about 3 × 10 20} / cm ^3. The state up to this point is shown in FIG.

^{Next, the n ++} type source region 7 is selectively formed on ^{the surface layer of the p +} type base layer 6 so as to be in contact ^{with the p +++} type contact region 8 by photolithography and ion implantation of n-type impurities. For example, the dose amount at the time of ion implantation for forming the ^{n ++} type source region 7 may be set so ^{that the impurity concentration is about 3 × 10 20} / cm ^3. The formation order of the n ⁺⁺ type source region 7 and the p ⁺⁺⁺ type contact region 8 may be exchanged.

Next, photolithography and etching are performed to form a trench 18 that ^{penetrates the n ++} type source region 7 and the p ⁺ type base layer 6 and reaches the n type region 5 and the lower second p ^{+ type region 4a.} An oxide film is used as a mask when forming a trench. The state up to this point is shown in FIG.

Next, a low-concentration thin film 14 ”which becomes a low-concentration thin film 14 is epitaxially grown on ^{the n ++} type source region 7, on the p ^{+++ type contact region 8, and inside the trench 18 to be thicker than 0.1 μm.} As a result, ^{the semiconductor film 14 "is thickly deposited on the n ++} type source region 7, on the p ⁺⁺⁺ type contact region 8, and on the upper portion, the side wall surface, and the bottom of the trench 18. The upper part of the trench 18 is a portion on the source side from the region in contact ^{with the trench 18 and the n ++ type source region 7.} The side wall of the trench 18 is a ^{portion in contact with the n ++} type source region 7, the p ⁺ type base layer 6, and the n type region 5. As shown in FIG. 12, the upper part of the trench 18 is deposited particularly thickly, and a low-concentration thin film 14 ”is formed so as to cover the opening of the trench 18.

For example, the conditions for epitaxial growth for forming the low-concentration thin film 14 "may be set so that ^{the impurity concentration of the low-concentration thin film 14" is about 1 × 10 14 to} 5 × 10 ¹⁶ / cm ^3. The density error of the low-concentration thin film 14 "is about ± 100%. Here, the conductive type of the low-concentration thin film 14" may be n-type or p-type. Further, the low-concentration thin film 14 "may be non-doped. The state up to this point is shown in FIG.

Specifically, when the non-doped low-concentration thin film 14 ”is epitaxially grown, the silicon carbide substrate 100 is carried into the epitaxial growth apparatus, and the temperature of the silicon carbide substrate 100 is set as desired within a range of 1500 ° C. or higher and 1700 ° C. or lower. _{At a temperature, hydrogen (H 2} ) gas is used as a carrier gas on the surface of the silicon carbide substrate 100, and _{silane (SiH 4} ) gas and propane (C ₃ H ₈ ) gas, which are raw material gases, are simultaneously supplied. , by controlling the pressure of the gas to the desired pressure in the 20000Pa below the range of 5000 Pa, by setting the film forming time corresponding to a desired set thickness, the flow rate of the .H ₂ gas to form an epitaxial layer Is, for example, 50 slm or more and 200 slm (standard liter per minute) or less, _{the flow rate of SiH 4} gas is, for example, 10 sccm or more and 100 sccm (standard cubic centimeter per minute) or less, and _{the flow rate of C 3} H ₈ gas is, for example, 10 sccm. It is 100 sccm or more and 100 sccm or less.

Further, when the n-type low-concentration thin film 14 ”is epitaxially grown, the silicon carbide substrate 100 is carried into the epitaxial growth apparatus, and the temperature of the silicon carbide substrate 100 is set to a desired set temperature within a range of 1500 ° C. or higher and 1700 ° C. or lower. _{Then, hydrogen (H 2} ) gas is used as a carrier gas on the surface of the silicon carbide substrate 100, and _{silane (SiH 4} ) gas and propane (C ₃ H ₈ ) gas, which are raw material gases, are simultaneously supplied. A dopant gas containing nitrogen (N ₂ ) is supplied, the pressure of the gas is controlled to a desired pressure in the range of 5000 Pa or more and 20000 Pa or less, and the film forming time is set according to the desired set film thickness. The flow rate of H ₂ gas is, for example, 50 slm or more and 200 slm or less, _{the flow rate of SiH 4} gas is, for example, 10 sccm or more and 100 sccm or less, and _{the flow rate of C 3} H ₈ gas is, for example, 10 sccm. It is set to 100 sccm or less, and _{the flow rate of N 2} gas is set to, for example, 1 sccm or more and 20 sccm or less.

Further, when the p-type low-concentration thin film 14 ”is epitaxially grown, the silicon carbide substrate 100 is carried into the epitaxial growth apparatus, and the temperature of the silicon carbide substrate 100 is set to a desired set temperature within a range of 1500 ° C. or higher and 1700 ° C. or lower. _{Then, hydrogen (H 2} ) gas is used as a carrier gas on the surface of the silicon carbide substrate 100, and _{silane (SiH 4} ) gas and propane (C ₃ H ₈ ) gas, which are raw material gases, are simultaneously supplied. A dopant gas containing trimethylaluminum (TMA: Trimethylluminium: (CH ₃ ) ₃ Al) is supplied, and the pressure of the gas is controlled to a desired pressure in the range of 5000 Pa or more and 20000 Pa or less to obtain a desired set film thickness. An epitaxial layer is formed by setting the film formation time according to the _{above. The flow rate of H 2} gas is, for example, 50 slm or more and 200 slm or less, and _{the flow rate of SiH 4} gas is, for example, 10 sccm or more and 100 sccm or less, and C ₃ H. _{The flow rate of 8} gas is, for example, 10 sccm or more and 100 sccm or less, and the flow rate of TMA gas is, for example, 0.01 sccm or more and 0.5 sccm or less.

Next, etching back is performed to remove the low-concentration thin film 14 "at the top and bottom of the trench 18 to form a low-concentration thin film 14'. Specifically, the n ⁺⁺ type source region of the low-concentration thin film 14". On the 7th, on the p ⁺⁺⁺ type contact region 8 and on the side wall of the trench 18, the thickness of each is 0.03 to 0.1 μm, and the thickness of the trench 18 of the low-concentration thin film 14 ”is increased to 0.03 to 0.1 μm. Anisotropic etching is performed until the bottom portion disappears. In this way ^{, the thickness is 0.03 to 0.03 to above the n ++} type source region 7, on the p ⁺⁺⁺ type contact region 8, and inside the trench 18. A thin film can be formed up to 0.1 μm. It is difficult to control the time, flow rate, pressure, etc. for epitaxial growth of a thin thin film, but a thin film can be easily formed by forming a thick film and thinning it by etching. The state up to this point is shown in FIG.

Specifically, the etchback of the low-concentration thin film 14 ”is carried into an ICP etching apparatus adopting an inductively coupled plasma system (ICP), and the silicon carbide substrate 100 is carried into the surface of the silicon carbide substrate 100. Using a mixed gas of sulfur hexafluoride (SF ₆ ) gas, oxygen (O ₂ ) and argon (Ar), which are etching gases, the antenna power is 1000 or more and 2000 W or less, the bias power is 100 or more and 500 W or less, and the gas Etching back is performed by controlling the pressure to a desired pressure within the range of 0.1 or more and 2.0 Pa or less and setting the etching time according to the desired set film thickness. The flow rate of _{SF 6 gas is determined.} For example, 1 sccm or more and 50 sccm or less, _{the flow rate of O 2} gas is, for example, 1 sccm or more and 50 sccm or less, and the flow rate of Ar gas is, for example, 50 sccm or more and 300 sccm or less.

Further, after forming the low-concentration thin film 14', isotropic etching for removing damage to the trench 18 and hydrogen annealing for rounding the corners of the bottom of the trench 18 and the opening of the trench 18 may be performed. Only one of isotropic etching and hydrogen annealing may be performed. Further, hydrogen annealing may be performed after performing isotropic etching. Hydrogen annealing is performed, for example, at 1500 ° C.

When hydrogen annealing is performed, the low-concentration thin film 14'becomes a low-concentration thin film 14 by hydrogen annealing. That is, the low-concentration thin film 14 having the same conductive type as the contacted region is formed. Specifically, a portion in contact with the n ⁺⁺ type source region 7 of low density thin film 14 'is, n-type impurities from n ⁺⁺ type source region 7, for example, phosphorus (P) is diffused in the horizontal and vertical directions , The conductive type becomes n ^- type. Here, the lateral direction is the width direction of the trench, and the portion that diffuses in the lateral direction is a portion where the low-concentration thin film 14'in the trench 18 ^{is in contact with the n ++} type source region 7. The vertical direction is the depth direction of the trench, and the portion that diffuses in the vertical direction is a portion where the low-concentration thin film ^{14'is in} contact with the n ++ type source region 7 at the upper part of the silicon carbide substrate 100. Similarly, a portion in contact with the p ⁺ -type base layer 6 of a low density thin film 14 'is diffused from the p ⁺ -type base layer 6 p-type impurity, such as aluminum (Al) is laterally conductivity type p ^- type and Become. The same applies to the portion of the low-concentration thin film 14'that ^{is in contact with the p +} type base layer 6 and the n-type region 5. Since silicon carbide is a material in which impurities are difficult to diffuse, impurities diffused in the horizontal direction are less likely to be further diffused in the vertical direction. Therefore, the low-concentration thin film 14 is the same as the conductive type in the region in contact with the low-concentration thin film 14.

Further, since the low-concentration thin film 14 diffuses p-type or n-type impurities from the region in contact with the low-concentration thin film 14, the impurity concentration of the low-concentration thin film 14 is based on the n ⁺⁺ type source region 7 and p ⁺ type. The portion in contact with the layer 6 and the like becomes higher, and ^{becomes lower as the distance from the n ++} type source region 7 and the p ⁺ type base layer 6 and the like increases. As a result, the low-concentration thin film 14 has a profile in which the impurity concentration decreases as it approaches the center O of the trench 18.

Next, activation annealing is performed on the ion-implanted region. For example, activation annealing is performed at 1700 ° C. As a result, ^{the impurities ion-implanted into the n ++} type source region 7 and the p ⁺⁺⁺ type contact region 8 are activated. Here, when hydrogen annealing is not performed on the trench 18, the low-concentration thin film 14'becomes a low-concentration thin film 14 by activation annealing. The processing content is the same as in the case of hydrogen annealing for the trench 18, and is therefore omitted. The state up to this point is shown in FIG. In addition, activation annealing may be performed before forming the trench 18. In this case, it is necessary to perform hydrogen annealing on the trench 18 in order to form the low-concentration thin film 14.

Next, the gate insulating film 9 is formed along the front surface of the silicon carbide substrate 100 and the inner wall of the trench 18. Next, for example, polysilicon is deposited and etched so as to be embedded in the trench 18 to leave polysilicon to be the gate electrode 10 inside the trench 18. At that time, the polysilicon may be etched back so as to remain inside the surface of the substrate, or the polysilicon may protrude outward from the surface of the substrate by performing patterning and etching. The state up to this point is shown in FIG.

Next, the step of forming the drain electrode 13 is performed from the step of forming the interlayer insulating film 11 as in the first embodiment. In this way, the MOSFET shown in FIG. 9 is completed.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, in the second embodiment, since the low-concentration thin film is not provided at the bottom of the trench, the capacitance between the drift and the gate is reduced, and the loss during switching can be reduced. As a result, it is possible to realize a semiconductor device having less power loss and less heat generation during operation.

Further, in order to form a low-concentration thin film by epitaxial growth, it is difficult to control the time, flow rate, pressure, etc. However, in the second embodiment, since a thick film is formed and thinned by etching, the low-concentration thin film is formed. It can be easily created.

(Embodiment 3)
Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. FIG. 16 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the third embodiment. The difference between the silicon carbide semiconductor device according to the third embodiment and the silicon carbide semiconductor device according to the second embodiment is that, as shown in FIG. 16, in the third embodiment, the first p ⁺⁺ type in contact with the bottom of the trench 18 The point is that the region 3 is not provided.

Here, when the first 1p ⁺⁺ type region 3 is present, because there is no low density thin film 14 on the bottom of the trench 18, in n-type impurity is soaked to the 1p ⁺⁺ type region 3, the 1p ⁺⁺ type region 3 Becomes a resistance, and the on-resistance increases. On the other hand, in the third embodiment, since ^{there is no first p ++} type region 3, there is no region that becomes a resistance, and the on-resistance is further reduced as compared with the second embodiment. Since the electric field is concentrated at the bottom of the trench 18 due to the absence of the first p ⁺⁺ type region 3, for example, the interlayer insulating film 11 is thickened, or between the trench 18 and the second p ⁺⁺ type region 4. By shortening the distance between the two, the electric field concentration at the bottom of the trench 18 can be relaxed.

Next, a method for manufacturing the silicon carbide semiconductor device according to the third embodiment will be described. First, as in the first embodiment, the n ⁺ type silicon carbide substrate 1 is prepared, and the steps up to the step of epitaxially growing the lower n-type region 5a are performed in order (see FIG. 2).

^{Next, the lower second p ++} type region 4a is selectively formed on the surface layer of the lower n-type region 5a by photolithography and ion implantation of p-type impurities. ^{That is, the first p ++} type region 3 is not formed on the surface layer of the lower n type region 5a. The only difference from FIG. 3 of the first embodiment is that there is no first p ⁺⁺ type region 3, and therefore the illustration is omitted. Then, as in the second embodiment, the MOSFET shown in FIG. 16 is completed by sequentially performing the steps after the step of epitaxially growing the upper n-type region 5b.

As described above, according to the third embodiment, the same effect as that of the second embodiment can be obtained. Further, the third embodiment does not ^{include a first p ++} type region in contact with the bottom of the trench. As a result, since there is no region where n-type impurities permeate and become a resistance, the on-resistance can be further reduced as compared with the second embodiment.

(Example)
In this embodiment, the silicon carbide substrate 100 is carried into the epitaxial growth apparatus, the temperature of the silicon carbide substrate 100 is set to 1630 ° C., and H ₂ gas is used as a carrier gas on the surface of the silicon carbide substrate 100 as a raw material gas. SiH ₄ gas and C ₃ H ₈ gas are supplied at the same time, _{and a dopant gas containing N 2} is supplied to control the gas pressure to a pressure of 10000 Pa to form an n-type low-concentration thin film 14 ”. The flow rate of the formed H ₂ gas was 100 slm, the flow rate of the SiH ₄ gas was 50 _{sccm, the flow rate of the C 3} H ₈ gas was 20 sccm, and the flow rate of the N ₂ gas was 3 sccm.

_{Next, the silicon carbide substrate 100 is carried into the ICP etching apparatus, and a mixed gas of SF 6} gas, O ₂ and Ar, which is an etching gas, is used on the surface of the silicon carbide substrate 100 to set the antenna power to 1700 W and bias. Etching back was performed by setting the power to 210 W and controlling the gas pressure to 0.8 Pa. The flow rate of SF ₆ gas was 10 sccm, the flow rate of O ₂ gas was 15 sccm, and the flow rate of Ar gas was 140 sccm.

By producing the silicon carbide semiconductor device in this way and shortening the channel length, it was confirmed that the on-resistance was lowered, and further, it was confirmed that the threshold voltage was not lowered. It was also confirmed that the loss during switching can be reduced and the power loss during operation is reduced.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set in various ways according to the required specifications and the like. Further, in each of the above-described embodiments, MOSFETs are described as an example, but the present invention is not limited to this, and various types of silicon carbide that conduct and cut off current by being gate-driven and controlled based on a predetermined gate threshold voltage. It can be widely applied to semiconductor devices. Examples of the silicon carbide semiconductor device whose gate drive is controlled include an IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) and the like. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is described as an example, but it can also be applied to a widebandgap semiconductor such as gallium nitride (GaN) other than silicon carbide. Is. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are particularly useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines. Suitable for silicon carbide semiconductor devices with a trench gate structure.

1 n ⁺ type silicon carbide substrate 2 n ^- type drift layer 3 1st p ⁺⁺ type region 4 2nd p ⁺⁺ type region 4a Lower 2nd p ⁺⁺ type region 4b Upper 2nd p ⁺⁺ type region 5 n type region 5a Lower Side n-type region 5b Upper n-type region 6 p ⁺ type base layer 7 n ⁺⁺ type source region 8 p ⁺⁺⁺ type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Source electrode 13 Drain electrode 14 Low concentration Thin film 15 Nickel VDD film 18 Trench

Claims (7)

The first conductive type first semiconductor layer provided on the front surface of the silicon carbide substrate and
A second conductive type second semiconductor layer provided on the opposite side of the first semiconductor layer with respect to the silicon carbide substrate side,
A first conductive type first semiconductor region having a higher impurity concentration than the first semiconductor layer, which is selectively provided inside the second semiconductor layer,
A trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer,
A semiconductor film provided inside the trench and in contact with the second semiconductor layer and the first semiconductor layer,
A gate electrode provided inside the trench and inside the semiconductor film via a gate insulating film, and
The first electrode in contact with the first semiconductor region and the second semiconductor layer, and
A second electrode provided on the back surface of the silicon carbide substrate and
With
In the semiconductor film, the region in contact with the second semiconductor layer is a second conductive type region having a lower impurity concentration than the second semiconductor layer, and the region in contact with the first semiconductor layer is from the first semiconductor layer. Ri region der of low impurity concentration first conductivity type silicon carbide semiconductor device in which the impurity concentration closer to the center of the trench and having a profile lower. The semiconductor film is characterized in that the region in contact with the second semiconductor layer is a second conductive type having a lower impurity concentration than the second semiconductor layer and is not provided at the bottom of the trench. The silicon carbide semiconductor device according to the above. The first step of forming the first conductive type first semiconductor layer on the front surface of the silicon carbide substrate, and
A second step of forming a second conductive type second semiconductor layer on the side of the first semiconductor layer opposite to the silicon carbide substrate side,
A third step of selectively forming a first conductive type first semiconductor region having a higher impurity concentration than the first semiconductor layer inside the second semiconductor layer.
A fourth step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer.
A fifth step of forming a semiconductor film in contact with the second semiconductor layer and the first semiconductor layer inside the trench.
A sixth step of forming a gate electrode provided inside the trench and inside the semiconductor film via a gate insulating film, and
The seventh step of forming the first electrode in contact with the first semiconductor region and the second semiconductor layer, and
The eighth step of forming the second electrode on the back surface of the silicon carbide substrate, and
With
In the fifth step, a region of the semiconductor film in contact with the second semiconductor layer is formed in a second conductive type region having a lower impurity concentration than the second semiconductor layer, and the region is formed with the first semiconductor layer of the semiconductor film. The contacting region is formed in the first conductive type region having a lower impurity concentration than the first semiconductor layer, and the semiconductor film is formed so as to have a profile in which the impurity concentration becomes lower as it approaches the center of the trench. A method for manufacturing a silicon carbide semiconductor device as a feature. The fifth step is
A step of epitaxially growing the semiconductor film on the first semiconductor region, on the second semiconductor layer, and inside the trench.
The step of removing the semiconductor film at the bottom of the trench and
A step of forming a region of the semiconductor film in contact with the second semiconductor layer into a second conductive type region having a lower impurity concentration than the second semiconductor layer.
The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the process includes the above. In the step of removing the semiconductor film at the bottom of the trench, the semiconductor film on the first semiconductor region, on the second semiconductor layer, and on the side wall of the trench is thinned, and the semiconductor film at the bottom of the trench is removed. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the silicon carbide semiconductor device is manufactured. In the fifth step, the semiconductor film having a profile in which the impurity concentration becomes lower as it approaches the center of the trench is formed by the treatment of activating the first semiconductor region formed in the third step. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 3 to 5. The fifth step is characterized in that, by annealing the trench formed in the fourth step, the semiconductor film having a profile in which the impurity concentration becomes lower as it approaches the center of the trench is formed. The method for manufacturing a silicon carbide semiconductor device according to any one of 3 to 5.

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