JP6908388B2 - Symbol reproduction circuit and relay device - Google Patents

Description

The present invention relates to a digital signal transmission technique, and more particularly to a symbol reproduction circuit and a relay device for terrestrial digital broadcasting, which uses a low density parity check (LDPC) code as an error correction code.

In recent years, a digital broadcasting system that employs an LDPC code, which is a high-performance error correction code, has been standardized, and actual broadcasting has already been performed in some countries. The LDPC code is a block code characterized by a low density of "1" in the parity check matrix and a long code length, and it is known that performance close to the Shannon limit can be obtained.

Until now, in digital broadcasting, it has been the mainstream to use a convolutional code for the internal code and a Reed-Solomon code for the external code, but since the LDPC code was put into practical use, the LDPC code has been used for the internal code and the BCH code has been used for the external code. Proposals for new methods to be used are being made one after another.

Examples of the broadcasting system using the LDPC code include an advanced wide area satellite digital broadcasting system, DVB-S2, DVB-T2, DVB-NGH, and the like. DVB-T2 is a European terrestrial digital broadcasting system using an LDPC code, and a non-regular LDPC code having a code length of 64,800 bits is adopted.

In Japan, terrestrial digital broadcasting by the ISDB-T method is carried out. ISDB-T, like DVB-T2, is a method based on Orthogonal Frequency Division Multiplexing (OFDM), but a conventional convolutional code is used as the internal code. In the future, it is expected that a new Japanese next-generation terrestrial digital broadcasting system that uses LDPC codes will appear.

On the other hand, in Japan, many relay stations are installed in order to deliver the radio waves of terrestrial digital broadcasting all over the country, and many of the relay stations receive, amplify, and retransmit the radio waves of higher-level stations as a relay method. We have adopted a broadcast wave relay.

The relay device provided in the relay station not only simply receives the radio waves transmitted from the higher-level station and performs amplification and retransmission processing, but also has a function of equalizing the multipath distortion contained in the received radio waves. And some have a function of removing noise components by determination processing (see, for example, Patent Document 1, Non-Patent Documents 1 and 2). Such a relay device is useful for reducing signal quality deterioration in multi-stage relay.

JP-A-2002-330112

Shunji Nakahara, Hiroyuki Hamazumi, Kazuhiko Shibuya, Hiroo Arada, "Application of Space Diversity Reception in Broadcast Wave Relay of Digital Terrestrial Broadcasting-Examination of Broadcast Wave Relay for Frequency Axis Equalization and Equalization Judgment-", ITE Technical Report , Vol.25, No.50, PP.13-18, BCS2001-26 ROF2001-66 (Jul.2001) Tomoaki Takeuchi, Kazuhiko Shibuya, "Transmission Characteristics in Judgment Playback Relay of Digital Terrestrial Broadcasting", IEICE Technical Report, EMCJ2005-141 (2006-03)

FIG. 1 is a block diagram showing a configuration example of a terrestrial broadcasting system including a relay station. This terrestrial broadcasting system is composed of a master station (transmitting device) 200, a relay station (relay device) 202, and a receiver 204. The broadcast wave transmitted from the master station 200 is transmitted to the relay station 202 via the transmission line 201 between the master station 200 and the relay station 202. The broadcast wave transmitted from the relay station 202 is transmitted to the receiver 204 via the transmission line 203 between the relay station 202 and the receiver 204 installed in a general household.

The master station 200 performs various processes such as modulation and transmits a broadcast wave, and the relay station 202 receives the broadcast wave transmitted from the master station 200 and performs various processes such as transmission line equalization, symbol determination and remapping. Performs processing and transmits broadcast waves. The receiver 204 receives the broadcast wave transmitted from the relay station 202 and performs various processes such as transmission line equalization and demodulation / decoding.

In FIG. 1, the white Gaussian noise a represents the thermal noise in the receiving unit (not shown) of the relay station 202, and the white Gaussian noise b represents the thermal noise in the tuner unit (not shown) of the receiver 204. Represents.

Hereinafter, the C / N of the reception signal of the relay station 202 in the reception of the upper station (the level of the signal from the transmission line 201 is C and the level of the white Gaussian noise a is N) is referred to as the relay station reception C / N. Further, the C / N of the received signal of the receiver 204 in the area reception (the level of the signal from the transmission line 203 is C and the level of the white Gaussian noise b is N) is referred to as an area reception C / N. The higher station reception means the reception of the broadcast wave transmitted from the master station 200, which is the higher station, by the relay station 202, and the area reception means the reception of the broadcast wave transmitted from the relay station 202 by the receiver 204. Refers to reception in the area where the broadcast was made. It is assumed that the LDPC code is used for the error correction coding process.

In the terrestrial broadcasting system shown in FIG. 1, it is assumed that the relay station reception C / N is low and the relay station reception C / N is close to the required C / N in a white Gaussian noise environment directly connected to modulation / demodulation. In this case, when the relay station 202 performs the symbol hardness determination, the required C / N for area reception may be higher than when the symbol hardness determination is not performed.

This means that the process of determining the symbol hardness at the relay station 202, which is performed to improve the transmission characteristics, conversely deteriorates the transmission characteristics. Therefore, it is necessary to establish a symbol determination method that can always improve the transmission characteristics regardless of the relay station reception C / N.

In receiver 204, the Sum-Product algorithm is used to decode the LDPC code. The Sum-Product algorithm is an algorithm that improves the bit likelihood of the entire code by repeatedly exchanging the likelihood (reliability) of each bit between the bit node and the check node. Therefore, in order to fully demonstrate the correction ability, the accuracy of the likelihood (initial likelihood) given first is important.

On the other hand, when the relay station 202 performs the symbol hardness determination, the signal point of the received signal of the relay station 202 is forcibly remapped to the specified signal point on the nearest constellation. Therefore, when the level of noise included in the received signal of the relay station 202 is high, a large error may occur in the likelihood information of each bit of the received signal.

When the relay station reception C / N is high to some extent, the effect of removing the noise component by the symbol hardness determination is large, and the required C / N in the area reception is improved. However, when the relay station reception C / N becomes low, a large error occurs in the likelihood information related to the noise component of the reception signal of the relay station 202, and the required C / N in the area reception deteriorates on the contrary.

Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a symbol reproduction circuit and a relay device which prevent deterioration of required C / N in area reception and improve transmission characteristics. To do.

In order to solve the above problem, the symbol reproduction circuit according to claim 1 is a symbol reproduction circuit that reproduces a symbol of a received signal, and is a nearest vicinity point that detects a specified signal point closest to the symbol of the received signal. A subtraction circuit for obtaining an error by subtracting the symbol of the specified signal point detected by the nearest neighbor point detection circuit from the detection circuit and the symbol of the received signal, and the error obtained by the subtraction circuit are reduced and remain. As described above, it is characterized by including a generation circuit that generates a new symbol in place of the symbol of the received signal and outputs the new symbol as a symbol after reproduction.

Further, in the symbol reproduction circuit according to claim 2, in the symbol reproduction circuit according to claim 1 , the generation circuit includes a multiplication circuit and an addition circuit, and the error obtained by the multiplication circuit by the subtraction circuit is reduced. And so as to remain, the preset suppression coefficient is multiplied by the error to obtain the error of the multiplication result, and the addition circuit multiplies the symbol of the specified signal point detected by the nearest neighbor point detection circuit with the multiplication. It is characterized in that the error of the multiplication result obtained by the circuit is added to generate the new symbol in place of the symbol of the received signal, and the new symbol is output as the symbol after reproduction.

Further, in the symbol reproduction circuit according to claim 3, in the symbol reproduction circuit according to claim 1 , the generation circuit includes an absolute value clip circuit, an addition circuit and a selection circuit, and the absolute value clip circuit is the subtraction circuit. The absolute value of the error is clipped to a preset clip value without changing the phase of the error obtained by the above, and the addition circuit is added to the error clipped to the clip value by the absolute value clip circuit. The symbols of the specified signal points detected by the nearest neighbor point detection circuit are added to generate a symbol in which the error is clipped to the clip value, and the selection circuit obtains the absolute value of the error obtained from the subtraction circuit. When it is smaller than the clip value, the symbol of the received signal is output as the symbol after reproduction, and when the absolute value of the error obtained from the subtraction circuit is larger than the clip value, the addition is performed. The error generated by the circuit is characterized in that a symbol clipped to the clip value is output as the symbol after reproduction.

Further, in the symbol reproduction circuit according to claim 4, in the symbol reproduction circuit according to claim 2 , the generation circuit further includes a suppression coefficient generation circuit, and the suppression coefficient generation circuit has a reception C / N and a suppression coefficient. The suppression coefficient corresponding to the reception C / N of the received signal is generated by using a predetermined table or mathematical formula in which the relationship of As described above, the suppression coefficient generated by the suppression coefficient generation circuit is multiplied by the error to obtain the error of the multiplication result.

Further, in the symbol reproduction circuit according to the fifth aspect, in the symbol reproduction circuit according to the fourth aspect, when the symbol reproduction circuit reproduces the carrier symbol of the received OFDM signal, the suppression coefficient generation circuit is the predetermined one. Using the table or mathematical formula of the above, a suppression coefficient corresponding to the entire received C / N in the received OFDM signal or the received C / N for each carrier symbol is generated, and the received OFDM signal is used as the received C / N. It is characterized in that a value calculated based on a control symbol, a pilot symbol or a data symbol included in is used.

Further, the symbol reproduction circuit according to claim 6 is the symbol reproduction circuit according to claim 3 , wherein the generation circuit further includes a clip value generation circuit, and the clip value generation circuit has a reception C / N and a clip value. A clip value corresponding to the reception C / N of the received signal is generated by using a predetermined table or mathematical formula in which the relationship of The absolute value of the error is clipped to the clip value generated by the clip value generation circuit without changing, and an error signal is generated in which the absolute value of the error is clipped to the clip value. And.

Further, in the symbol reproduction circuit according to claim 7, when the symbol reproduction circuit reproduces the carrier symbol of the received OFDM signal in the symbol reproduction circuit according to claim 6, the clip value generation circuit is the predetermined. A clip value corresponding to the entire received C / N in the received OFDM signal or the received C / N for each carrier symbol is generated using the table or mathematical formula of the above, and the received OFDM signal is used as the received C / N. It is characterized in that a value calculated based on a control symbol, a pilot symbol or a data symbol included in is used.

Further, the relay device according to claim 8 is characterized by including the symbol reproduction circuit according to any one of claims 1 to 7.

As described above, according to the present invention, it is possible to prevent deterioration of the required C / N in area reception and improve transmission characteristics.

It is a block diagram which shows the configuration example of the terrestrial broadcasting system including a relay station. It is a figure explaining the principle of error suppression type remapping. It is a figure explaining the principle of error clip type remapping. It is a figure which shows the uniform constellation when the modulation method is 1024QAM. It is a figure which shows the example of the non-uniform constellation when the modulation method is 1024QAM. It is a system diagram of a computer simulation. It is a figure which shows the BER characteristic with respect to the area reception C / N when the constellation type is UC, and the relay station reception C / N is 30dB when the error suppression type remapping is used. It is a figure which shows the BER characteristic with respect to the area reception C / N when the constellation type is UC, and the relay station reception C / N is 29dB when the error suppression type remapping is used. It is a figure which shows the BER characteristic with respect to the area reception C / N when the constellation type is NUC, and the relay station reception C / N is 28dB when the error suppression type remapping is used. It is a figure which shows the BER characteristic with respect to the area reception C / N when the constellation type is UC, and the relay station reception C / N is 29dB when the error clip type remapping is used. It is a figure which shows the BER characteristic with respect to the area reception C / N when the constellation type is NUC, and the relay station reception C / N is 28dB when the error clip type remapping is used. It is a figure which shows the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is UC and the suppression amount is an optimum value when the error suppression type remapping is used. It is a figure which shows the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is NUC and the suppression amount is an optimum value when the error suppression type remapping is used. It is a figure which shows the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is UC and the clip value is the optimum value when the error clip type remapping is used. It is a figure which shows the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is NUC and the clip value is the optimum value when the error clip type remapping is used. It is a figure which shows the BER characteristic with respect to the area reception C / N when the relay station reception C / N is used as a parameter, and the conventional symbol hardness determination is used for the processing of the relay station symbol determination. It is a block diagram which shows the configuration example of the SISO type relay device. It is a block diagram which shows the structural example of the MIMO type relay device. It is a block diagram which shows the structural example of the SISO type equalization determination apparatus. It is a block diagram which shows the structural example of the MIMO type equalization determination apparatus. It is a block diagram which shows the structural example of the symbol reproduction circuit which performs error suppression type remapping. It is a block diagram which shows the structural example of the symbol reproduction circuit which performs error clip type remapping.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
[Outline of the present invention]
First, the outline of the present invention will be described. In the present invention, when the received signal is symbol-determined and remapped, the received signal is not remapped to a point that completely coincides with the specified signal point as in the rigid determination, but the received signal point and the specified signal point are used. It is characterized by reducing the error (distance) between them and remapping so that the error remains to some extent. Hereinafter, such processing is referred to as error residual type remapping (or error residual type symbol determination).

As a result, for example, when the relay station 202 shown in FIG. 1 performs the error residual type remapping process, the influence of noise included in the relay station reception signal is the likelihood of the LDPC decoding process of the receiver 204 in the area reception. It will be partially reflected in the information. The receiver 204 performs the LDPC code decoding process using the Sum-Product algorithm on the likelihood information reflecting the influence of the noise of the relay station reception signal and the noise in the area reception, thereby performing the relay station reception signal. The bit error rate characteristic can be improved as compared with the case where the influence of the noise contained in is not reflected at all. Therefore, it is possible to prevent the required C / N in area reception from deteriorating on the contrary by performing the symbol determination process, and it is possible to improve the transmission characteristics of the receiver 204.

Specific examples of error residual type remapping include error suppression type remapping and error clipping type remapping. Hereinafter, the error suppression type remapping and the error clip type remapping will be described in detail.

[Error-suppressing remapping]
First, error-suppressing remapping will be described. FIG. 2 is a diagram illustrating the principle of error-suppressing remapping. In this example, the modulation method is 64QAM, and the constellation type is uniform constellation (UC).

とし、この位相は変化させず、絶対値のみをγ倍したベクトルを残留誤差ベクトル

βとする。ここで、γは抑圧係数であり、

及び０≦γ≦１を満たすスカラー量である。 Let A be the signal point of the received signal (input symbol), and B be the specified signal point (signal point at the time of mapping) on the constellation closest to the signal point A of the received signal (the distance between the signal points is the smallest). The error vector is the vector connecting the specified signal point B and the received signal point A, starting from the specified signal point B.

The residual error vector is a vector obtained by multiplying only the absolute value by γ without changing this phase.

Let it be β. Here, γ is the suppression coefficient,

And a scalar amount satisfying 0 ≦ γ ≦ 1.

を加算して得られる信号点Ｃを、再生シンボルの信号点（再マッピング点）とする。抑圧係数γが小さいほど、再マッピング点Ｃは規定信号点Ｂに近づき、抑圧係数γが大きいほど、再マッピング点Ｃは規定信号点Ｂから離れて受信信号点Ａに近づく。 γ = 0 corresponds to the conventional hard judgment, and γ = 1 corresponds to no judgment. The reciprocal of the suppression coefficient γ is used as the suppression amount. Residual error vector at the specified signal point B

The signal point C obtained by adding the above is used as the signal point (remapping point) of the reproduction symbol. The smaller the suppression coefficient γ, the closer the remapping point C is to the specified signal point B, and the larger the suppression coefficient γ, the closer the remapping point C is to the receiving signal point A, away from the specified signal point B.

As shown in FIG. 2, due to the error suppression type remapping, the received signal at the signal point A is not remapped to the nearest specified signal point B, but the suppression coefficient between the signal point B and the signal point A. It is remapped to the signal point C defined by γ. An error remains in the signal at the remapping point C.

[Error clip type remapping]
Next, the error clip type remapping will be described. FIG. 3 is a diagram illustrating the principle of error clip type remapping. In this example, as in FIG. 2, the modulation method is 64QAM and the constellation type is uniform constellation.

As an example of the signal point of the received signal, A1 and A2, the specified signal point on the constellation closest to the signal points A1 and A2 of the received signal is B, the signal points C1 and C2 are the remapping points, and R is the threshold value (clip value). And.

とし、この位相は変化させることなく、その絶対値だけを閾値Ｒにクリップして得られるベクトルを残留誤差ベクトル

とする。そして、残留誤差ベクトル

を規定信号点Ｂに加算して得られる信号点を再マッピング点Ｃ１とする。 The reception signal point A1 is outside the circle having a radius R centered on the specified signal point B. The error vector is a vector whose start point is the specified signal point B and whose end point is the received signal point A1.

The residual error vector is the vector obtained by clipping only the absolute value to the threshold value R without changing this phase.

And. And the residual error vector

Is added to the specified signal point B, and the signal point obtained is set as the remapping point C1.

On the other hand, the received signal point A2 is inside a circle having a radius R centered on the specified signal point B. Therefore, the received signal point A2 is set as the remapping point C2 as it is.

As shown in FIG. 3, the signals at the received signal points A1 and A2 are not remapped to the nearest specified signal point B by the error clip type remapping. The signal of the received signal point A1 outside the circle centered on the specified signal point B and having the clip value R as the radius is the signal point which is the intersection of the circle of the radius R and the straight line connecting the signal point A1 and the signal point B. Remapped to C1. Further, the signal of the received signal point A2 inside the circle having the radius R centered on the specified signal point B is remapped to the signal point C2 at the same position as the received signal point A2. Here, the smaller the clip value R, which is the threshold value, the closer the remapping point is to the specified signal point B, and the larger the threshold value R of the clip value, the farther the remapping point is from the specified signal point B.

Note that FIGS. 2 and 3 show a case of a uniform constellation in which the distance between the specified signal points is constant, but a non-uniform constellation (NUC: Non-Uniform Constellation) in which the distance between the specified signal points is uneven. ), The exact same processing can be applied.

FIG. 4 is a diagram showing a uniform constellation when the modulation method is 1024QAM, and FIG. 5 is a diagram showing an example of a non-uniform constellation when the modulation method is 1024QAM.

In the example of the uniform constellation shown in FIG. 4, the distance between the specified signal points is constant, and in the example of the non-uniform constellation shown in FIG. 5, the distance between the specified signal points is not constant and uneven.

[Effect of residual error remapping]
Next, the effect of the error residual type remapping shown in FIGS. 2 and 3 will be described. FIG. 6 is a system diagram of a computer simulation carried out for verifying the characteristics when the error residual type remapping is used for the symbol determination processing of the relay station 202.

ここで、Ｙ_Iは受信シンボルのＩ軸成分、Ｙ_Qは受信シンボルのＱ軸成分、ｉは１つのシンボルで送る情報ビットの番号（例えば変調方式が１０２４ＱＡＭの場合、ｉ＝１〜１０）、ｊは変調シンボルのコンスタレーション上の信号点番号（例えば変調方式が１０２４ＱＡＭの場合、ｊ＝１〜１０２４）、Ｘ_I,jはコンスタレーション上のｊ番目の信号点のＩ軸成分、Ｘ_Q,jはコンスタレーション上のｊ番目の信号点のＱ軸成分、σ²は雑音分散(シンボル当たりの雑音電力)である。また、｛Ｊ_i,1｝はコンスタレーション上の信号点のうちｉ番目のビットが１である信号点番号の集合、｛Ｊ_i,0｝はコンスタレーション上の信号点のうちｉ番目のビットが０である信号点番号の集合である。 The specifications of this computer simulation are as shown in Table 1 below. In this simulation, an OFDM signal including a pilot carrier is assumed as a transmission signal. Furthermore, the log-likelihood ratio (LLR) was calculated based on the following formula.

Here, Y _I is the I-axis component _{of the received symbol, Y Q} is the Q-axis component of the received symbol, and i is the number of the information bit to be sent by one symbol (for example, i = 1 to 10 when the modulation method is 1024QAM). j is the signal point number on the constellation of the modulation symbol (for example, when the modulation method is 1024QAM, j = 1 to 1024), X _{I, j} is the I-axis component of the jth signal point on the constellation, X _{Q, j} is the Q-axis component of the jth signal point on the constellation, and σ ² is the noise dispersion (noise power per symbol). Also, {J _{i, 1} } is a set of signal point numbers in which the i-th bit of the signal points on the constellation is 1, and {J _{i, 0} } is the i-th bit of the signal points on the constellation. Is a set of signal point numbers where is 0.

The noise variance σ ² is a value per symbol of the sum of the error power of the relay station output signal and the power of Gaussian noise added in area reception, and is calculated and given (estimated on the receiver 204 side). Not a value). Moreover, since the propagation environment assumes an AWGN environment without multipath, the noise variance σ ² is a constant value within the band.

In FIG. 6, the master station 200 generates a PN (Pseudo Noise) code of transmission data, performs LDPC coding, bit interleaving, and mapping processing to perform data symbols (symbols of data carriers in the frequency region). Is generated, SP (Scattered Pilot) and CP (Continual Pilot) are generated, and an OFDM frame is composed of data symbols, SP, CP, and the like. Then, the master station 200 performs each process such as IFFT (Inverse Fast Fourier Transform) and GI (Guard Interval) addition of the carrier symbol framed in OFDM, and the OFDM signal in the time domain is performed. Is output. White Gaussian noise a is added to the OFDM signal output from the master station 200 when the host station receives the signal.

The relay station 202 inputs an OFDM signal to which white Gaussian noise a is added, extracts an effective symbol period through an FFT (Fast Fourier Transform) window, FFTs the effective symbol period, and carries out a carrier in the frequency domain. Convert to a symbol. Then, the relay station 202 performs processing such as symbol determination and SP replacement by error residual type remapping, IFFTs the carrier symbol after the processing, performs each processing such as GI addition, and converts it into an OFDM signal in the time domain. Convert and output. White Gaussian noise b is added to the OFDM signal output from the relay station 202 in area reception.

The receiver 204 inputs the OFDM signal to which the white Gaussian noise b is added, extracts the effective symbol period in the FFT window, FFTs the effective symbol period, converts it into a carrier symbol in the frequency domain, and converts the SP and CP into carrier symbols. Each process such as extraction, channel estimation, equalization, LLR calculation, bit deinterleave and LDPC code decoding is performed, and the decoded data is output. Then, the BER (Bit Error Rate) of the decoded data output from the receiver 204 is measured.

Below, FIGS. 7, 8, 9, 12 and 13 show the simulation results when the error suppression type remapping is used, and FIGS. 10, 11, 14, 14 and 15 show the error clip type remapping. The simulation result when mapping is used is shown.

FIG. 7 shows the BER characteristics of the output of the receiver 204 with respect to the area reception C / N when the constellation type is UC and the relay station reception C / N is 30 dB when the error suppression type remapping is used. ing. Details such as parameters are shown in Table 1.

The vertical axis represents the bit error rate (BER) after decoding the LDPC code, and the horizontal axis represents the area reception C / N. The same applies to FIGS. 8 to 11. The required C / N is a C / N in which pseudo error-free is obtained after decoding the BCH code, and BER = 1.0 ^-7 before decoding the BCH code (that is, after decoding the LDPC code) is obtained.

In FIG. 7, simple relay (a), suppression amount = 0 dB (b), suppression amount = 2 dB (c), suppression amount = 4 dB (d), suppression amount = 8 dB (e), suppression amount = 14 dB (f). And each characteristic of the symbol hardness determination (g) is shown. Simple relay means that the determination process is not performed. The amount of suppression is the reciprocal of the suppression coefficient γ, as explained in FIG.

From FIG. 7, with respect to the simple relay (a) in which the determination process is not performed, the required C / N decreases as the suppression amount increases, such as suppression amount = 2dB (c) and suppression amount = 4dB (d). You can see that. However, when the amount of suppression exceeds the amount of suppression = 8 dB (e) and the amount of suppression increases to the amount of suppression = 14 dB (f), the required C / N starts to increase. Then, in the case of the conventional symbol hardness determination (g) in which the suppression amount is infinite, the required C / N becomes higher than the suppression amount = 2 dB (c).

As described above, it can be seen from FIG. 7 that when the error suppression type remapping is used, the suppression amount for improving the transmission characteristics has an appropriate value. Further, the characteristic of the suppression amount = 0 dB (b) is improved as compared with the simple relay (a) because of the effect of replacing the SP.

FIG. 8 shows the BER characteristics of the output of the receiver 204 with respect to the area reception C / N when the constellation type is UC and the relay station reception C / N is 29 dB when the error suppression type remapping is used. ing. Details such as parameters are shown in Table 1. The only difference between FIG. 7 and FIG. 8 is that the relay station reception C / N in FIG. 7 is 30 dB, whereas the relay station reception C / N in FIG. 8 is 29 dB.

In FIG. 8, simple relay (a), suppression amount = 0 dB (b), suppression amount = 1 dB (c), suppression amount = 2 dB (d), suppression amount = 3 dB (e), suppression amount = 4 dB (f). , Suppression amount = 8 dB (g), suppression amount = 12 dB (h), and symbol hardness determination (i) are shown.

From FIG. 8, since the required C / N of the symbol hardness determination (g) is higher than that of the simple relay (a), the characteristic of the symbol hardness determination (g) is worse than that of the simple relay (a). You can see that. Further, the required C / N is lowest in the vicinity of the suppression amount = 4 dB (f) in FIG. 8 and in the vicinity of the suppression amount = 8 dB (e) in FIG. 7. Therefore, the amount of suppression at which the required C / N is the lowest in the case of FIG. 8 is smaller than that in the case of FIG. 7.

As described above, from FIGS. 7 and 8, when the error suppression type remapping is used, the optimum suppression amount for improving the transmission characteristics (the suppression amount that minimizes the area reception required C / N) is the relay station. It can be seen that it changes depending on the reception C / N.

FIG. 9 shows the BER characteristics of the output of the receiver 204 with respect to the area reception C / N when the constellation type is NUC and the relay station reception C / N is 28 dB when the error suppression type remapping is used. ing. Details such as parameters are shown in Table 1. The difference between FIGS. 7 and 8 and FIG. 9 is that the constellation type in FIGS. 7 and 8 is UC, whereas in FIG. 9, it is NUC, and the relay station reception C / in FIGS. 7 and 8 N is 30 dB and 29 dB, respectively, whereas in FIG. 9, only the point is 28 dB.

In FIG. 9, simple relay (a), suppression amount = 0 dB (b), suppression amount = 2 dB (c), suppression amount = 4 dB (d), suppression amount = 6 dB (e), suppression amount = 14 dB (f). And each characteristic of the symbol hardness determination (g) is shown.

Comparing the characteristics of FIG. 9 with that of FIG. 7, there are differences between the constellation type (NUC in FIG. 9, UC in FIG. 7) and the relay station reception C / N (28 dB in FIG. 9, 30 dB in FIG. 7). The characteristics show the same tendency. Further, it can be seen from FIG. 9 that the error suppression type remapping shown in FIG. 2 can be applied as it is even when the constellation type is NUC.

That is, the error suppression type remapping shown in FIG. 2 can apply the same processing regardless of whether the constellation type is UC or NUC. Then, the required C / N can be improved by selecting the optimum suppression amount (the suppression amount at which the area reception required C / N is the lowest) according to the relay station reception C / N.

FIG. 10 shows the BER characteristics of the output of the receiver 204 with respect to the area reception C / N when the constellation type is UC and the relay station reception C / N is 29 dB when the error clip type remapping is used. ing. Details such as parameters are shown in Table 1.

In FIG. 10, a simple relay (a), an error clip value = 28 dB (b), an error clip value = 30 dB (c), an error clip value = 32 dB (d), an error clip value = 34 dB (e), and an error clip value. Each characteristic of = 40 dB (f) and symbol hardness determination (g) is shown. The error clip level, that is, the error clip value is a dB display (signs are inverted) of the ratio to the average level (√ of the power average value) in the modulation method.

From FIG. 10, the clip value becomes smaller (the dB value becomes larger) such that the error clip value = 28 dB (b) and the error clip value = 30 dB (c) with respect to the simple relay (a) in which the determination process is not performed. It can be seen that the required C / N decreases accordingly. However, when the error clip value = 34 dB (e) is exceeded and the clip value is reduced to the error clip value = 40 dB (f), the required C / N starts to increase. Then, in the case of the conventional symbol hardness determination (g) in which the clip value is 0 (infinity in dB value), the required C / N is higher than that in the simple relay (a).

As described above, from FIG. 10, it can be seen that when the error clip type remapping is used, the clip value for improving the transmission characteristic has an appropriate value. Further, as in the case of using the error suppression type remapping, the optimum clip value for improving the transmission characteristics (the clip value at which the area reception required C / N is the lowest) depends on the relay station reception C / N. And change.

FIG. 11 shows the BER characteristics of the output of the receiver 204 with respect to the area reception C / N when the constellation type is NUC and the relay station reception C / N is 28 dB when the error clip type remapping is used. ing. Details such as parameters are shown in Table 1. The difference between FIG. 10 and FIG. 11 is that the constellation type in FIG. 10 is UC, whereas in FIG. 11, it is NUC, and the relay station reception C / N in FIG. 10 is 29 dB. In FIG. 11, it is only the point that it is 28 dB.

In FIG. 11, simple relay (a), error clip value = 28 dB (b), error clip value = 30 dB (c), error clip value = 32 dB (d), error clip value = 34 dB (e), error clip value. Each characteristic of = 40 dB (f) and symbol hardness determination (g) is shown.

Comparing the characteristics of FIG. 11 with that of FIG. 10, there are differences between the constellation type (NUC in FIG. 11, NC in FIG. 10) and the relay station reception C / N (28 dB in FIG. 11, 29 dB in FIG. 10). The characteristics show the same tendency. Further, it can be seen from FIG. 11 that the error clip type remapping shown in FIG. 3 can be applied as it is even when the constellation type is NUC.

That is, the error clip type remapping shown in FIG. 3 can apply the same processing regardless of whether the constellation type is UC or NUC. Then, the required C / N can be improved by selecting the optimum clip value (the clip value at which the area reception required C / N is the lowest) according to the relay station reception C / N.

In this way, the optimum values of the suppression amount of error suppression type remapping and the clip value of error clip type remapping are the constellation type, the number of modulation multi-values, the coding rate, and the bit interleaving in addition to the relay station reception C / N. It changes depending on such things.

FIG. 12 is a diagram showing the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is UC and the suppression amount is the optimum value when the error suppression type remapping is used. .. Details such as parameters are shown in Table 1.

FIG. 12 shows the characteristics of simple relay (no determination) (a), symbol hardness determination (b), and symbol determination (c) by error-suppressing remapping. In the simple relay, the SP is not replaced, but in the symbol hardness determination and the error suppression type remapping, the SP is replaced with the specified value.

From FIG. 12, in the case of the symbol hardness determination (b), as the relay station reception C / N becomes lower, the improvement effect on the simple relay (a) becomes smaller, eventually reverses, and finally error-free (QEF) is obtained. It turns out that it will not be possible. Further, in the case of the error suppression type remapping (c), it can be seen that the improvement effect is always obtained with respect to the simple relay (a).

FIG. 13 is a diagram showing the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is NUC and the suppression amount is the optimum value when the error suppression type remapping is used. .. Details such as parameters are shown in Table 1. The only difference between FIG. 12 and FIG. 13 is that the constellation type in FIG. 12 is UC, whereas in FIG. 13, it is NUC.

FIG. 13 shows the characteristics of the simple relay (a), the symbol hardness determination (b), and the error suppression type remapping (c).

From FIGS. 12 and 13, the relay station reception C / N in which the characteristics of the simple relay (a) and the symbol hardness determination (b) are reversed is lower when the constellation type is NUC than when it is UC. I understand. The amount of improvement in the area reception required C / N is larger when the constellation type is NUC than when it is UC, but it can be seen that both show the same tendency.

FIG. 14 is a diagram showing the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is UC and the clip value is the optimum value when the error clip type remapping is used. ..

Further, FIG. 15 is a diagram showing the relationship between the relay station reception C / N and the area reception required C / N when the constellation type is NUC and the clip value is the optimum value when the error clip type remapping is used. Is. Details such as parameters are shown in Table 1.

14 and 15 show the characteristics of simple relay (a), symbol hardness determination (b), and symbol determination (c) by error clip type remapping.

From FIGS. 14 and 15, it can be seen that the error clip type remapping shows the same tendency as the error suppression type remapping shown in FIGS. 12 and 13.

FIG. 16 shows the BER characteristics of the output of the receiver 204 with respect to the area reception C / N when the conventional symbol hardness determination is used for the symbol determination process of the relay station 202 with the relay station reception C / N as a parameter. ing. Regarding the details such as parameters, some of the specifications shown in Table 1 are different, and the UMP-BP method (min-sum method) is applied to the LDPC code decoding method assuming actual hardware. .. Also, considering that the data is represented by a finite word length, when _{the absolute value of the logarithmic external value ratio α mn} exceeds a certain value, that value is clipped to the fixed value.

In FIG. 16, relay station reception C / N = 30 dB (a), relay station reception C / N = 31 dB (b), relay station reception C / N = 32 dB (c), relay station reception C / N = 33 dB ( d), each characteristic of relay station reception C / N = 34 dB (e) and relay station reception C / N = 35 dB (f) is shown.

From FIG. 16, when the relay station reception C / N = 30 dB (a) to 33 dB (d), when the area reception C / N is increased ^{, the BER once reduced to 1 × 10 -7} or less increases again. You can see that it will be done. This is related to clipping the absolute value of the logarithmic external value ratio α _mn to a certain value or less in the LDPC code decoding process, and is a phenomenon that also occurs in an actual device.

When remapped to the wrong specified signal point by the symbol hardness determination process, the apparent error becomes smaller as the area reception C / N becomes higher, and the log-likelihood ratio of the bits transmitted by that symbol becomes incorrect. This is due to the fact that it shows a large value in spite of the fact that it shows a large value.

As described above, in the error suppression type remapping shown in FIG. 2 and the error clipping type remapping shown in FIG. 3, even if the specified signal point B in the re-neighborhood is different from the original correct specified signal point. , In order to perform remapping with an error remaining, by appropriately setting the suppression amount of error suppression type remapping or the clip value of error clip type remapping, BER again as the area reception C / N rises. It is possible to alleviate and eliminate the problem (characteristic shown in FIG. 16) in the conventional symbol hardness determination that the value increases.

The simulation results were carried out to show the effect of the error residual type remapping according to the present invention in an easy-to-understand manner, and the calculation conditions (LDPC decoding algorithm, number of iterations, LLR calculation method, noise variance σ ^2). It should be added that the numerical value itself changes if the method of giving the SP, the insertion interval of the SP, the boost ratio of the SP, etc. are different, but it does not stop there.

[Embodiment]
Next, a specific embodiment using the error residual type remapping of the present invention will be described in detail. Hereinafter, the transmission signal conforms to the ISDB-T format having a pilot symbol such as SP (Scattered Pilot), CP (Continual Pilot), AC (Auxiliary Channel), and a control symbol such as TMCC (Transmission and Multiplexing Configuration Control). A case where it is an OFDM signal will be described.

[SISO type relay device]
First, a relay device with equalization and determination functions used in a SISO (Single-Input Single-Output) type broadcasting system (transmission format of one transmitting antenna and one receiving antenna) will be described. FIG. 17 is a block diagram showing a configuration example of a SISO type relay device. The relay device 1 includes a receiving antenna 10, a receiving BPF (Band Pass Filter) 11, a receiving unit 12, an equalization determination device 13, a transmitting unit 14, a PA (Power Amplifier) unit 15, and a transmitting BPF 16. And a transmitting antenna 17.

When the relay device 1 receives the broadcast wave transmitted from the master station 200, the reception BPF 11 inputs the reception signal via the reception antenna 10, extracts only the desired band component from the reception signal, and receives after filtering. The signal is output to the receiving unit 12. The receiving unit 12 inputs the received signal after the filter processing from the receiving BPF 11, and performs processing such as low noise amplification, AGC (Automatic Gain Control), and frequency conversion. Then, the receiving unit 12 generates a signal (IF signal) in the IF (Intermediate Frequency) band and outputs it to the equalization determination device 13.

The equalization determination device 13 inputs an IF signal from the reception unit 12, equalizes the transmission line response distortion included in the IF signal, and reduces or removes the noise component by the symbol determination process of the error residual type remapping. Then, the equalization determination device 13 outputs the IF signal after the error residual type remapping to the transmission unit 14. Details of the equalization determination device 13 will be described later.

The transmission unit 14 inputs the IF signal after the error residual type remapping from the equalization determination device 13, converts the frequency of the IF signal and amplifies it, and generates a signal (RF signal) in the RF (Radio Frequency) band. Then, it is output to the PA unit 15.

The PA unit 15 inputs an RF signal from the transmission unit 14, amplifies the RF signal to a desired power, and outputs the RF signal after the power amplification to the transmission BPF 16. The transmission BPF 16 inputs the RF signal after power amplification from the PA unit 15, removes spurious and out-of-band unnecessary components, and outputs the filtered RF signal. The filtered RF signal is retransmitted as a broadcast wave via the transmission antenna 17.

[MIMO type relay device]
Next, a relay device with equalization and determination functions used in a MIMO (Multiple-Input Multiple-Output) type broadcasting system (transmission format of two transmitting antennas and two receiving antennas) will be described. FIG. 18 is a block diagram showing a configuration example of a MIMO type relay device. The relay device 2 includes receiving antennas 20-1, 20-2, receiving BPF21-1,21-2, receiving units 22-1,22-2, equalization determination device 23, and transmitting units 24-1,24-2. , PA units 25-1, 25-2, transmission BPF 26-1, 26-2, and transmission antennas 27-1, 27-2 are provided. Since the relay device 2 is a two-system configuration of the relay device 1 shown in FIG. 17, detailed description thereof will be omitted.

Here, the equalization determination device 23 inputs two systems of IF signals from the receiving units 22-1, 22-2, equalizes the transmission line response distortion included in the IF signals of each system, and re-errors the residual type. The noise component is reduced or removed by the symbol determination process of the mapping. The equalization determination device 23 also cancels and removes croctalk (interference component, cross-polarized component in the case of polarized MIMO) between each system. Therefore, the equalization determination device 23 has a format in which the IF signals of the two systems are collectively processed and output. Details of the equalization determination device 23 will be described later.

Each IF signal output from the equalization determination device 23 is transmitted via the transmitting unit 24-1, 24-2, the PA unit 25-1, 25-2, and the transmitting BPF 26-1, 26-2, respectively. It is supplied to 1,27-2. Each RF signal filtered by the transmission BPFs 26-1 and 26-2 is retransmitted as a broadcast wave from the transmission antennas 27-1 and 27-2.

[Equalization judgment device 13 / SISO type]
Next, the SISO type equalization determination device 13 shown in FIG. 17 will be described in detail. FIG. 19 is a block diagram showing a configuration example of the SISO type equalization determination device 13. The equalization determination device 13 includes an input BPF 30, an amplifier 31, an A / D converter 32, an NCO (Numerical Controlled Oscillator) 33, a QDEM (Quadrature DE Modulator) 34, and a downsample (DS) circuit. 35, synchronous reproduction circuit 36, AFC (Automatic Frequency Control) circuit 37, FFT window circuit 38, FFT circuit 39, SP extraction circuit 40, transmission path response estimation circuit 41, equalization circuit 42, symbol separation circuit 43. , C / N estimation circuit 44, symbol reproduction circuit 45, AC and TMCC rigid determination circuit 46, SP generation circuit 47, frame configuration circuit 48, IFFT circuit 49, GI addition circuit 50, upsample (US) circuit 51, NCO52, It is equipped with a QMOD (Quadrature MODulation) 53, a D / A converter 54, an amplifier 55, and an output BPF 56.

As described above, the equalization determination device 13 equalizes the transmission line response distortion included in the IF signal input from the receiving unit 12, reduces or removes the noise component by the symbol determination process of the error residual type remapping, and causes the error residual. The IF signal after type remapping is output to the transmission unit 14.

The input BPF 30 inputs an IF signal from the receiving unit 12, removes unnecessary out-of-band components from the IF signal, and the amplifier 31 amplifies the IF signal filtered by the input BPF 30 to a predetermined level.

The A / D converter 32 converts the analog IF signal amplified by the amplifier 31 into a digital IF signal. The QDEM 34 inputs an IF signal converted into a digital signal by the A / D converter 32, converts it into an equivalent baseband signal (IQ signal) using a local signal supplied from the NCO 33, and outputs the signal.

The downsampling circuit 35 inputs the IQ signal output from the QDEM 34, performs thinning processing (downsampling processing), and outputs the sample at a reduced sampling rate. The synchronous reproduction circuit 36 performs a synchronous reproduction process based on the IQ signal thinned out by the downsample circuit 35, reproduces a synchronous signal such as symbol synchronization and clock synchronization, and is not specified in FIG. The synchronization signal is supplied to each part that requires it.

The AFC circuit 37 inputs the IQ signal thinned out from the downsample circuit 35, and removes the frequency error of the IQ signal by using the synchronous signal reproduced by the synchronous reproduction circuit 36. The FFT window circuit 38 sets the timing of the FFT window for the IQ signal from which the frequency error has been removed by the AFC circuit 37 using the synchronous signal reproduced by the synchronous reproduction circuit 36, and extracts the effective symbol period of the OFDM signal. do.

The FFT circuit 39 performs a high-speed Fourier transform on the IQ signal of the effective symbol period extracted by the FFT window circuit 38 to generate and output a carrier symbol in the frequency domain. The SP extraction circuit 40 extracts a predetermined SP (a pilot symbol distributed and BPSK-modulated in both the symbol direction and the carrier direction) from the carrier symbols in the frequency domain output from the FFT circuit 39. The transmission line response estimation circuit 41 removes the modulation component of the SP extracted by the SP extraction circuit 40, performs interpolation processing in the symbol direction and the carrier direction, and estimates the transmission line response of all the carrier symbols.

The equalization circuit 42 uses the transmission line response for each carrier symbol estimated by the transmission line response estimation circuit 41 to equalize the carrier symbol in the frequency domain output from the FFT circuit 39 (transmission line response of the carrier symbol). The process of dividing by) is performed.

The symbol separation circuit 43 separates the data symbol, AC, TMCC, and the like from the carrier symbol that has been equalized by the equalization circuit 42. The data symbol is supplied to the C / N estimation circuit 44 and the symbol reproduction circuit 45, and signals such as AC and TMCC are supplied to the C / N estimation circuit 44 and the AC and TMCC hard determination circuit 46.

The C / N estimation circuit 44 inputs data symbols, AC, TMCC, etc. from the symbol separation circuit 43, and inputs a transmission line response for each carrier symbol from the transmission line response estimation circuit 41. Then, the C / N estimation circuit 44 calculates the error of each carrier symbol in the data symbol, AC, TMCC, etc., and averages the error of each carrier symbol to calculate the average error. The error of the carrier symbol means the distance between the signal point of the carrier symbol and the specified signal point after the hardness determination of the carrier symbol. In C / N estimation, there are a method using data symbols, a method using AC and TMCC, a method using SP, and a method combining these methods, but these are known techniques and are described in detail here. Omit the explanation.

The C / N estimation circuit 44 estimates the received C / N of the entire signal from, for example, the average error, and estimates the received C / N for each carrier symbol (for each carrier) from the error for each carrier symbol and the transmission path response. .. After estimating the reception C / N of the entire signal, the C / N estimation circuit 44 estimates the reception C / N of the entire signal and then receives the reception C / N of each carrier symbol from the estimated value of the reception C / N of the entire signal and the transmission path response of each carrier symbol. N may be estimated. The same applies to the C / N estimation circuit 74 described later.

The symbol reproduction circuit 45 inputs a data symbol from the symbol separation circuit 43, and also inputs the reception C / N of the entire signal or the reception C / N for each carrier from the C / N estimation circuit 44 as reception C / N information. Then, the symbol reproduction circuit 45 performs the symbol determination process of the error residual type remapping based on the data symbol and the received C / N information, and reproduces the symbol.

Here, the symbol reproduction circuit 45 sets the optimum suppression coefficient γ according to the received C / N information when performing error suppression type remapping as the symbol determination processing of error residual type remapping. Further, when performing error clip type remapping as a symbol determination process of error residual type remapping, the symbol reproduction circuit 45 sets an optimum clip value according to the received C / N information. The details of the symbol reproduction circuit 45 will be described later.

The AC and TMCC hard determination circuit 46 performs symbol hard determination processing on signals of AC and TMCC and the like (AC and TMCC and the like which are DBPSK modulated in the symbol direction) separated by the symbol separation circuit 43 to remove noise components. do. The SP generation circuit 47 generates SP.

The frame configuration circuit 48 uses data symbols reproduced by the symbol reproduction circuit 45, signals such as AC and TMCC processed by the AC and TMCC rigidity determination circuit 46, and SP generated by the SP generation circuit 47. input. Then, the frame configuration circuit 48 constitutes an OFDM symbol from these data symbols, signals such as AC and TMCC, and SP, and further constitutes an OFDM frame.

The IFFT circuit 49 performs inverse fast Fourier transform on the carrier symbol for each OFDM symbol configured by the frame configuration circuit 48, and generates an OFDM signal in the time domain for the effective symbol period.

The GI addition circuit 50 copies a part of the trailing edge of the valid symbol period from the OFDM signal in the time domain for the valid symbol period generated by the IFFT circuit 49, and adds it as a GI to the leading edge of the valid symbol period.

The upsampling circuit 51 performs upsampling processing on the OFDM signal (equivalent baseband signal, IQ signal) to which the GI is added by the GI addition circuit 50 to increase the sampling speed (for example, increase it 16 times).

The QMOD 53 performs quadrature modulation processing of the IQ signal format OFDM signal upsampled by the upsampling circuit 51 using the local signal supplied from the NCO 52, and converts it into a digital IF signal. For example, the QMOD 53 multiplies the OFDM signal by a local signal having a frequency of 37.15 MHz to generate and output a digital IF signal having a center frequency of 37.15 MHz.

The D / A converter 54 inputs the digital IF signal output from the QMOD 53 and converts it into an analog IF signal. The amplifier 55 inputs an analog IF signal from the D / A converter 54 and amplifies it to a predetermined level. The output BPF 56 removes unnecessary out-of-band components from the IF signal amplified by the amplifier 55, and outputs the IF signal as an IF signal after error residual type remapping to the transmission unit 14.

[Equalization judgment device 23 / MIMO type]
Next, the MIMO-type equalization determination device 23 shown in FIG. 18 will be described in detail. FIG. 20 is a block diagram showing a configuration example of the MIMO type equalization determination device 23. The equalization determination device 23 includes inputs BPF60-1,60-2, amplifiers 61-1 and 61-2, A / D converters 62-1 and 62-2, NCO63, QDEM64-1, 64-2, and down. Sample circuit 65-1, 65-2, synchronous playback circuit 66, AFC circuit 67-1, 67-2, FFT window circuit 68-1, 68-2, FFT circuit 69-1, 69-2, SP extraction circuit 70 -1,70-2, transmission line response estimation circuit 71, MIMO detector 72, symbol separation circuit 73-1,73-2, C / N estimation circuit 74, symbol reproduction circuit 75-1,75-2, AC and TMCC rigid determination circuit 76-1,76-2, SP generation circuit 77-1,77-2, frame configuration circuit 78-1,78-2, IFFT circuit 79-1,79-2, GI addition circuit 80-1 , 80-2, Upsample Circuits 81-1, 81-2, NCO82, QMOD83-1,83-2, D / A Converters 84-1, 84-2, Amplifiers 85-1, 85-2 and Output BPF86 It is equipped with -1,86-2.

As described above, the equalization determination device 23 equalizes the transmission line response distortion included in the IF signal input from the receivers 22-1, 22-2, and reduces the noise component by the symbol determination process of the error residual type remapping. Alternatively, it is removed, and interference between each system and cancellation and removal of interference components are also performed. Then, the equalization determination device 23 outputs the IF signal after the error residual type remapping to the transmission units 24-1 and 24-2.

The configuration of the equalization determination device 23 shown in FIG. 20 is similar to the one in which two systems of the SISO type equalization determination device 13 shown in FIG. 19 are arranged, but some of them are completely arranged in two systems. There is a difference in the composition of. Hereinafter, the differences will be mainly described.

The input BPF60-1 inputs an IF signal from the receiving unit 22-1, and the input BPF60-2 inputs an IF signal from the receiving unit 22-2. The configuration from the input BPF 60-1 and 60-2 to the SP extraction circuits 70-1 and 70-2 is a configuration in which two configurations from the input BPF 30 to the SP extraction circuit 40 shown in FIG. 19 are arranged side by side.

The NCO 63 is a component common to both systems, and supplies a common local signal to the QDEM64-1 and 64-2, respectively. The synchronous reproduction circuit 66 is also a component common to both systems, and performs synchronous reproduction processing based on the respective IQ signals thinned out by the downsample circuits 65-1 and 65-2 to reproduce the synchronous signal. Then, the synchronous reproduction circuit 66 supplies a common synchronous signal to the AFC circuits 67-1 and 67-2 and the FFT window circuits 68-1 and 68-2. Further, although not specified in FIG. 20, the synchronous reproduction circuit 66 supplies the reproduced synchronous signal to each part that requires the synchronous signal.

The NCO 63 and the synchronous reproduction circuit 66 may be made into a component for each system without being shared by both systems. Further, the AFC circuits 67-1 and 67-2 operate independently for each system because there is a possibility that a frequency deviation may occur between the two systems in the frequency conversion process on the transmitting side and the receiving side. In the FFT window circuits 68-1 and 68-2, there is a possibility that a slight delay time difference may occur between the two systems due to the difference in the group delay characteristics or propagation path characteristics of the transmitting side and the receiving side, so the timing of the FFT window is also the system. Set separately for each.

The transmission line response estimation circuit 71 corresponds to the transmission line response estimation circuit 41 shown in FIG. 19, and is used for each carrier symbol of the OFDM signal from the SP of each system extracted by the SP extraction circuits 70-1 and 70-2. Calculate the four components of the MIMO channel response matrix. Then, the transmission line response estimation circuit 71 outputs the four components of the MIMO transmission line response matrix for each carrier symbol to the MIMO detector 72 and the C / N estimation circuit 74. In FIG. 20, the eight signal lines from the transmission line response estimation circuit 71 to the MIMO detector 72 and the C / N estimation circuit 74 indicate that each of the four components is a complex number.

The MIMO detector 72 corresponds to the equalization circuit 42 shown in FIG. 19, and the carrier symbols of each system are input from the FFT circuits 69-1 and 69-2, and each carrier symbol is input from the transmission line response estimation circuit 71. Input the four components of the MIMO channel response matrix. The MIMO detector 72 performs system separation and equalization of each system by division processing (in other words, inverse matrix multiplication processing) by a carrier symbol of each system and a 2 × 2 MIMO transmission line response matrix composed of four components. Realize processing at the same time.

In the configuration from the symbol separation circuits 73-1 and 73-2 to the output BPF86-1 and 86-2 in the subsequent stage of the MIMO detector 72, the configurations from the symbol separation circuit 43 to the output BPF56 shown in FIG. 19 are arranged in two systems. It has become a symbol. The NCO 82 is a component common to both systems, and supplies a common local signal to the QMOD 83-1 and 83-2, respectively, to synchronize the frequencies of the signals of both systems.

The C / N estimation circuit 74 corresponds to the C / N estimation circuit 44 shown in FIG. 19, and data symbols, AC, TMCC, etc. of each system are input and transmitted from the symbol separation circuits 73-1 and 73-2. The four components of the MIMO transmission line response matrix for each carrier symbol are input from the road response estimation circuit 71. Then, the C / N estimation circuit 74 estimates the reception C / N of the entire signal for each system, and also estimates the reception C / N for each carrier symbol (each carrier).

The C / N estimation circuit 74 uses the reception C / N of the entire signal in the first system or the reception C / N of each carrier symbol (each carrier) as the reception C / N information of the first system as the symbol reproduction circuit 75. Output to -1. Further, the C / N estimation circuit 74 symbolizes the reception C / N of the entire signal in the second system or the reception C / N for each carrier symbol (for each carrier) as the reception C / N information of the second system. Output to circuit 75-2.

The symbol reproduction circuits 75-1 and 75-2 correspond to the symbol reproduction circuit 45 shown in FIG. 19, and the data symbols of the corresponding systems are input from the symbol separation circuits 73-1 and 73-2, and the C / N is input. The reception C / N information of the corresponding system is input from the estimation circuit 74. Then, the symbol reproduction circuits 75-1 and 75-2 perform the symbol determination process of the error residual type remapping based on the data symbol and the received C / N information, and reproduce the symbol.

Here, the symbol reproduction circuits 75-1 and 75-2, similarly to the symbol reproduction circuit 45 shown in FIG. 19, receive C / when performing error suppression type remapping as a symbol determination process of error residual type remapping. The optimum suppression coefficient γ is set according to the N information. Further, the symbol reproduction circuits 75-1 and 75-2, similarly to the symbol reproduction circuit 45 shown in FIG. 19, receive C / N when performing error clip type remapping as a symbol determination process of error residual type remapping. Set the optimum clip value according to the information. Details of the symbol reproduction circuits 75-1 and 75-2 will be described later.

[Symbol reproduction circuits 45, 75 that perform error-suppressing remapping]
Next, details of the case where the symbol reproduction circuit 45 shown in FIG. 19 and the symbol reproduction circuits 75-1 and 75-2 (collectively referred to as the symbol reproduction circuit 75) shown in FIG. 20 perform error suppression type remapping are described in detail. Explain to.

FIG. 21 is a block diagram showing a configuration example of the symbol reproduction circuits 45 and 75 that perform error suppression type remapping. The symbol reproduction circuits 45 and 75 include a suppression coefficient generation circuit 90, delay circuits 91 and 95, a nearest neighbor point detection circuit 92, a subtraction circuit 93, a multiplication circuit 94, and an addition circuit 96. The generation circuit that generates the carrier symbol after reproduction by the error suppression type remapping by the suppression coefficient generation circuit 90, the delay circuits 91 and 95, the nearest neighbor point detection circuit 92, the subtraction circuit 93, the multiplication circuit 94 and the addition circuit 96. It is composed.

The SISO type symbol reproduction circuit 45 inputs a carrier symbol (data symbol) from the symbol separation circuit 43 via the equalization circuit 42 and distributes the two. Further, the MIMO type symbol reproduction circuit 75 (75-1 and 75-2 of the symbol reproduction circuit) inputs a carrier symbol (data symbol) from the symbol separation circuits 73-1 and 73-2 via the MIMO detector 72. And divide it into two. The two-distributed carrier symbols are complex signals of IQ axis components, one is input to the delay circuit 91 and the other is input to the nearest emphasis mark detection circuit 92.

Further, the SISO type symbol reproduction circuit 45 inputs the received C / N information from the C / N estimation circuit 44, and the MIMO type symbol reproduction circuit 75 inputs the received C / N information from the C / N estimation circuit 74. do. The received C / N information is input to the suppression coefficient generation circuit 90.

The suppression coefficient generation circuit 90 can be realized by a ROM table, a polynomial approximation calculation circuit, or the like. For example, the suppression coefficient generation circuit 90 generates the suppression coefficient γ by reading the suppression coefficient γ corresponding to the reception C / N for each carrier symbol included in the input reception C / N information from a preset table. do. The suppression coefficient γ is input to the multiplication circuit 94.

As described with reference to FIGS. 7 to 9, by selecting the optimum suppression amount (suppression amount that minimizes the area reception required C / N) according to the reception C / N (relay station reception C / N), The required C / N can be improved. The preset table defines the relationship between the reception C / N and the suppression coefficient γ, and stores the optimum suppression coefficient γ for each reception C / N obtained by simulation or the like.

For example, in the table, the suppression coefficient γ decreases so that the reception C / N and the suppression coefficient γ are inversely proportional to each other, that is, as the reception C / N increases (the suppression coefficient C becomes closer to the specified signal point B). (Assuming γ), the suppression coefficient γ increases as the reception C / N decreases (so that the remapping point C becomes the suppression coefficient γ that is closer to the reception signal point A away from the specified signal point B). The suppression coefficient γ corresponding to / N is stored. As described above, the smaller the suppression coefficient γ, the closer the remapping point C is to the specified signal point B, and the larger the suppression coefficient γ, the farther the remapping point C is from the specified signal point B and the closer to the receiving signal point A.

Further, the suppression coefficient generation circuit 90 may calculate the suppression coefficient γ corresponding to the received C / N for each carrier symbol by using a predetermined mathematical formula instead of using the table. Similar to the table, the predetermined formula defines the relationship between the reception C / N and the suppression coefficient γ, and is defined so that the optimum suppression coefficient γ corresponds to each reception C / N.

The delay circuit 91 is a circuit for compensating for the delay in the nearest neighbor point detection circuit 92, and delays the input carrier symbol by the same amount of delay as the nearest neighbor point detection circuit 92. The delayed carrier symbol is input to the subtraction circuit 93. The nearest neighbor point detection circuit 92 detects a specified signal point on the constellation having the shortest distance between signal points in the signal space with respect to the input carrier symbol, and outputs the carrier symbol of the detected specified signal point. The carrier symbol of the specified signal point is divided into two, one is input to the subtraction circuit 93 and the other is input to the delay circuit 95.

The subtraction circuit 93 subtracts the carrier symbol of the specified signal point detected by the nearest neighbor point detection circuit 92 from the carrier symbol (carrier symbol including an error due to noise or distortion) delayed by the delay circuit 91, and obtains an error signal. To generate. The error signal is input to the multiplication circuit 94.

The multiplication circuit 94 multiplies the error signal generated by the subtraction circuit 93 by the suppression coefficient γ generated by the suppression coefficient generation circuit 90. The error signal after multiplication by the suppression coefficient is a signal whose error is smaller than that of the error signal generated by the subtraction circuit 93, and is input to the addition circuit 96. The delay circuit 95 is a circuit for compensating for the delay in the subtraction circuit 93 and the multiplication circuit 94, and delays the carrier symbol of the input specified signal point by the same delay amount as the subtraction circuit 93 and the multiplication circuit 94. The carrier symbol of the delayed specified signal point is input to the adder circuit 96.

The addition circuit 96 adds the error signal after multiplication of the suppression coefficient input from the multiplication circuit 94 and the carrier symbol of the nearest specified signal point input from the delay circuit 95, and outputs the addition result as the carrier symbol after reproduction. do. The carrier symbol after reproduction is input to the frame constituent circuits 48, 78-1, 78-2.

[Symbol reproduction circuits 45, 75 that perform error clip type remapping]
Next, a case where the symbol reproduction circuit 45 shown in FIG. 19 and the symbol reproduction circuit 75 shown in FIG. 20 perform error clip type remapping will be described in detail.

FIG. 22 is a block diagram showing a configuration example of the symbol reproduction circuits 45 and 75 that perform error clip type remapping. The symbol reproduction circuits 45 and 75 include a clip value generation circuit 100, a delay circuit 101, 102, 104, 109, 110, 111, a nearest neighbor point detection circuit 103, a subtraction circuit 105, an absolute value calculation circuit 106, a division circuit 107, and a comparison. It includes a circuit 108, a multiplication circuit 112, an addition circuit 113, and a selection circuit 114. Each of the circuits 100 to 114 constitutes a generation circuit that generates a carrier symbol after reproduction by error clip type remapping.

The SISO type symbol reproduction circuit 45 inputs a carrier symbol (data symbol) from the symbol separation circuit 43 via the equalization circuit 42 and distributes the three. Further, the MIMO type symbol reproduction circuit 75 (75-1 and 75-2 of the symbol reproduction circuit) inputs a carrier symbol (data symbol) from the symbol separation circuits 73-1 and 73-2 via the MIMO detector 72. And distribute to 3. The three-distributed carrier symbols are complex signals of IQ axis components, which are input to the delay circuits 102 and 104 and the nearest emphasis mark detection circuit 103, respectively.

Further, the SISO type symbol reproduction circuit 45 inputs the received C / N information from the C / N estimation circuit 44, and the MIMO type symbol reproduction circuit 75 inputs the received C / N information from the C / N estimation circuit 74. do. The received C / N information is input to the clip value generation circuit 100.

The clip value generation circuit 100 can be realized by a ROM table, a polynomial approximation calculation circuit, or the like. For example, the clip value generation circuit 100 generates a clip value by reading the clip value corresponding to the received C / N for each carrier symbol included in the input received C / N information from a preset table. The clip value is input to the delay circuit 101.

As described with reference to FIGS. 10 and 11, by selecting the optimum clip level (the clip level at which the area reception required C / N is the lowest) according to the reception C / N (relay station reception C / N), The required C / N can be improved. The preset table defines the relationship between the received C / N and the clip value, and stores the optimum clip value for each received C / N obtained by simulation or the like.

For example, in the table, the clip value becomes smaller as the reception C / N and the clip value are inversely proportional to each other, that is, as the reception C / N becomes higher (assuming that the remapping point C becomes a clip value closer to the specified signal point B). , The clip value corresponding to the reception C / N is stored so that the clip value increases as the reception C / N decreases (so that the remapping point C is a clip value away from the specified signal point B). As described above, the smaller the clip value, the closer the remapping point C is to the specified signal point B, and the larger the clip value, the farther the remapping point C is from the specified signal point B.

Further, the clip value generation circuit 100 may calculate the clip value corresponding to the received C / N for each carrier symbol by using a predetermined mathematical formula instead of using the table. Similar to the table, the predetermined formula defines the relationship between the received C / N and the clip value, and is defined so that the optimum clip value corresponds to each received C / N.

The delay circuit 101 is a circuit for compensating for the delay in the delay circuit 102, the subtraction circuit 105, and the absolute value calculation circuit 106, and delays the input clip value by the same delay amount as the total delay amount of these circuits. .. The delayed clip value is divided into two, one is input to the division circuit 107 and the other is input to the comparison circuit 108.

The delay circuit 102 is a circuit for compensating for the delay in the nearest neighbor point detection circuit 103, and delays the input carrier symbol by the same delay amount as that of the nearest neighbor point detection circuit 103. The delayed carrier symbol is input to the subtraction circuit 105.

The nearest neighbor point detection circuit 103 detects a specified signal point on the constellation having the shortest distance between signal points in the signal space with respect to the input carrier symbol, and outputs the carrier symbol of the detected specified signal point. The carrier symbol of the specified signal point is divided into two, one is input to the subtraction circuit 105 and the other is input to the delay circuit 111.

The delay circuit 104 is a circuit for compensating for the delays of the delay circuit 102, the subtraction circuit 105, the delay circuit 110, the multiplication circuit 112, and the addition circuit 113, and the input carrier symbol is combined with the sum of the delay amounts of these circuits. Delay by the same amount of delay. The delayed carrier symbol is input to the selection circuit 114.

The subtraction circuit 105 subtracts the carrier symbol of the specified signal point detected by the nearest neighbor point detection circuit 103 from the carrier symbol (carrier symbol including an error due to noise or distortion) delayed by the delay circuit 102, and obtains an error signal. To generate. The error signal is divided into two, one is input to the absolute value calculation circuit 106, and the other is input to the delay circuit 110.

The absolute value calculation circuit 106 calculates the absolute value of the error signal generated by the subtraction circuit 105. The absolute value of the error signal is divided into two, one is input to the division circuit 107 and the other is input to the comparison circuit 108.

The division circuit 107 divides the clip value delayed by the delay circuit 101 by the absolute value of the error signal calculated by the absolute value calculation circuit 106, and generates the division result as a coefficient signal. The coefficient signal is input to the multiplication circuit 112.

The comparison circuit 108 compares the clip value delayed by the delay circuit 101 with the absolute value of the error signal calculated by the absolute value calculation circuit 106. The comparison circuit 108 sets “1” as the comparison result when the clip value is larger than the absolute value of the error signal, and sets “0” as the comparison result when the clip value is equal to or less than the absolute value of the error signal. do. The comparison result is input to the delay circuit 109.

In the delay circuit 109, the total delay amount of the absolute value calculation circuit 106, the comparison circuit 108, and the delay circuit 109 is the same as the total delay amount of the delay circuit 110, the multiplication circuit 112, and the addition circuit 113. Set the delay amount. Then, the delay circuit 109 delays the comparison result input from the comparison circuit 108 by a set delay amount. The delayed comparison result is input to the selection circuit 114.

When the total delay amount of the absolute value calculation circuit 106 and the comparison circuit 108 is larger than the total delay amount of the delay circuit 110, the multiplication circuit 112, and the addition circuit 113, the delay circuit 109 is referred to as the addition circuit 113. It may be arranged between the selection circuit 114 and the selection circuit 114. In this case, the comparison result set by the comparison circuit 108 is directly input to the selection circuit 114.

The delay circuit 110 is a circuit for compensating for the delays of the absolute value calculation circuit 106 and the division circuit 107, and delays the input error signal by the same delay amount as the total delay amount of these circuits. The delayed error signal is input to the multiplication circuit 112.

The delay circuit 111 is a circuit for compensating for the delays of the subtraction circuit 105, the delay circuit 110, and the multiplication circuit 112, and the carrier symbol of the input specified signal point is set to the same delay amount as the total delay amount of these circuits. Delay. The carrier symbol of the delayed specified signal point is input to the adder circuit 113.

The multiplication circuit 112 multiplies the error signal delayed by the delay circuit 110 by the coefficient signal generated by the division circuit 107. The phase of the multiplication result is the same as the phase of the error signal generated by the subtraction circuit 105, and the absolute value of the multiplication result is the same as the clip value. The multiplication result is an error signal having such a phase and an absolute value and having an error smaller than that of the error signal generated by the subtraction circuit 105. The error signal of the multiplication result is input to the addition circuit 113.

Here, as for the error signal of the multiplication result input to the addition circuit 113, the absolute value of the error signal is generated by the clip value generation circuit 100 without changing the phase of the error signal generated by the subtraction circuit 105. It is a signal clipped to the clip value. In the symbol reproduction circuits 45 and 75, it is assumed that the delay circuits 101 and 110, the absolute value calculation circuit 106, the division circuit 107, and the multiplication circuit 112 constitute an absolute value clip circuit. The absolute value clip circuit clips the absolute value of the error signal to the clip value generated by the clip value generation circuit 100 without changing the phase of the error signal generated by the subtraction circuit 105. The signal obtained by clipping the absolute value of the error signal to the clip value corresponds to the error signal of the multiplication result generated by the multiplication circuit 112, and is input to the addition circuit 113.

The addition circuit 113 adds the error signal of the multiplication result input from the multiplication circuit 112 and the carrier symbol of the specified signal point delayed by the delay circuit 111. The addition result is a carrier symbol in which the absolute value of the error is clipped to the clip value. The carrier symbol clipped to the clip value is input to the selection circuit 114.

The selection circuit 114 inputs the carrier symbol delayed from the delay circuit 104, inputs the carrier symbol whose absolute error value is clipped to the clip value from the addition circuit 113, and inputs the comparison result from the delay circuit 109.

The selection circuit 114 has a reception signal when the comparison result is “1”, that is, when the clip value is larger than the absolute value of the error signal (the error between the carrier symbol and the carrier symbol of the specified signal point) (in FIG. 3, FIG. When the point is A2), the carrier symbol input from the delay circuit 104 is selected. Further, the selection circuit 114 has an error input from the addition circuit 113 when the comparison result is "0", that is, when the clip value is equal to or less than the absolute value of the error signal (when the reception signal point is A1 in FIG. 3). Select a carrier symbol whose absolute value of is clipped to the clip value.

The selection circuit 114 selects the carrier symbol input to the symbol reproduction circuits 45 and 75 or the carrier symbol obtained by clipping the error of the carrier symbol to the clip value according to the comparison result of the comparison circuit 108, and after the symbol reproduction, the selection circuit 114 selects the carrier symbol. Output as a carrier symbol. The carrier symbol after symbol reproduction is input to the frame constituent circuits 48, 78-1, 78-2.

As described above, according to the symbol reproduction circuits 45 and 75 of the embodiment of the present invention, when the received signal is symbol-determined and remapped, the received signal is at a point that completely coincides with the specified signal point as in the rigid determination. Instead of remapping, the error (distance) between the received signal point and the specified signal point is reduced, and the error is remapped so as to remain to some extent.

Specifically, according to the symbol reproduction circuits 45 and 75 that perform the error suppression type remapping shown in FIG. 21, the suppression coefficient generation circuit 90 uses a predetermined table or mathematical formula based on the received C / N information. The optimum suppression coefficient γ (suppression coefficient γ that minimizes the area reception required C / N) is generated according to the reception C / N. The nearest neighbor point detection circuit 92 detects a specified signal point closest to the signal point of the receiving carrier symbol, and the subtraction circuit 93 subtracts the carrier symbol of the specified signal point from the carrier symbol of the received signal point to obtain an error signal. To generate.

The multiplication circuit 94 multiplies the error signal by the suppression coefficient γ, and the addition circuit 96 adds the error signal after multiplication of the suppression coefficient and the carrier symbol of the specified signal point, and outputs the addition result as the carrier symbol after reproduction. ..

Further, according to the symbol reproduction circuits 45 and 75 that perform the error clip type remapping shown in FIG. 22, the clip value generation circuit 100 receives the reception C using a predetermined table or mathematical formula based on the reception C / N information. The optimum clip value according to / N (the clip value at which the area reception required C / N is the lowest) is generated. Then, the nearest nearest point detection circuit 103 detects the specified signal point closest to the signal point of the receiving carrier symbol, and the subtraction circuit 105 subtracts the carrier symbol of the specified signal point from the carrier symbol of the received signal point. Generate an error signal. The division circuit 107 divides the clip value by the absolute value of the error signal to generate a coefficient signal.

The multiplication circuit 112 multiplies the error signal by the coefficient signal, and the addition circuit 113 adds the error signal after multiplying the coefficient signal and the carrier symbol of the specified signal point, and the absolute value of the error is clipped to the clip value. Generate a carrier symbol.

When the clip value is larger than the absolute value of the error signal, the selection circuit 114 selects the carrier symbol of the reception signal point and outputs this as the carrier symbol after reproduction. Further, when the clip value is equal to or less than the absolute value of the error signal, the selection circuit 114 selects a carrier symbol whose absolute value of error is clipped to the clip value, and outputs this as a carrier symbol after reproduction.

As a result, an error remains in the carrier symbol after reproduction so that the area reception required C / N is the lowest. Then, for example, when the relay station 202 shown in FIG. 1 includes the symbol reproduction circuit 45 or 75, the influence of noise included in the relay station reception signal is added to the likelihood information of the LDPC decoding process of the receiver 204 in the area reception. Will also be partially reflected. The receiver 204 relays the likelihood information reflecting the influence of the noise of the relay station reception signal and the noise in the area reception to the likelihood information by performing the LDPC code decoding process using the Sum-Product algorithm. The correction capability can be improved as compared with the case where the influence of noise contained in the station reception signal is not reflected at all.

Therefore, it is possible to prevent the required C / N in area reception from deteriorating, and it is possible to improve the transmission characteristics of the receiver 204.

Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical idea. In the above embodiment, the symbol reproduction circuits 45 and 75 are provided in the relay devices 1 and 2, but may be provided in a communication device other than the relay devices 1 and 2.

Further, the suppression coefficient generation circuit 90 of the symbol reproduction circuits 45 and 75 uses a preset table or mathematical formula to obtain a suppression coefficient γ corresponding to the reception C / N for each carrier symbol included in the reception C / N information. I tried to generate it. On the other hand, the suppression coefficient generation circuit 90 may generate the suppression coefficient γ corresponding to the reception C / N of the entire signal.

Further, the clip value generation circuit 100 of the symbol reproduction circuits 45 and 75 generates a clip value corresponding to the reception C / N for each carrier symbol included in the reception C / N information by using a preset table or mathematical formula. I tried to do it. On the other hand, the clip value generation circuit 100 may generate a clip value corresponding to the reception C / N of the entire signal. In the suppression coefficient generation circuit 90 and the clip value generation circuit 100, the optimum suppression coefficient γ corresponds to the reception C / N for each carrier symbol or the reception C / N for the entire signal to the preset table or mathematical formula. Stored or defined to do so.

In this case, the C / N estimation circuits 44 and 74 are signals used in the suppression coefficient generation circuit 90 or the clip value generation circuit 100 from the error of the control symbol such as TMCC and the pilot symbol such as SP, CP and AC. Estimate the overall received C / N. Further, the C / N estimation circuits 44 and 74 may estimate the reception C / N of the entire signal used in the suppression coefficient generation circuit 90 or the clip value generation circuit 100 from the error of the data symbol. The present invention does not limit the estimation process of the received C / N by the C / N estimation circuits 44 and 74 to the above process, and other processes can be applied. In short, the suppression coefficient γ and the clip value are generated according to the reception C / N for each carrier symbol or the reception C / N for the entire signal.

Further, in the above embodiment, the receiver 204 performs the LDPC code decoding process using the Sum-Product algorithm on the likelihood information of the received signal reflecting the influence of noise. The present invention does not limit the decoding process by the receiver 204 to the decoding process of the LDPC code using the Sum-Product algorithm, and other processes can be applied. In short, the present invention is applicable when the receiver 204 performs a decoding process using the likelihood information of the received signal.

Further, in the above-described embodiment, as shown in FIGS. 17 and 18, as a transmission signal, an example of an OFDM signal that performs multi-carrier transmission has been described. The present invention does not limit the transmission signal to an OFDM signal, but is also applicable to a signal for single carrier transmission.

1,2 Relay device 10,20 Receiving antenna 11,21 Receiving BPF
12, 22 Receiving unit 13, 23 Equalization judgment device 14, 24 Transmission unit 15, 25 PA unit 16, 26 Transmission BPF
17,27 Transmit antenna 30,60 Input BPF
31,55,61,85 Amplifier 32,62 A / D converter 33,63,52,82 NCO (Numerical Control Oscillator)
34,64 QDEM (Orthogonal Demodulation Circuit)
35,65 Downsample (DS) circuit 36,66 Synchronous playback circuit 37,67 AFC circuit 38,68 FFT window circuit 39,69 FFT circuit 40,70 SP extraction circuit 41,71 Transmission path response estimation circuit 42 Equalization circuit 43 , 73 Symbol separation circuit 44,74 C / N estimation circuit 45,75 Symbol reproduction circuit 46,76 AC and TMCC rigid determination circuit 47,77 SP generation circuit 48,78 Frame configuration circuit 49,79 Fourier circuit 50,80 GI addition Circuits 51,81 Upsample (US) Circuits 53,83 QMOD (Quadrature Modulation Circuit)
54,84 D / A converter 56,86 Output BPF
72 MIMO detector 90 Suppression coefficient generation circuit 91, 95, 101, 102, 104, 109, 110, 111 Delay circuit 92 Nearest point detection circuit 93, 105 Subtraction circuit 94, 112 Multiplication circuit 96, 113 Addition circuit 100 Clip value generation Circuit 103 Nearest point detection circuit 106 Absolute value calculation circuit 107 Dividing circuit 108 Comparison circuit 114 Selection circuit 200 Master station (transmitter)
201, 203 Transmission line 202 Relay station (relay device)
204 receiver

Claims (8)

In a symbol reproduction circuit that reproduces the symbol of the received signal
A nearest neighbor point detection circuit that detects a specified signal point closest to the symbol of the received signal, and
A subtraction circuit for obtaining an error by subtracting the symbol of the specified signal point detected by the nearest neighbor point detection circuit from the symbol of the received signal.
A generation circuit that generates a new symbol in place of the symbol of the received signal and outputs the new symbol as a symbol after reproduction so that the error obtained by the subtraction circuit is reduced and remains.
A symbol reproduction circuit characterized by being equipped with. In the symbol reproduction circuit according to claim 1,
The generation circuit includes a multiplication circuit and an addition circuit.
The multiplication circuit
The error of the multiplication result is obtained by multiplying the error by a preset suppression coefficient so that the error obtained by the subtraction circuit is reduced and remains.
The adder circuit
The error of the multiplication result obtained by the multiplication circuit is added to the symbol of the specified signal point detected by the nearest neighbor point detection circuit to generate the new symbol in place of the symbol of the received signal, and the new symbol is generated. A symbol reproduction circuit, characterized in that a symbol is output as a symbol after reproduction. In the symbol reproduction circuit according to claim 1,
The generation circuit includes an absolute value clip circuit, an adder circuit, and a selection circuit.
The absolute value clip circuit is
The absolute value of the error is clipped to a preset clip value without changing the phase of the error obtained by the subtraction circuit.
The adder circuit
The symbol of the specified signal point detected by the nearest neighbor point detection circuit is added to the error clipped to the clip value by the absolute value clip circuit to generate a symbol in which the error is clipped to the clip value.
The selection circuit
When the absolute value of the error obtained from the subtraction circuit is smaller than the clip value, the symbol of the received signal is output as the symbol after reproduction, and the absolute value of the error obtained from the subtraction circuit is calculated. A symbol reproduction circuit characterized in that, when it is larger than the clip value, the error generated by the addition circuit outputs a symbol clipped to the clip value as a symbol after reproduction. In the symbol reproduction circuit according to claim 2,
The generation circuit further includes a suppression coefficient generation circuit.
The suppression coefficient generation circuit is
Using a predetermined table or mathematical formula that defines the relationship between the received C / N and the suppression coefficient, the suppression coefficient corresponding to the reception C / N of the received signal is generated.
The multiplication circuit
A symbol reproduction circuit characterized in that the suppression coefficient generated by the suppression coefficient generation circuit is multiplied by the error to obtain the error of the multiplication result so that the error obtained by the subtraction circuit is reduced and remains. .. In the symbol reproduction circuit according to claim 4,
When the symbol reproduction circuit reproduces the carrier symbol of the received OFDM signal,
The suppression coefficient generation circuit is
Using the predetermined table or mathematical formula, a suppression coefficient corresponding to the total received C / N in the received OFDM signal or the received C / N for each carrier symbol is generated.
A symbol reproduction circuit characterized in that a value calculated based on a control symbol, a pilot symbol, or a data symbol included in the received OFDM signal is used as the reception C / N. In the symbol reproduction circuit according to claim 3,
The generation circuit further includes a clip value generation circuit.
The clip value generation circuit is
Using a predetermined table or mathematical formula that defines the relationship between the received C / N and the clip value, a clip value corresponding to the received C / N of the received signal is generated.
The absolute value clip circuit is
The absolute value of the error is clipped to the clip value generated by the clip value generation circuit without changing the phase of the error obtained by the subtraction circuit, and the absolute value of the error is clipped to the clip value. A symbol reproduction circuit characterized by generating an error signal. In the symbol reproduction circuit according to claim 6,
When the symbol reproduction circuit reproduces the carrier symbol of the received OFDM signal,
The clip value generation circuit is
Using the predetermined table or mathematical formula, a clip value corresponding to the entire received C / N in the received OFDM signal or the received C / N for each carrier symbol is generated.
A symbol reproduction circuit characterized in that a value calculated based on a control symbol, a pilot symbol, or a data symbol included in the received OFDM signal is used as the reception C / N. A relay device including the symbol reproduction circuit according to any one of claims 1 to 7.

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