JP6900759B2 - Power conversion circuit control device - Google Patents

Description

The present invention relates to a control device of a power conversion circuit in which two multi-level inverters having three or more levels having a neutral point potential are connected in a BTB (back to back) configuration, and particularly suppresses the pulsation of the neutral point potential. Regarding technology.

As a configuration example of the power conversion circuit, a three-level inverter that outputs a three-level phase voltage as shown in FIG. 10A has been conventionally known. Each phase voltage is generated by the ON / OFF operation of the switching elements T1 to T4 in the inverter. Examples of the type of the three-level inverter include the NPC type shown in FIG. 10 (a) and the T type shown in FIG. 10 (b). Further, C1 and C2 in FIGS. 10A and 10B are first and second DC capacitors for smoothing the DC voltages Vdc1 and Vdc2.

In such an inverter, it is important to suppress fluctuations in the potential of the neutral point NP, which is the connection point of the first and second DC capacitors C1 and C2, and maintain the DC voltage Vdc1 = Vdc2. It is known that the potential of the neutral point NP (hereinafter referred to as the neutral point potential) pulsates at a frequency three times the AC output voltage when AC power is output from the inverter, and pulsates especially when the ineffective power is output. Becomes larger.

Patent Document 1 describes a technique for suppressing this pulsation by superimposing a third harmonic on the zero phase of the output voltage. The amplitude of the pulsation is represented by the mathematical formula 11 of Patent Document 1. It is maximum at the time of invalid power output (φ = 90 deg), but it is shown that two-thirds of the pulsation at the time of invalid power output occurs even at the time of active power output (φ = 0 deg or 180 deg).

FIG. 7 of Patent Document 1 describes a zero-phase third harmonic to be superimposed on the output voltage required for suppressing pulsation. The phase of the third harmonic at the time of reactive power output (φ = 90 deg) is β = 30 deg or -30 deg, and the phase of the third harmonic at the time of active power output (φ = 0 deg or 180 deg) is β = 0 deg.

Further, as shown in FIG. 7 of Patent Document 1, the ratio of the third harmonic to be superposed (superimposition rate k) to the fundamental wave amplitude (peak height value γ) of the voltage command value is the ratio of the third harmonic to be superposed when the reactive power is output (φ = 90 deg). ), Which is a very large value and cannot be realized, but at the time of active power output (φ = 0 deg or 180 deg), k ≈ 0.25.

Zero-phase modulation is a technique for superimposing a third-order zero-phase voltage on the output voltage. This is a technique for lowering the amplitude of the output voltage command value and increasing the fundamental wave component of the output voltage without increasing the DC voltage, as described in Patent Document 2.

FIG. 11 is an arithmetic block that realizes “the absolute value of the maximum value and the minimum value in the voltage command value of each phase is always equal” in claim 1 of Patent Document 2. As shown in FIG. 11, the maximum value and the minimum value are extracted from the three-phase voltage command values Vu *'and Vv *'Vw *', and the average value of the maximum value and the minimum value is calculated. The technique of Patent Document 2 can be realized by subtracting this average value from the three-phase voltage command values Vu *', Vv *', and Vw *'.

At this time, the phase of the third harmonic component of the waveform superimposed on the three-phase voltage command values Vu *', Vv *', and Vw *'is β = 0 deg. That is, if the power factor of the electric power output from the inverter is high to some extent, the pulsation of the neutral point potential can be reduced to some extent only by performing the zero-phase modulation of Patent Document 2.

FIG. 12 shows the numerical calculation results of the neutral point potential pulsation assuming that the output current is 14.1 A, the amplitude of the output voltage command value is 0.8, and C1 = C2 = 500uF. Assuming that the three-phase voltage command values are Vu *, Vv *, Vw * and the output currents are IinvU, IinvV, and IinvW, the current iNP flowing out from the neutral point can be expressed by the following equation (1).

By integrating this and dividing by C1 + C2, the neutral point potential can be obtained.

12 (a) shows the voltage command values Vu *, Vv *, Vw *, and the output current IinvU, when zero-phase modulation is performed with a power factor of 1, and (b) shows the voltage command values Vu *, Vv *, Vw * when zero-phase modulation is performed with a power factor of 1. It shows IinvV, IinvW, and the neutral point potential pulsation obtained by numerical calculation. Comparing FIGS. 12 (a) and 12 (b), it can be seen that the neutral point potential pulsation can be reduced to 1/4 only by performing zero-phase modulation.

12 (c) and 12 (d) show the case where the power factor is changed to 0.9 and the presence / absence of zero-phase modulation is switched. In this case as well, the neutral point potential pulsation is reduced only by performing zero-phase modulation. It becomes 1/2.

When zero-phase modulation is performed using the calculation block shown in FIG. 11, the ratio of the third harmonic to the fundamental wave amplitude of the voltage command value is k≈0.2067, which is close to k in Patent Document 1 at the time of active power output. It becomes a value. Hereinafter, the reason why k≈0.2067 will be described will be described.

When the voltage command value Vu * after zero-phase modulation is expanded by Fourier series, the harmonics an and bn included in the voltage command value Vu * are the following equations (2) and (4).

As shown in the following equation (3), an takes a certain value only when n = 1 or an odd multiple of 3, and becomes zero when n is not.

As shown in the following equation (4), bn is always zero.

The ratio of the amplitude of the third harmonic to the fundamental wave is given by Eq. (5) below.

Since the techniques of Patent Documents 1 and 2 superimpose the third harmonic on the output voltage command value, the output phase voltage is distorted. However, since the superposed third harmonic is zero phase (the harmonics of the same phase are superposed on the U phase, V phase, and W phase), the line voltage is not distorted. In a three-phase three-wire circuit in which the connection between the inverter and the system is general, the output current depends only on the line voltage and is not affected by the phase voltage. Two techniques can be applied.

Japanese Unexamined Patent Publication No. 5-227996 Japanese Unexamined Patent Publication No. 3-107373 Japanese Unexamined Patent Publication No. 2004-11286 Japanese Unexamined Patent Publication No. 2007-300678 JP-A-2015-47056

1 and 2 are power conversion circuits having a BTB (back to back) configuration in which two inverters are connected on the DC side. The first inverter INV1 on the left side is connected to the grid, and the second inverter INV2 on the right side is driven by a motor. I do. In FIG. 1, the first inverter INV1 is connected to the three-phase four-wire system 23a, 23b, 23c.

When the techniques of Patent Documents 1 and 2 are applied to such a power conversion circuit, the superimposed zero-phase third-order harmonic voltage is applied to the filter 25 (systems 23a, 23b, 23c and the first inverter INV1) via the neutral wire 24. Since it is applied to the circuit consisting of the reactor and the capacitor in between), a large zero-phase third harmonic current flows through the neutral wire 24 in the first inverter INV1, and the power conversion circuit stops due to overcurrent. In some cases, the switching element may have an abnormality due to an overcurrent. The techniques of Patent Documents 1 and 2 cannot be applied to an inverter having a path through which a zero-phase current flows.

Further, Patent Document 3 describes an example in which the neutral point of the filter circuit of the inverter is connected to the neutral point of the inverter in order to suppress the noise flowing out to the system or the load. This configuration is shown in FIG. In this case as well, when the zero-phase voltage is superimposed on the first inverter INV1, the zero-phase current flows through the filter 25 and the neutral wire 24.

When a zero-phase third harmonic current flows, there is a risk that an abnormality will occur in the filter 25 in addition to an abnormality in the switching element. There is also a method of inserting an LC parallel resonant circuit into the neutral wire 24 to suppress the zero-phase current as in Patent Document 4, but in that case, additional parts are required.

In any case, the techniques of Patent Documents 1 and 2 cannot be applied to the three-phase four-wire type first inverter INV1 of FIGS. 1 and 2. Since the second inverter INV2 on the right side does not have a path through which the zero-phase current flows, the techniques of Patent Documents 1 and 2 can be applied, and the pulsation of the neutral point potential generated by the second inverter INV2 can be suppressed. .. However, the pulsation of the neutral point potential generated by the first inverter INV1 cannot be suppressed.

The pulsation of the neutral point potential causes an increase in the responsibilities of the first and second DC capacitors C1 and C2 and an increase in the strain of the inverter output voltage / current. As a countermeasure, large-capacity first and second DC capacitors C1 and C2 are required, which leads to an increase in the volume and cost of the power conversion circuit.

From the above, it is an issue to reduce the pulsation of the neutral point potential with a simple control block configuration in the power conversion circuit.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is a system of two first and second DC capacitors connected in series and the two first and second DC capacitors. A control device for a three-phase power conversion circuit having a first inverter connected between the two inverters and a second inverter connected between the two first and second DC capacitors and a load. The first zero-phase modulation command value calculation unit that outputs the average value of the maximum value and the minimum value as the first zero-phase modulation command value among the three-phase first voltage command values of the second inverter, and the first zero-phase modulation command value calculation unit. The first inverter includes a second zero-phase modulation command value calculation unit that outputs the average value of the maximum value and the minimum value of the three-phase voltage command values of the inverter as the second zero-phase modulation command value. It is driven based on the three-phase voltage command value of the first inverter, and the second inverter subtracts the first zero-phase modulation command value from the first voltage command value of the three phases of the second inverter. It is characterized in that it is driven based on the correction voltage command value to which the second zero-phase modulation command value is added.

Further, as one aspect thereof, a value obtained by multiplying the square root of the sum of squares of the three-phase voltage command values of the first inverter by 1/4 is used as a divisor, and the square root of the sum of squares of the first voltage command values of the second inverter is used as a divisor. The value obtained by multiplying √3 / 2 by √3 / 2 is subtracted from 1, and the division is performed. If the division result is smaller than 1, the second zero-phase modulation command value is multiplied by the division result. Then, the second zero-phase modulation command value to be added to the first voltage command value is limited.

Further, as another embodiment, the value obtained by multiplying the d-axis voltage command value of the first inverter by 1/4 is a divisor, and the value obtained by multiplying the q-axis voltage command value of the second inverter by √3 / 2 is 1. The value subtracted from is used as the division number, and division is performed. If the division result is smaller than 1, the second zero-phase modulation command value is multiplied by the division result and added to the first voltage command value. It is characterized in that the second zero-phase modulation command value is limited.

Another aspect is to multiply the second zero-phase modulation command value by a predetermined coefficient.

Further, as one aspect thereof, the first inverter includes first and second switching elements of each phase connected in series between the positive end of the first DC capacitor and the negative end of the second DC capacitor. Each phase of the third and fourth switching elements connected in anti-series between the common connection point of the first and second switching elements and the common connection point of the first and second DC capacitors is provided. The common connection point of the first and second switching elements is connected to the system via a filter, and the second inverter is located between the positive end of the first DC capacitor and the negative end of the second DC capacitor. Each connected in reverse series between the 5th and 6th switching elements of each connected phase, the common connection point of the 5th and 6th switching elements, and the common connection point of the 1st and 2nd DC capacitors. A phase 7th and 8th switching elements are provided, and a common connection point of the 5th and 6th switching elements is connected to a load.

Further, as another embodiment, the first to eighth switching elements common to each phase, which are sequentially connected in series between the positive end of the first DC capacitor and the negative end of the second DC capacitor, and the first one. The first flying capacitor common to each phase connected between the common connection point of the second switching element and the common connection point of the third and fourth switching elements, and the common connection point of the fifth and sixth switching elements. A second flying capacitor common to each phase connected to the common connection point of the 7th and 8th switching elements is provided, and the common connection point of the 4th and 5th switching elements is the 1st and 1st. The first inverter is connected to the common connection point of the two DC capacitors, and the first inverter of each phase is sequentially connected in series between the positive end of the first DC capacitor and the common connection point of the second and third switching elements. The 9th and 10th switching elements, and the 11th and 12th switching elements of each phase sequentially connected in series between the common connection point of the 6th and 7th switching elements and the negative end of the 2nd DC capacitor. The 13th to 16th switching elements of each phase sequentially connected in series between the common connection point of the 9th and 10th switching elements and the common connection point of the 11th and 12th switching elements, and the 13th , The first and second capacitors of each phase connected in series between the common connection point of the 14th switching element and the common connection point of the 15th and 16th switching elements are provided. The common connection point of the diode is connected to the common connection point of the first and second DC capacitors, the common connection point of the 14th and 15th switching elements is connected to the system via a filter, and the second inverter The 17th and 18th switching elements of each phase sequentially connected in series between the positive end of the 1st DC capacitor and the common connection point of the 2nd and 3rd switching elements, and the 6th and 7th switching elements. The 19th and 20th switching elements of each phase sequentially connected in series between the common connection point of the second DC capacitor and the negative end of the second DC capacitor, the common connection point of the 17th and 18th switching elements, and the 19th , The 21st to 24th switching elements of each phase sequentially connected in series with the common connection point of the 20th switching element, the common connection point of the 21st and 22nd switching elements, and the 23rd and 24th switching. The third and fourth diodes are sequentially connected in series with the common connection point of the element, and the common connection point of the third and fourth diodes is that of the first and second DC capacitors. It is characterized in that it is connected to a common connection point and the common connection point of the 22nd and 23rd switching elements is connected to the load.

Further, as one aspect thereof, the filter or the system is characterized in that the filter or the system is connected to the common connection point of the first and second DC capacitors by a neutral wire.

According to the present invention, in the control device of the power conversion circuit, it is possible to reduce the pulsation of the neutral point potential with a simple control block configuration.

The figure which shows the structure of the 3 level power conversion circuit connected to the three-phase four-wire system. The figure which shows the structure of the 3 level power conversion circuit which connected the neutral point of a filter and the neutral point of a power conversion circuit. The block diagram which shows the control device of the power conversion circuit in Embodiment 1. FIG. The block diagram which shows the control device of the power conversion circuit in Embodiment 2. The figure which shows the waveform of the zero-phase modulation of Patent Document 2. The block diagram which shows the control device of the power conversion circuit in Embodiment 3. The figure which shows the structure of the 5 level power conversion circuit in Embodiment 4. FIG. A time chart showing a simulation result when Patent Document 1 is applied. A time chart showing a simulation result when the fourth embodiment is applied. The figure which shows the main circuit composition per one phase of a three-level inverter. The block diagram which shows the zero-phase modulation instruction value calculation part. A time chart showing the reduction of neutral potential pulsation by zero-phase modulation.

Hereinafter, embodiments 1 to 4 of the power conversion circuit control device according to the present invention will be described in detail with reference to FIGS. 1 to 9.

[Embodiment 1]
The control device of the power conversion circuit in the first embodiment controls the three-level first and second inverters INV1 and INV2 shown in FIGS. 1 and 2.

Hereinafter, the three-level inverter shown in FIG. 1 will be described. Two first and second DC capacitors C1 and C2 are connected in series. The common connection point of the first and second DC capacitors C1 and C2 is defined as the neutral point NP.

The first and second switching elements Tr1, Tr2 and Ts1, Ts2 and Tt1, Tt2 of each phase are connected in series between the positive end of the first DC capacitor C1 and the negative end of the second DC capacitor C2, respectively. There is.

Further, the common connection point of the first and second switching elements Tr1 and Tr2, the common connection point of the first and second switching elements Ts1 and Ts2, the common connection point and the neutral point of the first and second switching elements Tt1 and Tt2. The third and fourth switching elements Tr3, Tr4, Ts3, Ts4, and Tt3, Tt4 are connected in anti-series to the NP.

The first inverter INV1 is mainly composed of the first to fourth switching elements Tr1 to Tr4, Ts1 to Ts4, and Tt1 to Tt4.

A filter 25 is used at the common connection points of the first and second switching elements Tr1 and Tr2, the common connection points of the first and second switching elements Ts1 and Ts2, and the common connection points of the first and second switching elements Tt1 and Tt2. The systems 23a, 23b, and 23c are connected to each other via the system. The systems 23a, 23b, and 23c are connected to the neutral point NP by the neutral wire 24.

Further, the fifth and sixth switching elements Tu5, Tu6 and Tv5, Tv6 and Tw5, Tw6 are connected in series between the positive end of the first DC capacitor C1 and the negative end of the second DC capacitor C2, respectively. ..

Further, common connection points of fifth and sixth switching elements Tu5 and Tu6, common connection points of fifth and sixth switching elements Tv5 and Tv6, common connection points and neutral points of fifth and sixth switching elements Tw5 and Tw6. Seventh and eighth switching elements Tu7, Tu8 and Tv7, Tv8 and Tw7, Tw8 are connected in anti-series to the NP.

The second inverter INV2 is mainly composed of the fifth to eighth switching elements Tu5 to Tu8, Tv5 to Tv8, and Tw5 to Tw8.

Motors M are located at the common connection points of the fifth and sixth switching elements Tu5 and Tu6, the common connection points of the fifth and sixth switching elements Tv5 and Tv6, and the common connection points of the fifth and sixth switching elements Tw5 and Tw6. It is connected.

Next, the three-level inverter shown in FIG. 2 will be described. The description of the same parts as those in FIG. 1 will be omitted. In the three-level inverter shown in FIG. 2, the filter capacitor of the filter 25 is connected to the neutral point NP by the neutral wire 24.

FIG. 3 shows a block diagram of the control device according to the first embodiment. Vu *'is the first voltage command value of the phase voltage between the u terminal and the neutral point NP in FIGS. 1 and 2. The same applies to Vv *'and Vw *'. The first voltage command values Vu *', Vv *', and Vw *'are connected to a load (motor M in FIG. 1) in which a zero-phase current is unlikely to flow, as in the second inverter INV2 in FIG. This is the output voltage command value of the second inverter INV2. The first voltage command values Vu *', Vv *', and Vw *'are given by feedforward, and may also be given by feedback control of output voltage and output current.

The first zero-phase modulation command value calculation unit 1 inputs the first voltage command values Vu *', Vv *', and Vw *', and outputs the first zero-phase voltage command value for performing zero-phase modulation. The first zero-phase modulation command value calculation unit 1 is the same as that of FIG.

The first zero-phase modulation command value calculation unit 1 selects and outputs the maximum value among the first voltage command values Vu *', Vv *', and Vw *'in the maximum value selection unit max. The minimum value selection unit min selects and outputs the minimum value among the first voltage command values Vu *', Vv *', and Vw *'. The adder 7 adds the outputs of the maximum value selection unit max and the minimum value selection unit min. The multiplier 8 multiplies the output of the adder 7 by 0.5, and sets the average value of the maximum and minimum values of the first voltage command values Vu *', Vv *', and Vw *'as the first zero-phase modulation command. Output as a value.

The subtractors 2a, 2b, and 2c subtract the first zero-phase modulation command value from the first voltage command values Vu *', Vv *', and Vw *'. The outputs of the subtractors 2a, 2b, and 2c are set to the second voltage command values Vu * ", Vv *", Vw * ".

Vr * is a voltage command value of the phase voltage between the r terminal and the neutral point NP in FIGS. 1 and 2. The same applies to Vs * and Vt *. The voltage command values Vr *, Vs *, and Vt * are connected to the system 23 (23a, 23b, 23c) in which a zero-phase current may flow, as in the first inverter INV1 of FIGS. 1 and 2. 1 This is the voltage command value of the inverter INV1. The voltage command values Vr *, Vs *, and Vt * are given by feedforward, and may also be given by feedback control of the AC input voltage and AC input current of the first inverter INV1.

The second zero-phase modulation command value calculation unit 3 inputs the voltage command values Vr *, Vs *, and Vt *, and outputs the second zero-phase voltage command value for performing zero-phase modulation.

The second zero-phase modulation command value calculation unit 3 selects and outputs the maximum value among the voltage command values Vr *, Vs *, and Vt * in the maximum value selection unit max. The minimum value selection unit min selects and outputs the minimum value among the voltage command values Vr *, Vs *, and Vt *. The adder 5 adds the outputs of the maximum value selection unit max and the minimum value selection unit min. The multiplier 6 multiplies the output of the adder 5 by 0.5, and outputs the average value of the maximum value and the minimum value of the voltage command values Vr *, Vs *, and Vt * as the second zero-phase modulation command value.

The voltage command values Vr *, Vs *, and Vt * are input to the PWM modulator for the first inverter in the subsequent stage, which is not shown as it is, and the gate of each switching element of the first inverter INV1 is compared with the carrier signal. A command (on / off command) is generated and input to the first inverter INV1.

The adders 4a, 4b, 4c add the second zero-phase modulation command values to the second voltage command values Vu * ", Vv *", Vw * "of the second inverter INV2. The output correction voltage command values Vu *, Vv *, and Vw * are input to the PWM modulator for the second inverter in the subsequent stage (not shown), and each switching of the second inverter INV2 is performed based on the comparison with the carrier signal. A gate command (on / off command) for the element is generated and input to the second inverter INV2.

A zero-phase voltage cannot be superimposed on the first inverter INV1 in which a zero-phase current may flow. Therefore, by superimposing the second zero-phase modulation command value of the first inverter INV1 on the second voltage command value of the second inverter INV2 capable of superimposing the zero-phase voltage, the pulsation of the neutral point potential generated by the first inverter INV1. Can be suppressed by the second inverter INV2. The first embodiment is a configuration that realizes this.

When superimposing the output result of the second zero-phase modulation command value calculation unit 3 on the second voltage command values Vu * ”, Vv *”, Vw * ”, the reason for adding instead of subtracting will be described. When there is no power storage element such as a battery on the DC voltage side, the active power input from the first inverter INV1 and the active power output from the second inverter INV2 are almost equal.

At this time, when the second inverter INV2 is used as a reference, the direction of the active power of the first inverter INV1 is reversed. When adjusting the neutral point potential using the zero-phase voltage, it is necessary to change the sign of the zero-phase voltage according to the direction of the output active power. Therefore, the adders 4a, 4b, and 4c are used instead of the subtractor to set the second zero-phase modulation command value of the first inverter INV1 to the second voltage command value Vu * ”, Vv *”, Vw * ”of the second inverter INV2. Superimpose on.

In the first embodiment, it is assumed that both the first inverter INV1 and the second inverter INV2 operate at a power factor of approximately 1. In FIGS. 1 and 2, the first inverter IN1 is assumed to be a grid-connected inverter, but this assumption holds because a normal grid-connected inverter operates at a power factor of 1 in order to suppress reactive current and reduce loss. To do.

Even when the static power compensation function is installed, if the static power output is about 43% of the rating (that is, the condition of the power factor of 0.9 at the rated current output), it is neutral according to the first embodiment as shown in FIG. The point potential pulsation can be reduced by half. Since the second inverter INV2 can superimpose a zero-phase voltage, it can be used in combination with the technique of Patent Document 1 when operating at a low power factor.

According to the first embodiment, in the BTB configuration of two three-level inverters, the pulsation of the neutral point potential is reduced even when connected to the three-phase four-wire system 23 (23a, 23b, 23c). can do.

When the power factor of the two inverters is close to 1, the pulsation of the neutral point potential can be sufficiently reduced only by the technique of the first embodiment. As a result, it is possible to suppress the capacities of the first and second DC capacitors C1 and C2 connected to the DC side, and to reduce the size and cost of the device.

Moreover, since a zero-phase current is not generated, the duty of the filter and the switching element is reduced and the loss does not increase. Furthermore, since no feedback loop, phase lead compensator, neutral point current detection and estimation, and third-order sine wave generator are used, it can be realized with a very simple control block configuration, and the cost of the board on which the control circuit is mounted. Can be reduced.

Further, since the first embodiment is not a method of superimposing the third harmonic on the output voltage command value as in Patent Documents 1 and 2, a large zero-phase 3 is provided on the first inverter INV1 via the neutral wire 24. There is no problem that the power converter is overcurrent stopped or damaged due to the flow of the next harmonic.

[Embodiment 2]
FIG. 4 is a block diagram showing a control device for the power conversion circuit of the second embodiment. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The multipliers 9a, 9b, 9c square the voltage command values Vr *, Vs *, Vt * of the first inverter INV1. The adder 10 calculates the sum of the multipliers 9a, 9b, 9c. The square root calculator 11 calculates the square root of the output of the adder 10 to obtain the amplitude V1 * of the voltage command value of the first inverter INV1. The multiplier 12 obtains the product of the amplitude V1 * and 1/4 of the voltage command value of the first inverter INV1.

The multipliers 13a, 13b, 13c square the first voltage command values Vu *', Vv *', Vw *'of the second inverter INV2. The adder 14 calculates the sum of the outputs of the multipliers 13a, 13b, 13c. The square root calculator 15 calculates the square root of the output of the adder 14 to obtain the amplitude V2 * of the first voltage command value of the second inverter INV2. The multiplier 16 obtains the product of the amplitude V2 * of the first voltage command value of the second inverter INV2 and √3 / 2 (≈0.866). The subtractor 17 subtracts the output of the multiplier 16 from 1.

The divider 18 divides by using 1-0.866 × V2 * as the divisor and V1 * / 4 as the divisor. The limiter 19 limits the output of the divider 18 to the range 0 to 1. The multiplier 20 calculates the product of the output of the limiter 19 and the second zero-phase modulation command value, and adds the product to the second voltage command values Vu * ”, Vv *”, Vw * ”.

In the first embodiment, as the AC input voltage of the first inverter INV1 increases, the amplitude of the second zero-phase modulation command value superimposed on the second inverter INV2 also increases. If the output voltage of the second inverter INV2 also increases, the amplitudes of the correction voltage command values Vu *, Vv *, and Vw * exceed 1 and overmodulation may occur, resulting in distortion of the output voltage.

In the second embodiment, the amplitude of the second zero-phase modulation command value superimposed when the output voltage amplitude increases is limited to avoid overmodulation.

First, the amplitudes V1 * and V2 * of the voltage command value are obtained from the square root of the sum of squares of each phase of the voltage command value of the first inverter INV1 and the first voltage command value of the second inverter INV2. At this time, the amplitude of the second zero-phase modulation command value on the first inverter INV1 side is V1 * / 4. The reason will be described below.

The first voltage command values Vu *', Vv *', and Vw *'of the second inverter INV2 in FIG. 11 are represented by the following equation (6).

The second voltage command value Vu * ”after the zero-phase modulation of the U phase is expressed by the following equation (7).

In FIG. 5, the first voltage command value Vu *', Vv *', Vw *'is superimposed on the zero-phase voltage command value Vz, and the second voltage command value after zero-phase modulation is Vu * ", Vv *", Vw * ". Is shown.

From FIG. 5, the zero-phase voltage command value Vz appears to decrease monotonically in the range of phase 0 deg to 60 deg (0 <ωt <π / 3). First, check this. The zero-phase voltage command value Vz in the phases 0 deg to 60 deg is expressed by the following equation (8).

This is differentiated by t as shown in Eq. (9) below.

In the range of the phase 0 deg to 60 deg, dVz / dt <0, so that the zero-phase voltage command value Vz is certainly monotonically decreasing. The zero-phase voltage command value Vz takes the maximum value at phase 0 deg (ωt = 0) and the minimum value at 60 deg (ωt = π / 3) as shown in FIG. 5, and becomes V / 4, −V / 4, respectively.

The command value amplitude of the second inverter INV2 after zero-phase modulation is √3V2 * / 2. The reason will be described below.

The amplitude peak of the second voltage command value Vu * ”after the zero-phase modulation is confirmed. From FIG. 5, it is clear that the maximum is in the range of the phase 0 deg to 60 deg. When Vu * ”is differentiated by t, the following equation (10) is obtained.

Since this equation (10) becomes zero at the phase of 30 deg (ωt = π / 6), becomes positive at ωt <π / 6, and becomes negative at ωt> π / 6, the second voltage command value Vu * ”is at the phase of 30 deg. It takes the maximum value, and the value is √3V / 2.

That is, 1-√3V2 * / 2 is the margin until the second inverter INV2 is overmodulated.

If V1 * / 4 exceeds this margin, overmodulation can be prevented by reducing the amplitude of the zero-phase modulation command value on the first inverter INV1 side. In the second embodiment, the following equation (11) is calculated.

If the calculation result of Eq. (11) is smaller than 1, that is, V1 * / 4 is larger than 1-√3V2 * / 2, this value is multiplied by the second zero-phase modulation command value on the first inverter INV1 side. The second zero-phase modulation command value is corrected to be small and added to the second voltage command values Vu * ", Vv *", Vw * "of the second inverter INV2.

If the calculation result of Eq. (11) is larger than 1, that is, 1-√3V2 * / 2 is larger than V1 * / 4, the voltage command value of the second inverter INV2 has a margin, so the limiter in FIG. 4 19 outputs 1 and adds the second zero-phase modulation command value as it is to the second voltage command values Vu * ”, Vv *”, Vw * ”of the second inverter INV2.

As shown above, according to the second embodiment, the same effects as those of the first embodiment are obtained. Further, the second inverter INV2 can suppress the neutral point potential pulsation caused by the first inverter INV1 as much as possible within a range that does not cause overmodulation.

[Embodiment 3]
FIG. 6 is a block diagram showing a control device for the power conversion circuit of the third embodiment. The same parts as those in the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The third embodiment is the second embodiment with the following changes.

The dq inverse converter 21 sets the d-axis voltage command value Vd1 * on the rotating coordinates of the first inverter INV1 and the q-axis voltage command value Vq1 * on the rotating coordinates of the first inverter INV1 on the fixed coordinates of the first inverter INV1. Converts to the three-phase voltage command values Vr *, Vs *, and Vt *. The first inverter INV1 assumes a q-axis voltage command value Vq1 * ≈0 in a grid interconnection application in which a power factor of 1 operation is performed. The dq inverse converter 21 performs the calculation of the following equation (12).

The θ of the equation (12) is the voltage phase of the system 23 (23a, 23b, 23c) shown in FIGS. 1 and 2. Further, in the third embodiment, the amplitude V1 * of the second embodiment is replaced with the d-axis voltage command value Vd1 * on the rotating coordinates.

The dq inverse converter 22 uses the d-axis voltage command value Vd2 * on the rotating coordinates of the second inverter INV2 and the q-axis voltage command value Vq2 * on the rotating coordinates of the second inverter INV2 as the three-phase third phase on the fixed coordinates. 1 Convert to voltage command values Vu *', Vv *', Vw *'. The second inverter INV2 assumes a d-axis voltage command value Vd2 * ≈0 for motor drive applications. The dq inverse converter 22 performs the calculation of the following equation (13).

The θ of the equation (13) is the phase of the AC output voltage of the second inverter INV2 shown in FIGS. 1 and 2. Further, in the third embodiment, the amplitude V2 * of the second embodiment is replaced with the q-axis voltage command value Vq2 * on the rotating coordinates.

The third embodiment is a method in which the calculation load of the second embodiment is reduced. In the second embodiment, as shown in FIG. 4, the square root calculation was required twice. In the third embodiment, the d-axis and q-axis voltage command values Vd1 * and Vq1 * on the rotating coordinates of the voltage command values Vr *, Vs * and Vt * of the first inverter INV1 are used. When either the d-axis or q-axis voltage command value Vd1 * or Vq1 * on the rotating coordinates is close to 0 (here, Vq1 ≈ 0), Vd1 * ≈ V1 * is used to calculate the square root. Is no longer needed.

Generally, in the first inverter INV1 connected to the system, the q-axis voltage command value Vq1 * on the rotating coordinates becomes almost zero by performing the PLL so as to synchronize the d-axis and the system voltage. Further, in the second inverter INV2 for driving the motor M, the d-axis is often aligned with the magnetic pole, and the d-axis voltage command value Vd2 * on the rotating coordinates becomes almost zero (when weakening magnetic flux control is not performed).

In FIG. 6, the first inverter INV1 assuming a grid interconnection application has a d-axis voltage command value Vd1 * on the rotating coordinates, and the second inverter INV2 assuming a motor drive application has a q-axis voltage command value Vq2 on the rotating coordinates. *It was used.

Further, when the system connected to the first inverter INV1 is stable and the voltage fluctuation is small, or when it is necessary to stop the inverter when the voltage fluctuation occurs, the d-axis voltage command value Vd1 * on the rotating coordinates is almost constant. Therefore, the division can be reduced and the calculation load can be further reduced by replacing the divisor of the equation (1-√3V2 * / 2) ÷ 0.25V1 * with a fixed value. In this case, in FIG. 4, a predetermined coefficient K, which is a fixed value, is input to the multiplier 20 instead of the output of the limiter 19.

[Embodiment 4]
FIG. 7 shows the main circuit configuration of the fourth embodiment. The first embodiment can be applied not only to a three-level inverter but also to a multi-level inverter having a neutral point potential. The fourth embodiment is an example in which the control block of the first embodiment is applied to a five-level inverter.

The main circuit of the fourth embodiment will be described with reference to FIG. 7. The first and second DC capacitors C1 and C2 are connected in series. The common connection point and the neutral point NP of the first and second DC capacitors C1 and C2 are used.

The first to eighth switching elements T1 to T8 are sequentially connected in series between the positive end of the first DC capacitor C1 and the negative end of the second DC capacitor C2.

The first flying capacitor FC1 is connected between the common connection points of the first and second switching elements T1 and T2 and the common connection points of the third and fourth switching elements T3 and T4. The second flying capacitor FC2 is connected between the common connection points of the fifth and sixth switching elements T5 and T6 and the common connection points of the seventh and eighth switching elements T7 and T8.

The common connection points of the fourth and fifth switching elements T4 and T5 are connected to the neutral point NP.

The ninth and tenth switching Tr9 and Tr10 are connected in series between the positive end of the first DC capacitor C1 and the common connection point of the second and third switching elements T2 and T3. The eleventh and twelfth switching elements Tr11 and Tr12 are connected in series between the common connection point of the sixth and seventh switching elements T6 and T7 and the negative end of the second DC capacitor C2.

Between the common connection points of the 9th and 10th switching elements Tr9 and Tr10 and the common connection points of the 11th and 12th switching elements Tr11 and Tr12, the 13th to 16th switching elements Tr13, Tr14a, Tr14b, Tr15a, Tr15b, Tr16s are sequentially connected in series.

The first and second diodes Dr1a, Dr1b, Dr2a, and Dr2b are sequentially connected in series between the common connection points of the 13th and 14th switching elements Tr13 and Tr14a and the common connection points of the 15th and 16th switching elements Tr15b and Tr16. Will be done.

The common connection points of the first and second diodes Dr1b and Dr2a are connected to the neutral point NP. Further, the common connection points of the 14th and 15th switching elements Tr14b and Tr15a are connected to the system 23 via the filter 25.

Further, the filter capacitor of the filter 25 is connected to the neutral point NP by the neutral wire 24. As shown in FIG. 1, the system 23 may be connected to the neutral point NP by the neutral wire 24.

The r-phase first inverter INV1 is mainly composed of the 9th to 16th switching elements Tr9 to Tr16 and the 1st to 2nd diodes Dr1a to Dr2b. The same applies to the s phase and the t phase.

The 17th and 18th switching elements Tu17 and Tu18 are connected in series between the positive end of the first DC capacitor C1 and the common connection point of the second and third switching elements T2 and T3. The 19th and 20th switching elements Tu19 and Tu20 are connected in series between the common connection point of the 6th and 7th switching elements T6 and T7 and the negative end of the 2nd DC capacitor C2.

Between the common connection points of the 17th and 18th switching elements Tu17 and Tu18 and the common connection points of the 19th and 20th switching elements Tu19 and Tu20, the 21st to 24th switching elements Tu21, Tu22a, Tu22b, Tu23a, Tu23b, Tu24s are sequentially connected in series.

The third to fourth diodes Du3a, Du3b, Du4a, and Du4b are sequentially connected in series between the common connection point of the 21st and 22nd switching elements Tu21 and Tu22a and the common connection point of the 23rd and 24th switching elements Tu23b and Tu24. Will be done.

The common connection point of the third and fourth diodes Du3b and Du4a is connected to the neutral point NP. The common connection points of the 22nd and 23rd switching elements Tu22b and Tu23a are connected to the load (motor M).

The u-phase second inverter INV2 is mainly composed of the 17th to 24th switching elements Tu17 to Tu24 and the 3rd to 4th diodes Du3a to Du4b. The same applies to the v phase and the w phase.

In the fourth embodiment, the 14th, 15th, 22nd, and 23rd switching elements Tr14a, Tr14b, Tr15a, Tr15b, Tu22a, Tu22b, Tu23a, Tu23b, and the first to fourth diodes Dr1a, Dr1b, Dr2a , Dr2b, Du3a, Du3b, Du4a, Du4b have two switching elements connected in series for the reason of withstand voltage, but if the problem of withstand voltage can be solved, one switching element may be used. Further, each switching element may be configured by connecting a plurality of switching elements in parallel or in series.

The calculation block of the three-phase correction voltage command values Vu *, Vv *, and Vw * can use the first embodiment (FIG. 3) as it is without depending on the number of inverter levels.

8 and 9 show the simulation results of Patent Document 1 and the fourth embodiment. The simulation conditions were assumed to be a device rating of 6.6 kV and 1.2 MVA, and a voltage output of 80%, a current output of 100%, and a power factor of 0.8 were set from the second inverter INV2. The first inverter INV1 is connected to the 6.6 kV, 50 Hz system 23 via the filter 25, constantly controls the DC voltage Vdc1 + Vdc2, and inputs 0.768 MW of active power.

FIG. 8 shows a case where only the method of Patent Document 1 is applied, and FIG. 9 shows a case where the present embodiment 4 is applied in addition to Patent Document 1. Looking at the pulsations of the DC voltages Vdc1 and Vdc2, the difference between the maximum value and the minimum value was 613V in FIG. 8 and 461V in FIG. The main component of the pulsation in FIG. 8 is caused by the first inverter INV1 at 150 Hz, but it is reduced in FIG. 9, and the effectiveness of the fourth embodiment can be confirmed.

Although the first embodiment is used as the control block in the fourth embodiment, the control blocks of the second embodiment and the third embodiment can also be applied.

Although the above description has been made in detail only with respect to the specific examples described in the present invention, it is clear to those skilled in the art that various modifications and modifications can be made within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

INV1, INV2 ... 1st and 2nd inverters 1 ... 1st zero-phase modulation command value calculation unit 2a, 2b, 2c ... subtractor 3 ... 2nd zero-phase modulation command value calculation unit 4a, 4b, 4c ... adder 5 ... Adder 6 ... Divider 7 ... Adder 8 ... Divider

Claims (6)

Two first and second DC capacitors connected in series,
The first inverter, which is a multi-level inverter with three or more levels connected between the two first and second DC capacitors and the system,
A second inverter, which is a multi-level inverter with three or more levels connected between the two first and second DC capacitors and the load,
A filter connected between the first inverter and the system,
Have a, the first inverter is connected to a common connection point of the first, second DC capacitor, the filter or the lines are connected to a common connection point of the first, second DC capacitor by a neutral line It is a control device for a three-phase power conversion circuit.
A first zero-phase modulation command value calculation unit that outputs the average value of the maximum value and the minimum value as the first zero-phase modulation command value among the three-phase first voltage command values of the second inverter.
A second zero-phase modulation command value calculation unit that outputs the average value of the maximum value and the minimum value among the three-phase voltage command values of the first inverter as the second zero-phase modulation command value is provided.
The first inverter is driven based on the three-phase voltage command values of the first inverter.
In the second inverter, the second zero-phase modulation command value is added to the second voltage command value obtained by subtracting the first zero-phase modulation command value from the three-phase first voltage command value of the second inverter. A control device for a power conversion circuit characterized in that it is driven based on a corrected voltage command value. The value obtained by multiplying the square root of the sum of squares of the three-phase voltage command values of the first inverter by 1/4 is used as a divisor, and the square root of the sum of squares of the first voltage command values of the second inverter is multiplied by √3 / 2. The value obtained by subtracting the value from 1 is used as the number to be divided, and if the division result is smaller than 1, the second zero-phase modulation command value is multiplied by the division result to obtain the second voltage. and limiting said second zero phase modulation instruction value to be added to the command value, if the division result is greater than 1, to the second zero phase modulation instruction value to be added to the second voltage command value as it is The control device for a power conversion circuit according to claim 1, wherein the control device is characterized. The d-axis voltage command value of the first inverter multiplied by 1/4 is used as a divisor, and the q-axis voltage command value of the second inverter multiplied by √3 / 2 is subtracted from 1 as the divisor. , If the division result is smaller than 1, the second zero-phase modulation command value is multiplied by the division result and added to the second voltage command value. The control of the power conversion circuit according to claim 1 , wherein when the division result is larger than 1, the second zero-phase modulation command value to be added to the second voltage command value is left as it is. apparatus. The control device for a power conversion circuit according to claim 1, wherein the second zero-phase modulation command value is multiplied by a predetermined coefficient. The first inverter
The first and second switching elements of each phase connected in series between the positive end of the first DC capacitor and the negative end of the second DC capacitor,
The third and fourth switching elements of each phase connected in anti-series between the common connection point of the first and second switching elements and the common connection point of the first and second DC capacitors, and
The common connection point of the first and second switching elements is connected to the system via a filter.
The second inverter
The fifth and sixth switching elements of each phase connected between the positive end of the first DC capacitor and the negative end of the second DC capacitor, and
The 7th and 8th switching elements of each phase connected in anti-series between the common connection point of the 5th and 6th switching elements and the common connection point of the 1st and 2nd DC capacitors, and
With
The control device for a power conversion circuit according to any one of claims 1 to 4, wherein a common connection point of the fifth and sixth switching elements is connected to a load. The first to eighth switching elements common to each phase, which are sequentially connected in series between the positive end of the first DC capacitor and the negative end of the second DC capacitor,
A first flying capacitor common to each phase connected between the common connection point of the first and second switching elements and the common connection point of the third and fourth switching elements.
A second flying capacitor common to each phase connected between the common connection point of the fifth and sixth switching elements and the common connection point of the seventh and eighth switching elements is provided, and the fourth and fourth switching elements are provided. The common connection point of the 5 switching elements is connected to the common connection point of the first and second DC capacitors.
The first inverter
The ninth and tenth switching elements of each phase sequentially connected in series between the positive end of the first DC capacitor and the common connection point of the second and third switching elements, and
The 11th and 12th switching elements of each phase, which are sequentially connected in series between the common connection point of the 6th and 7th switching elements and the negative end of the 2nd DC capacitor,
The 13th to 16th switching elements of each phase, which are sequentially connected in series between the common connection point of the 9th and 10th switching elements and the common connection point of the 11th and 12th switching elements,
The first and second diodes of each phase connected in series between the common connection point of the 13th and 14th switching elements and the common connection point of the 15th and 16th switching elements,
The common connection point of the first and second diodes is connected to the common connection point of the first and second DC capacitors, and the common connection point of the 14th and 15th switching elements is connected to the system via a filter. Connected,
The second inverter
The 17th and 18th switching elements of each phase, which are sequentially connected in series between the positive end of the first DC capacitor and the common connection point of the second and third switching elements,
The 19th and 20th switching elements of each phase sequentially connected in series between the common connection point of the 6th and 7th switching elements and the negative electrode end of the 2nd DC capacitor, and
The 21st to 24th switching elements of each phase, which are sequentially connected in series between the common connection point of the 17th and 18th switching elements and the common connection point of the 19th and 20th switching elements,
The third and fourth diodes, which are sequentially connected in series between the common connection point of the 21st and 22nd switching elements and the common connection point of the 23rd and 24th switching elements,
The common connection point of the third and fourth diodes was connected to the common connection point of the first and second DC capacitors, and the common connection point of the 22nd and 23rd switching elements was connected to the load. The control device for a power conversion circuit according to any one of claims 1 to 4.

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