JP6986385B2 - Semiconductor device, mounting structure of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device in which the semiconductor element is a Hall element and is in the form of a surface mount type resin package, and a mounting structure when the semiconductor device is mounted on a wiring substrate.

A semiconductor device in which a semiconductor element is a Hall element is applied to various electronic devices such as mobile phones. For example, when controlling the light source of the display of a mobile phone, if the semiconductor device is applied, the light source can be turned on or off by opening and closing the main body of the mobile phone. With the thinning of electronic devices to which the semiconductor devices are applied, further reduction in height is required for the semiconductor devices as well.

Patent Document 1 discloses a semiconductor device in which pellets (semiconductor elements), which are Hall elements, are mounted on a metal island. Since the pellet is thinner than the conventional one, it has a structure that contributes to lowering the height of the semiconductor device. However, since the semiconductor device disclosed in Patent Document 1 has a configuration in which pellets are mounted on the island, it is necessary to include the thickness of the island in the thickness of the semiconductor device. Therefore, depending on the thickness of the island to be applied, there is a concern that it may be difficult to further reduce the height of the semiconductor device.

Japanese Unexamined Patent Publication No. 2014-86677

In view of the above circumstances, the main object of the present invention is to provide a semiconductor device having a further reduced profile.

According to the first aspect of the present invention, a semiconductor element having a front surface and a back surface facing each other in the thickness direction, a plurality of terminals arranged apart from the semiconductor element and conducting conduction to the surface, and the above-mentioned A semiconductor device comprising a sealing resin that covers a semiconductor device and has a first surface that faces in the same direction as the surface, wherein each terminal has a main surface that is exposed from the first surface. A featured semiconductor device is provided.

In the embodiment of the present invention, the main surface is preferably flush with the first surface.

Preferably, in the embodiment of the present invention, the terminal includes a main surface conductive layer covering the main surface.

In the embodiment of the present invention, it is preferable to further include a heat radiating layer provided in contact with the back surface, and the sealing resin further has a second surface facing the side opposite to the first surface, and the heat radiating. The layer is exposed from the second surface.

In the embodiment of the present invention, the heat dissipation layer is preferably a conductor.

In the embodiment of the present invention, preferably, in the thickness direction view of the semiconductor element, the peripheral edge of the heat radiating layer has a section located inside the peripheral edge of the semiconductor element.

In the embodiment of the present invention, the exposed surface of the heat radiating layer exposed from the sealing resin is preferably flush with the second surface.

In the embodiment of the present invention, preferably, the terminal has a first side surface facing outward in a first direction orthogonal to the thickness direction of the semiconductor element, a thickness direction of the semiconductor element, and the first direction. The sealing resin has a second side surface facing outward in a second direction orthogonal to both of the above, and the sealing resin has a third surface facing the first direction and a fourth surface facing the second direction. The first side surface is flush with the third surface, and the second side surface is flush with the fourth surface.

In the embodiment of the present invention, each of the terminals preferably has a base portion having a bottom surface facing in the same direction as the back surface, and a protrusion portion protruding from the base portion toward the first surface and having the main surface. , Further prepare.

Preferably, in the embodiment of the present invention, the terminal is recessed from both the bottom surface and the second side surface, and further has a recess formed through the terminal in the first direction, and the recess is formed. The sealing resin faces each other.

In embodiments of the present invention, preferably, the protrusion further comprises a first inner surface that is separated from the second side surface in the second direction and intersects the main surface, wherein the base is the first. It has a second inner surface that is separated from the second side surface in two directions and is connected to the first inner surface, and both the first inner surface and the second inner surface are curved surfaces.

In the embodiment of the present invention, the first inner surface and the second inner surface are preferably connected by a continuous curved surface, and at the terminal, the first inner surface and the second inner surface intersecting the first side surface. There is an inflection on the boundary with.

In the embodiment of the present invention, it is preferable to further include a wire for making the surface and the first inner surface mutually conductive.

Preferably, in the embodiment of the present invention, the terminal further includes an internal conductive layer covering the first inner surface and the second inner surface.

In the embodiment of the present invention, it is preferable that the insulating film provided in contact with the second surface and having electrical insulating properties is further provided, and the plurality of the bottom surfaces and the exposed surface of the heat radiating layer are both described above. It is covered with an insulating film.

Preferably, in the embodiment of the present invention, the terminal further includes an external conductive layer that covers the first side surface, the second side surface, and the main surface conductive layer.

In the embodiment of the present invention, the external conductive layer preferably contains an alloy containing Sn as a component.

In the embodiment of the present invention, the semiconductor element is preferably a Hall element, and in the thickness direction view of the semiconductor element, the first side surface and the first side surface and the angle at which the first direction and the second direction intersect are preferable. Both sides of the second side are in contact with each other.

According to the second aspect of the present invention, among the semiconductor devices provided by the first aspect of the present invention, when the semiconductor device having the terminal provided with the external conductive layer is mounted on the wiring substrate, the insulating film is said to be the same. Provided is a semiconductor device mounting structure that faces a wiring board and is characterized in that a conductive bonding layer for mounting the semiconductor device on the wiring board is in contact with the external conductive layer.

According to the third aspect of the present invention, among the semiconductor devices provided by the first aspect of the present invention, when the semiconductor device in which the semiconductor element is a hole element is mounted on a wiring substrate, the first surface is said. Provided is a semiconductor device mounting structure, characterized in that a conductive bonding layer facing the wiring board and for mounting the semiconductor device on the wiring board faces the main surface conductive layer.

According to the semiconductor device according to the first aspect of the present invention, the protrusion included in each terminal includes a main surface exposed from the first surface of the sealing resin covering the semiconductor element. This configuration is established by making the height (length in the thickness direction) of the protruding portion as low as possible in the step of exposing the protruding portion from the sealing resin at the time of manufacturing the semiconductor device. Therefore, according to the semiconductor device, it is possible to further reduce the height.

According to the mounting structure of the semiconductor device according to the second aspect of the present invention, when the terminal is a semiconductor device provided with an external conductive layer, when the semiconductor device is mounted on the wiring board, the insulating film faces the wiring board. Moreover, the conductive bonding layer used for mounting is in contact with the external conductive layer. By adopting this configuration, the mounting height of the semiconductor device can be further lowered. At the same time, the mounting strength of the semiconductor device on the wiring board is further improved.

According to the mounting structure of the semiconductor device according to the third aspect of the present invention, in the case of a semiconductor device to which a Hall element is applied as a semiconductor element, when the semiconductor device is mounted on a wiring board, the surface faces the wiring board. And the conductive bonding layer faces the main surface conductive layer. By adopting this configuration, the distance between the magnet arranged outside and the semiconductor element becomes closer, so that the accuracy of detecting the change in the magnetic flux density by the semiconductor device is further improved.

Other features and advantages of the present invention will be more apparent by the detailed description given below based on the accompanying drawings.

It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 1st Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. 1. It is a right side view of the semiconductor device shown in FIG. 1. It is a front view of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the VV line of FIG. It is a block diagram of the circuit to which the semiconductor device shown in FIG. 1 is applied. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing when the semiconductor device shown in FIG. 1 is mounted on a wiring board. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 2nd Embodiment of this invention. FIG. 22 is a right side view of the semiconductor device shown in FIG. 22. It is a front view of the semiconductor device shown in FIG. 22. 22 is a cross-sectional view taken along the line XXV-XXV of FIG. 22. It is a partially enlarged view of FIG. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. 22. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 3rd Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. 31. FIG. 31 is a right side view of the semiconductor device shown in FIG. 31. It is a front view of the semiconductor device shown in FIG. 31. FIG. 3 is a cross-sectional view taken along the line XXXV-XXXV of FIG. 31. It is a partially enlarged view of FIG. 33. FIG. 31 is an enlarged plan view of the semiconductor device (when the heat dissipation layer is composed of Ag paste) shown in FIG. 31. It is sectional drawing when the semiconductor device shown in FIG. 31 is mounted on a wiring board. It is a bottom view of the semiconductor device which concerns on the modification of the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device shown in FIG. 39. It is sectional drawing when the semiconductor device shown in FIG. 39 is mounted on a wiring board. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 4th Embodiment of this invention. FIG. 42 is a right side view of the semiconductor device shown in FIG. 42. It is a front view of the semiconductor device shown in FIG. 42. It is sectional drawing which follows the XLV-XLV line of FIG. 42. It is sectional drawing when the semiconductor device shown in FIG. 42 is mounted on a wiring board. It is sectional drawing when the semiconductor device shown in FIG. 42 is mounted on a wiring board. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 5th Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. 48. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 6th Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. It is a right side view of the semiconductor device shown in FIG. It is a front view of the semiconductor device shown in FIG. FIG. 5 is a cross-sectional view taken along the line LIV-LIV of FIG. It is sectional drawing when the semiconductor device shown in FIG. 50 is mounted on a wiring board. It is a bottom view of the semiconductor device which concerns on the modification of the 6th Embodiment of this invention. It is sectional drawing of the semiconductor device shown in FIG. 56. It is sectional drawing when the semiconductor device shown in FIG. 56 is mounted on a wiring board. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 7th Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. 59. It is a right side view of the semiconductor device shown in FIG. 59. It is a front view of the semiconductor device shown in FIG. 59. FIG. 5 is a cross-sectional view taken along the line LXIII-LXIII of FIG. 59. It is sectional drawing when the semiconductor device shown in FIG. 59 is mounted on a wiring board. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 8th Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. 65. It is a right side view of the semiconductor device shown in FIG. 65. It is a front view of the semiconductor device shown in FIG. 65. FIG. 6 is a cross-sectional view taken along the line LXIX-LXIX of FIG. 65. It is sectional drawing when the semiconductor device shown in FIG. 65 is mounted on a wiring board. It is sectional drawing when the semiconductor device shown in FIG. 65 is mounted on a wiring board. It is a top view (permeating the sealing resin) of the semiconductor device which concerns on 9th Embodiment of this invention. It is a bottom view of the semiconductor device shown in FIG. 72. It is a right side view of the semiconductor device shown in FIG. 72. It is a front view of the semiconductor device shown in FIG. 72. FIG. 7 is a cross-sectional view taken along the line LXXVI-LXXVI of FIG. 72. It is sectional drawing when the semiconductor device shown in FIG. 72 is mounted on a wiring board.

An embodiment for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
The semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 5. The semiconductor device A10 includes a semiconductor element 11, an insulating layer 12, a plurality of terminals 2, a sealing resin 3, and a wire 4.

FIG. 1 is a plan view of the semiconductor device A10, and is transparent to the sealing resin 3 for convenience of understanding. In FIG. 1, the outer shape of the transmitted sealing resin 3 is shown by an imaginary line (dashed-dotted line). FIG. 5 is a cross-sectional view taken along the VV line (dotted chain line shown in FIG. 1) of FIG. Further, in FIGS. 1 to 5, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A10 shown in these figures is of a type that is surface-mounted on a wiring board of various electronic devices such as mobile phones. The semiconductor device A10 has a rectangular shape in the thickness direction Z view (hereinafter referred to as “planar view”) of the semiconductor element 11. Here, for convenience of explanation, the lateral direction of the semiconductor device A10 orthogonal to the thickness direction Z of the semiconductor element 11 (hereinafter, simply referred to as “thickness direction Z”) is the first direction X and the thickness direction. The longitudinal direction of the semiconductor device A10 orthogonal to both Z and the first direction X is referred to as the second direction Y.

The semiconductor element 11 is a central part of the function of the semiconductor device A10. As shown in FIG. 1, the semiconductor element 11 has a rectangular shape in a plan view. The semiconductor element 11 is a Hall element. Therefore, the semiconductor device A10 is a magnetic sensor (Hall IC). Further, the Hall element according to the present embodiment is a GaAs type Hall element. The GaAs type Hall element has an advantage that it is excellent in the linearity of the Hall voltage with respect to the change of the magnetic flux density and is not easily affected by the temperature change. As shown in FIG. 5, the semiconductor device 11 has a front surface 111 and a back surface 112 facing opposite sides in the thickness direction Z. The surface 111 is a surface covered with the sealing resin 3. In the present embodiment, a plurality of electrode pads (not shown) made of, for example, Al are formed on the surface 111. A wire 4 is connected to each electrode pad. The back surface 112 is a surface in contact with the insulating layer 12. Further, in the present embodiment, the magnetic sensing layer 113 for detecting the change in the magnetic flux density is formed in the vicinity of the back surface 112 of the semiconductor element 11.

As shown in FIGS. 1 and 5, the insulating layer 12 is a portion that is arranged in contact with the back surface 112 of the semiconductor element 11 and is an electrical insulator. The upper end of the insulating layer 12 shown in FIG. 5 is in contact with the back surface 112, and the lower end of the insulating layer 12 shown in FIG. 5 is exposed from the sealing resin 3. The insulating layer 12 is made of, for example, an epoxy resin or polyimide. The length (thickness) of the insulating layer 12 in the thickness direction Z is shorter than the length (thickness) of the base 21 described later.

As shown in FIGS. 1 to 5, the plurality of terminals 2 are conductors constituting a conductive path between the semiconductor element 11 and the wiring board on which the semiconductor device A10 is mounted. The plurality of terminals 2 are composed of four terminals 2A, 2B, 2C, and 2D. Terminal 2A is located at the upper right of FIG. Terminal 2B is located at the lower right of FIG. Terminal 2C is located at the lower left of FIG. It is located at the upper left of FIG. 1 of the terminal 2D. Also in the semiconductor devices A20 to A90 described later, the plurality of terminals 2 are composed of four terminals 2A, 2B, 2C, and 2D, and the positions of the plurality of terminals 2 according to each embodiment are all the positions of the semiconductor device A10. Is the same as. In this embodiment, each terminal 2 includes a base 21, a protrusion 22, a main surface conductive layer 281, a bottom conductive layer 282, and an internal conductive layer 29. Of these, the base portion 21 and the protruding portion 22 form the main portion of the terminal 2, the base portion 21 can be referred to as the “first portion” of the terminal 2, and the protruding portion 22 can be referred to as the “second portion” of the terminal 2. The main part of the terminal 2 is composed of, for example, an alloy containing Cu as a main component. Further, the terminal 2 has a first side surface 23 and a second side surface 24 in the main portion thereof. In the present embodiment, the terminal 2 is arranged so that both the first side surface 23 and the second side surface 24 are in contact with the corner of the semiconductor device A10 where the first direction X and the second direction Y intersect in a plan view.

As shown in FIG. 1, the base portion 21 is a main portion (first portion) of the terminal 2 which is arranged apart from the semiconductor element 11 and conducts to the surface 111 of the semiconductor element 11. In the present embodiment, the base 21 is conductive to the electrode pad formed on the surface 111 of the semiconductor element 11 via the wire 4. The base 21 according to this embodiment has a rectangular shape in a plan view. The base 21 has a terminal surface 211, a bottom surface 212, and a second inner surface 213. As shown in FIGS. 1 and 5, the terminal surface 211 is a surface facing the same direction as the surface 111 of the semiconductor element 11 and is covered with the sealing resin 3. In this embodiment, the wire 4 is conducting to the terminal surface 211. As shown in FIGS. 2 and 5, the bottom surface 212 is a surface facing the side opposite to the terminal surface 211 and is exposed from the sealing resin 3. As shown in FIGS. 3 and 5, the second inner surface 213 is formed so as to face the inside of the semiconductor device A10 in the second direction Y and along the thickness direction Z, and is connected to the terminal surface 211 and the bottom surface 212. It is a face. The second inner surface 213 is covered with the sealing resin 3.

As shown in FIGS. 1 and 5, the protruding portion 22 is a main portion (second portion) of the terminal 2 protruding from the terminal surface 211 of the base 21 in the direction in which the surface 111 of the semiconductor element 11 faces. The protruding portion 22 has a configuration supported by the terminal surface 211 of the base portion 21. In plan view, the area of the protrusion 22 is smaller than the area of the base 21. Further, the shape of the protruding portion 22 according to the present embodiment is a rectangular parallelepiped shape. The protrusion 22 has a main surface 221 and a first inner surface 222. As shown in FIGS. 1 and 3 to 5, the main surface 221 is a surface facing the same direction as the surface 111 of the semiconductor element 11 and is exposed from the sealing resin 3. As shown in FIGS. 3 and 5, the first inner surface 222 is a surface formed in parallel with the second inner surface 213 of the base portion 21 in a plan view and connected to the main surface 221 and the terminal surface 211 of the base portion 21. Therefore, the first inner surface 222 faces in the same direction as the second inner surface 213 of the base 21.

As shown in FIGS. 1 to 4, the first side surface 23 is a surface facing the first direction X and is exposed from the sealing resin 3. The shape of the first side surface 23 according to the present embodiment is an L shape. As shown in FIG. 3, in the second direction Y, the first side surface 23 is connected to the second side surface 24, the first inner surface 222 of the protrusion 22, and the second inner surface 213 of the base 21. Further, in the thickness direction Z, the first side surface 23 is connected to the main surface 221 of the protruding portion 22, the terminal surface 211 of the base portion 21, and the bottom surface 212.

As shown in FIGS. 1 to 5, the second side surface 24 is a surface facing the outside of the semiconductor device A10 in the second direction Y, and is exposed from the sealing resin 3. The second side surface 24 according to the present embodiment has a rectangular shape. The upper end of the second side surface 24 shown in FIG. 4 is connected to the main surface 221 of the protruding portion 22, and the lower end of the second side surface 24 shown in FIG. 4 is connected to the bottom surface 212 of the base portion 21. Therefore, as shown in FIG. 1, the first side surface 23 and the second side surface 24 are formed along the corners of the semiconductor device A10 in a plan view.

As shown in FIGS. 1, 3 to 5, the terminal 2 includes a main surface conductive layer 281 that covers the main surface 221 of the protrusion 22 and is exposed to the outside of the semiconductor device A10. The main surface conductive layer 281 according to the present embodiment is an alloy layer containing Sn. The alloy layer is a lead-free solder alloy such as a Sn—Sb based alloy or a Sn—Ag based alloy. Here, the main surface conductive layer 281 may be composed of a Ni layer laminated to each other and an alloy layer containing Sn. Further, the main surface conductive layer 281 may be composed of a Ni layer, a Pd layer and an Au layer laminated on each other. Further, the main surface conductive layer 281 may have a structure including a Pd layer and an Au layer laminated on each other, or a structure including an Au layer. In each of the configurations of the main surface conductive layer 281 including these Au layers, the Au layer is exposed to the outside.

As shown in FIGS. 2 to 5, the terminal 2 includes a bottom conductive layer 282 that covers the bottom surface 212 of the base 21. The structure of the bottom conductive layer 282 is the same as the structure of the main surface conductive layer 281. Therefore, the bottom conductive layer 282 is a conductor.

As shown in FIGS. 1, 3 and 5, the terminal 2 includes an internal conductive layer 29 that covers the terminal surface 211 of the base 21. The internal conductive layer 29 is an Ag layer. Further, as shown in FIGS. 3 and 5, in the present embodiment, the internal conductive layer 29, together with the terminal surface 211 of the base 21, has the bottom surface 212 and the second inner surface 213 of the base 21, and the protrusion 22. 1 Covers the inner surface 222.

As shown in FIGS. 2 to 5, the sealing resin 3 is a portion that covers the semiconductor element 11 and a part of the sealing resin 3. The sealing resin 3 is a thermosetting synthetic resin having electrical insulation, and the synthetic resin is, for example, a black epoxy resin. Further, the epoxy resin according to the present embodiment contains a glass frit. The sealing resin 3 has a first surface 31, a second surface 32, a third surface 33, and a fourth surface 34.

As shown in FIGS. 3 to 5, the first surface 31 is a surface facing the same direction as the surface 111 of the semiconductor element 11. In the present embodiment, the main surface 221 of the protrusion 22 is flush with the first surface 31.

As shown in FIGS. 2 to 5, the second surface 32 is a surface facing the opposite side to the first surface 31. In this embodiment, the bottom surface 212 of the base 21 is flush with the second surface 32. Further, the insulating layer 12 is exposed from the second surface 32.

As shown in FIGS. 2 and 3, the third surface 33 is a pair of surfaces that are connected to both the first surface 31 and the second surface 32, face the first direction X, and are separated from each other in the first direction X. Is. In this embodiment, the first side surface 23 of the terminal 2 is flush with the third surface 33.

As shown in FIGS. 2 and 4, the fourth surface 34 is a pair of surfaces that are connected to both the first surface 31 and the second surface 32, face the second direction Y, and are separated from each other in the second direction Y. Is. Each fourth surface 34 is connected to a pair of third surfaces 33 at both ends in the first direction X. In this embodiment, the second side surface 24 of the terminal 2 is flush with the fourth surface 34.

As shown in FIGS. 1 and 5, the wire 4 conducts the surface 111 of the semiconductor element 11 and the terminal surface 211 of the base 21 with each other. In the present embodiment, there are four wires 4 in the semiconductor device A10, and each wire 4 makes the electrode pad formed on the surface 111 and the terminal surface 211 mutually conductive. The wire 4 is composed of, for example, Au.

Next, an example of a circuit to which the semiconductor device A10 in which the semiconductor element 11 is a Hall element is applied will be described with reference to FIG. FIG. 6 is a block diagram of a circuit to which the semiconductor device A10 is applied.

As shown in FIG. 6, the circuit is composed of a semiconductor device A10, an integrated circuit 61, and a controlled object 62. Examples of the control target 62 include a light source of a display of a mobile phone, a DC motor, and the like. The integrated circuit 61 includes a device drive region 611, a voltage detection region 612, and a control region 613. The device drive region 611 is a region in which a hole current is passed through the magnetic sensitive layer 113 of the semiconductor element 11 of the semiconductor device A10. The voltage detection region 612 is a region for detecting the electromotive force (Hall voltage) appearing in the magnetic sensing layer 113 of the semiconductor element 11 due to the Hall effect. The control area 613 is an area for controlling the operation of the control target 62. Now, when the magnet 63 is brought close to the semiconductor device A10, the magnetic sensing layer 113 of the semiconductor element 11 detects a change in the magnetic flux density, and an electromotive force appears in the magnetic sensing layer 113 of the semiconductor element 11 due to the Hall effect. The electromotive force is detected by the voltage detection region 612. The voltage detection area 612 transmits this detection result to the control area 613. The control area 613 controls (starts, stops, etc.) the operation of the controlled object 62 based on the transmitted detection result.

Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 7 to 20.

7 to 11, FIGS. 13 to 16, and FIGS. 18 to 20 are cross-sectional views illustrating a method for manufacturing the semiconductor device A10, the cross-sectional positions thereof being the same as those in FIG. Regarding the thickness direction Z, the first direction X, and the second direction Y of the first base material 81 shown in FIGS. 7 to 20, the thickness direction Z, the first direction X shown in FIGS. 1 to 5. And corresponds to the second direction Y.

First, as shown in FIGS. 7 to 10, it has a front surface 811 and a back surface 812 facing opposite to each other in the thickness direction Z, and a base portion 814, a protruding portion 815, a penetrating portion 816, and an internal conductive layer 817 are formed. The first base material 81, which is the conductor, is prepared. The first base material 81 is an aggregate of terminals 2 of the semiconductor device A10. The first base material 81 is composed of an alloy containing Cu as a main component, and its thickness is 200 to 300 μm. Both the front surface 811 and the back surface 812 are uniform flat surfaces. The first base material 81 is prepared by the following steps.

First, a mask is formed on the first base material 81. As shown in FIG. 7, after forming the first resist layer 881 so as to cover the entire front surface 811 and the back surface 812 of the first base material 81, the first resist layer 881 covering the front surface 811 is exposed by photolithography.・ Develop. As a result, a mask is formed on the first base material 81. The first resist layer 881 is formed by applying a photosensitive resist with a spin coater (rotary coating device) or the like. Since the first resist layer 881 according to the present embodiment is of the positive type, the exposed portion of the first resist layer 881 is removed by the developer, and the surface 811 is exposed from the removed portion.

Next, as shown in FIG. 8, a recess 813 recessed from the surface 811 is formed in the first base material 81 by primary removal. The recess 813 is formed on the surface 811 not covered by the first resist layer 881. The primary removal according to this embodiment is performed by wet etching. The etching solution used for the primary removal is, for example, a mixed solution of _{sulfuric acid (H 2} SO ₄ ) and hydrogen peroxide (H ₂ O _2).

Next, the mask is formed again on the first base material 81 on which the recess 813 is formed. As shown in FIG. 9, after forming the second resist layer 882 so as to cover the entire front surface 811 and the back surface 812 of the first base material 81, the second resist layer 882 covering the front surface 811 is exposed by photolithography.・ Develop. As a result, the mask is formed again with respect to the first base material 81. The material and forming method of the second resist layer 882 are both the same as those of the first resist layer 881. At this time, the recess 813 is exposed from the second resist layer 882.

Then, as shown in FIG. 10, the base portion 814, the protruding portion 815, and the penetrating portion 816 are formed on the first base material 81 by secondary removal. The base portion 814, the protruding portion 815, and the penetrating portion 816 are formed in the recess 813 not covered by the second resist layer 882 and its vicinity thereof. The secondary removal according to the present embodiment is performed by wet etching in the same manner as the primary removal described above. The etching solution used for the secondary removal is the same as the etching solution used for the primary removal.

As shown in FIG. 10, the base portion 814 is a portion having a part of the back surface 812. The protruding portion 815 is a portion that protrudes from the base portion 814 toward the surface 811 and has a part of the surface 811. The penetrating portion 816 is a portion that penetrates the first base material 81 from the front surface 811 to the back surface 812. After forming the base portion 814, the protruding portion 815 and the penetrating portion 816 on the first base material 81, the internal conductive layer 817 is formed on the first base material 81 by electrolytic plating. The internal conductive layer 817 corresponds to the internal conductive layer 29 of the semiconductor device A10. The internal conductive layer 817 according to this embodiment is an Ag layer. At this time, the front surface 811, the back surface 812, the base portion 814, and the protruding portion 815 of the first base material 81 are covered with the internal conductive layer 817. The first base material 81 is prepared by the above steps.

Next, as shown in FIG. 11, a second base material 82, which is an electrical insulator that supports the first base material 81, is prepared from the back surface 812. The second base material 82 according to the present embodiment is, for example, an insulating tape. By attaching the second base material 82 to the back surface 812 of the first base material 81, the first base material 81 is in a state of being supported by the second base material 82. At this time, the second base material 82 has an exposed portion 821 exposed from the penetrating portion 816 of the first base material 81.

In the step of preparing the first base material 81 and the second base material 82, in addition to the step of preparing the second base material 82 after preparing the first base material 81 as described above, the second base material 82 is prepared. After that, it may be a step of preparing the first base material 81. In this case, the second base material 82 is attached to the back surface 812 instead of the first resist layer 881 formed by covering the back surface 812 of the first base material 81 shown in FIG. 7. By taking this step, the formation of the first resist layer 881 and the second resist layer 882 covering the back surface 812 of the first base material 81 is omitted, respectively. Further, the back surface 812 of the first base material 81 is not covered with the internal conductive layer 817.

FIG. 12 shows a state when the first base material 81 and the second base material 82 are prepared. As shown in FIG. 12, the portion surrounded by the region 89 of the first base material 81 is the portion to be the terminal 2 of the semiconductor device A10. Further, on the surface 811 of the first base material 81, the exposed portion 821 of the second base material 82 is visually recognized from the penetrating portion 816.

Next, as shown in FIG. 13, the semiconductor element 831 is mounted on the exposed portion 821 of the second base material 82. The semiconductor element 831 corresponds to the semiconductor element 11 of the semiconductor device A10. In mounting the semiconductor element 831, first, the bonding material 832, which is an electrical insulator, is applied to the exposed portion 821 of the second base material 82. The bonding material 832 according to the present embodiment is a synthetic resin having electrical insulating properties such as epoxy resin and polyimide. Next, the semiconductor element 831 adsorbed by the collet or the like is transferred onto the exposed portion 821 of the second base material 82 and adhered to the bonding material 832. Finally, the bonding material 832 is thermoset in a curing furnace or the like. At this time, the thermosetting bonding material 832 corresponds to the insulating layer 12 of the semiconductor device A10. Therefore, the semiconductor element 831 is mounted on the exposed portion 821 of the second base material 82 by interposing the bonding material 832 between the exposed portion 821 of the second base material 82 and the semiconductor element 831.

Next, as shown in FIG. 14, a wire 84 that conducts the semiconductor element 831 and the base portion 814 of the first base material 81 is formed. The wire 84 corresponds to the wire 4 of the semiconductor device A10. The wire 84 is formed by wire bonding. The material of the wire 84 according to this embodiment is, for example, Au.

Next, as shown in FIG. 15, a sealing resin 85 that covers the first base material 81 and the semiconductor element 831 is formed. The sealing resin 85 corresponds to the sealing resin 3 of the semiconductor device A10. The sealing resin 85 according to the present embodiment is formed by thermosetting a black epoxy resin having electrical insulation and fluidity and containing glass frit by transfer molding. At this time, the sealing resin 85 covers the base portion 814 and the protruding portion 815 of the first base material 81, and is in a state of being filled in the penetrating portion 816 of the first base material 81.

Next, a part of each of the sealing resin 85 and the protruding portion 815 of the first base material 81 is removed to expose the protruding portion 815 of the first base material 81 from the sealing resin 85. In the present embodiment, the protrusion 815 of the first base material 81 and the sealing resin 85 are uniformly ground by mechanical polishing from the opposite side of the back surface 812 of the first base material 81, so that the first base material 81 protrudes. A part of each of the part 815 and the sealing resin 85 is removed. 16 and 17 show a state in which the protrusion 815 of the first base material 81 is exposed from the sealing resin 85. As shown in FIG. 17, on the opposite side of the back surface 812 of the first base material 81, the rectangular protruding portion 815 of the first base material 81 is visually recognized from the sealing resin 85.

Then, as shown in FIG. 18, the second base material 82 is removed from the first base material 81. At this time, the back surface 812 of the first base material 81 covered with the internal conductive layer 817 is exposed, and the cured bonding material 832 and the sealing resin 85 are exposed from the penetrating portion 816 on the back surface 812.

Next, as shown in FIG. 19, a conductive layer 86 that covers the protrusion 815 of the first base material 81 exposed from the sealing resin 85 is formed. The conductive layer 86 covering the protrusion 815 corresponds to the main surface conductive layer 281 of the semiconductor device A10. In this embodiment, the conductive layer 86 is formed by electrolytic plating. Further, although the conductive layer 86 according to the present embodiment is obtained by precipitating an alloy layer containing Sn, it may be formed by precipitating a Ni layer and an alloy layer containing Sn in this order. Further, the conductive layer 86 may be formed by precipitating the Ni layer, the Pd layer, and the Au layer in this order, further, precipitating the Pd layer and the Au layer in this order, or precipitating the Au layer. In these cases, the outermost layer of the conductive layer 86 is an alloy layer or Au layer containing Sn. At this time, since the back surface 812 of the first base material 81 is exposed from the sealing resin 85 in a state of being covered with the internal conductive layer 817, the conductive layer 86 covering the back surface 812 is also formed. The conductive layer 86 covering the back surface 812 corresponds to the bottom surface conductive layer 282 of the semiconductor device A10. Therefore, in the semiconductor device A10, the configuration of the bottom conductive layer 282 is the same as the configuration of the main surface conductive layer 281.

Then, the first base material 81 and the sealing resin 85 are divided into individual pieces by cutting along the first direction X and the second direction Y. For cutting, for example, a dicing saw is used to cut from the back surface 812 of the first base material 81. In the present embodiment, when the first base material 81 and the sealing resin 85 are cut along the first direction X, the portion surrounded by the cutting line CL shown by the imaginary line in FIG. 20 is removed. The pieces divided in the process form the semiconductor device A10. Through the above steps, the semiconductor device A10 is manufactured.

Next, the mounting structure of the semiconductor device A10 in which the semiconductor element 11 is a Hall element will be described with reference to FIG. The cross-sectional position of FIG. 21 is the same as that of FIG.

As shown in FIG. 21, when the semiconductor device A10 is mounted on the wiring board 71 on which the wiring pattern is formed by the reflow method, the semiconductor device A10 is mounted on the wiring board 71 between the protrusion 22 and the wiring board 71. The conductive bonding layer 72 of the above is interposed. The conductive bonding layer 72 is, for example, cream solder. At this time, the main surface 221 of the protrusion 22 and the first surface 31 of the sealing resin 3 both face the wiring board 71. When the main surface conductive layer 281 covering the main surface 221 is an alloy layer containing Sn, the main surface conductive layer 281 is melted and fused with the conductive bonding layer 72.

Next, the semiconductor device A10 and its manufacturing method, and the operation and effect of the mounting structure of the semiconductor device A10 will be described.

The semiconductor device A10 covers the semiconductor element 11 having a surface 111, a plurality of terminals 2 arranged apart from the semiconductor element 11 and having a base portion 21 and a protruding portion 22, and the same as the surface 111. A sealing resin 3 having a first surface 31 facing a direction is provided. The projecting portion 22 projects from the base portion 21 in the direction in which the surface 111 faces, and has a main surface 221 that is flush with the first surface 31. Further, the terminal 2 includes a main surface conductive layer 281 that covers the main surface 221. By adopting this configuration, it is possible to further reduce the height of the semiconductor device A10.

The main surface conductive layer 281 included in the terminal 2 of the semiconductor device A10 is an alloy layer containing Sn. In this case, as shown in FIG. 21, since the main surface conductive layer 281 is melted and integrated with the conductive bonding layer 72, the mounting strength of the semiconductor device A10 on the wiring board 71 can be ensured. Further, by configuring the main surface conductive layer 281 as an alloy layer containing a Ni layer and Sn laminated on each other, the terminal 2 can be protected from thermal shock in the mounting of the semiconductor device A10. Further, by forming the main surface conductive layer 281 to be a Ni layer, a Pd layer, and an Au layer laminated with each other, the conductive bonding layer with respect to the terminal 2 is protected from thermal shock in the mounting of the semiconductor device A10. The wettability of 72 can be improved.

The terminal 2 of the semiconductor device A10 has a first side surface 23 facing the first direction X and a second side surface 24 facing the second direction Y. Further, the sealing resin 3 of the semiconductor device A10 has a third surface 33 facing the first direction X and a fourth surface 34 facing the second direction Y. The first side surface 23 is flush with the third surface 33, and the second side surface 24 is flush with the fourth surface 34. By adopting this configuration, the dimensions of the sealing resin 3 in a plan view are reduced, which contributes to the miniaturization of the apparatus.

The semiconductor device A10 is arranged in contact with the back surface 112 facing the front surface 111 of the semiconductor element 11, and includes an insulating layer 12 which is an electrical insulator. The insulating layer 12 is exposed from the second surface 32 of the sealing resin 3. Further, the length (thickness) of the insulating layer 12 in the thickness direction Z is shorter than the length (thickness) of the base 21. By adopting this configuration, the length between the surface 111 and the second surface 32 is shortened in the thickness direction Z, which contributes to lowering the height of the apparatus.

The terminal 2 of the semiconductor device A10 is formed with an internal conductive layer 29 that covers the terminal surface 211 of the base 21. The internal conductive layer 29 can protect the terminal 2 from the thermal shock generated when the wire 4 is conducted to the terminal surface 211.

The sealing resin 3 of the semiconductor device A10 is an epoxy resin containing a glass frit. By applying such a sealing resin 3, it is possible to increase the strength of the sealing resin 3 and suppress the occurrence of cracks in the sealing resin 3.

Further, the method for manufacturing the semiconductor device A10 includes a step of exposing the protruding portion 815 of the first base material 81 from the sealing resin 85 before the step of forming the conductive layer 86. In this step, a part of the protruding portion 815 of the first base material 81 and a part of the sealing resin 85 are removed by mechanical polishing. Therefore, the height of the protruding portion 815 of the first base material 81 (the length of the first base material 81 in the thickness direction Z) can be made as low as possible within a range in which the wire 84 is not damaged. It is possible to manufacture the semiconductor device A10 with a low profile. Further, the thickness of the protruding portion 815 of the first base material 81 can be freely adjusted.

According to the manufacturing method of the semiconductor device A10, even when a part of the protruding portion 815 is removed from the first base material 81, as shown in FIG. 17, the first base material 81 is first by the base portion 814. Continuity is ensured in both directions X and the second direction Y. Therefore, the conductive layer 86 can be formed by electrolytic plating.

In the method for manufacturing the semiconductor device A10, a first base material 81 on which a penetration portion 816 from the front surface 811 to the back surface 812 is formed and a second base material 82 that supports the first base material 81 from the back surface 812 are prepared. It has a process. By providing this step, the semiconductor element 831 can be mounted on the exposed portion 821 of the second base material 82 exposed from the penetrating portion 816, so that the semiconductor device A10 can be manufactured. Further, since the sealing resin 85 is formed in a state where the first base material 81 is reinforced against bending by the second base material 82, the warp generated in the first base material 81 due to the curing shrinkage of the sealing resin 85. The rise can be suppressed.

Further, according to the mounting structure of the semiconductor device A10, when the semiconductor device A10 is mounted on the wiring board 71, the main surface 221 of the protruding portion 22 and the first surface 31 of the sealing resin 3 both face the wiring board 71. By adopting this configuration, when the semiconductor element 11 is a Hall element, the distance between the magnet 63 arranged outside and the semiconductor element 11 shown in FIG. 6 becomes closer, so that the change in the magnetic flux density can be detected by the semiconductor device A10. The accuracy is improved. Further, when the magnetic sensing layer 113 of the semiconductor element 11 is formed close to the back surface 112, such a mounting structure further improves the detection accuracy of the change in the magnetic flux density by the semiconductor device A10.

[Second Embodiment]
The semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. 22 to 26. Here, FIG. 22 is a plan view of the semiconductor device A20, and is transmitted through the sealing resin 3 for convenience of understanding. In FIG. 22, the outer shape of the transmitted sealing resin 3 is shown by an imaginary line. FIG. 25 is a cross-sectional view taken along the line XXV-XXV of FIG. 22 (the alternate long and short dash line shown in FIG. 22). Further, in FIGS. 22 to 25, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A20 has a configuration of the plurality of terminals 2 and the sealing resin 3 different from that of the semiconductor device A10 described above. As shown in FIG. 22, the semiconductor device A20 has a rectangular shape in a plan view. In the present embodiment as well, as in the semiconductor device A10, the terminal 2 is such that both the first side surface 23 and the second side surface 24 are in contact with the corner of the semiconductor device A20 where the first direction X and the second direction Y intersect in a plan view. Is placed.

As shown in FIGS. 23 to 25, the second side surface 24 of the terminal 2 includes an inner side surface 241 and an outer side surface 242. The inner side surface 241 and the outer side surface 242 both face the second direction Y and are connected to the first side surface 23. The inner side surface 241 is a surface connected to the main surface 221 of the protrusion 22. The outer side surface 242 is a surface that protrudes to the outside of the semiconductor device A20 from the inner side surface 241 and is connected to the bottom surface 212 of the base portion 21. Further, as shown in FIG. 26, the second side surface 24 further includes an intermediate surface 243. The intermediate surface 243 is a surface in which one end is connected to the inner side surface 241 and the other end is connected to the outer surface 242 in the thickness direction Z. The intermediate surface 243 is a curved surface facing the main surface 221 side (upper side of FIG. 26) of the protrusion 22.

As shown in FIGS. 22 to 26, the terminal 2 includes a side conductive layer 283 that covers the inner side surface 241. The configuration of the side conductive layer 283 is the same as the configuration of the main surface conductive layer 281. Therefore, the side conductive layer 283 is a conductor.

As shown in FIGS. 23 to 25, the inner side surface 241 and the outer side surface 242 and the intermediate surface 243 are continuously connected to the fourth surface 34 of the sealing resin 3, respectively. Therefore, the inner surface 241 and the outer surface 242 and the intermediate surface 243 do not have a step between the inner surface 241 and the fourth surface 34 in the first direction X.

Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to FIGS. 27 to 30.

28 to 30 are cross-sectional views illustrating a method for manufacturing the semiconductor device A20, the cross-sectional positions thereof being the same as those in FIG. 25. Regarding the thickness direction Z, the first direction X, and the second direction Y of the first base material 81 shown in FIGS. 27 to 30, the thickness direction Z and the first direction X shown in FIGS. 22 to 26. And corresponds to the second direction Y.

First, the first base material 81 and the second base material 82 are prepared. Since this step is the same as the step of preparing the first base material 81 and the second base material 82 in the manufacture of the semiconductor device A10 shown in FIGS. 7 to 12, the description thereof is omitted here. Therefore, the first base material 81 according to the present embodiment is formed with a base portion 814, a protruding portion 815, a penetrating portion 816, and an internal conductive layer 817. Further, the second base material 82 has an exposed portion 821 that supports the first base material 81 from the back surface 812 and is exposed from the penetrating portion 816.

Next, the semiconductor element 831 is mounted on the exposed portion 821 of the second base material 82. Since this step is the same as the step of mounting the semiconductor element 831 in the manufacture of the semiconductor device A10 shown in FIG. 13, the description thereof is omitted here.

Next, a wire 84 that conducts the semiconductor element 831 and the base portion 814 of the first base material 81 is formed. Since this step is the same as the step of forming the wire 84 in the manufacturing of the semiconductor device A10 shown in FIG. 14, the description thereof is omitted here.

Next, the sealing resin 85 that covers the first base material 81 and the semiconductor element 831 is formed. Since this step is the same as the step of forming the sealing resin 85 in the production of the semiconductor device A10 shown in FIG. 15, the description thereof is omitted here.

Next, a part of each of the protruding portion 815 and the sealing resin 85 of the first base material 81 is removed to expose the protruding portion 815 from the sealing resin 85. Since this step is the same as the step of exposing the protruding portion 815 of the first base material 81 from the sealing resin 85 in the production of the semiconductor device A10 shown in FIGS. 16 and 17, the description thereof is omitted here.

Next, as shown in FIGS. 27 and 28, a groove 87 extending in the first direction X is formed on the first base material 81 from the opposite side of the back surface 812. For forming the groove 87, for example, a dicing saw is used. In FIG. 27, the portion surrounded by the imaginary line is the formation range of the groove 87. As shown in FIG. 28, a part of the protrusion 815 of the first base material 81 is removed with the formation of the groove 87. In the present embodiment, with the formation of the groove 87, a part of the base portion 814 of the first base material 81 and a part of the sealing resin 85 are further removed. The groove 87 is formed so as to have a width W1 (length in the second direction Y) shown in FIG. 28. In this embodiment, the groove 87 does not penetrate the base portion 814 in the thickness direction Z of the first base material 81.

Next, as shown in FIG. 29, the conductive layer 86 that covers the protruding portion 815 of the first base material 81 exposed from the sealing resin 85 is formed. In the present embodiment, the conductive layer 86 that covers the portion of the first base material 81 exposed by the formation of the groove 87 is formed. The conductive layer 86 covering the portion corresponds to the side conductive layer 283 of the semiconductor device A10. The configuration and formation method of the conductive layer 86 according to the present embodiment is the same as the configuration and formation method of the conductive layer 86 according to the manufacture of the semiconductor device A10. Therefore, in the semiconductor device A10, the configuration of the side conductive layer 283 is the same as the configuration of the main surface conductive layer 281.

Then, the first base material 81 and the sealing resin 85 are divided into individual pieces by cutting along the first direction X and the second direction Y. For cutting, for example, a dicing saw is used to cut from the back surface 812 of the first base material 81. In the present embodiment, when the first base material 81 and the sealing resin 85 are cut along the first direction X, the portion surrounded by the cutting line CL shown by the imaginary line in FIG. 30 is removed. At this time, the width W2 (length in the second direction Y) of the cutting line CL is set to be shorter than the width W1 of the groove 87. The pieces divided in the process form the semiconductor device A20. Through the above steps, the semiconductor device A20 is manufactured.

Next, the effects of the semiconductor device A20 and its manufacturing method will be described.

Similar to the semiconductor device A10 described above, the semiconductor device A20 includes a semiconductor element 11 having a surface 111, a plurality of terminals 2 arranged apart from the semiconductor element 11 and having a base 21 and a protruding portion 22, and a semiconductor element 11. It is provided with a sealing resin 3 for covering the above. The sealing resin 3 has a first surface 31 that faces in the same direction as the surface 111. Further, the protruding portion 22 protrudes from the base portion 21 in the direction in which the surface 111 faces, and has a main surface 221 that is flush with the first surface 31. Further, the terminal 2 includes a main surface conductive layer 281 that covers the main surface 221. Therefore, it is possible to further reduce the height of the semiconductor device A20.

The terminal 2 of the semiconductor device A20 includes a side conductive layer 283 that covers the inner side surface 241 included in the second side surface 24. By adopting this configuration, when the semiconductor device A20 is mounted on the wiring board by the reflow method, the formation of the solder fillet on the inner side surface 241 can be promoted. Therefore, it is possible to improve the mounting strength of the semiconductor device A20 on the wiring board as compared with the semiconductor device A10.

The second side surface 24 of the terminal 2 of the semiconductor device A20 includes an outer surface 242 projecting to the outside of the semiconductor device A20 from the inner side surface 241. The outer side surface 242 is used to prevent cutting of the conductive layer 86 that covers the portion of the first base material 81 exposed by the formation of the groove 87 when cutting the first base material 81 and the sealing resin 85 in the manufacture of the semiconductor device A20. It was formed in.

Further, the manufacturing method of the semiconductor device A20 also includes a step of exposing the protruding portion 815 of the first base material 81 from the sealing resin 85 before the step of forming the conductive layer 86. In this step, a part of the protruding portion 815 of the first base material 81 and a part of the sealing resin 85 are removed by mechanical polishing. Therefore, the thickness of the protrusion 815 of the first base material 81 can be made as thin as possible within a range that does not damage the wire 84, so that the semiconductor device A20 can be manufactured.

The method for manufacturing the semiconductor device A20 includes a step of forming a groove 87 extending in the first direction X on the first base material 81 from the opposite side of the back surface 812 before the step of forming the conductive layer 86. By providing such a step, in the step of forming the conductive layer 86, the side conductive layer 283 that covers the inner side surface 241 of the semiconductor device A20 can be formed.

According to the manufacturing method of the semiconductor device A20, even when the groove 87 is formed, the first base material 81 is in a state where conduction is ensured in both directions of the first direction X and the second direction Y by the base portion 814. Become. Therefore, the conductive layer 86 can also be formed by electrolytic plating depending on the manufacturing method of the semiconductor device A20.

[Third Embodiment]
The semiconductor device A30 according to the third embodiment of the present invention will be described with reference to FIGS. 31 to 38. Here, FIG. 31 is a plan view of the semiconductor device A30, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. FIG. 35 is a cross-sectional view taken along the line XXXV-XXXV of FIG. 31 (the alternate long and short dash line shown in FIG. 31). Further, in FIGS. 31 to 35, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A30 is different from the semiconductor device A10 described above in that the configuration of the plurality of terminals 2 and the provision of the heat radiating layer 13 and the insulating film 5 are provided. As shown in FIG. 31, the semiconductor device A30 has a rectangular shape in a plan view. The configuration of the semiconductor element 11 according to the present embodiment is the same as the configuration of the semiconductor element 11 of the semiconductor device A10. The main parts (base 21 and protrusion 22) of the terminal 2 according to the present embodiment are made of Cu or an alloy containing Cu as a main component. Also in this embodiment, the main surface 221 of the protruding portion 22 is flush with the first surface 31 of the sealing resin 3, as in the semiconductor device A10.

As shown in FIGS. 31, 32 and 34, the terminal 2 has a first side surface 23 facing outward of the semiconductor device A30 in the first direction X. Further, the terminal 2 has a second side surface 24 facing the outside of the semiconductor device A30 in the second direction Y. At the corner of the semiconductor device A30 where the first direction X and the second direction Y intersect, the second side surface 24 intersects the first side surface 23. Therefore, the terminal 2 is arranged so that both the first side surface 23 and the second side surface 24 are in contact with the corner of the semiconductor device A30 where the first direction X and the second direction Y intersect in a plan view. Also in this embodiment, as in the semiconductor device A10, the first side surface 23 is flush with the third surface 33 of the sealing resin 3, and the second side surface 24 is flush with the fourth surface 34 of the sealing resin 3. It is flush.

As shown in FIGS. 31, 33 and 35, the protrusion 22 of the terminal 2 has a first inner surface 222 that is separated from the second side surface 24 in the second direction Y and intersects the main surface 221. Further, the base portion 21 of the terminal 2 has a second inner surface 213 which is separated from the second side surface 24 in the second direction Y, is connected to the first inner surface 222, and intersects the bottom surface 212. In the present embodiment, unlike the semiconductor device A10, the terminal surface 211 is omitted in the base 21. Both the first inner surface 222 and the second inner surface 213 are curved surfaces. The first inner surface 222 and the second inner surface 213 are connected to each other by a continuous curved surface. The first inner surface 222 and the second inner surface 213 both intersect the first side surface 23 in the first direction X.

As shown in FIG. 36, in the terminal 2, the inflection point IP exists at the boundary between the first inner surface 222 and the second inner surface 213 that intersect the first side surface 23. In the present embodiment, the plane S arranged along the first direction X and the second direction Y and passing through the boundary is defined as the boundary between the base portion 21 and the protruding portion 22. In a plan view, the locus through which the inflection point IP passes is shown by a two-dot chain line in FIG. Further, each curved section where the first inner surface 222 and the second inner surface 213 intersect with the first side surface 23 is an arc. In the present embodiment, the radius of curvature r1 of the curved section of the first inner surface 222 is larger than the radius of curvature r2 of the curved section of the second inner surface 213.

As shown in FIGS. 33 and 35, the terminal 2 includes an internal conductive layer 29 that covers the first inner surface 222 and the second inner surface 213. The internal conductive layer 29 is an Ag layer. Further, in the present embodiment, the internal conductive layer 29 also covers the bottom surface 212 of the base portion 21. The internal conductive layer 29 may be configured not to cover the bottom surface 212.

As shown in FIG. 35, the wire 4 makes the surface 111 of the semiconductor element 11 and the first inner surface 222 of the terminal 2 (protruding portion 22) conductive to each other. The wire 4 may be configured to be conductive to both the first inner surface 222 and the second inner surface 213 of the terminal 2 (base 21). In the present embodiment, in the wire 4, the first connecting portion 41 is connected to the internal conductive layer 29 covering the first inner surface 222, and the second connecting portion 42 is connected to the electrode pad formed on the surface 111. Here, the first connection portion 41 is a so-called ball bonding portion. The second connection portion is a so-called Stitch Bonding portion. The wire 4 has a connection form opposite to this, that is, a connection in which the first connection portion 41 is connected to the electrode pad formed on the surface 111, and the second connection portion 42 is connected to the internal conductive layer 29 covering the first inner surface 222. It may be in the form. The material constituting the wire 4 according to the present embodiment is the same as that of the wire 4 of the semiconductor device A10.

The main surface conductive layer 281 according to the present embodiment is an Ag layer. Further, the main surface conductive layer 281 may be composed of a Ni layer, a Pd layer and an Au layer laminated on each other. Further, the main surface conductive layer 281 may have a structure including a Pd layer and an Au layer laminated on each other, or a structure including an Au layer. In each of the configurations of the main surface conductive layer 281 including these Au layers, the Au layer is exposed to the outside. In this embodiment, unlike the semiconductor device A10, the terminal 2 does not include the bottom conductive layer 282.

As shown in FIG. 35, the semiconductor device A30 includes a heat dissipation layer 13 provided in contact with the back surface 112 of the semiconductor element 11. The heat radiating layer 13 is a conductor. The heat radiating layer 13 according to the present embodiment is made of a conductive die attach film. The heat radiating layer 13 may be made of a die attach paste (so-called Ag paste) containing Ag. The heat radiating layer 13 is exposed from the second surface 32 of the sealing resin 3. The exposed surface 131 of the heat radiating layer 13 exposed from the sealing resin 3 is flush with the second surface 32.

As shown in FIGS. 31, 32 and 35, when the heat radiating layer 13 is made of a die attach film, the position of the peripheral edge of the heat radiating layer 13 is the same as the position of the peripheral edge of the semiconductor element 11 in a plan view. As shown in FIG. 37, when the heat radiating layer 13 is composed of Ag paste, the peripheral edge of the heat radiating layer 13 has a section located inside the peripheral edge of the semiconductor element 11 in a plan view.

As shown in FIGS. 31 to 35, the semiconductor device A30 is provided in contact with the second surface 32 of the sealing resin 3 and includes an insulating film 5 having electrical insulating properties. Both the bottom surface 212 of the plurality of terminals 2 and the exposed surface 131 of the heat radiating layer 13 are covered with the insulating film 5. The insulating film 5 is made of a film material or a synthetic resin paste. The film material contains, for example, polyimide or polyamide-imide as a component thereof. The synthetic resin paste contains, for example, an epoxy resin or a silicone resin as a component thereof.

FIG. 38 shows the mounting structure of the semiconductor device A30 (the cross-sectional position is the same as that of FIG. 35). When the semiconductor device A30 is mounted on the wiring board 71 by the reflow method, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 for mounting the semiconductor device A30 on the wiring board 71 is provided. It faces the main surface conductive layer 281 (contacts in this embodiment). The conductive bonding layer 72 is made of, for example, cream solder.

Next, the effects of the semiconductor device A30 and the mounting structure of the semiconductor device A30 will be described.

The semiconductor device A30 includes a semiconductor element 11 having a surface 111, a plurality of terminals 2 having a base 21 separated from the semiconductor element 11 and conducting conduction to the surface 111, and a sealing resin 3 covering the semiconductor element 11. The terminal 2 includes a protrusion 22 that protrudes from the base 21 in the direction in which the surface 111 faces. The sealing resin 3 has a first surface 31 facing in the same direction as the surface 111, and the main surface 221 of the protrusion 22 is exposed from the first surface 31. In this configuration, when the semiconductor device A30 is manufactured, the height of the protruding portion 22 (thickness direction) is used when a part of the sealing resin 3 located on the side opposite to the semiconductor element 11 in the thickness direction Z is removed. It is established by making the length of Z) as low as possible (see FIG. 16). Therefore, by adopting this configuration, it is possible to further reduce the height of the semiconductor device A30.

The semiconductor device A30 includes a heat dissipation layer 13 provided in contact with the back surface 112 of the semiconductor element 11. The heat radiating layer 13 is exposed from the second surface 32 of the sealing resin 3. By adopting this configuration, the heat generated from the semiconductor element 11 when the semiconductor device A30 is used can be efficiently discharged to the outside of the semiconductor device A30.

The semiconductor device A30 includes an insulating film 5 provided in contact with the second surface 32 of the sealing resin 3. The insulating film 5 covers the bottom surface 212 of the plurality of terminals 2 and the exposed surface 131 of the heat radiating layer 13. By adopting this configuration, a short circuit caused by the conductive bonding layer 72 coming into contact with a plurality of terminals 2 when the semiconductor device A30 is mounted on the wiring board 71, and a leakage current from the semiconductor element 11 when the semiconductor device A30 is used. Can be prevented from leaking.

In the terminal 2 of the semiconductor device A30, both the first inner surface 222 of the protruding portion 22 and the second inner surface 213 of the base portion 21 are curved surfaces. By adopting this configuration, the stress concentration acting on the sealing resin 3 is relaxed as compared with the semiconductor device A10, so that the generation of cracks in the sealing resin 3 can be suppressed.

Further, the first inner surface 222 and the second inner surface 213 are connected to each other by a continuous curved surface. At the same time, in the terminal 2, the inflection point IP exists at the boundary between the first inner surface 222 and the second inner surface 213 that intersect the first side surface 23. By adopting this configuration, the vicinity of the boundary between the first inner surface 222 and the second inner surface 213 becomes a substantially flat surface. Therefore, in conducting the wire 4 to the first inner surface 222, from the viewpoint of the bondability of the wire 4. It can be said that it is suitable.

According to the mounting structure of the semiconductor device A30, when the semiconductor device A30 is mounted on the wiring board 71, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 is the main surface conductive layer 281. Facing. By adopting this configuration, when the semiconductor element 11 is a Hall element, the distance between the magnet 63 arranged outside and the semiconductor element 11 shown in FIG. 6 becomes closer, so that the change in the magnetic flux density can be detected by the semiconductor device A30. The accuracy is improved. The main surface conductive layer 281 according to the present embodiment is an Ag layer. Therefore, the main surface conductive layer 281 has an effect of protecting the terminal 2 from the thermal shock caused by the conductive bonding layer 72 in the mounting of the semiconductor device A30.

[Modified example of the third embodiment]
A semiconductor device A31 according to a modified example of the third embodiment of the present invention will be described with reference to FIGS. 39 to 41. Here, FIG. 40 is a cross-sectional view of the semiconductor device A31, and the cross-sectional position thereof is the same as that of FIG. 35.

The semiconductor device A31 is different from the above-mentioned semiconductor device A30 in that the insulating film 5 is not provided. As shown in FIGS. 39 and 40, on the first surface 31 of the sealing resin 3, the exposed surface 131 of the heat radiating layer 13 and the plurality of terminals 2 are both exposed to the outside of the semiconductor device A31. In this modification, the terminal 2 includes a bottom conductive layer 282 together with a main surface conductive layer 281.

FIG. 41 shows the mounting structure of the semiconductor device A31 (the cross-sectional position is the same as that of FIG. 40). The mounting structure of the semiconductor device A31 is the same as that of the semiconductor device A30 shown in FIG. 38.

The semiconductor device A31 has the same configuration as the semiconductor device A30 in that the semiconductor element 11, the plurality of terminals 2, and the sealing resin 3 are configured. Therefore, it is possible to further reduce the height of the semiconductor device A31. Further, since the semiconductor device A31 does not include the insulating film 5, the exposed surface 131 of the heat radiation layer 13 is exposed to the outside of the semiconductor device A31. Therefore, the heat dissipation efficiency of the semiconductor device A31 can be improved as compared with the semiconductor device A30.

[Fourth Embodiment]
The semiconductor device A40 according to the fourth embodiment of the present invention will be described with reference to FIGS. 42 to 47. Here, FIG. 42 is a plan view of the semiconductor device A40, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. FIG. 45 is a cross-sectional view taken along the XLV-XLV line (dotted chain line shown in FIG. 42) of FIG. 42. Further, in FIGS. 42 to 45, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A40 has a configuration of the plurality of terminals 2 different from that of the semiconductor device A30 described above. As shown in FIG. 42, the semiconductor device A40 has a rectangular shape in a plan view. Further, also in the present embodiment, as in the semiconductor device A30, both the first side surface 23 and the second side surface 24 are in contact with the corners of the semiconductor device A40 where the first direction X and the second direction Y intersect in a plan view. Terminal 2 is arranged.

As shown in FIGS. 42 to 45, the terminal 2 includes an external conductive layer 27 that covers the first side surface 23, the second side surface 24, and the main surface conductive layer 281. The external conductive layer 27 can be formed, for example, by barrel plating. The external conductive layer 27 according to the present embodiment is an alloy layer containing Sn. The alloy layer is a lead-free solder alloy such as a Sn—Sb based alloy or a Sn—Ag based alloy. Further, the external conductive layer 27 may be composed of a Ni layer laminated to each other and an alloy layer containing Sn.

FIG. 46 shows the first form of the mounting structure of the semiconductor device A40 (the cross-sectional position is the same as that of FIG. 45). When the semiconductor device A40 is mounted on the wiring board 71 by the reflow method, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 faces the main surface conductive layer 281. In the present embodiment, a part of the conductive bonding layer 72 wraps around directly under the external conductive layer 27 that covers the main surface conductive layer 281, and further, with respect to the main surface conductive layer 281, with each of the first side surface 23 and the second side surface 24. The conductive bonding layer 72 reaches the external conductive layer 27 located on the opposite side.

FIG. 47 shows a second form of the mounting structure of the semiconductor device A40 (the cross-sectional position is the same as that of FIG. 45). When the semiconductor device A40 is mounted on the wiring board 71 by the reflow method, the insulating film 5 faces the wiring board 71 and the conductive bonding layer 72 is in contact with the external conductive layer 27. In the present embodiment, the insulating film 5 is in contact with the wiring board 71.

Next, the effects of the semiconductor device A40 and the mounting structure of the semiconductor device A40 will be described.

Similar to the semiconductor device A30 described above, the semiconductor device A40 includes a semiconductor element 11 having a surface 111, a base portion 21 separated from the semiconductor element 11, and a plurality of terminals 2 conductive to the surface 111, and covers the semiconductor element 11. It is provided with a sealing resin 3. The terminal 2 includes a protrusion 22 that protrudes from the base 21 in the direction in which the surface 111 faces. The sealing resin 3 has a first surface 31 facing in the same direction as the surface 111, and the main surface 221 of the protrusion 22 is exposed from the first surface 31. Therefore, it is possible to further reduce the height of the semiconductor device A40.

The terminal 2 of the semiconductor device A40 includes an external conductive layer 27 that covers the first side surface 23, the second side surface 24, and the main surface conductive layer 281. By adopting this configuration, the conductive bonding layer 72 comes into contact with the external conductive layer 27, so that the second form of the mounting structure of the semiconductor device A40 shown in FIG. 47 can be taken.

According to the second embodiment of the mounting structure of the semiconductor device A40 shown in FIG. 47, when the semiconductor device A40 is mounted on the wiring board 71, the insulating film 5 faces the wiring board 71 and the conductive bonding layer 72 is the external conductive layer. Contact 27. By adopting this configuration, since the conductive bonding layer 72 does not intervene between the wiring substrate 71 and the semiconductor device A40, the mounting height of the semiconductor device A40 can be further lowered. At the same time, since the contact area of the conductive bonding layer 72 with respect to the terminal 2 is larger than the mounting structure of the semiconductor device A30, the mounting strength of the semiconductor device A40 with respect to the wiring substrate 71 is further improved. Further, by providing the insulating film 5, it is possible to prevent the occurrence of a short circuit due to the conductive bonding layer 72 coming into contact with the plurality of terminals 2 when the semiconductor device A40 is mounted on the wiring board 71. In this case, if the external conductive layer 27 is an alloy layer containing Sn, the wettability of the conductive bonding layer 72 with respect to the terminal 2 is good, so that the contact area of the conductive bonding layer 72 with respect to the terminal 2 becomes larger. Further, since the external conductive layer 27 is composed of a Ni layer laminated with each other and an alloy layer containing Sn, the terminal 2 can be protected from the thermal shock by the conductive bonding layer 72 in mounting the semiconductor device A40.

Further, according to the first aspect of the mounting structure of the semiconductor device A40 shown in FIG. 46, when the semiconductor device A40 is mounted on the wiring board 71, the first surface 31 of the sealing resin 3 faces the wiring board 71 and The conductive bonding layer 72 faces the main surface conductive layer 281. Also in this case, the conductive bonding layer 72 is in contact with the external conductive layer 27, as in the second form of the mounting structure of the semiconductor device A40 shown in FIG. 47. The contact area of the conductive bonding layer 72 with respect to the external conductive layer 27 is larger than the contact area with respect to the external conductive layer 27 covering the main surface conductive layer 281. The area is larger. Therefore, the mounting strength of the semiconductor device A40 on the wiring board 71 is improved as compared with the mounting structure of the semiconductor device A30 while suppressing the amount of the conductive bonding layer 72 that wraps around directly under the external conductive layer 27 that covers the main surface conductive layer 281. Can be made to.

[Fifth Embodiment]
The semiconductor device A50 according to the fifth embodiment of the present invention will be described with reference to FIGS. 48 and 49. Here, FIG. 48 is a plan view of the semiconductor device A40, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. Further, in FIGS. 48 and 49, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

In the semiconductor device A50, the arrangement form of the semiconductor element 11 is different from that of the semiconductor device A30 described above. As shown in FIG. 48, the semiconductor device A50 has a rectangular shape in a plan view. Further, also in the present embodiment, as in the semiconductor device A30, both the first side surface 23 and the second side surface 24 are in contact with the corner of the semiconductor device A50 where the first direction X and the second direction Y intersect in a plan view. Terminal 2 is arranged.

As shown in FIGS. 48 and 49, the semiconductor element 11 is arranged in a state of being rotated by 45 ° in the thickness direction Z with respect to the semiconductor device A30. In this case, the rotation center C of the semiconductor element 11 shown in FIG. 48 is an intersection of the diagonal lines (two-dot chain line shown in FIG. 48) of the semiconductor element 11. The mounting structure of the semiconductor device A50 is the same as the mounting structure of the semiconductor device A30 shown in FIG. 38.

Next, the operation and effect of the semiconductor device A50 will be described.

Similar to the semiconductor device A30 described above, the semiconductor device A50 includes a semiconductor element 11 having a surface 111, a base 21 separated from the semiconductor element 11, and a plurality of terminals 2 conductive to the surface 111, and covers the semiconductor element 11. It is provided with a sealing resin 3. The terminal 2 includes a protrusion 22 that protrudes from the base 21 in the direction in which the surface 111 faces. The sealing resin 3 has a first surface 31 facing in the same direction as the surface 111, and the main surface 221 of the protrusion 22 is exposed from the first surface 31. Therefore, it is possible to further reduce the height of the semiconductor device A50.

The semiconductor element 11 is arranged in a state of being rotated by 45 ° in the thickness direction Z with respect to the semiconductor device A30. By adopting such an arrangement form, the separation distance of the terminal 2 with respect to the semiconductor element 11 can be shortened as compared with the semiconductor device A30. Therefore, according to the semiconductor device A50, the device can be further miniaturized.

[Sixth Embodiment]
The semiconductor device A60 according to the sixth embodiment of the present invention will be described with reference to FIGS. 50 to 55. Here, FIG. 50 is a plan view of the semiconductor device A60, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. FIG. 54 is a cross-sectional view taken along the LIV-LIV line of FIG. 50 (dotted chain line shown in FIG. 50). Further, in FIGS. 50 to 54, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A60 has a configuration of the plurality of terminals 2 different from that of the semiconductor device A30 described above. As shown in FIG. 50, the semiconductor device A60 has a rectangular shape in a plan view. Further, also in the present embodiment, as in the semiconductor device A30, both the first side surface 23 and the second side surface 24 are in contact with the corners of the semiconductor device A60 where the first direction X and the second direction Y intersect in a plan view. Terminal 2 is arranged.

As shown in FIGS. 50 to 54, the terminal 2 has a recess 25. The recess 25 is recessed from both the bottom surface 212 of the base 21 and the second side surface 24, and is formed so as to penetrate the terminal 2 in the first direction X. The sealing resin 3 faces the recess 25. In the present embodiment, the recess 25 is filled with the sealing resin 3. Therefore, as shown in FIG. 53, in the sealing resin 3, the length of the boundary between the second surface 32 and the fourth surface 34 matches the length of the semiconductor device A60 in the first direction X. As shown in FIG. 54, the internal conductive layer 29 is configured to cover the inner peripheral surface of the recess 25 in addition to the configuration of the internal conductive layer 29 of the semiconductor device A30.

FIG. 55 shows the mounting structure of the semiconductor device A60 (the cross-sectional position is the same as that of FIG. 54). When the semiconductor device A60 is mounted on the wiring board 71 by the reflow method, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 faces the main surface conductive layer 281.

Next, the effects of the semiconductor device A60 and the mounting structure of the semiconductor device A60 will be described.

Similar to the semiconductor device A30 described above, the semiconductor device A60 includes a semiconductor element 11 having a surface 111, a base 21 separated from the semiconductor element 11, and a plurality of terminals 2 conducting on the surface 111, and covers the semiconductor element 11. It is provided with a sealing resin 3. The terminal 2 includes a protrusion 22 that protrudes from the base 21 in the direction in which the surface 111 faces. The sealing resin 3 has a first surface 31 facing in the same direction as the surface 111, and the main surface 221 of the protrusion 22 is exposed from the first surface 31. Therefore, it is possible to further reduce the height of the semiconductor device A60.

The terminal 2 of the semiconductor device A60 has a recess 25 formed by being recessed from both the bottom surface 212 of the base portion 21 and the second side surface 24 and penetrating the terminal 2 in the first direction X. The sealing resin 3 faces the recess 25. By adopting this configuration, it is possible to more effectively prevent the terminal 2 from falling off with respect to the sealing resin 3.

According to the mounting structure of the semiconductor device A60, when the semiconductor device A60 is mounted on the wiring board 71, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 is the main surface conductive layer 281. Facing. By adopting this configuration, the same effect as the mounting structure of the semiconductor device A30 shown in FIG. 38 can be obtained.

[Variation example of the sixth embodiment]
A semiconductor device A61 according to a modified example of the sixth embodiment of the present invention will be described with reference to FIGS. 56 to 58. Here, FIG. 57 is a cross-sectional view of the semiconductor device A61, and the cross-sectional position thereof is the same as that of FIG. 54.

The semiconductor device A61 is different from the above-mentioned semiconductor device A60 in that the insulating film 5 is not provided. As shown in FIGS. 56 and 57, on the first surface 31 of the sealing resin 3, the exposed surface 131 of the heat radiating layer 13 and the plurality of terminals 2 are both exposed to the outside of the semiconductor device A61. In this modification, the terminal 2 includes a bottom conductive layer 282 together with a main surface conductive layer 281.

FIG. 58 shows the mounting structure of the semiconductor device A61 (the cross-sectional position is the same as that of FIG. 57). The mounting structure of the semiconductor device A61 is the same as that of the semiconductor device A30 shown in FIG. 38.

The semiconductor device A61 has the same configuration as the semiconductor device A30 in that the semiconductor element 11, the plurality of terminals 2, and the sealing resin 3 are configured. Therefore, it is possible to further reduce the height of the semiconductor device A61. Further, since the semiconductor device A61 does not include the insulating film 5, the exposed surface 131 of the heat radiation layer 13 is exposed to the outside of the semiconductor device A61. Therefore, the heat dissipation efficiency of the semiconductor device A61 can be improved as compared with the semiconductor device A60.

[7th Embodiment]
The semiconductor device A70 according to the seventh embodiment of the present invention will be described with reference to FIGS. 59 to 64. Here, FIG. 59 is a plan view of the semiconductor device A70, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. FIG. 63 is a cross-sectional view taken along the line LXIII-LXIII of FIG. 59 (dotted chain line shown in FIG. 59). Further, in FIGS. 59 to 63, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A70 has a configuration of the plurality of terminals 2 different from that of the semiconductor device A30 described above. As shown in FIG. 59, the semiconductor device A70 has a rectangular shape in a plan view. The configuration of the semiconductor element 11 according to the present embodiment is the same as the configuration of the semiconductor element 11 of the semiconductor device A10. Further, in the present embodiment, the terminal 2 is arranged so that both the first side surface 23 and the second side surface 24 are in contact with the corner of the semiconductor device A70 where the first direction X and the second direction Y intersect in a plan view. There is.

In the present embodiment, as shown in FIGS. 59 to 63, the semiconductor element 11 and the plurality of terminals 2 separated from the semiconductor element 11 are both mounted on the insulating film 5. The sealing resin 3 covers the semiconductor element 11, the wire 4, and a part of each terminal 2.

As shown in FIGS. 59 to 63, the terminal 2 includes a main surface 201, a bottom surface 202, a pair of first side surfaces 23, and a pair of second side surfaces 24. In the present embodiment, the terminal 2 includes an internal conductive layer 29 and an external conductive layer 27, and unlike the semiconductor device A10, the terminal 2 does not include a main surface conductive layer 281 and a bottom conductive layer 282. The terminal 2 excluding the internal conductive layer 29 and the external conductive layer 27 has a rectangular parallelepiped shape. Therefore, unlike the semiconductor device A10, the terminal 2 does not have the base portion 21 and the protruding portion 22.

As shown in FIGS. 59 and 61 to 63, the main surface 201 is a surface facing the same direction as the surface 111 of the semiconductor element 11. As shown in FIGS. 60 to 63, the bottom surface 202 is a surface facing the opposite side to the main surface 201. Both the main surface 201 and the bottom surface 202 are covered with the internal conductive layer 29. The wire 4 makes the surface 111 and the main surface 201 conductive to each other.

As shown in FIGS. 59 to 62, the pair of first side surfaces 23 are separated from each other in the first direction X. The pair of first side surfaces 23 intersect both ends of each second side surface 24 in the first direction X. Of the pair of first side surfaces 23, one of the first side surfaces 23 is flush with the third surface 33 and is covered with the external conductive layer 27. Further, the other first side surface 23 is covered with the internal conductive layer 29.

As shown in FIGS. 59 to 63, the pair of second side surfaces 24 are separated from each other in the second direction Y. The pair of second side surfaces 24 intersect both ends of each first side surface 23 in the second direction Y. Of the pair of second side surfaces 24, one of the second side surfaces 24 is flush with the fourth surface 34 and is covered with the external conductive layer 27. Further, the other second side surface 24 is covered with the internal conductive layer 29.

In this embodiment, the heat radiating layer 13 is provided. Instead of the heat radiating layer 13, the insulating layer 12 may be provided as in the semiconductor device A10. Further, the heat radiating layer 13 and the insulating layer 12 may not be provided, and the insulating film 5 may be in contact with the back surface 112 of the semiconductor element 11.

FIG. 64 shows the mounting structure of the semiconductor device A70 (the cross-sectional position is the same as that of FIG. 63). When the semiconductor device A70 is mounted on the wiring board 71 by the reflow method, the insulating film 5 faces the wiring board 71 and the conductive bonding layer 72 is in contact with the external conductive layer 27. In the present embodiment, the insulating film 5 is in contact with the wiring board 71.

Next, the effects of the semiconductor device A70 and the mounting structure of the semiconductor device A70 will be described.

The semiconductor device A70 includes an insulating film 5, a semiconductor element 11 mounted on the insulating film 5, a plurality of terminals 2 mounted on the insulating film 5 and separated from the semiconductor element 11, and a sealing resin covering the semiconductor element 11. 3 and. The sealing resin 3 has a third surface 33 and a fourth surface 34. In this case, the terminal 2 is exposed from either the third surface 33 or the fourth surface 34. In this configuration, when manufacturing the semiconductor device A70, a part of the sealing resin 3 located on the side opposite to the insulating film 5 in the thickness direction Z is removed, and the thickness of the sealing resin 3 is made as thin as possible. (See FIG. 16). Therefore, by adopting this configuration, it is possible to further reduce the height of the semiconductor device A70.

The terminal 2 of the semiconductor device A70 covers the first side surface 23 which is flush with the third surface 33 of the sealing resin 3 and the second side surface 24 which is flush with the fourth surface 34 of the sealing resin 3. The conductive layer 27 is provided. By adopting this configuration, the conductive bonding layer 72 is in contact with the external conductive layer 27, so that the mounting structure of the semiconductor device A70 shown in FIG. 64 can be obtained.

According to the mounting structure of the semiconductor device A70, when the semiconductor device A70 is mounted on the wiring board 71, the insulating film 5 faces the wiring board 71 and the conductive bonding layer 72 is in contact with the external conductive layer 27. By adopting this configuration, since the conductive bonding layer 72 does not intervene between the wiring board 71 and the semiconductor device A70, the mounting height of the semiconductor device A70 can be further lowered. At the same time, since the contact area of the conductive bonding layer 72 with respect to the terminal 2 is larger than that of the mounting structure of the semiconductor device A10, the mounting strength of the semiconductor device A70 with respect to the wiring board 71 is further improved. Further, by providing the insulating film 5, it is possible to prevent the occurrence of a short circuit due to the conductive bonding layer 72 coming into contact with the plurality of terminals 2 when the semiconductor device A70 is mounted on the wiring board 71.

[Eighth Embodiment]
The semiconductor device A80 according to the eighth embodiment of the present invention will be described with reference to FIGS. 65 to 71. Here, FIG. 65 is a plan view of the semiconductor device A80, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. FIG. 69 is a cross-sectional view taken along the line LXIX-LXIX of FIG. 65 (dotted chain line shown in FIG. 69). Further, in FIGS. 65 to 69, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A80 has a configuration of the plurality of terminals 2 different from that of the semiconductor device A70 described above. As shown in FIG. 65, the semiconductor device A80 has a rectangular shape in a plan view. Further, also in the present embodiment, as in the semiconductor device A70, both the first side surface 23 and the second side surface 24 are in contact with the corners of the semiconductor device A80 where the first direction X and the second direction Y intersect in a plan view. Terminal 2 is arranged.

As shown in FIGS. 65 to 69, in the present embodiment, the configuration of the terminal 2 excluding the external conductive layer 27 is the same as the configuration of the terminal 2 of the semiconductor device A30 excluding the main surface conductive layer 281. The external conductive layer 27 covers the first side surface 23, the second side surface 24, and the main surface 221 of the protrusion 22. The configuration of the internal conductive layer 29 is the same as that of the semiconductor device A30.

In this embodiment, the heat radiating layer 13 is provided. Instead of the heat radiating layer 13, the insulating layer 12 may be provided as in the semiconductor device A10. Further, the heat radiating layer 13 and the insulating layer 12 may not be provided, and the insulating film 5 may be in contact with the back surface 112 of the semiconductor element 11.

FIG. 70 shows the first form of the mounting structure of the semiconductor device A80 (the cross-sectional position is the same as that of FIG. 69). When the semiconductor device A80 is mounted on the wiring board 71 by the reflow method, the insulating film 5 faces the wiring board 71 and the conductive bonding layer 72 is in contact with the external conductive layer 27. In the present embodiment, the insulating film 5 is in contact with the wiring board 71.

FIG. 71 shows a second form of the mounting structure of the semiconductor device A80 (the cross-sectional position is the same as that of FIG. 69). When the semiconductor device A80 is mounted on the wiring board 71 by the reflow method, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 is in contact with the external conductive layer 27. In the present embodiment, a part of the conductive bonding layer 72 wraps around directly under the external conductive layer 27 that covers the main surface 221 of the protruding portion 22, and further, with respect to the main surface 221 with each of the first side surface 23 and the second side surface 24. The conductive bonding layer 72 reaches the external conductive layer 27 located on the opposite side.

Next, the effects of the semiconductor device A80 and the mounting structure of the semiconductor device A80 will be described.

Similar to the semiconductor device A70 described above, the semiconductor device A80 includes an insulating film 5, a semiconductor element 11 mounted on the insulating film 5, and a plurality of terminals 2 mounted on the insulating film 5 and separated from the semiconductor element 11. It includes a sealing resin 3 that covers the semiconductor element 11. The sealing resin 3 has a third surface 33 and a fourth surface 34. In this case, the terminal 2 is exposed from either the third surface 33 or the fourth surface 34. Therefore, it is possible to further reduce the height of the semiconductor device A80.

The terminal 2 of the semiconductor device A80 includes an external conductive layer 27 that covers the first side surface 23, the second side surface 24, and the main surface 221 of the protrusion 22. By adopting this configuration, the conductive bonding layer 72 is in contact with the external conductive layer 27, so that the mounting structure of the semiconductor device A70 shown in FIGS. 70 and 71 can be obtained.

According to the first aspect of the mounting structure of the semiconductor device A80 shown in FIG. 70, when the semiconductor device A80 is mounted on the wiring board 71, the insulating film 5 faces the wiring board 71 and the conductive bonding layer 72 is the external conductive layer. Contact 27. By adopting this configuration, the contact area of the conductive bonding layer 72 with respect to the external conductive layer 27 becomes larger than that of the semiconductor device A70 shown in FIG. Therefore, the mounting strength of the semiconductor device A80 on the wiring board 71 can be improved as compared with the mounting structure of the semiconductor device A70.

According to the second form of the mounting structure of the semiconductor device A80 shown in FIG. 71, when the semiconductor device A80 is mounted on the wiring board 71, the first surface 31 of the sealing resin 3 faces the wiring board 71 and is conductively bonded. The layer 72 is in contact with the external conductive layer 27. In this case, the contact area of the conductive bonding layer 72 with respect to the external conductive layer 27 is larger than the contact area with respect to the external conductive layer 27 covering the main surface 221 of the protruding portion 22 (terminal 2), with respect to the first side surface 23 and the second side surface 24. The contact area with respect to the external conductive layer 27 covering both of the above is larger. Therefore, the mounting strength of the semiconductor device A80 on the wiring board 71 is measured in the mounting structure of the semiconductor device A80 shown in FIG. 70 while suppressing the amount of the conductive bonding layer 72 that wraps around directly under the external conductive layer 27 that covers the main surface 221. It can be the same as the first form.

[9th Embodiment]
The semiconductor device A90 according to the ninth embodiment of the present invention will be described with reference to FIGS. 72 to 77. Here, FIG. 72 is a plan view of the semiconductor device A90, and for convenience of understanding, the sealing resin 3 is transmitted and the internal conductive layer 29 is omitted. FIG. 76 is a cross-sectional view taken along the line LXXVI-LXXVI of FIG. 72 (dotted chain line shown in FIG. 72). Further, in FIGS. 72 to 76, the description of the reference numerals of overlapping similar elements for the terminal 2 is omitted.

The semiconductor device A90 has a configuration of the plurality of terminals 2 different from that of the semiconductor device A70 described above. As shown in FIG. 72, the semiconductor device A90 has a rectangular shape in a plan view. Further, also in the present embodiment, as in the semiconductor device A70, both the first side surface 23 and the second side surface 24 are in contact with the corner of the semiconductor device A90 where the first direction X and the second direction Y intersect in a plan view. Terminal 2 is arranged.

As shown in FIGS. 72 to 76, in the present embodiment, the configuration of the terminal 2 excluding the external conductive layer 27 is the same as the configuration of the terminal 2 of the semiconductor device A60 excluding the main surface conductive layer 281. The external conductive layer 27 covers the first side surface 23, the second side surface 24, and the main surface 221 of the protrusion 22. The structure of the internal conductive layer 29 is the same as that of the semiconductor device A60.

In this embodiment, the heat radiating layer 13 is provided. Instead of the heat radiating layer 13, the insulating layer 12 may be provided as in the semiconductor device A10. Further, the heat radiating layer 13 and the insulating layer 12 may not be provided, and the insulating film 5 may be in contact with the back surface 112 of the semiconductor element 11.

FIG. 77 shows the mounting structure of the semiconductor device A90 (the cross-sectional position is the same as that of FIG. 76). When the semiconductor device A90 is mounted on the wiring board 71 by the reflow method, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 is in contact with the external conductive layer 27. In the present embodiment, a part of the conductive bonding layer 72 wraps around directly under the external conductive layer 27 that covers the main surface 221 of the protruding portion 22, and further, with respect to the main surface 221 with each of the first side surface 23 and the second side surface 24. The conductive bonding layer 72 reaches the external conductive layer 27 located on the opposite side.

Next, the effects of the semiconductor device A90 and the mounting structure of the semiconductor device A90 will be described.

Similar to the semiconductor device A70 described above, the semiconductor device A90 includes an insulating film 5, a semiconductor element 11 mounted on the insulating film 5, and a plurality of terminals 2 mounted on the insulating film 5 and separated from the semiconductor element 11. It includes a sealing resin 3 that covers the semiconductor element 11. The sealing resin 3 has a third surface 33 and a fourth surface 34. In this case, the terminal 2 is exposed from either the third surface 33 or the fourth surface 34. Therefore, it is possible to further reduce the height of the semiconductor device A90.

The terminal 2 of the semiconductor device A90 includes an external conductive layer 27 that covers the first side surface 23, the second side surface 24, and the main surface 221 of the protrusion 22. By adopting this configuration, the conductive bonding layer 72 is in contact with the external conductive layer 27, so that the mounting structure of the semiconductor device A90 shown in FIG. 77 can be obtained.

According to the mounting structure of the semiconductor device A90, when the semiconductor device A90 is mounted on the wiring board 71, the first surface 31 of the sealing resin 3 faces the wiring board 71, and the conductive bonding layer 72 is on the external conductive layer 27. Contact. By adopting this configuration, the mounting strength of the semiconductor device A90 on the wiring board 71 is measured by the semiconductor device A70 shown in FIG. 64 while suppressing the amount of the conductive bonding layer 72 that wraps around directly under the external conductive layer 27 that covers the main surface 221. It can be similar to the mounting structure of.

The present invention is not limited to the above-described embodiment. The specific configuration of each part of the present invention can be freely redesigned.

The technical configuration of the semiconductor device and the like provided by the present invention will be described below.

[Appendix 1A]
A semiconductor device having a front surface and a back surface facing opposite to each other in the thickness direction,
A plurality of terminals provided with a base portion arranged apart from the semiconductor element and conducting to the surface of the semiconductor element, and a protruding portion protruding from the base portion in a direction in which the surface faces.
A semiconductor device comprising a sealing resin that covers the semiconductor element and has a first surface that faces in the same direction as the surface.
The protrusion has a main surface that is flush with the first surface of the sealing resin.
The terminal is a semiconductor device including a main surface conductive layer that covers the main surface.
[Appendix 2A]
The base portion has a terminal surface facing the same direction as the surface of the semiconductor element and a bottom surface facing the opposite side to the terminal surface.
The semiconductor device according to Appendix 1A, wherein the protruding portion protrudes from the terminal surface.
[Appendix 3A]
The sealing resin has a second surface facing away from the first surface.
The semiconductor device according to Appendix 2A, wherein the second surface is flush with the bottom surface.
[Appendix 4A]
The semiconductor device according to Appendix 3A, wherein the terminal further includes a bottom conductive layer that covers the bottom surface of the base.
[Appendix 5A]
The semiconductor device according to Appendix 4A, wherein the structure of the bottom conductive layer is the same as that of the main surface conductive layer.
[Appendix 6A]
It is provided with an insulating layer that is arranged in contact with the back surface of the semiconductor element and is an electrical insulator.
The semiconductor device according to any one of Supplementary note 3A to 5A, wherein the insulating layer is exposed from the second surface of the sealing resin.
[Appendix 7A]
The terminal has a first side surface that faces a first direction that is perpendicular to the thickness direction of the semiconductor element, and a second direction that is perpendicular to both the thickness direction of the semiconductor element and the first direction. With a second side facing,
The sealing resin has a third surface facing the first direction and a fourth surface facing the second direction.
The first side surface is flush with the third side surface.
The semiconductor device according to any one of Supplementary Provisions 2A to 6A, wherein the second side surface is flush with the fourth side surface.
[Appendix 8A]
The second side surface includes an inner surface connected to the main surface and an outer surface protruding outward from the inner side surface and connected to the bottom surface.
The semiconductor device according to Appendix 7A, wherein a side conductive layer covering the inner side surface is formed on the terminal.
[Appendix 9A]
The semiconductor device according to Appendix 8A, wherein the structure of the side conductive layer is the same as the structure of the main surface conductive layer.
[Appendix 10A]
The semiconductor device according to Appendix 8A or 9A, wherein the inner surface and the outer surface are smoothly connected to the fourth surface, respectively.
[Appendix 11A]
Described in any of Supplementary note 7A to 10A, wherein both the first side surface and the second side surface are in contact with the angle at which the first direction and the second direction intersect in the thickness direction view of the semiconductor element. Semiconductor device.
[Appendix 12A]
The semiconductor device according to Appendix 11A, wherein the semiconductor element is a Hall element.
[Appendix 13A]
The semiconductor device according to Appendix 12A, wherein a magnetic sensitive layer for detecting a change in magnetic flux density is formed in the vicinity of the back surface of the semiconductor element.
[Appendix 14A]
The semiconductor device according to any one of Supplementary Provisions 2A to 13A, comprising a wire for making the surface of the semiconductor element and the terminal surface of the base mutually conductive.
[Appendix 15A]
The semiconductor device according to Appendix 14A, wherein an internal conductive layer covering the terminal surface of the base is formed on the terminal.
[Appendix 16A]
The semiconductor device according to Appendix 15A, wherein the internal conductive layer is an Ag layer.
[Appendix 17A]
The semiconductor device according to any one of Supplementary note 1A to 16A, wherein the main portion of the terminal is composed of an alloy containing Cu as a main component.
[Appendix 18A]
The semiconductor device according to any one of Supplementary note 1A to 17A, wherein the main surface conductive layer includes an alloy layer containing Sn.
[Appendix 19A]
The semiconductor device according to Appendix 18A, wherein the main surface conductive layer is composed of a Ni layer laminated to each other and an alloy layer containing Sn.
[Appendix 20A]
The semiconductor device according to any one of Supplementary note 1A to 17A, wherein the main surface conductive layer includes an Au layer.
[Appendix 21A]
The semiconductor device according to Appendix 20A, wherein the main surface conductive layer includes a Pd layer and an Au layer laminated on each other.
[Appendix 22A]
The semiconductor device according to Appendix 21A, wherein the main surface conductive layer is composed of a Ni layer, a Pd layer, and an Au layer laminated on each other.
[Appendix 23A]
The semiconductor device according to any one of Supplementary note 1A to 22A, wherein the sealing resin is an epoxy resin containing a glass frit.
[Appendix 24A]
A base portion having a front surface and a back surface facing opposite to each other in the thickness direction and having a part of the back surface, a protrusion portion protruding from the base portion in a direction in which the front surface faces, and having a part of the front surface, said. Electrical insulation having a first base material, which is a conductor on which a penetrating portion extending from the front surface to the back surface, and an exposed portion that supports the first base material from the back surface and is exposed from the penetrating portion. The process of preparing the second base material, which is the body, and
The process of mounting the semiconductor element on the exposed portion of the second base material, and
A step of forming a sealing resin covering the first base material and the semiconductor element, and
A step of removing a part of each of the protruding portion and the sealing resin of the first base material to expose the protruding portion from the sealing resin.
A method for manufacturing a semiconductor device, which comprises a step of forming a conductive layer covering the protruding portion of the first base material exposed from the sealing resin.
[Appendix 25A]
In the step of preparing the first base material and the second base material, the base portion, the protruding portion and the penetrating portion are formed into the first base material by removing a part of the first base material from the surface. The method for manufacturing a semiconductor device according to Appendix 24A, which is formed.
[Appendix 26A]
In the step of preparing the first base material and the second base material, a recess recessed from the surface is formed in the first base material by the primary removal, and the base portion, the protrusion portion and the penetration portion are formed by the secondary removal. 25A is a method for manufacturing a semiconductor device according to Appendix 25A, wherein is formed on the first base material.
[Appendix 27A]
The method for manufacturing a semiconductor device according to Appendix 26A, wherein both the primary removal and the secondary removal are performed by wet etching.
[Appendix 28A]
24A to 27A, wherein in the step of exposing the protruding portion of the first base material from the sealing resin, a part of each of the protruding portion and the sealing resin is removed by mechanical polishing. Manufacturing method for semiconductor devices.
[Appendix 29A]
The method for manufacturing a semiconductor device according to any one of Supplementary note 24A to 28A, wherein the conductive layer is formed by electrolytic plating in the step of forming the conductive layer.
[Appendix 30A]
Between the step of exposing the protruding portion of the first base material from the sealing resin and the step of forming the conductive layer, in the first direction perpendicular to the thickness direction of the first base material. The method for manufacturing a semiconductor device according to Appendix 29A, which comprises a step of forming an extending groove on the first base material from the opposite side of the back surface.
[Appendix 31A]
The method for manufacturing a semiconductor device according to Appendix 30A, wherein in the step of forming the groove, a part of the protruding portion of the first base material is removed with the formation of the groove.
[Appendix 32A]
In the step of mounting the semiconductor element, the semiconductor element is mounted on the exposed portion by interposing a bonding material which is an electric insulator between the exposed portion of the second base material and the semiconductor element. , A method for manufacturing a semiconductor device according to any one of Supplementary Provisions 24A to 31A.
[Appendix 33A]
Appendix 24A, which comprises a step of forming a wire for conducting the semiconductor element and the base portion of the first base material by wire bonding between the step of mounting the semiconductor element and the step of forming the sealing resin. The method for manufacturing a semiconductor device according to any one of 32A.
[Appendix 34A]
Any of the appendices 24A to 33A comprising a step of removing the second base material from the first base material between the step of exposing the protrusion from the sealing resin and the step of forming the conductive layer. The method for manufacturing a semiconductor device according to the above.
[Appendix 35A]
When the semiconductor device according to the appendix 12A or 13A is mounted on a wiring board, the semiconductor device is characterized in that both the main surface of the protruding portion and the first surface of the sealing resin face the wiring board. Implementation structure.

[Appendix 1B]
An insulating film with electrical insulation and
A semiconductor device mounted on the insulating film and having a back surface facing the insulating film and a surface facing the opposite side to the back surface.
A plurality of terminals mounted on the insulating film, separated from the semiconductor element, and conductive on the surface.
A third surface facing the first direction orthogonal to the thickness direction of the semiconductor element, and a fourth surface facing the second direction orthogonal to both the thickness direction of the semiconductor element and the first direction. A semiconductor device comprising, and a sealing resin for covering the semiconductor element.
A semiconductor device, wherein the terminal is exposed from any of the third surface and the fourth surface.
[Appendix 2B]
The semiconductor device according to Appendix 1B, wherein the terminals are exposed from both the third surface and the fourth surface.
[Appendix 3B]
The terminal comprises an external conductive layer and
The semiconductor device according to Appendix 1B or 2B, wherein the external conductive layer covers a portion of the terminal exposed from the sealing resin.
[Appendix 4B]
The semiconductor device according to Appendix 3B, wherein the external conductive layer contains an alloy containing Sn as a component.
[Appendix 5B]
Further provided with a heat radiating layer provided in contact with the back surface,
The sealing resin further has a second surface facing away from the surface.
The semiconductor device according to Appendix 3B or 4B, wherein the heat dissipation layer is exposed from the second surface.
[Appendix 6B]
The semiconductor device according to Appendix 5B, wherein the heat dissipation layer is a conductor.
[Appendix 7B]
The semiconductor device according to Appendix 5B or 6B, wherein the exposed surface of the heat radiation layer exposed from the sealing resin is flush with the second surface.
[Appendix 8B]
The semiconductor element is a Hall element and is
The semiconductor device according to any one of Supplementary note 3B to 7B, wherein the terminal is in contact with the angle where the first direction and the second direction intersect in the thickness direction view of the semiconductor element.
[Appendix 9B]
The terminal further comprises a base that conducts to the surface and a protrusion that projects from the base in the direction in which the surface faces.
The sealing resin further has a first surface that faces in the same direction as the surface.
The protrusion has a main surface that is flush with the first surface.
The semiconductor device according to Appendix 8B, wherein the main surface is covered with the external conductive layer.
[Appendix 10B]
The terminal has a first side surface facing outward in the first direction and a second side surface facing outward in the second direction and intersecting the first side surface.
The base has a bottom surface that faces in the same direction as the back surface.
The terminal further has a recess formed from both the bottom surface and the second side surface and penetrating the terminal in the first direction.
The semiconductor device according to Appendix 9B, wherein the sealing resin faces the recess.
[Appendix 11B]
The protrusion further has a first inner surface that is separated from the second side surface in the second direction and intersects the main surface.
The base has a second inner surface that is separated from the second side surface in the second direction and is connected to the first inner surface.
The semiconductor device according to Appendix 9B or 10B, wherein both the first inner surface and the second inner surface are curved surfaces.
[Appendix 12B]
The first inner surface and the second inner surface are connected by a continuous curved surface, and are connected to each other.
The semiconductor device according to Appendix 11B, wherein an inflection exists at a boundary between the first inner surface and the second inner surface intersecting the first side surface of the terminal.
[Appendix 13B]
12. The semiconductor device according to Appendix 12B, further comprising a wire for making the surface and the first inner surface mutually conductive.
[Appendix 14B]
When the semiconductor device according to the appendices 3B to 13B is mounted on the wiring board, the insulating film faces the wiring board, and the conductive bonding layer for mounting the semiconductor device on the wiring board is on the external conductive layer. A mounting structure for a semiconductor device, characterized by being in contact with each other.
[Appendix 15B]
When the semiconductor device according to the appendices 9B to 13B is mounted on the wiring board, the main surface faces the wiring board, and the conductive bonding layer for mounting the semiconductor device on the wiring board is on the external conductive layer. A mounting structure for a semiconductor device, characterized by being in contact with each other.

A10, A20, A30, A31, A40, A50, A60, A61: Semiconductor device A70, A80, A90: Semiconductor device 11: Semiconductor element (Hall element)
111: Front surface 112: Back surface 113: Magnetically sensitive layer 12: Insulation layer 13: Heat dissipation layer 131: Exposed surface 2 (2A, 2B, 2C, 2D): Terminal 201: Main surface 202: Bottom surface 21: Base 211: Terminal surface 212 : Bottom surface 213: Second inner surface 22: Protruding portion 221: Main surface 222: First inner surface 23: First side surface 24: Second side surface 241: Inner side surface 242: Outer surface 243: Intermediate surface 25: Recessed portion 27: External conductive layer 281: Main surface conductive layer 282: Bottom conductive layer 283: Side conductive layer 29: Internal conductive layer 3: Encapsulating resin 31: First surface 32: Second surface 33: Third surface 34: Fourth surface 4: Wire 41 : 1st connection 42: 2nd connection 5: Insulation film 61: Integrated circuit 611: Device drive area 612: Voltage detection area 613: Control area 62: Control target 63: Magnet 71: Wiring board 72: Conductive junction layer 81 : 1st base material 811: Front surface 812: Back side 813: Recessed part 814: Base 815: Protruding part 816: Penetration part 817: Internal conductive layer 82: 2nd base material 821: Exposed part 831: Semiconductor element 832: Bonding material 84: Wire 85: Encapsulating resin 86: Conductive layer 87: Groove 881: First resist layer 882: Second resist layer 89: Region CL: Cutting line W1, W2: Width r1, r2: Radius IP: Curved point S: Flat surface C: Center of rotation Z: Thickness direction X: First direction Y: Second direction

Claims (15)

A semiconductor device having a front surface and a back surface facing opposite to each other in the thickness direction,
A plurality of terminals arranged apart from the semiconductor element and conducting on the surface,
It has a first surface facing in the same direction as the surface , a second surface facing the opposite side to the first surface, and a sealing resin covering the semiconductor element .
The plurality of terminals have a main surface exposed from the first surface and include a main surface conductive layer covering the main surface.
It has an exposed surface exposed from the second surface, and further includes a heat radiating layer in contact with the back surface.
A semiconductor device in which the peripheral edge of the heat radiating layer includes a section located inside the peripheral edge of the semiconductor element when viewed along the thickness direction . A semiconductor device having a front surface and a back surface facing opposite to each other in the thickness direction,
A plurality of terminals arranged apart from the semiconductor element and conducting on the surface,
It has a first surface facing in the same direction as the surface, a second surface facing the opposite side to the first surface, and a sealing resin covering the semiconductor element.
The plurality of terminals are provided on a main surface exposed from the first surface, a first side surface facing outward in a first direction orthogonal to the thickness direction, and both in the thickness direction and the first direction. It has a second side surface that faces outward in a second direction that is orthogonal to it.
The plurality of terminals have a base portion having a bottom surface facing in the same direction as the back surface, a protruding portion having the main surface and protruding from the base portion toward the first surface, and a main surface covering the main surface. With a conductive layer,
The sealing resin has a third surface that faces the first direction and is flush with the first side surface, and a fourth surface that faces the second direction and is flush with the second side surface. Have,
A heat-dissipating layer having an exposed surface exposed from the second surface and in contact with the back surface,
It also has electrical insulation and is further provided with an insulating film in contact with the second surface.
The insulating film is a semiconductor device that covers the bottom surface and the exposed surface. The semiconductor device according to claim 2 , wherein the plurality of terminals further include an external conductive layer that covers the first side surface, the second side surface, and the main surface conductive layer. The semiconductor device according to claim 3, wherein the external conductive layer contains an alloy containing Sn as a component. A semiconductor element that has a front surface and a back surface that face each other in the thickness direction and is a Hall element, and a semiconductor element that is a Hall element.
A plurality of terminals arranged apart from the semiconductor element and conducting on the surface,
It has a first surface facing in the same direction as the surface, a second surface facing the opposite side to the first surface, and a sealing resin covering the semiconductor element.
The plurality of terminals are provided on a main surface exposed from the first surface, a first side surface facing outward in a first direction orthogonal to the thickness direction, and both in the thickness direction and the first direction. It has a second side surface that faces outward in a second direction that is orthogonal to it.
The first side surface and the second side surface are in contact with the angle at which the first direction and the second direction intersect when viewed along the thickness direction.
The plurality of terminals have a base portion having a bottom surface facing in the same direction as the back surface, a protruding portion having the main surface and protruding from the base portion toward the first surface, and a main surface covering the main surface. With a conductive layer,
The sealing resin has a third surface that faces the first direction and is flush with the first side surface, and a fourth surface that faces the second direction and is flush with the second side surface. Have,
A semiconductor device having an exposed surface exposed from the second surface and further provided with a heat radiating layer in contact with the back surface. The plurality of terminals are recessed from the bottom surface and the second side surface, and have recesses penetrating in the first direction.
The semiconductor device according to any one of claims 2 to 5, wherein the sealing resin faces the recess. The protrusion has a first inner surface that is located away from the second side surface in the second direction and is connected to the main surface.
The base has a second inner surface that is located away from the second side surface in the second direction and is connected to the first inner surface.
The semiconductor device according to any one of claims 2 to 6 , wherein both the first inner surface and the second inner surface are curved surfaces. The first inner surface and the second inner surface are connected to each other by a continuous curved surface.
The semiconductor device according to claim 7 , wherein an inflection exists at a boundary between the first inner surface and the second inner surface intersecting the first side surface. The semiconductor device according to claim 8, further comprising a wire for making the surface and the first inner surface mutually conductive. The semiconductor device according to claim 9, wherein the plurality of terminals further include an internal conductive layer that covers the first inner surface and the second inner surface. The semiconductor device according to any one of claims 1 to 10, wherein the main surface is flush with the first surface. The semiconductor device according to any one of claims 1 to 11, wherein the heat radiating layer is a conductor. The semiconductor device according to any one of claims 1 to 12, wherein the exposed surface is flush with the second surface. When the semiconductor device according to claim 3 or 4 is mounted on a wiring board, the insulating film faces the wiring board, and the conductive bonding layer for mounting the semiconductor device on the wiring board is the external conductive layer. The mounting structure of the semiconductor device in contact with. When the semiconductor device according to claim 5 is mounted on a wiring board, the first surface faces the wiring board, and the conductive bonding layer for mounting the semiconductor device on the wiring board is the main surface conductive layer. The mounting structure of the semiconductor device facing the.

Images