JP6985812B2 - How to make a transistor - Google Patents

Description

The present invention relates to a product, a method, or a manufacturing method. Alternatively, the invention relates to a process, machine, manufacture, or composition (composition of matter). Further, one aspect of the present invention relates to a semiconductor device, a display device, a light emitting device, a lighting device, a power storage device, a storage device, a processor, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device including an oxide semiconductor, a display device, or a light emitting device.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Display devices, light emitting devices, lighting devices, electro-optic devices, semiconductor circuits and electronic devices may have semiconductor devices.

Silicon is known as one of the materials used for the semiconductor layer of a transistor. Amorphous silicon and polycrystalline silicon are used as silicon depending on the application. For example, when silicon is used for the semiconductor layer of a transistor constituting a large display device, it is preferable to use amorphous silicon for which a technique for forming a large-area substrate has been established. Further, when silicon is used for the semiconductor layer of the transistor constituting the high-performance display device in which the drive circuit and the display unit are integrally formed, it is preferable to use photoresist silicon capable of producing a transistor having high field effect mobility. be.

On the other hand, in recent years, oxide semiconductors have been attracting attention as a material used for the semiconductor layer of a transistor. For example, a transistor using an amorphous oxide semiconductor having indium, gallium, and zinc is known (see Patent Document 1).

Since the oxide semiconductor can be formed by using a sputtering method or the like, it can be used for the semiconductor layer of a transistor constituting a large display device. In addition, since it is possible to improve and use a part of the transistor production equipment using amorphous silicon, the capital investment can be suppressed. Further, since the transistor using the oxide semiconductor has high field effect mobility, it is possible to realize a high-performance display device in which a drive circuit and a display unit are integrally formed.

In addition, it is known that a transistor using an oxide semiconductor for a semiconductor layer has an extremely small leakage current in a non-conducting state. For example, a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Patent Document 2).

Japanese Unexamined Patent Publication No. 2006-165528 Japanese Unexamined Patent Publication No. 2012-257187

One aspect of the present invention is to provide a transistor having good electrical characteristics. Alternatively, one of the problems is to provide a transistor having stable electrical characteristics. Alternatively, one of the challenges is to provide a transistor with low power consumption. Alternatively, one of the challenges is to provide a transistor with good reliability. Alternatively, one of the challenges is to provide a new transistor. Alternatively, one of the challenges is to provide a semiconductor device having at least one of these transistors.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

In a transistor having a top gate structure in which an oxide semiconductor layer is used for the semiconductor layer on which a channel is formed, after forming the gate electrode, impurities are introduced into the oxide semiconductor using the gate electrode as a mask. Alternatively, plasma treatment with an inert gas or nitrogen gas is performed. Subsequently, after heat treatment, an insulating layer in which impurities are difficult to permeate is formed without being exposed to the atmosphere on the way. As the insulating layer from which impurities are difficult to permeate, an aluminum oxide layer or the like can be used. The aluminum oxide layer can be formed by forming a film of aluminum and then heat-treating or plasma-treating it in an oxidizing atmosphere.

One aspect of the present invention includes a first gate electrode, a first gate insulating layer provided on the first gate electrode, and an oxide semiconductor layer provided on the first gate insulating layer. The second gate insulating layer provided on the oxide semiconductor layer, the second gate electrode provided on the second gate insulating layer, the second gate electrode, and the oxide. The transistor has a first insulating layer provided on the semiconductor layer, and the density of the first insulating layer is 3.0 g / cm ³ or less.

Alternatively, one aspect of the present invention includes a step of forming a first gate electrode, a step of forming a first gate insulating layer on the first gate electrode, and oxidation on the first gate insulating layer. A step of forming a physical semiconductor layer, a step of forming a second gate insulating layer on the oxide semiconductor layer, a step of forming a second gate electrode on the second gate insulating layer, and a first step. 1. The first heat treatment includes a step of performing the heat treatment of 1 and a step of forming the first insulating layer on the first gate insulating layer and the oxide semiconductor layer by a sputtering method. This is a method for manufacturing a transistor, which comprises performing the steps from the step of forming the first insulating layer to the step of forming the first insulating layer without exposing to the atmosphere.

When the first insulating layer is formed by a sputtering method, the formation temperature of the first insulating layer is preferably room temperature or higher and 150 ° C. or lower.

Alternatively, one aspect of the present invention includes a step of forming a first gate electrode, a step of forming a first gate insulating layer on the first gate electrode, and oxidation on the first gate insulating layer. A step of forming a physical semiconductor layer, a step of forming a second gate insulating layer on the oxide semiconductor layer, a step of forming a second gate electrode on the second gate insulating layer, and a first step. 1. A step of performing the heat treatment, a step of forming a metal layer on the first gate insulating layer and the oxide semiconductor layer, and a step of oxidizing the metal layer to form a first insulating layer. This is a method for manufacturing a transistor, which comprises the above-mentioned step of performing the first heat treatment to the step of forming the first insulating layer without exposing to the atmosphere.

The first heat treatment may be carried out in an inert atmosphere and then in an oxidizing atmosphere. Oxidation of the metal layer for forming the first insulating layer can be realized by performing the second heat treatment in an oxidizing atmosphere. Alternatively, the oxidation of the metal layer for forming the first insulating layer can be realized by performing plasma treatment in an oxidizing atmosphere. The second heat treatment and the plasma treatment may be performed at the same time. The first heat treatment and the second heat treatment may be performed at 200 ° C. or higher and 500 ° C. or lower, respectively.

The metal layer contains, for example, aluminum. The second insulating layer contains, for example, aluminum and oxygen. The oxide semiconductor layer contains, for example, indium, gallium, and zinc.

According to one aspect of the present invention, it is possible to provide a transistor having good electrical characteristics. Alternatively, it is possible to provide a transistor having stable electrical characteristics. Alternatively, it is possible to provide a transistor with low power consumption. Alternatively, it is possible to provide a transistor with good reliability. Alternatively, a new transistor can be provided. Alternatively, a semiconductor device having at least one of these transistors can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

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The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals may be used in common among different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted.

In addition, the position, size, range, etc. of each configuration shown in the drawings may not represent the actual position, size, range, etc. in order to facilitate the understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may be omitted for ease of understanding.

Further, in order to facilitate understanding of the invention, in particular, in a top view (also referred to as a “plan view”) or a perspective view, the description of some components may be omitted. In addition, some hidden lines may be omitted.

The ordinal numbers such as "first" and "second" in the present specification and the like are attached to avoid confusion of the components, and do not indicate any order or order such as process order or stacking order. In addition, even terms that do not have ordinal numbers in the present specification and the like may be given ordinal numbers within the scope of the claims in order to avoid confusion of the components. Further, even if the terms have ordinal numbers in the present specification and the like, different ordinal numbers may be added within the scope of the claims. Further, even if the terms have ordinal numbers in the present specification and the like, the ordinal numbers may be omitted in the scope of claims.

Further, in the present specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. Further, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally provided.

In the present specification and the like, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other. For example, in the case of the expression "electrode B on the insulating layer A", it is not necessary that the electrode B is provided in direct contact with the insulating layer A, and another configuration is provided between the insulating layer A and the electrode B. Do not exclude those that contain elements.

In addition, the functions of the source and drain are interchanged depending on the operating conditions, such as when transistors with different polarities are adopted or when the direction of the current changes in the circuit operation, so which one is the source or drain is limited. Is difficult. Therefore, in the present specification, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is also described in the figure or text.

Further, in the present specification and the like, "electrically connected" includes the case of being connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. Therefore, even when it is expressed as "electrically connected", in an actual circuit, there is a case where there is no physical connection portion and only the wiring is extended.

The channel length is, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when the transistor is on) and a gate electrode overlap each other in a top view of a transistor, or a region where a channel is formed. In, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, the source and the drain facing each other in the region where the semiconductor (or the part where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the region where the channel is formed. The length of the part that is used. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter, “apparently”). Also referred to as "channel width") and may be different. For example, when the gate electrode covers the side surface of the semiconductor layer, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the ratio of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, the apparent channel width may be referred to as an "enclosed channel width (SCW)". Further, in the present specification, when simply described as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

When calculating the electric field effect mobility of the transistor, the current value per channel width, or the like, the enclosed channel width may be used for calculation. In that case, the value may be different from the case calculated using the effective channel width.

The "impurity" of a semiconductor means, for example, a component other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may result in, for example, an increase in DOS (Density of States) of a semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main components of the above, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

In the case of oxide semiconductors, water may also function as an impurity. Further, in the case of an oxide semiconductor, oxygen deficiency may be formed, for example, by mixing impurities. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

Further, in the present specification, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less. Further, "vertical" and "orthogonal" mean a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

In the present specification and the like, when the count value and the measured value are referred to as "same", "same", "equal" or "uniform" (including synonyms thereof), unless otherwise specified. , Plus or minus 20% error shall be included.

Further, in the present specification and the like, when a resist mask is formed by a photolithography method and then an etching step (removal step) is performed, the resist mask is removed after the etching step is completed unless otherwise specified. And.

Further, in the present specification and the like, the high power supply potential VDD (also referred to as “VDD” or “H potential”) indicates a power supply potential having a higher potential than the low power supply potential VSS. Further, the low power supply potential VSS (also referred to as “VSS” or “L potential”) indicates a power supply potential having a potential lower than that of the high power supply potential VDD. Further, the ground potential (also referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

The word "membrane" and the word "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and is located between the source and the drain via the channel forming region. It is capable of passing an electric current. In the present specification and the like, the channel region means a region in which a current mainly flows.

Further, the transistor shown in the present specification and the like shall be an enhancement type (normally off type) field effect transistor unless otherwise specified. Further, the transistor shown in the present specification and the like shall be an n-channel type transistor unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be larger than 0V unless otherwise specified.

In the present specification and the like, Vth of a transistor having a back gate means Vth when the potential of the back gate is the same as that of the source or the gate, unless otherwise specified.

Further, in the present specification and the like, unless otherwise specified, the off current means a drain current when the transistor is in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, the off state is a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor. Is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off current of the transistor may depend on Vgs. Therefore, the fact that the off current of the transistor is I or less may mean that there is a value of Vgs in which the off current of the transistor is I or less. The off-current of a transistor may refer to an off-current in a predetermined Vgs, an off-state in Vgs within a predetermined range, an off-state in Vgs in which a sufficiently reduced off-current is obtained, and the like.

As an example, the threshold voltage Vth is 0.5 V, the drain current at Vgs is 0.5 V is 1 × 10 ^-9 A, and the drain current at Vgs is 0.1 V is 1 × 10 ^-13 A. Assume an n-channel transistor having a drain current of 1 × 10 ^-19 A at Vgs of −0.5 V and a drain current of 1 × 10 ^{-22 A at Vgs of −0.8 V. Since the drain current of the transistor is 1 × 10 -19} A or less in the range of Vgs of −0.5 V or Vgs in the range of −0.5 V to −0.8 V, the off current of the transistor is 1. It may be said that it is × 10 ^{-19 A or less.} Since there are Vgs in which the drain current of the transistor is 1 × ^10-22 A or less, it may be said that the off current of the transistor is 1 × 10 ^-22 A or less.

The off current of the transistor may depend on the temperature. In the present specification, the off-current may represent an off-current at room temperature (RT: Room Temperature), 60 ° C., 85 ° C., 95 ° C., or 125 ° C., unless otherwise specified. Alternatively, an off-current at a temperature at which the reliability of the semiconductor device or the like containing the transistor is guaranteed, or a temperature at which the semiconductor device or the like containing the transistor is used (for example, a temperature of 5 ° C. or higher and 35 ° C. or lower). May represent. The off current of a transistor is I or less, which means RT, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. It may indicate that there is a value of Vgs in which the off current of the transistor is I or less at a temperature at which a semiconductor device or the like is used (for example, a temperature of 5 ° C. or higher and 35 ° C. or lower).

The off current of the transistor may depend on the voltage Vds between the drain and the source. In the present specification, the off current has Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. , Or may represent off-current at 20V. Alternatively, it may represent Vds in which the reliability of the semiconductor device or the like including the transistor is guaranteed, or the off-current in Vds used in the semiconductor device or the like including the transistor. When the off current of the transistor is I or less, Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V. , Vds in which the reliability of the semiconductor device including the transistor is guaranteed, or Vds used in the semiconductor device including the transistor, and the value of Vgs in which the off current of the transistor is I or less exists. May point to.

In the above description of the off-current, the drain may be read as the source. That is, the off current may refer to the current flowing through the source when the transistor is in the off state.

Further, in the present specification and the like, it may be described as a leak current in the same meaning as an off current. Further, in the present specification and the like, the off current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state.

(Embodiment 1)
The transistor 100 of one aspect of the present invention will be described with reference to the drawings.

<Structural example of transistor 100>
FIG. 1A is a plan view of the transistor 100. FIG. 1B is a cross-sectional view of a portion shown by a alternate long and short dash line of X1-X2 shown in FIG. 1A. FIG. 1 (C) is a cross-sectional view of a portion shown by a alternate long and short dash line of Y1-Y2 shown in FIG. 1 (A). FIG. 2A is an enlarged view of the portion 131 shown in FIG. 1B.

The transistor 100 is a kind of top gate type transistor. The transistor 100 includes an electrode 102, an insulating layer 103, an insulating layer 104, an insulating layer 105, an oxide semiconductor layer 106, an insulating layer 108, an insulating layer 109, an electrode 112, an insulating layer 110, an insulating layer 115, an electrode 114a, and an electrode 114b. Has.

The electrode 102 is provided on the substrate 101. The insulating layer 103 is provided so as to cover the electrode 102. The insulating layer 104 is provided on the insulating layer 103. The insulating layer 105 is provided on the insulating layer 104. The oxide semiconductor layer 106 is provided on the insulating layer 105. The electrode 102 and the oxide semiconductor layer 106 have regions that overlap each other via the insulating layer 103, the insulating layer 104, and the insulating layer 105.

Further, the insulating layer 108 is provided on the insulating layer 105 and the oxide semiconductor layer 106. The insulating layer 109 is provided on the insulating layer 108. The electrode 112 is provided on the insulating layer 109. The insulating layer 108, the insulating layer 109, and the electrode 112 have a region overlapping with the oxide semiconductor layer 106. The insulating layer 110 is provided on the insulating layer 105, the oxide semiconductor layer 106, the insulating layer 108, the insulating layer 109, and the electrode 112. The insulating layer 115 is provided on the insulating layer 110.

The electrode 114a is provided on the insulating layer 115. The electrode 114a is electrically connected to a part of the oxide semiconductor layer 106 at openings provided in the insulating layer 115 and the insulating layer 110, respectively. The electrode 114b is provided on the insulating layer 115. The electrode 114b is electrically connected to the other part of the oxide semiconductor layer 106 at the openings provided in the insulating layer 115 and the insulating layer 110, respectively.

When the same kind of material is used for the insulating layer 108 and the insulating layer 109, the interface between the insulating layer 108 and the insulating layer 109 may not be clearly confirmed. Therefore, in the present embodiment, the interface between the insulating layer 108 and the insulating layer 109 is shown by a broken line. In the present embodiment, the two-layer structure of the insulating layer 108 and the insulating layer 109 has been described, but one aspect of the present invention is not limited to this, and for example, only one of the insulating layer 108 and the insulating layer 109 is used. It may be a layered structure or a laminated structure of three or more layers.

Further, as shown in FIGS. 3 (B) and 3 (C), the insulating layer 111 may be provided on the insulating layer 110. FIG. 3A is a plan view of the transistor 100. FIG. 3B is a cross-sectional view of the portion shown by the alternate long and short dash line of X1-X2 shown in FIG. 3A. FIG. 3C is a cross-sectional view of the portion shown by the alternate long and short dash line of Y1-Y2 shown in FIG. 3A.

When the insulating layer 110 and the insulating layer 111 are provided on the transistor 100, it is preferable to use an insulating material in which impurities do not easily permeate into one or both of the insulating layer 110 and the insulating layer 111. For example, at least one of the insulating layer 110 and the insulating layer 111 may be a silicon nitride layer, an aluminum oxide layer, or the like. Further, one of the insulating layer 110 and the insulating layer 111 may be a silicon nitride layer or the like, and the other may be an aluminum oxide layer or the like.

In particular, it is preferable to form the aluminum oxide layer as the insulating layer 110 by a sputtering method. By forming the insulating layer 110 using a sputtering gas containing oxygen, oxygen can be supplied to the cambium to be formed. Further, it is particularly preferable to form the aluminum oxide layer as the insulating layer 111 by the ALD method. By forming the insulating layer 111 by the ALD method, the insulating layer 111 having good covering properties can be provided.

The oxide semiconductor layer 106 is not limited to a single layer, and may be a laminate of a plurality of layers. For example, as shown in FIG. 4A, the oxide semiconductor layer 106 may be a two-layer laminate of the oxide semiconductor layer 106_1 and the oxide semiconductor layer 106_2. Further, for example, as shown in FIG. 4B, the oxide semiconductor layer 106 may be a three-layer laminate of the oxide semiconductor layer 106_1, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_3. Of course, the oxide semiconductor layer 106 may be laminated with four or more layers. Note that both FIGS. 4 (A) and 4 (B) are cross-sectional views corresponding to FIG. 1 (B).

[Gate electrode and back gate electrode]
The electrodes 102 and 112 can function as gate electrodes. When one of the electrode 102 or the electrode 112 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 100 shown in FIGS. 1A to 1C, when the electrode 102 is referred to as a “gate electrode”, the electrode 112 is referred to as a “backgate electrode”. When the electrode 102 is used as a "gate electrode", the transistor 100 can be considered as a kind of bottom gate type transistor. Either one of the electrode 102 and the electrode 121 may be referred to as a "first gate electrode", and the other may be referred to as a "second gate electrode".

Generally, the gate electrode and the back gate electrode are formed of a conductive layer. Further, the gate electrode and the back gate electrode are arranged so as to sandwich the channel forming region of the semiconductor layer (oxide semiconductor layer). In other words, the gate electrode and the back gate electrode surround the semiconductor layer. With such a configuration, the oxide semiconductor layer 106 included in the transistor 100 can be electrically surrounded by the electric fields of the electrode 112 that functions as a gate electrode and the electrode 102 that functions as a back gate electrode. The structure of the transistor that electrically surrounds the semiconductor layer on which the channel is formed by the electric fields of the gate electrode and the back gate electrode can be called a Surrounded channel (S-channel) structure.

The backgate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same potential as that of the gate electrode, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently without interlocking with the gate electrode.

As described above, the electrode 112 can function as a gate electrode. Therefore, the insulating layer 108 and the insulating layer 109 can function as a gate insulating layer. Further, the electrode 102 can also function as a gate electrode. Therefore, the insulating layer 103, the insulating layer 104, and the insulating layer 105 can also function as the gate insulating layer.

By providing the electrodes 102 and 112 with the oxide semiconductor layer 106 interposed therebetween, and further setting the electrodes 102 and 112 to have the same potential, the region in which the carriers flow in the oxide semiconductor layer 106 becomes wider in the film thickness direction. As the size increases, the amount of carrier movement increases. As a result, the on-current of the transistor increases and the field effect mobility increases.

Therefore, the transistor can be a transistor having a large on-current with respect to the occupied area. That is, the occupied area of the transistor can be reduced with respect to the required on-current. Therefore, it is possible to realize a semiconductor device having a high degree of integration.

Further, since the gate electrode and the back gate electrode are formed of a conductive layer, it has a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity). .. In a plan view, the back gate electrode is formed larger than the semiconductor layer, and the semiconductor layer is covered with the back gate electrode, whereby the electric field shielding function can be enhanced.

Since each of the electrode 102 and the electrode 112 has a function of shielding an electric field from the outside, electric charges such as charged particles generated above the electrode 112 and below the electrode 102 do not affect the channel formation region of the oxide semiconductor layer 106. .. As a result, deterioration of electrical characteristics in a stress test (for example, a negative voltage applied to a gate-GBT (Gate Bias-Temperature) stress test) is suppressed. Further, the electrodes 102 and 112 can be cut off so that the electric field generated from the drain electrode does not act on the semiconductor layer. Therefore, it is possible to suppress fluctuations in the rising voltage of the on-current due to fluctuations in the drain voltage. It should be noted that this effect is remarkable when the potential is supplied to the electrode 102 and the electrode 112.

The GBT stress test is a kind of accelerated test, and it is possible to evaluate a change in transistor characteristics (change over time) caused by long-term use in a short time. In particular, the fluctuation amount of the threshold voltage of the transistor before and after the GBT stress test is an important index for examining the reliability. It can be said that the smaller the fluctuation amount of the threshold voltage is, the higher the reliability of the transistor is before and after the GBT stress test.

Further, by having the electrode 102 and the electrode 112 and setting the electrode 102 and the electrode 112 to the same potential, the fluctuation amount of the threshold voltage is reduced. Therefore, the variation in electrical characteristics among the plurality of transistors is also reduced at the same time.

Further, the transistor having the back gate electrode has a smaller fluctuation of the threshold voltage before and after the + GBT stress test in which a positive voltage is applied to the gate than the transistor having no back gate electrode.

Further, when light is incident from the back gate electrode side, by forming the back gate electrode with a conductive film having a light-shielding property, it is possible to prevent light from being incident on the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent photodegradation of the semiconductor layer and prevent deterioration of electrical characteristics such as a shift of the threshold voltage of the transistor.

One of the electrodes 114a or 114b can function as one of the source electrode or the drain electrode. The other of the electrodes 114a or 114b can function as the other of the source or drain electrodes.

〔substrate〕
As the substrate 101, in addition to a glass substrate and a ceramic substrate, a flexible substrate (flexible substrate) having heat resistance sufficient to withstand the processing temperature in this manufacturing process can be used. If the substrate does not require translucency, a metal substrate such as a stainless alloy with an insulating layer provided on the surface may be used. As the glass substrate, for example, a non-alkali glass substrate such as barium borosilicate glass, aluminosilicate glass, or aluminosilicate glass may be used. In addition, a quartz substrate, a sapphire substrate, or the like can be used.

Further, as the substrate 101, the third generation (550 mm × 650 mm), the 3.5 generation (600 mm × 720 mm, or 620 mm × 750 mm), the fourth generation (680 mm × 880 mm, or 730 mm × 920 mm), and the fifth generation (1100 mm). × 1300 mm), 6th generation (1500 mm × 1850 mm), 7th generation (1870 mm × 2200 mm), 8th generation (2200 mm × 2400 mm), 9th generation (2400 mm × 2800 mm, 2450 mm × 3050 mm), 10th generation (2950 mm ×) A glass substrate such as 3400 mm) can be used.

When a flexible substrate is used as the substrate 101, a transistor, a capacitive element, or the like may be directly manufactured on the flexible substrate, or a transistor, a capacitive element, or the like may be manufactured on another manufactured substrate, and then possible. It may be peeled off or transposed on a flexible substrate. In addition, in order to peel off and transpose from the manufactured substrate to the flexible substrate, it is preferable to provide a peeled layer between the manufactured substrate and a transistor, a capacitive element, or the like.

As the flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. The flexible substrate used for the substrate 101 is preferable because the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed. As the flexible substrate used for the substrate 101, for example, a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a flexible substrate.

As the substrate 101, a single crystal semiconductor substrate made of silicon, silicon carbide, or the like, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, or the like can also be used. Further, an SOI substrate or a semiconductor substrate on which a semiconductor element such as a strain transistor or a FIN type transistor is provided can also be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphate, silicon germanium and the like applicable to a high electron mobility transistor (HEMT) may be used. That is, the substrate 101 is not limited to a simple support substrate, but may be a substrate on which a device such as another transistor is formed. In this case, at least one of the gate, source, or drain of the transistor 100 may be electrically connected to the other device.

[Insulation layer]
The insulating layer 103 to the insulating layer 105, the insulating layer 108, the insulating layer 109, the insulating layer 110, and the insulating layer 115 are aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum nitride, magnesium oxide, silicon nitride, silicon oxide, and oxide. Materials selected from silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. are used in a single layer or in a laminated manner. Further, a material obtained by mixing a plurality of materials among an oxide material, a nitride material, an oxide nitride material, and a nitride oxide material may be used.

In the present specification, the nitride oxide refers to a compound having a higher nitrogen content than oxygen. Further, the oxidative nitride refers to a compound having a higher oxygen content than nitrogen. The content of each element can be measured by using, for example, Rutherford backscattering method (RBS) or the like.

In particular, it is preferable that the insulating layer 104 and / or the insulating layer 110 is formed by using an insulating material in which impurities are difficult to permeate. For example, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, aluminum oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Aluminum nitride and the like can be mentioned.

By using an insulating material in which impurities do not easily permeate into the insulating layer 104, it is possible to prevent the diffusion of impurities from the substrate 101 side and improve the reliability of the transistor. Insulating layer 110 By using an insulating material in which impurities are difficult to permeate, it is possible to prevent the diffusion of impurities from the upper layer side of the insulating layer 110 and improve the reliability of the transistor.

In addition, for the insulating layer 104 and / or the insulating layer 110, it is preferable to use an insulating material in which oxygen is difficult to diffuse and / or is hardly absorbed. By using an insulating material in which oxygen is difficult to diffuse and / or is hardly absorbed in the insulating layer 104 and / or the insulating layer 110, it is possible to prevent the diffusion of oxygen to the outside.

As the insulating layer 104 and / or the insulating layer 110, a plurality of insulating layers formed of these materials may be laminated and used.

Further, in order to prevent an increase in the hydrogen concentration in the oxide semiconductor layer 106, it is preferable to reduce the hydrogen concentration in the insulating layer. In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the oxide semiconductor layer 106. In the present embodiment, it is preferable to reduce the hydrogen concentration of the insulating layer 105 and the insulating layer 108. Specifically, the hydrogen concentration in the insulating layer is determined by 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less in secondary ion mass spectrometry (SIMS). It is more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and further preferably 5 × 10 ¹⁸ atoms / cm ³ or less. Further, in order to prevent an increase in the nitrogen concentration in the oxide semiconductor, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer is set to ^{less than 5 × 10 19} atoms / cm ³ in SIMS, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, More preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, it is preferable that at least one of the insulating layer 105, the insulating layer 108, and the insulating layer 109 is formed by using an insulating layer that releases oxygen by heating. Specifically, in a heated desorption gas analysis method (TDS: Thermal Desorption Gascopy) performed by a heat treatment in which the surface temperature of the insulating layer is 100 ° C. or higher and 700 ° C. or lower, preferably 100 ° C. or higher and 500 ° C. or lower, oxygen atoms The amount of oxygen desorbed in terms of is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 × 10 ¹⁹ atoms / cm ³ or more, and more preferably 1.0 × 10 ²⁰ atoms / cm ³ or more. It is good to use a layer. In addition, in this specification and the like, oxygen released by heating is also referred to as "excess oxygen".

Further, it is particularly preferable that the insulating layer in contact with the oxide semiconductor layer has a small amount of defects. Typically, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 3 × 10 ¹⁷ spins / cm ³ or less by electron spin resonance (ESR) measurement. Is preferable. If the insulating layer has many defects, oxygen may be bound to the defects to reduce excess oxygen.

In particular, the insulating layer in contact with the oxide semiconductor layer is an oxide insulation having a low level density due to _{nitrogen oxides (NO X} : X is greater than 0 and 2 or less, typically NO or NO _2.). It is preferable to use a layer. The silicon oxynitride layer having a small amount of nitrogen oxides released is a layer in which the amount of ammonia released is larger than the amount of nitrogen oxides released in the heated desorption gas analysis method, and the amount of ammonia released is typically high. 1 × 10 ¹⁸ pieces / cm ³ or more 5 × 10 ¹⁹ pieces / cm ³ or less. The amount of ammonia released is the amount released by heat treatment in which the surface temperature of the oxide insulating layer is 50 ° C. or higher and 650 ° C. or lower, preferably 50 ° C. or higher and 550 ° C. or lower.

Nitrogen oxides form levels in oxide semiconductor layers and insulating layers. The level is located within the energy gap of the oxide semiconductor. When the nitrogen oxide reaches the interface between the insulating layer and the oxide semiconductor layer, the level may trap electrons on the insulating layer side. As a result, the trapped electrons stay near the interface between the insulating layer and the oxide semiconductor layer, so that the threshold voltage of the transistor is shifted in the positive direction.

The level density due to the nitrogen oxide can be formed between the energy at the upper end of the valence band of the oxide semiconductor layer (Ev_os) and the energy at the lower end of the conduction band of the oxide semiconductor layer (Ec_os). In some cases. As the oxide insulating layer, a silicon nitride layer having a small amount of nitrogen oxides released, an aluminum nitride layer having a small amount of nitrogen oxides released, or the like can be used.

Nitrogen oxides also react with ammonia and oxygen in the heat treatment. Since the nitrogen oxides contained in the insulating layer react with ammonia contained in the insulating layer in the heat treatment, the nitrogen oxides contained in the insulating layer are reduced. Therefore, it is difficult for electrons to be trapped at the interface between the insulating layer and the oxide semiconductor layer.

In particular, by using the oxide insulating layer for the insulating layer in contact with the oxide semiconductor layer, it is possible to reduce the shift of the threshold voltage of the transistor and reduce the fluctuation of the electrical characteristics of the transistor. ..

The insulating layer containing excess oxygen can also be formed by subjecting the insulating layer to a treatment of adding oxygen. The treatment of adding oxygen can be performed by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Further, the treatment of adding oxygen can be performed by a heat treatment in an oxidizing atmosphere, a plasma treatment, a reverse sputtering treatment or the like. Further, for plasma treatment in an oxidizing atmosphere, it is preferable to use, for example, an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. Higher density oxygen radicals can be generated by using high density plasma. Further, by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the target layer. Alternatively, after the plasma treatment is performed in an inert atmosphere, the plasma treatment may be performed in an oxidizing atmosphere in order to supplement the desorbed oxygen. The addition of oxygen by the reverse sputtering treatment can also be expected to have a cleaning effect on the sample surface. On the other hand, the surface of the sample may be damaged depending on the treatment conditions. As the gas for adding oxygen, ^{oxygen gas such as 16} O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like can be used. In addition, in this specification, the process of adding oxygen is also referred to as "oxygen doping process".

Further, the oxygen doping treatment may increase the crystallinity of the semiconductor layer. In addition, the oxygen doping treatment may be able to remove impurities such as hydrogen and water in the target layer. That is, the "oxygen doping treatment" can be said to be an "impurity removal treatment". In particular, as the oxygen doping treatment, plasma treatment containing oxygen under reduced pressure and in an oxidizing atmosphere breaks the bonds related to hydrogen and water contained in the target insulating layer or semiconductor layer. Therefore, hydrogen and water in the target layer change to a state in which they are easily desorbed. Therefore, it is preferable to perform the oxygen doping treatment by plasma treatment while heating. Alternatively, it is preferable to perform heat treatment after plasma treatment. Further, by performing the plasma treatment after the heat treatment and further performing the heat treatment, the impurity concentration in the target layer can be reduced.

Further, an insulating layer having a function of flattening irregularities and the like caused by transistors and the like (hereinafter, also referred to as “flattening layer”) may be provided on the insulating layer 115. The material used for the flattening layer may be an insulating material. Therefore, the flattening layer can be formed by using an inorganic material or an organic material. For example, as the flattening layer, not only the above-mentioned inorganic material but also an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. A flattening layer may be formed by laminating a plurality of insulating layers formed of these materials.

The siloxane-based resin corresponds to a resin containing a Si—O—Si bond formed from a siloxane-based material as a starting material. As the substituent of the siloxane-based resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. Further, the organic group may have a fluoro group.

The method for forming the flattening layer is not particularly limited, and depending on the material, spatter method, SOG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset). Printing, etc.) may be used. By combining the firing step of the flattening layer and other heat treatment steps, it becomes possible to efficiently manufacture a transistor.

〔electrode〕
The conductive materials for forming the electrode 102, the electrode 114a, the electrode 114b, and the electrode 112 include aluminum (Al), chromium (Cr), iron (Fe), copper (Cu), silver (Ag), and gold (Ag). Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), cobalt (Co), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium ( A material containing at least one metal element selected from Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be) and the like can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

Further, as the conductive material, a Cu—X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. Since the layer formed of the Cu—X alloy can be processed by a wet etching process, it is possible to suppress the manufacturing cost.

Further, the above-mentioned conductive material containing a metal element and oxygen may be used. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. Further, indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide, indium gallium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide and indium tin oxide containing silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

When copper is used for the electrodes 114a and 114b in order to reduce the resistance of the electrodes 114a and 114b, it is preferable to provide a conductive material between the electrodes 114a and the oxide semiconductor layer 106 so that copper does not easily diffuse. .. Further, it is preferable to provide a conductive material between the electrode 114b and the oxide semiconductor layer 106 so that copper does not easily diffuse. Since copper easily diffuses in the semiconductor layer, it may destabilize the operation of the semiconductor device and significantly reduce the yield. The reliability of the transistor 100 can be improved by providing a conductive material in which copper does not easily diffuse between the wiring or the electrode containing copper and the semiconductor layer.

Examples of the conductive material in which copper does not easily diffuse include metal materials having a melting point higher than that of copper such as tungsten, titanium, and tantalum, and nitride materials thereof. Also, these conductive materials may cover the electrodes or wiring containing copper. The reliability of the transistor 100 can be further enhanced by covering or wrapping the wiring or electrode containing copper with a conductive material in which copper does not easily diffuse.

Further, by using a conductive material having a function of absorbing hydrogen by heat treatment in the region of the electrode 114a and the electrode 114b in contact with the oxide semiconductor layer 106, the hydrogen concentration in the oxide semiconductor layer 106 is obtained by the subsequent heat treatment. Can be reduced. Examples of conductive materials having a function of absorbing hydrogen include titanium, indium zinc oxide, and indium tin oxide to which silicon is added.

[Oxide semiconductor layer]
It is preferable to use an oxide semiconductor as the oxide semiconductor layer 106. Since the bandgap of the oxide semiconductor is 2 eV or more, if the oxide semiconductor is used for the oxide semiconductor layer 106, a transistor having an extremely small off-current can be realized. Further, a transistor using an oxide semiconductor in the semiconductor layer on which a channel is formed (also referred to as an “OS transistor”) has a high dielectric strength between a source and a drain. Therefore, it is possible to provide a transistor with good reliability. Further, it is possible to provide a transistor having a large output voltage and a high withstand voltage. Further, it is possible to provide a semiconductor device having good reliability. Further, it is possible to provide a semiconductor device having a large output voltage and a high withstand voltage.

The oxide semiconductor according to the present invention will be described. The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.

Here, consider the case where the oxide semiconductor is InMZnO having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

[structure]
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphous oxide semiconductor (a-lik). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. It is thought that this is the reason.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[Atomic number ratio]
Next, with reference to FIGS. 18 (A), 18 (B), and 18 (C), a preferable range of atomic number ratios of indium, element M, and zinc contained in the oxide semiconductor according to the present invention will be described. .. Note that FIGS. 18 (A), 18 (B), and 18 (C) do not describe the atomic number ratio of oxygen. Further, the terms of the atomic number ratios of indium, element M, and zinc contained in the oxide semiconductor are [In], [M], and [Zn].

In FIGS. 18 (A), 18 (B), and 18 (C), the broken line indicates the atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. (-1 ≤ α ≤ 1), [In]: [M]: [Zn] = (1 + α): (1-α): 2 atomic number ratio, [In]: [M] : [Zn] = (1 + α): (1-α): Line having an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 atomic numbers It represents a line having a ratio and a line having an atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 5.

Further, the one-point chain line has an atomic number ratio of [In]: [M]: [Zn] = 1: 1: β, and an atomic number ratio of [In]: [M]: [Zn] = 5: 1: β ( β ≧ 0) line, [In]: [M]: [Zn] = 2: 1: β atomic number ratio line, [In]: [M]: [Zn] = 1: 2: β Atomic number ratio line, [In]: [M]: [Zn] = 1: 3: β atomic number ratio line, and [In]: [M]: [Zn] = 1: 4: Represents a line that is the atomic number ratio of β.

The two-dot chain line represents a line having an atomic number ratio (-1 ≦ γ ≦ 1) of [In]: [M]: [Zn] = (1 + γ): 2: (1-γ). Further, the atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1 and its vicinity values shown in FIGS. 18 (A), 18 (B), and 18 (C). Oxide semiconductors tend to have a spinel-type crystal structure.

In addition, a plurality of phases may coexist in an oxide semiconductor (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is close to the atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel-type crystal structure and a layered crystal structure coexist. It's easy to do. Further, when the atomic number ratio is a value close to the atomic number ratio indicating [In]: [M]: [Zn] = 1: 0: 0, the two phases of the big bite type crystal structure and the layered crystal structure. Is easy to coexist. When a plurality of phases coexist in an oxide semiconductor, grain boundaries (also referred to as grain boundaries) may be formed between different crystal structures.

18 (A) and 18 (B) show an example of a preferable range of atomic number ratios of indium, element M, and zinc contained in the oxide semiconductor of one aspect of the present invention.

By increasing the content of indium in the oxide semiconductor, the carrier mobility (electron mobility) of the oxide semiconductor can be increased. Therefore, an oxide semiconductor having a high indium content has a higher carrier mobility than an oxide semiconductor having a low indium content.

On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility is low. Therefore, when the atomic number ratio is [In]: [M]: [Zn] = 0: 1: 0 and its vicinity value (for example, region C shown in FIG. 18C), the insulating property is high. ..

Therefore, it is preferable that the oxide semiconductor of one aspect of the present invention has the atomic number ratio shown in the region A of FIG. 18A, which tends to have a layered structure having high carrier mobility and few grain boundaries. ..

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the oxide semiconductor may be deteriorated due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability.

The region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1, and values in the vicinity thereof. The neighborhood value includes, for example, an atomic number ratio of [In]: [M]: [Zn] = 5: 3: 4. Further, the region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7, and the like. Includes neighborhood values.

The properties of oxide semiconductors are not uniquely determined by the atomic number ratio. Even if the atomic number ratio is the same, the properties of the oxide semiconductor may differ depending on the formation conditions. For example, when an oxide semiconductor is formed by a sputtering apparatus, a film having an atomic number ratio deviating from the target atomic number ratio is formed. Further, depending on the substrate temperature at the time of film formation, the film [Zn] may be smaller than the target [Zn]. Therefore, the region shown in the figure is a region showing an atomic number ratio in which the oxide semiconductor tends to have a specific characteristic, and the boundary between the regions A and C is not strict.

[Transistor with oxide semiconductor]
Subsequently, a case where the oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor for the transistor, carrier scattering and the like at the grain boundaries can be reduced, so that a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, it is preferable to use an oxide semiconductor having a low carrier density for the transistor. When the carrier density of the oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film may be lowered and the defect level density may be lowered. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, oxide semiconductors have a carrier density of ^{less than 8 × 10 11} / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 /. It ^{may be cm 3} or more.

Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, the electrical characteristics of the OS transistor having a high trap level density may become unstable.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

[impurities]
Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by SIMS) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 ×. 10 ¹⁷ atoms / cm ³ or less.

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible, and in particular, it is preferable that nitrogen in the region where channels are formed is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and further, in SIMS. It is preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. In particular, it is preferable that hydrogen in the region where the channel is formed is reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS ^{is less than 1 × 10 20} atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁸ atoms / cm. ^{Less than 3} , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced in the channel forming region of the transistor, stable electrical characteristics can be imparted to the transistor.

For example, as the oxide semiconductor layer 106, when forming the InGaZnO _{X (X>} 0) film by a thermal CVD method, trimethyl indium _{(In (CH 3) 3)} , trimethyl gallium (Ga _{(CH 3)} 3) , And dimethylzinc (Zn (CH ₃ ) ₂ ). Further, the combination is not limited to these, and triethylgallium (Ga (C ₂ H ₅ ) _{3 ) can be used instead of trimethylgallium, and diethylzinc (Zn (C 2} H ₅ ) ₂ ) can be used instead of dimethylzinc. Can also be used.

_{For example, when an InGaZnO X} (X> 0) film is formed as the oxide semiconductor layer 106 by the ALD method _{, In (CH 3} ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an InO ₂ layer. After the formation, Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are sequentially and repeatedly introduced to form a ZnO layer. Form. The order of these layers is not limited to this example. Further, these gases may be used _{to form a mixed compound layer such as an InGaO 2} layer _{, an InZNO 2} layer, a GaInO layer, a ZnInO layer, and a GaZnO layer. Incidentally, O ₃ may be used the H _{2 O} gas was bubbled water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. Further, instead of In (CH ₃ ) ₃ gas, In (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) indium may be used. Indium tris (acetylacetonato) is also referred to as _{In (acac) 3.} Further, Ga (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) gallium may be used instead of Ga (CH ₃ ) _{3 gas.} In addition, tris (acetylacetonato) gallium is also referred to as _{Ga (acac) 3.} Further, Zn (CH ₃ ) ₂ gas or zinc acetate may be used. It is not limited to these gas species.

When the oxide semiconductor layer 106 is formed by a sputtering method, it is preferable to use a target containing indium in order to reduce the number of particles. Further, when an oxide target having a high atomic number ratio of the element M is used, the conductivity of the target may be low. When a target containing indium is used, the conductivity of the target can be increased, and DC discharge and AC discharge become easy, so that it becomes easy to cope with a large area substrate. Therefore, the productivity of the semiconductor device can be increased.

When the oxide semiconductor layer 106 is formed by the sputtering method, the target atomic number ratio is 3: 1: 1, 3: 1: 2, 3: 1: 4, 1: 1: 0 for In: M: Zn. .5, 1: 1: 1, 1: 1: 2, 1: 1: 1.2, 1: 4: 4, 4: 2: 4.1, 1: 3: 2, 1: 3: 4, 5 It may be 1: 6, 5: 1: 8, or the like.

When the oxide semiconductor layer 106 is formed by a sputtering method, a film having an atomic number ratio deviating from the target atomic number ratio may be formed. In particular, zinc may have a smaller atomic number ratio in the film than the target atomic number ratio. Specifically, the atomic number ratio of zinc contained in the target may be 40 atomic% or more and 90atomic% or less.

Further, as shown in FIGS. 4A and 4B, when the oxide semiconductor layer 106 is laminated with a plurality of layers, the oxide semiconductor layer 106_1 is, for example, an oxide semiconductor having a large energy gap. It is preferable to use it. The energy gap of the oxide semiconductor layer 106_1 is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

The oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 are preferably formed of a material containing one or more of the same metal elements among the elements other than oxygen constituting the oxide semiconductor layer 106_1. When such a material is used, it is possible to make it difficult for an interface state to occur at the interface between the oxide semiconductor layer 106_1 and the oxide semiconductor layer 106_1 and at the interface between the oxide semiconductor layer 106_2 and the oxide semiconductor layer 106_1. Therefore, it is possible to improve the electric field effect mobility of the transistor by preventing the scattering and capture of carriers at the interface. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics.

Further, the oxide semiconductor layer 106_1 is an In-M-Zn oxide (an oxide containing In, elements M and Zn), and the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_1 are also In-M-Zn oxides. At one time, the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 are in In: M: Zn = x ₁ : y ₁ : z ₁ [atomic number ratio], and the oxide semiconductor layer 106_1 is in In: M: Zn = x ₂ : When y ₂ : z ₂ [atomic number ratio], preferably, the oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_1 in which _{y 1} / x ₁ is _{larger than y 2} / x _{2 are selected.} do. More preferably, the oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_1 in which _{y 1} / x ₁ is _{1.5 times or more larger than y 2} / x _{2 are selected.} More preferably, the oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_1 in which _{y 1} / x ₁ is _{twice or more larger than y 2} / x _{2 are selected.} More preferably, the oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_1 in which _{y 1} / x ₁ is _{three times or more larger than y 2} / x _{2 are selected.} At this time, in the oxide semiconductor layer 106_1, when y ₂ is x ₂ or more, stable electrical characteristics can be imparted to the transistor, which is preferable. However, when y ₂ becomes 5 times or more of x ₂ , the field effect mobility of the transistor decreases, so that y ₂ is preferably less than 5 times _{x 2.} By having the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 as described above, the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 can be made into a layer in which oxygen deficiency is less likely to occur than the oxide semiconductor layer 106_1. ..

When the oxide semiconductor layer 106_3 is an In-M-Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50atomic%, M is higher than 50atomic%, and In is more preferably. Less than 25 atomic%, M is higher than 75 atomic%. Further, when the oxide semiconductor layer 106_1 is an In—M—Zn oxide and the sum of In and M is 100 atomic%, In is preferably higher than 25 atomic%, M is less than 75 atomic%, and In is more preferably. It is higher than 34 atomic% and M is less than 66 atomic%. Further, when the oxide semiconductor layer 106_2 is an In—M—Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and In is more preferably. It is assumed that it is less than 25 atomic% and M is higher than 75 atomic%. The oxide semiconductor layer 106_2 may use an oxide of the same type as the oxide semiconductor layer 106_3.

For example, as the oxide semiconductor layer 106_3 containing In or Ga and the oxide semiconductor layer 106_2 containing In or Ga, In: Ga: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, In-Ga-Zn oxide formed using an atomic number ratio target such as 1: 4: 5, 1: 6: 4, or 1: 9: 6, or In: Ga = 1: 9, or 7 :. In-Ga oxide formed using a target having an atomic number ratio such as 93 can be used. Further, as the oxide semiconductor layer 106_1, an In-Ga-Zn oxide formed by using a target having an atomic number ratio such as In: Ga: Zn = 1: 1: 1 or 3: 1: 2 is used. Can be done. The atomic number ratios of the oxide semiconductor layer 106_3, the oxide semiconductor layer 106_1, and the oxide semiconductor layer 106_1 each include a variation of plus or minus 20% of the above-mentioned atomic number ratio as an error.

As the oxide semiconductor layer 106_1, it is preferable to use an oxide having a higher electron affinity than the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_1. For example, the oxide semiconductor layer 106_1 has an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0. Oxides larger than 15 eV and 0.4 eV or less may be used. The electron affinity is the difference between the vacuum level and the energy at the lower end of the conduction band.

Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the oxide semiconductor layer 106_2 contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

However, the oxide semiconductor layer 106_3 and / and the oxide semiconductor layer 106_2 may be gallium oxide. For example, if gallium oxide is used as the oxide semiconductor layer 106_3, the leakage current generated between the electrode 102 and the oxide semiconductor layer 106 can be reduced. That is, the off-current of the transistor 100 can be reduced.

At this time, when a gate voltage is applied, a channel is formed in the oxide semiconductor layer 106_1 having a large electron affinity among the oxide semiconductor layer 106_1, the oxide semiconductor layer 106_1, and the oxide semiconductor layer 106_1.

In order to impart stable electrical characteristics to the OS transistor, impurities and oxygen deficiencies in the oxide semiconductor layer are reduced to achieve high purity authenticity, and at least the oxide semiconductor layer 106_1 can be regarded as genuine or substantially genuine oxide. It is preferably a semiconductor layer. Further, it is preferable that at least the channel forming region in the oxide semiconductor layer 106_1 is a semiconductor layer that can be regarded as genuine or substantially genuine.

[Band diagram]
Subsequently, a case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. The laminated structure of the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3, the band diagram of the insulator in contact with the laminated structure, the laminated structure of the oxide semiconductor S2 and the oxide semiconductor S3, and the insulation in contact with the laminated structure. A band diagram of the body, a laminated structure of the oxide semiconductor S1 and the oxide semiconductor S2, and a band diagram of an insulator in contact with the laminated structure will be described with reference to FIG.

FIG. 19A is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. Further, FIG. 19B is an example of a band diagram in the film thickness direction of the laminated structure having the insulator I1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2. Further, FIG. 19C is an example of a band diagram in the film thickness direction of the laminated structure having the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, and the insulator I2. The band diagram shows the energy level (Ec) at the lower end of the conduction band of the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2 for easy understanding.

The oxide semiconductor S1 and the oxide semiconductor S3 have an energy level at the lower end of the conduction band closer to the vacuum level than the oxide semiconductor S2, and typically have an energy level at the lower end of the conduction band of the oxide semiconductor S2. It is preferable that the difference from the energy level at the lower end of the conduction band of the oxide semiconductor S1 and the oxide semiconductor S3 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 and the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less. preferable.

As shown in FIGS. 19A, 19B, and 19C, the energy level at the lower end of the conduction band changes gently in the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3. do. In other words, it can also be said to be continuously changing or continuously joining. In order to have such a band diagram, the defect level density of the mixed layer formed at the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is lowered. It is good to do.

Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, and the oxide semiconductor S2 and the oxide semiconductor S3 have a common element (main component) other than oxygen, so that the defect level density is low. Layers can be formed. For example, when the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, an In-Ga-Zn oxide semiconductor, a Ga-Zn oxide semiconductor, gallium oxide or the like is used as the oxide semiconductor S1 and the oxide semiconductor S3. It is good.

At this time, the main path of the carrier is the oxide semiconductor S2. Since the defect level density at the interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the interface between the oxide semiconductor S2 and the oxide semiconductor S3 can be lowered, the influence of interfacial scattering on carrier conduction is small. High on-current is obtained.

When electrons are trapped at the trap level, the trapped electrons behave like a fixed charge, and the threshold voltage of the transistor shifts in the positive direction. By providing the oxide semiconductor S1 and the oxide semiconductor S3, the trap level can be kept away from the oxide semiconductor S2. With this configuration, it is possible to prevent the threshold voltage of the transistor from shifting in the positive direction.

The oxide semiconductor S1 and the oxide semiconductor S3 use a material having a sufficiently low conductivity as compared with the oxide semiconductor S2. At this time, the oxide semiconductor S2, the interface between the oxide semiconductor S2 and the oxide semiconductor S1, and the interface between the oxide semiconductor S2 and the oxide semiconductor S3 mainly function as a channel region. For example, for the oxide semiconductor S1 and the oxide semiconductor S3, the oxide semiconductor having the atomic number ratio shown in the region C where the insulating property is high may be used in FIG. 18C. The region C shown in FIG. 18C is [In]: [M]: [Zn] = 0: 1: 0 and its neighboring values, [In]: [M]: [Zn] = 1: It shows the atomic number ratio of 3: 2 and its neighboring values, and [In]: [M]: [Zn] = 1: 3: 4, and its neighboring values.

In particular, when an oxide semiconductor having an atomic number ratio shown in region A is used for the oxide semiconductor S2, [M] / [In] is 1 or more, preferably 2 or more in the oxide semiconductor S1 and the oxide semiconductor S3. It is preferable to use an oxide semiconductor. Further, as the oxide semiconductor S3, it is preferable to use an oxide semiconductor having [M] / ([Zn] + [In]) of 1 or more, which can obtain sufficiently high insulating properties.

[About film formation method]
The insulating layer, the conductive layer for forming electrodes and wiring, the semiconductor layer, etc. are a sputtering method, a spin coat method, a CVD (Chemical Vapor Deposition) method (thermal CVD method, MOCVD (Metal Organic Vapor Deposition) method, PECVD). (Including Plasma Enhanced CVD) method, high density plasma CVD method, LPCVD method (low pressure CVD), APCVD method (atmospheric pressure CVD), etc.), ALD (Atomic Layer Deposition), ALD (Atomic Layer) (Molecular Beam Deposition) method, PLD (Pulsed Laser Deposition) method, dip method, spray coating method, droplet ejection method (inkprint method, etc.), printing method (screen printing, offset printing, etc.). Can be done.

The plasma CVD method can obtain a high quality film at a relatively low temperature. When a film forming method that does not use plasma during film formation, such as a MOCVD method, an ALD method, or a thermal CVD method, is used, damage to the surface to be formed is unlikely to occur. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the film forming method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, since plasma damage does not occur during film formation, a film having few defects can be obtained.

The CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage. In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming speed, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming speed.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the CVD method and the ALD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for film formation can be shortened by the amount of time required for transport and pressure adjustment, as compared with the case of forming a film using multiple film forming chambers. can. Therefore, it may be possible to increase the productivity of the semiconductor device.

When forming a film by the ALD method, it is preferable to use a gas that does not contain chlorine as the material gas.

When forming an oxide semiconductor by a sputtering method, the chamber in the sputtering apparatus uses an adsorption type vacuum exhaust pump such as a cryopump in order to remove water and the like which are impurities for the oxide semiconductor as much as possible. It is preferable to exhaust to a high vacuum (from 5 × 10 ^-7 Pa to about 1 × 10 ^{-4 Pa).} In particular, at stand of the sputtering apparatus, the partial pressure of the (gas molecules corresponding to m / z = 18) Gas molecules corresponding in _{H 2} O in the chamber 1 × ¹⁰ -4 Pa or less, preferably 5 × ^{10 -5} It is preferably Pa or less. The film formation temperature is preferably RT or higher and 500 ° C. or lower, more preferably RT or higher and 300 ° C. or lower, and further preferably RT or higher and 200 ° C. or lower.

It is also necessary to purify the sputtering gas. For example, the oxygen gas or argon gas used as the sputtering gas is a gas having a dew point of -40 ° C or lower, preferably -80 ° C or lower, more preferably -100 ° C or lower, and more preferably -120 ° C or lower. By using it, it is possible to prevent water and the like from being taken into the oxide semiconductor film as much as possible.

Further, when the insulating layer, the conductive layer, the semiconductor layer or the like is formed by the sputtering method, oxygen can be supplied to the cambium by using a sputtering gas containing oxygen. The more oxygen contained in the sputtering gas, the more oxygen is likely to be supplied to the cambium.

<Example of manufacturing method of transistor 100>
An example of a method for manufacturing the transistor 100 will be described with reference to FIGS. 5 (A) to 8 (C). The cross-sectional views shown in FIGS. 5 (A) to 8 (C) correspond to the cross sections of the portions shown by the alternate long and short dash lines in FIGS. 1 (A) and X2.

[Step 1]
First, a conductive layer 181 for forming the electrode 102 is formed on the substrate 101 (see FIG. 5A). In this embodiment, aluminum borosilicate glass is used as the substrate 101. Further, in the present embodiment, a titanium layer having a thickness of 50 nm and a copper layer having a thickness of 200 nm are formed as the conductive layer 181 in order by a sputtering method.

[Step 2]
Next, a resist mask is formed (not shown). The resist mask can be formed by appropriately using a photolithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by a printing method, an inkjet method, or the like, the manufacturing cost can be reduced because the photomask is not used.

The resist mask can be formed by the photolithography method by irradiating the photosensitive resist with light through the photomask and removing the resist in the exposed portion (or the non-exposed portion) with a developing solution. .. The light irradiated to the photosensitive resist includes KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light and the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, a photomask is not required.

Using the resist mask as a mask, a part of the conductive layer 181 is selectively removed to form the electrode 102 (see FIG. 5B). The conductive layer 181 can be removed by using a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used to remove the conductive layer 181.

After removing a part of the conductive layer 181, the resist mask is removed. The resist mask can be removed by a dry etching method such as ashing or a wet etching method using a special peeling liquid or the like. Both the dry etching method and the wet etching method may be used to remove the resist mask.

Further, it is preferable that the cross-sectional shape of the side surface of the electrode 102 is a tapered shape. The taper angle θ on the side surface of the electrode 102 is preferably 20 ° or more and less than 90 °, more preferably 30 ° or more and less than 80 °, and further preferably 40 ° or more and less than 70 °. The taper angle θ indicates the angle formed by the side surface and the bottom surface of the layer when the layer having the tapered shape is observed from the cross-sectional direction (the surface orthogonal to the surface of the substrate).

By imparting a tapered shape to the side surface of the electrode 102, it is possible to prevent step breakage of the layer formed on the electrode 102 and improve the covering property. Further, by forming the side surface of the electrode 102 into a tapered shape, the electric field concentration at the upper end portion of the electrode 102 can be relaxed. On the other hand, if the taper angle θ is too small, it may be difficult to miniaturize the transistor. Further, if the taper angle θ is too small, variations such as the size of the opening and the width of the wiring may become large.

Further, the side surface of the electrode 102 may have a staircase shape. By making the side surface stepped, it is possible to prevent step breakage of the layer formed on the side surface and improve the covering property. Not only the side surface of the electrode 102, but also the end of each layer has a tapered shape or a stepped shape to prevent a phenomenon (step break) in which the layer to be coated is interrupted, and the covering property is good. can do.

[Step 3]
Next, the insulating layer 103, the insulating layer 104, and the insulating layer 105 are formed in this order (see FIG. 5C). In the present embodiment, a silicon nitride layer having a thickness of 400 nm is formed as the insulating layer 103, an aluminum oxide layer having a thickness of 30 nm is formed as the insulating layer 104, and a silicon oxide layer having a thickness of 50 nm is formed as the insulating layer 105. do.

The silicon nitride layer used for the insulating layer 103 has a three-layer laminated structure including a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer. As an example of the three-layer laminated structure, it can be formed as follows.

As the first silicon nitride layer, for example, silane gas having a flow rate of 200 sccm, nitrogen gas having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 100 sccm are supplied to the reaction chamber of the PECVD apparatus as raw materials, and the pressure in the reaction chamber is controlled to 100 Pa. , A high frequency power supply of 27.12 MHz may be used to supply a power of 2000 W, and the thickness may be 50 nm.

As the second silicon nitride layer, a silane gas having a flow rate of 200 sccm, a nitrogen gas having a flow rate of 2000 sccm, and an ammonia gas having a flow rate of 2000 sccm are supplied as raw materials gas to the reaction chamber of the PECVD apparatus, and the pressure in the reaction chamber is controlled to 100 Pa. It may be formed so that the thickness is 300 nm by supplying 2000 W of power using a high frequency power supply of .12 MHz.

As the third silicon nitride layer, silane gas having a flow rate of 200 sccm and nitrogen gas having a flow rate of 5000 sccm are supplied as raw material gas to the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and a high frequency power supply of 27.12 MHz is supplied. It may be formed so as to have a thickness of 50 nm by supplying an electric power of 2000 W.

The substrate temperature at the time of forming the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer can be 350 ° C. or lower.

By forming the silicon nitride layer into the above-mentioned three-layer laminated structure, for example, when a conductive layer containing copper is used for the electrode 102, the following effects can be obtained.

The first silicon nitride layer can suppress the diffusion of copper element from the electrode 102. The second silicon nitride layer has a function of releasing hydrogen, and can improve the withstand voltage of the insulating layer that functions as a gate insulating layer. The third silicon nitride layer emits less hydrogen from the third silicon nitride layer and can prevent the diffusion of hydrogen released from the second silicon nitride layer.

As described above, the insulating layer 104 is preferably formed by using an insulating material in which impurities are difficult to permeate. Further, it is preferable that the insulating layer 104 is formed by using an insulating material in which oxygen does not easily diffuse. The aluminum oxide layer used for the insulating layer 104 may be formed by a DC sputtering method using an aluminum target, or may be formed by an AC sputtering method using an aluminum oxide target. Further, it may be formed by the ALD method.

As the insulating layer 105, it is preferable to use an insulating layer containing excess oxygen. The insulating layer 105 may be subjected to oxygen doping treatment. Further, it is preferable to perform heat treatment after the formation of the insulating layer 105 to reduce hydrogen and moisture contained in the insulating layer 105. Oxygen doping treatment may be performed after the heat treatment. The oxygen doping treatment may be performed, for example, by heating the substrate to 350 ° C. and exciting a gas containing argon and oxygen at a frequency of 2.45 GHz. The heat treatment and the oxygen doping treatment may be repeated a plurality of times.

Further, by exposing the insulating layer 105 to the plasma atmosphere of nitrogen or an inert gas, impurities such as hydrogen and carbon on the surface of the insulating layer 105 and in the vicinity of the surface can be reduced. For example, the substrate may be heated to 350 ° C. and the insulating layer 105 may be exposed to a plasma atmosphere in which a gas containing argon and nitrogen is excited at a frequency of 2.45 GHz.

The heat treatment is performed, for example, in an inert atmosphere containing nitrogen or a rare gas, in an oxidizing atmosphere, or in the case of measuring the water content using a dew point meter of the ultra-dry air (CRDS (cavity ring-down laser spectroscopy) method). Is performed under an atmosphere of 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, preferably 10 ppb or less. The "oxidizing atmosphere" refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or oxygen nitride. Further, the “inert atmosphere” refers to an atmosphere in which the above-mentioned oxidizing gas is less than 10 ppm and is filled with nitrogen or a noble gas. Although there are no particular restrictions on the pressure during the heat treatment, it is preferable that the heat treatment is performed under reduced pressure.

The heat treatment may be performed at 150 ° C. or higher and lower than the strain point of the substrate, preferably 200 ° C. or higher and 500 ° C. or lower, and more preferably 250 ° C. or higher and 400 ° C. or lower. The processing time shall be within 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

Further, the heat treatment can be performed using an electric furnace, an RTA device, or the like. By using the RTA device, the heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, it is possible to shorten the heating time. The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air having a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (argon, helium, etc.). good. It is preferable that the nitrogen, oxygen, ultra-dry air, or noble gas does not contain hydrogen, water, or the like.

[Step 4]
Next, the oxide semiconductor layer 182 is formed (see FIG. 5D). Before forming the oxide semiconductor layer 182, oxygen gas may be supplied to generate plasma. As a result, oxygen can be added to the insulating layer 105 which is the surface to be formed of the oxide semiconductor layer 182.

The oxide semiconductor layer 182 includes an indium zinc oxide, an indium gallium zinc oxide formed by using a target having an composition of In: Ga: Zn = 5: 1: 7 [atomic number ratio], and an indium gallium zinc oxide having an composition of In :. It is preferable to use indium gallium zinc oxide or the like formed by using a target of Ga: Zn = 4: 2: 4.1 [atomic number ratio].

In the present embodiment, as the oxide semiconductor layer 182, indium gallium-zinc oxide is formed by a sputtering method using a target having a composition of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. Further, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. In this embodiment, a mixed gas of oxygen and argon having an oxygen flow rate ratio of 10% is used as the sputtering gas.

When the film formation is performed with the flow rate ratio of oxygen contained in the sputtering gas set to 0% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor layer is formed. Transistors using an oxygen-deficient oxide semiconductor layer can obtain relatively high field-effect mobilities.

Further, when the oxide semiconductor layer 182 is formed, a part of oxygen contained in the sputtering gas may be supplied to the insulating layer 105. As the amount of oxygen contained in the sputtering gas increases, the amount of oxygen supplied to the insulating layer 105 also increases. A part of the oxygen supplied to the insulating layer 105 reacts with hydrogen remaining in the insulating layer 105 to become water, and is released from the insulating layer 105 by a subsequent heat treatment. In this way, the hydrogen concentration in the insulating layer 105 can be reduced. Further, by increasing the excess oxygen in the insulating layer 105, oxygen can be supplied to the oxide semiconductor layer 182 (later oxide semiconductor layer 106) in the subsequent heat treatment.

As shown in FIGS. 4 (A) and 4 (B), when the oxide semiconductor layer 106 is a laminated layer of two or three layers, the oxide semiconductor layer for forming the oxide semiconductor layer 106_1 is used. It is formed by the above materials and methods.

Further, it is preferable to use a highly crystalline oxide semiconductor layer as the oxide semiconductor layer for forming the oxide semiconductor layer 106_2 and / or the oxide semiconductor layer 106_3. For example, it is preferable to use CAAC-OS. For example, the exposed oxide semiconductor layer may be etched during the etching step for forming the insulating layer 108, the insulating layer 109, and the electrode 112, which may cause damage to the oxide semiconductor layer. The highly crystalline oxide semiconductor layer is difficult to be etched in the etching process. By using the oxide semiconductor layer having high crystallinity for the oxide semiconductor layer 183, it is possible to reduce the damage caused to the oxide semiconductor layer in the etching process. Therefore, the reliability of the transistor can be improved.

As the oxide semiconductor layer for forming the oxide semiconductor layer 106_2 and / or the oxide semiconductor layer 106_3, for example, indium gallium-zinc oxide is composed of In: Ga: Zn = 1: 1: 1.2 [number of atoms]. It is formed by a sputtering method using a target of [ratio]. Further, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. For example, oxygen is used as the sputtering gas at a ratio of 100%. The flow ratio of oxygen contained in the sputtering gas for forming the oxide semiconductor layer 106_2 and / or the oxide semiconductor layer 106_3 is preferably 70% or more, more preferably 80% or more, still more preferably 100%. By increasing the ratio (flow rate ratio) of oxygen contained in the sputtering gas, the crystallinity of the oxide semiconductor layer can be improved.

By introducing an impurity element after the formation of the oxide semiconductor layer 182, the threshold voltage of the transistor 100 can be changed. The impurity element can be introduced by an ion implantation method, an ion doping method, a plasma implantation ion implantation method, a plasma treatment using a gas containing the impurity element, or the like.

Further, after the oxide semiconductor layer 182 is formed, a heat treatment may be performed or an oxygen doping treatment may be performed. The heat treatment and the oxygen doping treatment may be repeated a plurality of times.

Further, after the heat treatment is performed in a nitrogen or noble gas atmosphere, the heat treatment may be performed in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water and the like contained in the oxide semiconductor layer can be desorbed, and oxygen can be supplied to the oxide semiconductor layer. As a result, oxygen deficiency contained in the oxide semiconductor layer can be reduced.

[Step 5]
Next, a resist mask is formed by a photolithography method (not shown). Using the resist mask as a mask, a part of the oxide semiconductor layer 182 is selectively removed to form an island-shaped oxide semiconductor layer 106 (see FIG. 6A).

The oxide semiconductor layer 182 can be removed by using a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used to remove the oxide semiconductor layer 182.

As shown in FIGS. 4A and 4B, when the semiconductor layer 106 is a two-layer or three-layer laminate, the oxide semiconductor layer 106_1 and the oxide are formed after the oxide semiconductor layer 106_1 is formed. The heat treatment may be performed after the formation of the semiconductor layer 106_2, or after the formation of the oxide semiconductor layer 106_1 to the oxide semiconductor layer 106_1, or the oxygen doping treatment may be performed. The heat treatment and the oxygen doping treatment may be repeated.

[Step 6]
Next, the insulating layer 108 and the insulating layer 109 are formed in order (see FIG. 6B). It is preferable that the insulating layer 108 and the insulating layer 109 are continuously formed without being exposed to the atmosphere on the way.

The insulating layer 108 is preferably an insulating layer containing excess oxygen. The thickness of the insulating layer 108 may be 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less. Further, by using an insulating layer capable of transmitting oxygen as the insulating layer 108, oxygen contained in the insulating layer 109 to be formed later can be transferred to the oxide semiconductor layer 106.

For example, as the insulating layer 108, a silicon oxide nitride layer formed by the PECVD method can be used. In this case, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane gas, disilane gas, trisilane gas, fluorinated silane gas and the like. Examples of the oxidizing gas include nitrous oxide gas and nitrogen dioxide gas. Further, the flow rate of the oxidizing gas is set to 20 times or more and 5000 times or less, preferably 40 times or more and 100 times or less with respect to the flow rate of the above-mentioned sedimentary gas.

In the present embodiment, a silicon oxide nitride layer having a thickness of 30 nm is formed as the insulating layer 108. Specifically, the substrate temperature is 350 ° C., silane gas having a flow rate of 20 sccm and nitrous oxide gas having a flow rate of 3000 sccm are used as raw material gases, the pressure in the processing chamber is set to 200 Pa, and the high frequency power supplied to the parallel plate electrode is 13.56 MHz. , The PECVD method of 100 W is used to form a silicon oxide nitride layer.

The insulating layer 109 is preferably an insulating layer containing excess oxygen. The thickness of the insulating layer 109 may be 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less.

Further, the insulating layer 109 preferably has a small amount of defects, and typically, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 1.5 × 10 ^{18 by ESR measurement.} It is preferably less than spins / cm ³ and more preferably 1 × 10 ¹⁸ spins / cm ^{3 or less.} Since the insulating layer 109 is separated from the oxide semiconductor layer 106 as compared with the insulating layer 108, the defect density may be higher than that of the insulating layer 108.

As the insulating layer 109, a silicon oxide layer or a silicon nitride nitride layer formed by the PECVD method can be used. For example, the substrate placed in the vacuum-exhausted processing chamber of the PECVD apparatus is kept at 180 ° C. or higher and 400 ° C. or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably. and 100Pa or more 200Pa or less, the process in the electrode provided in the indoor 0.17 W / cm ² or more 0.5 W / cm ² or less, more preferably supply the following high-frequency power 0.25 W / cm ² or more 0.35 W / cm ² A silicon oxide layer or a silicon nitride layer is formed depending on the conditions.

In the formation of the insulating layer 109, the high frequency power of the power density is supplied in the reaction chamber of the pressure, so that the decomposition efficiency of the raw material gas is enhanced in the plasma. That is, the oxygen radicals in the reaction chamber increase, and the oxidation of the raw material gas proceeds. Therefore, the oxygen content in the formed insulating layer 109 is higher than the stoichiometric composition.

Further, in the insulating layer formed at the above substrate temperature, since the bonding force between silicon and oxygen is weak, a part of oxygen in the insulating layer is desorbed by the heat treatment in the subsequent step. As a result, it is possible to form an oxide insulating layer containing more oxygen than oxygen satisfying the stoichiometric composition and desorbing a part of oxygen by heating.

In the present embodiment, a silicon oxide nitride layer having a thickness of 100 nm is formed as the insulating layer 109. Specifically, the substrate temperature is 220 ° C., silane gas having a flow rate of 160 sccm and nitrous oxide gas having a flow rate of 4000 sccm are used as raw material gases, the pressure in the processing chamber is 200 Pa, and the high frequency power supplied to the parallel plate electrode is 13.56 MHz. A silicon oxide nitride layer is formed by using a PECVD method of 1500 W.

In the process of forming the insulating layer 109, the insulating layer 108 serves as a protective layer for the oxide semiconductor layer 106. Therefore, the insulating layer 109 can be formed by using high frequency power having a high power density while reducing damage to the oxide semiconductor layer 106.

It is possible to reduce the amount of defects in the insulating layer 109 by increasing the flow rate of the sedimentary gas containing silicon with respect to the oxidizing gas under the conditions for forming the insulating layer 109. Typically, by ESR measurement, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon ^{is less than 6 × 10 17} spins / cm ³ , preferably 3 × 10 ¹⁷ spins / cm ³ or less. It is possible to form an oxide insulating layer having a small amount of defects, preferably 1.5 × 10 ¹⁷ spins / cm ^{3 or less.} As a result, the reliability of the transistor can be improved.

[Step 7]
A conductive layer 185 for forming the electrode 112 is formed on the insulating layer 109 (see FIG. 6C). In this embodiment, an indium gallium zinc oxide layer is used as the conductive layer 185. More specifically, a two-layer laminate of indium gallium zinc oxide is used as the conductive layer 185.

First, an indium gallium zinc oxide layer having a thickness of 10 nm was formed by using a target having a composition of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] and a sputtering gas containing 100% oxygen. Form. Next, using a target having a composition of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] and a sputtering gas having an oxygen ratio of 10% and an argon ratio of 90%, the thickness is increased. A 90 nm indium gallium zinc oxide layer is formed.

[Step 8]
Next, a resist mask is formed by a photolithography method (not shown). Using the resist mask as a mask, a part of the conductive layer 185 is selectively removed to form the electrode 112. At this time, the electrode 112 is also used as a mask to selectively remove a part of the insulating layer 108 and the insulating layer 109 (see FIG. 6D). By step 8, a part of the oxide semiconductor layer 106 is exposed.

The conductive layer 185, the insulating layer 108, and the insulating layer 109 can be removed by using a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used to remove the conductive layer 185, the insulating layer 108, and the insulating layer 109.

[Step 9]
Next, the impurity 171 is introduced into the region exposed in step 8 of the oxide semiconductor layer 106 (see FIG. 7A). Impurities may be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. By introducing an impurity such as nitrogen into the region, the resistance value in the region can be reduced.

Further, the region may be exposed to a plasma atmosphere of nitrogen or an inert gas. By exposing the region to a plasma atmosphere, it is possible to cause defects in the region and reduce the resistance value of the region.

The region in which impurities are introduced in the oxide semiconductor layer 106 or the region exposed to the plasma atmosphere can function as a source region or a drain region of the transistor. Further, the region overlapping the electrode 112 of the oxide semiconductor layer 106 can function as a channel forming region. That is, the source region and the drain region of the transistor can be formed by self-alignment.

In this embodiment, plasma treatment is performed in an atmosphere containing argon and nitrogen.

[Step 10]
Next, the heat treatment is performed in an inert atmosphere to reduce hydrogen and water contained in the oxide semiconductor layer 106, the insulating layer 108 and the insulating layer 109. Further, by performing the heat treatment after the step 9, the resistance values of the source region and the drain region of the oxide semiconductor layer 106 may decrease. The heat treatment may be performed under reduced pressure without supplying a gas such as an inert gas. In this embodiment, heat treatment is performed at 350 ° C. for 1 hour in a nitrogen atmosphere.

[Step 11]
Subsequently, the heat treatment may be performed in an oxidizing atmosphere. In this embodiment, heat treatment is performed at 350 ° C. for 1 hour in an oxygen atmosphere. For example, in the case of introducing nitrogen into the oxide semiconductor layer 106 in step 8, by performing heat treatment in an oxygen atmosphere, there is a case where NO _X in the source region and the drain region is increased, the resistance value decreases. Either step 10 or step 11 may be omitted.

[Step 12]
Next, the insulating layer 110 is formed (see FIG. 7B). As described above, the insulating layer 110 is preferably formed by using an insulating material in which impurities are difficult to permeate. Further, it is preferable that the insulating layer 110 is formed by using an insulating material in which oxygen does not easily diffuse. The thickness of the insulating layer 110 may be 5 nm to 40 nm.

In the present embodiment, an aluminum oxide layer having a thickness of 30 nm is formed as the insulating layer 110 by a sputtering method. When the insulating layer 110 is formed by the sputtering method, the formation temperature (substrate temperature) is preferably RT or higher and 400 ° C. or lower, more preferably RT or higher and 300 ° C. or lower, and further preferably RT or higher and 150 ° C. or lower. Further, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. The flow rate ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%. By using a sputtering gas containing oxygen, oxygen can be supplied to the cambium (insulating layer 108). The more oxygen contained in the sputtering gas, the more oxygen is likely to be supplied to the cambium. In this embodiment, 100% oxygen is used as the sputtering gas.

The aluminum oxide layer used for the insulating layer 110 may be formed by a DC sputtering method using an aluminum target, or may be formed by an AC sputtering method using an aluminum oxide target. After forming the insulating layer 110, the insulating layer 110 may be subjected to oxygen doping treatment.

Further, as the insulating layer 110, a silicon nitride layer containing no or little hydrogen may be used. Such a silicon nitride layer can be formed by, for example, a sputtering method.

When the insulating layer 111 is formed on the insulating layer 110 as in the transistor 100 shown in FIG. 3, it is preferable to form the aluminum oxide layer as the insulating layer 111 by a sputtering method or an ALD method. The thickness of the insulating layer 111 may be 5 nm to 40 nm. In particular, by forming the aluminum oxide layer by the ALD method, an aluminum oxide layer having good coverage can be provided. Therefore, the reliability of the transistor can be improved. Further, a silicon nitride layer may be used as the insulating layer 111.

Further, the density of the aluminum oxide layer formed by the sputtering method can be changed depending on the film formation temperature. For example, when the aluminum oxide layer is formed into a film at RT or more and 130 ° C. or less, an aluminum oxide layer having a density of 2.8 or more and 2.9 g / cm ³ or less can be obtained. Further, when the aluminum oxide layer is formed into a film at 250 ° C., an aluminum oxide layer having a density of ^{about 3.3 g / cm 3} can be obtained (see Example 2).

The aluminum oxide layer may absorb hydrogen by heating. Therefore, if an aluminum oxide layer is formed as the insulating layer 110 and then heat-treated, the hydrogen concentration and water content in the adjacent layers may decrease. The amount of hydrogen absorbed by the aluminum oxide layer increases as the density decreases. In particular, an aluminum oxide layer having a density of 3.0 g / cm ³ or less is preferable because it absorbs a large amount of hydrogen. The formation of the aluminum oxide layer having a density of 3.0 g / cm ³ or less can be realized not only by the sputtering method but also by heat-treating or plasma-treating the aluminum layer in an oxidizing atmosphere.

Steps 10 to 12 are continuously performed without being exposed to the atmosphere on the way. By doing so, it is possible to prevent the adsorption of hydrogen, moisture, etc. to the oxide semiconductor layer 106, and improve the reliability of the transistor. Further, by covering the oxide semiconductor layer 106 with the insulating layer 110, it is possible to prevent the infiltration of hydrogen, moisture and the like from the outside. In addition, it is possible to prevent the diffusion of oxygen to the outside.

[Step 13]
Next, the insulating layer 115 is formed (see FIG. 7C). In the present embodiment, a silicon oxide nitride layer having a thickness of 300 nm is formed as the insulating layer 115. Specifically, the substrate temperature is 220 ° C., silane gas having a flow rate of 160 sccm and nitrous oxide gas having a flow rate of 4000 sccm are used as raw material gases, the pressure in the processing chamber is 200 Pa, and the high frequency power supplied to the parallel plate electrode is 13.56 MHz. A silicon oxide nitride layer is formed by using a PECVD method of 1500 W.

[Step 14]
Next, a resist mask is formed by a photolithography method (not shown). Using the resist mask as a mask, a part of each of the insulating layer 115 and the insulating layer 110 is selectively removed to form an opening 186 (see FIG. 8A). At this time, a part of the oxide semiconductor layer 106 is exposed.

[Step 15]
Next, the conductive layer 186 is formed (see FIG. 8B). In particular, since the conductive layer 186 is in contact with the oxide semiconductor layer 106, it is preferable to use a conductive material having a function of absorbing hydrogen by heat treatment. By using such a material for the conductive layer 186, the hydrogen concentration in the oxide semiconductor layer 106 can be reduced by the subsequent heat treatment. Examples of conductive materials having a function of absorbing hydrogen include titanium, indium zinc oxide, and indium tin oxide to which silicon is added.

In this embodiment, a laminate of a titanium layer and a copper layer is used as the conductive layer 186. Specifically, a titanium layer having a thickness of 30 nm is formed, and a copper layer having a thickness of 200 nm is formed on the titanium layer.

[Step 16]
Next, a resist mask is formed by a photolithography method (not shown). Using the resist mask as a mask, a part of the conductive layer 186 is selectively removed to form the electrodes 114a and 114b (see FIG. 8C).

The conductive layer 186 can be removed by using a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used to remove the conductive layer 186.

After removing the resist mask, heat treatment may be performed. For example, heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere.

[Modification example]
Here, an example of a forming method different from the forming method of the insulating layer 110 described in the step 12 will be described.

For example, when a metal oxide layer is formed as the insulating layer 110 by a sputtering method, particles may be generated in the sputtering apparatus depending on the forming conditions. The particles contribute to a decrease in the manufacturing yield of the transistor.

Hereinafter, an example of a method for forming a metal oxide layer in which particles are unlikely to be generated will be described. Here, a case where an aluminum oxide layer is formed as the insulating layer 110 will be described.

The formation of the metal oxide layer can be realized by a method of forming a metal layer and oxidizing the metal layer, in addition to the sputtering method and the ALD method.

First, the metal layer 188 is formed. Here, an aluminum layer having a thickness of 10 nm is formed as the metal layer 188 (see FIG. 9A). At this time, a part of the metal element contained in the metal layer 188 is supplied into the oxide semiconductor layer 106 in contact with the metal layer 188. The resistance value of the oxide semiconductor layer 106 in the region to which the metal element is supplied decreases. Therefore, the region can function as a source region or a drain region. That is, the source region and the drain region of the transistor can be formed by self-alignment. Therefore, the above-mentioned step 9 can be omitted.

Next, heat treatment is performed in an oxidizing atmosphere, or plasma treatment is performed in an oxidizing atmosphere (see FIG. 9B). The above-mentioned oxygen doping treatment may be performed on the metal layer 188. Then, the metal layer 188 is oxidized to become a metal oxide layer (insulating layer 110) (see FIG. 9C). The plasma treatment may be performed while performing the heat treatment in an oxidizing atmosphere. In particular, in the step of oxidizing the metal layer 187, plasma treatment in an oxidizing atmosphere is preferable. As a step of oxidizing the metal layer 187, oxygen can be supplied to the insulating layer 108 or the insulating layer 109 by performing plasma treatment in an oxidizing atmosphere.

By contacting the metal layer 188 with the oxide semiconductor layer 106 and performing heat treatment, oxygen in the oxide semiconductor layer 106 and / or oxygen in the insulating layer 105 is absorbed by the metal layer 188 (FIG. 10 (FIG. 10). A), it may be a metal oxide layer (insulating layer 110) (see FIG. 10B). This phenomenon becomes remarkable when the oxide semiconductor layer 106 and / or the insulating layer 105 contains excess oxygen. Further, in the oxide semiconductor layer 106 in the region where oxygen is absorbed, oxygen deficiency may increase and the resistance value may decrease.

The method for forming the metal oxide layer is not limited to aluminum oxide, but can also be used for magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide and the like. ..

Therefore, as the metal layer 188, at least one of aluminum, magnesium, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum and the like can be used.

After forming the insulating layer 110 by the above method, the insulating layer 111 may be provided. As described above, the insulating layer 111 can be formed by an ALD method, a sputtering method, or the like. Further, the insulating layer 111 may be formed by the above method.

Further, if the insulating layer 110 is formed by the above method and then the insulating layer 111 is formed by a sputtering method using a sputtering gas containing oxygen, oxygen can be supplied to the insulating layer 110. Therefore, the insulating layer 110 can be an insulating layer containing excess oxygen.

Further, by forming the insulating layer 111 by a sputtering method using a sputtering gas containing oxygen after forming the metal layer 188, the metal layer 188 can be made into a metal oxide layer (insulating layer 110).

<Modification example of transistor 100>
A modification of the transistor 100 will be described with reference to the drawings.

[Modification 1]
FIG. 11A is a plan view of the transistor 100A. 11 (B) is a cross-sectional view of the portion shown by the alternate long and short dash line of X1-X2 shown in FIG. 11 (A). 11 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line of Y1-Y2 shown in FIG. 11 (A).

The transistor 100A differs from the transistor 100 in that the electrode 114c is provided on the insulating layer 115. The electrode 114c can be provided in the same process using the same materials and methods as the electrodes 114a and 114b. The electrode 114c is electrically connected to the electrode 112 at an opening provided in each of the insulating layer 115 and the insulating layer 110.

Further, the transistor 100A is different from the transistor 100 in that it has a region 123 surrounding the outside of the oxide semiconductor layer 106 when viewed in a plan view. In the region 123, the insulating layer 105 is removed, and the insulating layer 104 and the insulating layer 110 are in contact with each other.

By providing the region 123, the effect of preventing the infiltration of hydrogen, water, etc. from the outside can be enhanced. In addition, the effect of preventing the diffusion of oxygen to the outside can be enhanced.

[Modification 2]
FIG. 12A is a plan view of the transistor 100B. 12 (B) is a cross-sectional view of the portion shown by the alternate long and short dash line of X1-X2 shown in FIG. 12 (A). 12 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line of Y1-Y2 shown in FIG. 12 (A). 13 (A) is an enlarged view of the portion 131B shown in FIG. 12 (B). 13 (B) is an enlarged view of the portion 132B shown in FIG. 12 (C).

The transistor 100B has a different shape from that of the transistor 100 in the insulating layer 105. The transistor 100A has an island-shaped insulating layer 105 that overlaps with the oxide semiconductor layer 106. The island-shaped insulating layer 105 can be formed by continuously removing a part of the exposed insulating layer 105 when the oxide semiconductor layer 106 is formed in step 5.

Further, in the transistor 100B, the insulating layer 110 and the insulating layer 104 extend beyond the end portion of the oxide semiconductor layer 106 and the end portion of the insulating layer 105, and have a region in contact with each other. With such a configuration, the effect of preventing the infiltration of hydrogen, water, etc. from the outside can be enhanced. In addition, the effect of preventing the diffusion of oxygen to the outside can be enhanced.

[Modification 3]
FIG. 14A is a plan view of the transistor 100C. 14 (B) is a cross-sectional view of the portion shown by the alternate long and short dash line of X1-X2 shown in FIG. 14 (A). 14 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line of Y1-Y2 shown in FIG. 14 (A).

The transistor 100C is different from the transistor 100 in the shapes of the insulating layer 108 and the insulating layer 109. The transistor 100C has a structure in which the insulating layer 108 and the insulating layer 109 cover the oxide semiconductor layer 106. The transistor 100C leaves the insulating layer 108 and the insulating layer 109 unetched when the electrode 112 is formed in step 8.

By covering the oxide semiconductor layer 106 with the insulating layer 108 and the insulating layer 109, the amount of oxygen supplied from the insulating layer 108 and the insulating layer 109 to the oxide semiconductor layer 106 can be increased.

[Modification 4]
FIG. 15A is a plan view of the transistor 100D. 15 (B) is a cross-sectional view of a portion shown by the alternate long and short dash line of X1-X2 shown in FIG. 15 (A). 15 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line of Y1-Y2 shown in FIG. 15 (A).

The transistor 100D has a configuration in which the electrode 102 is removed from the transistor 100. The electrode 102 may not be provided depending on the performance and purpose required for the transistor. By not providing the electrode 102, the number of transistor manufacturing steps is reduced, so that the manufacturing cost can be reduced. In addition, the manufacturing yield of the transistor can be increased.

[Modification 5]
FIG. 16A is a plan view of the transistor 100E. 16 (B) is a cross-sectional view of the portion shown by the alternate long and short dash line of X1-X2 shown in FIG. 16 (A). 16 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line of Y1-Y2 shown in FIG. 16 (A). FIG. 17 is an enlarged view of the portion 131E shown in FIG. 16 (B).

The transistor 100E differs from the transistor 100 in that the insulating layer 118 is provided between the insulating layer 109 and the electrode 112. The insulating layer 118 may be formed by the same material and method as the insulating layer 108 or the insulating layer 109.

For example, as the insulating layer 118, a silicon oxide nitride layer having a thickness of 20 nm is formed. Specifically, the substrate temperature is 350 ° C., silane gas having a flow rate of 20 sccm and nitrous oxide gas having a flow rate of 3000 sccm are used as raw material gases, the pressure in the processing chamber is set to 200 Pa, and the high frequency power supplied to the parallel plate electrode is 13.56 MHz. , The PECVD method of 100 W is used to form a silicon oxide nitride layer.

Further, by using an insulating layer containing excess oxygen as the insulating layer 118, the amount of oxygen supplied to the oxide semiconductor layer 106 can be increased.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

(Embodiment 2)
In this embodiment, a display device and a display module will be described as an example of the semiconductor device using the transistor disclosed in the present specification and the like.

<Display device>
An example of a display device that can use the above-mentioned transistor will be described. FIG. 20A is a block diagram illustrating a configuration example of the display device 500.

The display device 500 shown in FIG. 20A has a drive circuit 511, a drive circuit 521a, a drive circuit 521b, and a display area 531. The drive circuit 511, the drive circuit 521a, and the drive circuit 521b may be collectively referred to as a "drive circuit" or a "peripheral drive circuit".

The drive circuit 521a and the drive circuit 521b can function as, for example, a scanning line drive circuit. Further, the drive circuit 511 can function as, for example, a signal line drive circuit. The drive circuit 521a and the drive circuit 521b may be either one or the other. Further, some kind of circuit may be provided at a position facing the drive circuit 511 across the display area 531.

Further, the display devices 500 exemplified in FIG. 20A are each arranged substantially in parallel, and have p wirings 535 whose potentials are controlled by the drive circuit 521a and / or the drive circuit 521b, respectively. Are arranged substantially in parallel and have q wirings 536 whose potential is controlled by the drive circuit 511 (p and q are both natural numbers of 1 or more). Further, the display area 531 has a plurality of pixels 532 arranged in a matrix. Pixel 532 has a pixel circuit 534 and a display element.

Further, by making the three pixels 532 function as one pixel, full-color display can be realized. Each of the three pixels 532 controls the transmittance, reflectance, or amount of emitted light of red light, green light, or blue light. The color of the light controlled by the three pixels 532 is not limited to the combination of red, green, and blue, and may be yellow, cyan, or magenta.

Further, the pixel 532 that controls white light may be added to the pixel that controls red light, green light, and blue light, and the four pixels 532 may be collectively functioned as one pixel. By adding the pixel 532 that controls the white light, the brightness of the display area can be increased. Further, by increasing the number of pixels 532 that function as one pixel and using red, green, blue, yellow, cyan, and magenta in appropriate combinations, the reproducible color gamut can be expanded.

By arranging the pixels in a matrix of 1920 × 1080, it is possible to realize a display device 500 capable of displaying at a so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution. Further, for example, by arranging the pixels in a matrix of 3840 × 2160, a display device 500 capable of displaying at a so-called ultra-high definition (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) resolution is realized. be able to. Further, for example, by arranging the pixels in a matrix of 7680 × 4320, a display device 500 capable of displaying at a resolution of so-called super high definition (also referred to as “8K resolution”, “8K4K”, “8K”, etc.) is realized. be able to. By increasing the number of pixels, it is possible to realize a display device 500 capable of displaying at a resolution of 16K or 32K.

The wiring 535_g in the gth row (g is a natural number of 1 or more and p or less) is the q pixels arranged in the g row among the plurality of pixels 532 arranged in the p row and the q column in the display area 531. It is electrically connected to 532. Further, the wiring 536_h in the hth column (h is a natural number of 1 or more and q or less) is electrically connected to the p pixels 532 arranged in the h column among the pixels 532 arranged in the p row and the q column. Connected to.

[Display element]
The display device 500 can use various forms or have various display elements. Examples of display elements include EL (electroluminescence) elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic substances), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors. (Transistor that emits light according to current), electron emitting element, liquid crystal element, electronic ink, electrophoresis element, grating light valve (GLV), display element using MEMS (micro electro mechanical system), digital micromirror Device (DMD), DMS (Digital Micro Shutter), MIRASOL®, IMOD (Interference Modulation) Element, Shutter MEMS Display Element, Optical Interference MEMS Display Element, Electrowetting Element, Some have a display medium such as a piezoelectric ceramic display and a display element using carbon nanotubes, in which the contrast, brightness, reflectance, transmittance, etc. are changed by an electric or magnetic action. Further, quantum dots may be used as the display element.

An EL display or the like is an example of a display device using an EL element. As an example of a display device using an electron emitting element, there is a field emission display (FED) or an SED type planar display (SED: Surface-conduction Electron-emitter Display). An example of a display device using quantum dots is a quantum dot display. An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display). An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. Further, the display device may be a plasma display panel (PDP). Further, the display device may be a retinal scanning type projection device.

In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

When an LED is used, graphene or graphite may be arranged under the electrode of the LED or the nitride semiconductor. Graphene and graphite may be formed by stacking a plurality of layers to form a multilayer film. By providing graphene or graphite in this way, a nitride semiconductor, for example, an n-type GaN semiconductor layer having crystals can be easily formed on the graphene. Further, a p-type GaN semiconductor layer having crystals or the like can be provided on the p-type GaN semiconductor layer to form the LED. An AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED can be formed by a sputtering method.

20 (B), 20 (C), 21 (A), and 21 (B) show a circuit configuration example that can be used for the pixel 532.

[Example of pixel circuit for light emitting display device]
The pixel circuit 534 shown in FIG. 20B includes a transistor 461, a capacitive element 463, a transistor 468, and a transistor 464. Further, the pixel circuit 534 shown in FIG. 20B is electrically connected to a light emitting element 469 that can function as a display element.

OS transistors can be used for the transistor 461, the transistor 468, and the transistor 464. In particular, it is preferable to use an OS transistor for the transistor 461.

One of the source and drain of the transistor 461 is electrically connected to the wiring 536_h. Further, the gate of the transistor 461 is electrically connected to the wiring 535_g. A video signal is supplied from the wiring 536_h.

The transistor 461 has a function of controlling the writing of the video signal to the node 465.

One of the pair of electrodes of the capacitive element 463 is electrically connected to the node 465 and the other is electrically connected to the node 467. Also, the other of the source and drain of the transistor 461 is electrically connected to the node 465.

The capacitance element 463 has a function as a holding capacitance for holding the data written in the node 465.

One of the source and drain of the transistor 468 is electrically connected to the potential supply line VL_a and the other is electrically connected to the node 467. Further, the gate of the transistor 468 is electrically connected to the node 465.

One of the source and drain of the transistor 464 is electrically connected to the potential supply line V0 and the other is electrically connected to the node 467. Further, the gate of the transistor 464 is electrically connected to the wiring 535_g.

One of the anode or cathode of the light emitting element 469 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the node 467.

As the light emitting element 469, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 469 is not limited to this, and for example, an inorganic EL element made of an inorganic material may be used.

For example, one of the potential supply line VL_a or the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.

In the display device 500 having the pixel circuit 534 of FIG. 20 (B), the pixel 532 of each row is sequentially selected by the drive circuit 521a and / or the drive circuit 521b, and the transistor 461 and the transistor 464 are turned on to transmit a video signal. Write to node 465.

The pixel 532 in which the data is written to the node 465 is put into a holding state when the transistor 461 and the transistor 464 are turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 468 is controlled according to the potential of the data written in the node 465, and the light emitting element 469 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

Further, as shown in FIG. 21A, a transistor having a back gate may be used as the transistor 461, the transistor 464, and the transistor 468. In the transistor 461 and the transistor 464 shown in FIG. 21 (A), the gate is electrically connected to the back gate. Therefore, the gate and the back gate always have the same potential. Further, the back gate of the transistor 468 is electrically connected to the node 467. Therefore, the back gate always has the same potential as the node 467.

The transistor shown in the above embodiment can be used for at least one of the transistor 461, the transistor 468, and the transistor 464.

[Example of pixel circuit for liquid crystal display device]
The pixel circuit 534 shown in FIG. 20C includes a transistor 461 and a capacitive element 463. Further, the pixel circuit 534 shown in FIG. 20C is electrically connected to a liquid crystal element 462 that can function as a display element. It is preferable to use an OS transistor for the transistor 461.

The potential of one of the pair of electrodes of the liquid crystal element 462 is appropriately set according to the specifications of the pixel circuit 534. For example, a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 462, or the potential may be the same as that of the capacitance line CL described later. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 462 for each pixel 532. The other of the pair of electrodes of the liquid crystal element 462 is electrically connected to the node 466. The orientation state of the liquid crystal element 462 is set by the data written to the node 466.

Examples of the driving method of the display device provided with the liquid crystal element 462 include a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a VA mode, an ASM (Axially Synmetrical Defined Micro-cell) mode, and an OCBlent (Occere) mode. Mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Element) mode, IPS mode, FFS mode, or TBA (Transvert) mode may be used. In addition to the driving method described above, the display device can be driven by an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, or the like. However, the present invention is not limited to this, and various liquid crystal elements and various driving methods thereof can be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like depending on the conditions.

Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing the liquid crystal showing the blue phase and the chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require an orientation treatment, and has a small viewing angle dependence. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .. Therefore, it is possible to improve the productivity of the liquid crystal display device.

Further, it is possible to use a method called multi-domain or multi-domain design, in which a pixel is divided into several areas (sub-pixels) and the molecules are tilted in different directions.

The intrinsic resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. The value of the intrinsic resistance in the present specification is a value measured at 20 ° C.

In the pixel circuit 534 in the g-row and h-th column, one of the source and drain of the transistor 461 is electrically connected to the wiring 536_h, and the other is electrically connected to the node 466. The gate of transistor 461 is electrically connected to wiring 535_g. A video signal is supplied from the wiring 536_h. The transistor 461 has a function of controlling the writing of a video signal to the node 466.

One of the pair of electrodes of the capacitive element 463 is electrically connected to a wiring (hereinafter, capacitive line CL) to which a specific potential is supplied, and the other is electrically connected to a node 466. The potential value of the capacitance line CL is appropriately set according to the specifications of the pixel circuit 534. The capacitance element 463 has a function as a holding capacitance for holding the data written in the node 466.

For example, in the display device 500 having the pixel circuit 534 of FIG. 20C, the pixel circuit 534 of each row is sequentially selected by the drive circuit 521a and / or the drive circuit 521b, the transistor 461 is turned on, and the video is sent to the node 466. Write a signal.

The pixel circuit 534 in which the video signal is written to the node 466 is put into a holding state when the transistor 461 is turned off. By sequentially performing this line by line, an image can be displayed in the display area 531.

Further, as shown in FIG. 21B, a transistor having a back gate in the transistor 461 may be used. In the transistor 461 shown in FIG. 21B, the gate is electrically connected to the back gate. Therefore, the gate and the back gate always have the same potential.

[Example of peripheral circuit configuration]
FIG. 22A shows a configuration example of the drive circuit 511. The drive circuit 511 has a shift register 512, a latch circuit 513, and a buffer 514. Further, FIG. 22B shows a configuration example of the drive circuit 521a. The drive circuit 521a has a shift register 522 and a buffer 523. The drive circuit 521b can also have the same configuration as the drive circuit 521a.

A start pulse SP, a clock signal CLK, and the like are input to the shift register 512 and the shift register 522.

[Display device configuration example]
Using the transistor shown in the above embodiment, a part or the whole of the drive circuit including the shift register can be integrally formed on the same substrate as the pixel portion to form a system on panel.

In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using an EL element will be described. In FIG. 23A, a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In FIG. 23A, a signal line formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. A drive circuit 4003 and a scanning line drive circuit 4004 are mounted. Further, various signals and potentials given to the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel unit 4002 are supplied from FPC4018a (FPC: Flexible printed circuit), FPC4018b.

In FIGS. 23B and 23C, a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. Further, a second substrate 4006 is provided on the pixel unit 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005, and the second substrate 4006. In FIGS. 23B and 23C, a single crystal semiconductor or a polycrystalline semiconductor is placed on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The signal line drive circuit 4003 formed by the above is mounted. In FIGS. 23B and 23C, various signals and potentials given to the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel unit 4002 are supplied from the FPC 4018.

Further, FIGS. 23 (B) and 23 (C) show an example in which the signal line drive circuit 4003 is separately formed and mounted on the first substrate 4001, but the configuration is not limited to this. The scanning line drive circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

The method for connecting the separately formed drive circuit is not particularly limited, and wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), COF (Chip On Film), and the like can be used. FIG. 23 (A) is an example of mounting the signal line drive circuit 4003 and the scanning line drive circuit 4004 by COG, and FIG. 23 (B) is an example of mounting the signal line drive circuit 4003 by COG. (C) is an example of mounting the signal line drive circuit 4003 by TCP.

Further, the display device may include a panel in which the display element is sealed and a module in which an IC or the like including a controller is mounted on the panel.

Further, the pixel portion and the scanning line drive circuit provided on the first substrate have a plurality of transistors, and the transistors shown in the above embodiment can be applied.

24 (A) and 24 (B) are cross-sectional views showing a cross-sectional configuration of a portion shown by a chain line of N1-N2 in FIG. 23 (B). FIG. 24A is an example of a liquid crystal display device using a liquid crystal element as a display element. Further, FIG. 24B is an example of a light emitting display device (also referred to as “EL display device”) using a light emitting element as a display element.

The display device shown in FIGS. 24 (A) and 24 (B) has an electrode 4015, and the electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. Further, the electrode 4015 is electrically connected to the wiring 4014 at the opening formed in the insulating layer 4112.

The electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed of the same conductive layer as the transistor 4010 and the source electrode and drain electrode of the transistor 4011.

Further, the pixel unit 4002 and the scanning line drive circuit 4004 provided on the first substrate 4001 have a plurality of transistors, and are included in the pixel unit 4002 in FIGS. 24 (A) and 24 (B). The transistor 4010 and the transistor 4011 included in the scanning line drive circuit 4004 are exemplified. In FIG. 24A, the insulating layer 4110 and the insulating layer 4111 are provided so as to cover the semiconductor layers of the transistor 4010 and the transistor 4011, and in FIG. 24B, the partition wall 4510 is formed on the insulating layer 4112. There is.

Further, the transistor 4010 and the transistor 4011 are provided on the insulating layer 4102. Further, the transistor 4010 and the transistor 4011 have an electrode 4017 formed on the insulating layer 4102, and the insulating layer 4104 and the insulating layer 4103 are formed on the electrode 4017. The electrode 4017 can function as a back gate electrode.

As the transistor 4010 and the transistor 4011, the transistor shown in the above embodiment can be used. It is preferable to use an OS transistor as the transistor 4010 and the transistor 4011. The OS transistor has suppressed fluctuations in electrical characteristics and is electrically stable. Therefore, the display device of the present embodiment shown in FIGS. 24 (A) and 24 (B) can be a highly reliable display device.

Further, the OS transistor can lower the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, since the OS transistor can obtain a relatively high field effect mobility, it can be driven at high speed. Therefore, by using the above-mentioned transistor in the drive circuit unit and the pixel unit of the display device, it is possible to provide a high-quality image. Further, since the drive circuit unit or the pixel unit can be manufactured separately on the same substrate, the number of parts of the display device can be reduced.

Further, the display device shown in FIGS. 24 (A) and 24 (B) has a capacitive element 4020. The capacitive element 4020 has an electrode 4021 formed in the same process as the back gate electrode of the transistor 4010, and an electrode formed in the same process as the gate electrode. The respective electrodes are overlapped with each other via the insulating layer 4103.

Generally, the capacitance of the capacitance element provided in the pixel portion of the display device is set so as to hold the electric charge for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. The capacitance of the capacitive element may be set in consideration of the off current of the transistor and the like.

For example, by using an OS transistor in the pixel portion of the liquid crystal display device, the capacity of the capacitive element can be reduced to 1/3 or less, and further to 1/5 or less of the liquid crystal capacity. By using an OS transistor, it is possible to omit the formation of a capacitive element.

The transistor 4010 provided in the pixel unit 4002 is electrically connected to the display element. In FIG. 24A, the liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. In addition, an insulating layer 4032 and an insulating layer 4033 that function as an alignment film are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are superimposed via the liquid crystal layer 4008.

Further, the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. There is. A spherical spacer may be used.

Further, in the display device, an optical member (optical substrate) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light from a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

Further, as the insulating layer 4111 and the insulating layer 4104, an insulating layer that does not easily transmit impurity elements is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, it is possible to prevent the infiltration of impurities from the outside. Further, by contacting the insulating layer 4111 and the insulating layer 4104 on the outside of the pixel portion 4002, the effect of preventing the infiltration of impurities from the outside can be enhanced.

The insulating layer 4104 may be formed, for example, by the same material and method as the insulating layer 104. The insulating layer 4111 may be formed, for example, by the same material and method as the insulating layer 110.

Further, as a display element included in the display device, a light emitting element (also referred to as “EL element”) utilizing electroluminescence can be applied. The EL element has a layer (also referred to as an "EL layer") containing a luminescent compound between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the luminescent substance contained in the EL layer emits light.

Further, the EL element is distinguished by whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage, electrons are injected into the EL layer from one electrode and holes are injected into the EL layer from the other electrode. Then, by recombination of these carriers (electrons and holes), the luminescent organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light emitting device is called a current excitation type light emitting device.

In addition to the luminescent compound, the EL layer includes a substance having a high hole injecting property, a substance having a high hole transporting property, a hole blocking material, a substance having a high electron transporting property, a substance having a high electron injecting property, or a bipolar substance. It may have a sex substance (a substance having high electron transport property and hole transport property) and the like.

The EL layer can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

The inorganic EL element is classified into a dispersed inorganic EL element and a thin film type inorganic EL element according to the element configuration. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is donor-acceptor recombination type light emission utilizing a donor level and an acceptor level. The thin film type inorganic EL element has a structure in which a light emitting layer is sandwiched between a dielectric layer and further sandwiched between electrodes, and the light emitting mechanism is localized light emission utilizing the inner-shell electron transition of metal ions. Here, an organic EL element will be used as the light emitting element.

The light emitting element may have at least one of a pair of electrodes transparent in order to extract light. Then, a top emission (top emission) structure in which a transistor and a light emitting element are formed on the substrate and light emission is taken out from the surface opposite to the substrate, and a bottom injection (bottom emission) structure in which light emission is taken out from the surface on the substrate side. , There is a light emitting element having a double-sided emission (dual emission) structure that extracts light emission from both sides, and any light emitting element having an injection structure can be applied.

The light emitting element 4513, which is a display element, is electrically connected to the transistor 4010 provided in the pixel unit 4002. The configuration of the light emitting element 4513 is a laminated structure of the first electrode layer 4030, the light emitting layer 4511, and the second electrode layer 4031, but is not limited to this configuration. The configuration of the light emitting element 4513 can be appropriately changed according to the direction of the light extracted from the light emitting element 4513 and the like.

The partition wall 4510 is formed by using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature.

The light emitting layer 4511 may be composed of a single layer or may be configured such that a plurality of layers are laminated.

A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, DLC (Diamond Like Carbon) and the like can be formed. Further, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. As described above, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material having high airtightness and less degassing so as not to be exposed to the outside air.

As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin can be used. , PVB (polyvinyl butyral), EVA (ethylene vinyl acetate) and the like can be used. Further, the filler 4514 may contain a desiccant.

As the sealing material 4005, a glass material such as a glass frit, a curable resin such as a two-component mixed resin that cures at room temperature, a photocurable resin, and a resin material such as a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.

If necessary, an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), and a color filter is attached to the ejection surface of the light emitting element. It may be provided as appropriate. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, it is possible to apply an anti-glare treatment that can diffuse the reflected light due to the unevenness of the surface and reduce the reflection.

Further, by forming the light emitting element with a microcavity structure, it is possible to extract light having high color purity. Further, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the displayed image can be improved.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) for applying a voltage to the display element, the direction of the light to be taken out, the place where the electrode layer is provided, and the place where the electrode layer is provided, and Translucency and reflectivity may be selected according to the pattern structure of the electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. A translucent conductive material such as tin oxide, indium zinc oxide, and indium tin oxide to which silicon oxide is added can be used.

Further, the first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium (Ti), Platinum (Pt), Aluminum (Al), Copper (Cu), Silver (Ag) and other metals, or alloys thereof, or their alloys. It can be formed from metal nitride using one or more.

Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed by using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples thereof include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer consisting of two or more kinds of aniline, pyrrole and thiophene or a derivative thereof.

Further, since the transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured by using a non-linear element.

By using the shift register shown in the above embodiment, a reliable display device can be provided. Further, by using the transistor shown in the above embodiment, the reliability of the display device can be further improved. Further, by using the transistor shown in the above embodiment, it is possible to provide a display device capable of increasing the definition and the area and having good display quality. Further, it is possible to provide a display device with reduced power consumption.

<Display module>
A display module will be described as an example of a semiconductor device using the above-mentioned transistor. The display module 6000 shown in FIG. 25 has a touch sensor 6004 connected to the FPC 6003, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, and a printed circuit board 6010 between the upper cover 6001 and the lower cover 6002. , Has a battery 6011. The backlight unit 6007, the battery 6011, the touch sensor 6004, and the like may not be provided.

The semiconductor device of one aspect of the present invention can be used, for example, in a touch sensor 6004, a display panel 6006, an integrated circuit mounted on a printed circuit board 6010, or the like. For example, the display device described above can be used for the display panel 6006.

The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the size of the touch sensor 6004, the display panel 6006, and the like.

As the touch sensor 6004, a resistance film type or a capacitance type touch sensor can be used by superimposing it on the display panel 6006. It is also possible to add a touch sensor function to the display panel 6006. For example, it is possible to provide a touch sensor electrode in each pixel of the display panel 6006 and add a capacitance type touch panel function. Alternatively, it is also possible to provide an optical sensor in each pixel of the display panel 6006 and add the function of an optical touch sensor. If it is not necessary to provide the touch sensor 6004, the touch sensor 6004 can be omitted.

The backlight unit 6007 has a light source 6008. A light source 6008 may be provided at the end of the backlight unit 6007, and a light diffusing plate may be used. Further, when a light emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.

The frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 side, in addition to the protective function of the display panel 6006. Further, the frame 6009 may have a function as a heat radiating plate.

The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal, a clock signal, and the like. The power source for supplying electric power to the power supply circuit may be a battery 6011 or a commercial power source. When a commercial power source is used as the power source, the battery 6011 can be omitted.

Further, members such as a polarizing plate, a retardation plate, and a prism sheet may be added to the display module 6000.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

(Embodiment 3)
The transistor and / or semiconductor device according to one aspect of the present invention can be used in various electronic devices. 26 and 27 show examples of electronic devices using transistors and / or semiconductor devices according to one aspect of the present invention.

As an electronic device using a semiconductor device according to one aspect of the present invention, it is stored in a display device such as a television or a monitor, a lighting device, a desktop or notebook type personal computer, a word processor, and a recording medium such as a DVD (Digital Versaille Disc). Image playback device, portable CD player, radio, tape recorder, headphone stereo, stereo, table clock, wall clock, cordless telephone handset, transceiver, mobile phone, car phone, portable game machine, High-frequency heating devices such as tablet terminals, large game machines such as pachinko machines, calculators, mobile information terminals, electronic notebooks, electronic book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, and microwave ovens. , Electric rice cooker, electric washing machine, electric vacuum cleaner, water heater, fan, hair dryer, air conditioner, humidifier, dehumidifier and other air conditioning equipment, dishwasher, dish dryer, clothes dryer, duvet dryer, Examples include electric refrigerators, electric freezers, electric freezers, freezers for storing DNA, flashlights, tools such as chainsaws, smoke detectors, medical devices such as dialysis machines, and the like. Further examples include industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalator, industrial robots, power storage systems, power leveling and power storage devices for smart grids.

In addition, mobile objects propelled by electric motors using electric power from power storage devices are also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid electric vehicle (HEV) having an internal combustion engine and an electric motor, a plug-in hybrid electric vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an infinite track, and an electric assist. Examples include motorized bicycles including bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space explorers and planetary explorers, and spacecraft.

The electronic devices shown in FIGS. 26A to 26G include a housing 9000, a display unit 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (force). , Displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, slope, vibration , Including the function of measuring odor or infrared rays), microphone 9008, etc.

The electronic devices shown in FIGS. 26 (A) to 26 (G) have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read and display programs or data recorded on recording media It can have a function of displaying on a unit, and the like. The functions that the electronic devices shown in FIGS. 26 (A) to 26 (G) can have are not limited to these, and can have various functions. Further, although not shown in FIGS. 26 (A) to 26 (G), the electronic device may have a configuration having a plurality of display units. In addition, a camera or the like is provided in the electronic device to shoot a still image, a moving image, a function to save the shot image in a recording medium (external or built in the camera), and a function to display the shot image on the display unit. It may have a function to perform, etc.

FIG. 26A is a perspective view showing the television device 9100. The television device 9100 can incorporate the display unit 9001 into a large screen, for example, a display unit 9001 having a size of 50 inches or more, or 100 inches or more.

FIG. 26B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the mobile information terminal 9101 can display character and image information on a plurality of surfaces thereof. For example, three operation buttons 9050 (also referred to as an operation icon or simply an icon) can be displayed on one surface of the display unit 9001. Further, the information 9051 indicated by the broken line rectangle can be displayed on the other surface of the display unit 9001. As an example of information 9051, a display for notifying an incoming call such as e-mail, SNS (social networking service), or telephone, a title such as e-mail or SNS, a sender name such as e-mail or SNS, a date and time, and a time. , Battery level, antenna reception strength, etc. Alternatively, the operation button 9050 or the like may be displayed instead of the information 9051 at the position where the information 9051 is displayed.

FIG. 26C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, the user of the mobile information terminal 9102 can check the display (here, information 9053) in a state where the mobile information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position that can be observed from above the mobile information terminal 9102. The user can check the display and determine whether or not to receive the call without taking out the mobile information terminal 9102 from the pocket.

FIG. 26 (D) is a perspective view showing a wristwatch-type portable information terminal 9200. The personal digital assistant 9200 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. Further, the display unit 9001 is provided with a curved display surface, and can display along the curved display surface. Further, the mobile information terminal 9200 can execute short-range wireless communication standardized for communication. For example, by communicating with a headset capable of wireless communication, it is possible to make a hands-free call. Further, the mobile information terminal 9200 has a connection terminal 9006, and can directly exchange data with another information terminal via a connector. It can also be charged via the connection terminal 9006. The charging operation may be performed by wireless power supply without going through the connection terminal 9006.

26 (E), 26 (F), and 26 (G) are perspective views showing a foldable mobile information terminal 9201. Further, FIG. 26 (E) is a perspective view of a state in which the mobile information terminal 9201 is expanded, and FIG. 26 (F) is a state in which the mobile information terminal 9201 is in the process of being changed from one of the expanded state or the folded state to the other. 26 (G) is a perspective view of the mobile information terminal 9201 in a folded state. The mobile information terminal 9201 is excellent in portability in the folded state, and is excellent in the listability of the display due to the wide seamless display area in the unfolded state. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the mobile information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the mobile information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

Next, an example of an electronic device different from the electronic device shown in FIGS. 26 (A) to 26 (G) is shown in FIGS. 27 (A) and 27 (B). 27 (A) and 27 (B) are perspective views of a display device having a plurality of display panels. 27 (A) is a perspective view in which a plurality of display panels are wound up, and FIG. 27 (B) is a perspective view in a state in which the plurality of display panels are unfolded.

The display device 9500 shown in FIGS. 27 (A) and 27 (B) has a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512. Further, the plurality of display panels 9501 have a display area 9502 and a translucent area 9503.

Further, the plurality of display panels 9501 have flexibility. Further, two adjacent display panels 9501 are provided so that a part of them overlap each other. For example, the translucent regions 9503 of two adjacent display panels 9501 can be overlapped. By using a plurality of display panels 9501, it is possible to make a large screen display device. Further, since the display panel 9501 can be wound up according to the usage situation, the display device can be made highly versatile.

Further, in FIGS. 27A and 27B, a state in which the display areas 9502 are separated by the adjacent display panel 9501 is shown, but the present invention is not limited to this, and for example, the adjacent display panel 9501. By superimposing the display areas 9502 without gaps, a continuous display area 9502 may be formed.

The electronic device described in the present embodiment is characterized by having a display unit for displaying some information. However, the semiconductor device of one aspect of the present invention can also be applied to an electronic device having no display unit.

In this embodiment, a sample 900A, a sample 900B, a sample 900C, a sample 900D, a sample 900E, a sample 900F, a sample 900G, and a sample 900H in which an oxide semiconductor layer and an insulating layer are laminated are prepared, and each sample is in the depth direction. The results of investigating the hydrogen concentration distribution using SIMS will be described.

<1. Composition of each sample and preparation method>
Samples 900A to 900H have a common laminated structure. FIG. 28 shows the laminated structure of Sample 900A to Sample 900H. The samples 900A to 900H are the substrate 901, the insulating layer 902 on the substrate 901, the oxide semiconductor layer 903 on the insulating layer 902, the insulating layer 904 on the oxide semiconductor layer 903, and the insulation on the insulating layer 904. It has a layer 905 and.

Next, a method for producing the samples 900A to 900H will be described.

First, a silicon substrate was prepared as the substrate 901. Subsequently, a thermal oxide film of 100 nm was formed on the substrate 901 as an insulating layer 902.

Next, an oxide semiconductor layer 903 containing 50 nm In, Ga, and Zn was formed on the insulating layer 902 by a DC sputtering method. The oxide semiconductor layer 903 uses an oxide semiconductor (atomic number ratio In: Ga: Zn = 4: 2: 4.1) target containing In, Ga, and Zn, and uses argon (Ar) having a flow rate of 40 sccm as a sputtering gas. ), And oxygen (O ₂ ) with a flow rate of 5 sccm, the film formation pressure was 0.7 Pa, the film formation power was 500 W, the substrate temperature was 130 ° C., and the target-substrate distance was 60 mm.

Subsequently, after heat treatment at 400 ° C. for 1 hour in a nitrogen atmosphere, the heat treatment was switched to an oxygen atmosphere, and heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere.

Next, a 20 nm aluminum oxide layer was formed on the oxide semiconductor layer 903 as the insulating layer 904 by using the RF sputtering method. The insulating layer 904 uses an Al ₂ O ₃ target, uses argon (Ar) having a flow rate of 25 sccm and oxygen (O ₂ ) having a flow rate of 25 sccm as the film forming gas, sets the film forming pressure to 0.4 Pa, and forms a film forming force. Was 2500 W, and the distance between the target and the substrate was 60 mm, and a film was formed.

Here, for the sample 900A, the sample 900C, the sample 900E, and the sample 900G, the substrate temperature of the insulating layer 904 at the time of film formation was set to 130 ° C. Further, in the sample 900B, the sample 900D, the sample 900F, and the sample 900H, the substrate temperature at the time of forming the insulating layer 904 was set to 250 ° C.

After forming the insulating layer 904, heat treatment was performed on the sample 900C, the sample 900D, the sample 900G, and the sample 900H. Specifically, after heat treatment at 400 ° C. for 1 hour in a nitrogen atmosphere, the heat treatment was switched to an oxygen atmosphere, and heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere. The heat treatment performed after the film formation of the insulating layer 904 is referred to as "heat treatment A".

Next, aluminum oxide having a thickness of 5 nm was formed on the insulating layer 904 as the insulating layer 905 by using the ALD method. The insulating layer 905 was formed into a film at a substrate temperature of 250 ° C. using _{trimethylaluminum (Al (CH 3} ) ₃ ), ozone (O ₃ ), and oxygen (O _{2) as precursors.}

After forming the insulating layer 905, the sample 900E, the sample 900F, the sample 900G, and the sample 900H were heat-treated. Specifically, after heat treatment at 400 ° C. for 1 hour in a nitrogen atmosphere, the heat treatment was switched to an oxygen atmosphere, and heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere. The heat treatment performed after the film formation of the insulating layer 905 is referred to as "heat treatment B".

By the above steps, Samples 900A to 900H of this example were prepared. Samples 900A to 900H differ in the combination of the film formation temperature of the insulating layer 904, the presence / absence of heat treatment A, and the presence / absence of heat treatment B. Table 1 shows the differences in sample preparation between Sample 900A and Sample 900H. In Table 1, "○ (circle)" means that heat treatment has been performed, and "x (cross mark)" means that heat treatment has not been performed.

<2. SIMS analysis of each sample>
SIMS was performed for each of Samples 900A to 900H to investigate the hydrogen concentration distribution in the depth direction. As the analyzer, a dynamic SIMS apparatus IMS-7f manufactured by CAMECA was used. SIMS was performed from the substrate side toward the sample surface. The arrow in FIG. 28 indicates the analysis direction of SIMS.

The SIMS analysis results of Samples 900A to 900H are shown in FIGS. 29 (A), 29 (B), 30 (A), and 30 (B). The horizontal axis of FIGS. 29 (A), 29 (B), 30 (A), and 30 (B) is the approximate depth from the sample surface when the sample surface is taken as a reference (zero). Shows. The vertical axis shows the hydrogen (H) concentration. The quantitative value of the hydrogen concentration is effective only in the oxide semiconductor layer 903.

Further, in each figure, a broken line indicating the background level (BGL) and a alternate long and short dash line indicating the boundary position of each layer are drawn. In SIMS, the depth is a guideline and does not necessarily match the thickness of each layer. The boundary position of each layer shown in each figure is estimated from the change in the intensity of aluminum ions (not shown) acquired at the same time during the analysis.

Profile 910A shown by a solid line in FIG. 29 (A) is a SIMS analysis result of sample 900A. Further, the profile 910B shown by the broken line in FIG. 29 (A) is the SIMS analysis result of the sample 900B.

When the heat treatment A and the heat treatment B were not performed, there was no significant difference in the hydrogen concentration in the oxide semiconductor layer 903 even if the film formation temperature of the insulating layer 904 was different.

Profile 910C shown by a solid line in FIG. 29B is a SIMS analysis result of sample 900C. Further, the profile 910D shown by the broken line in FIG. 29B is the SIMS analysis result of the sample 900D.

Comparing with Profile 910A and Profile 910B in FIG. 29 (A), it can be seen that in Profile 910C and Profile 910D, the hydrogen concentration in the oxide semiconductor layer 903 is significantly reduced. Further, it can be seen that the hydrogen concentration in the insulating layer 904 is greatly increased.

That is, it is presumed that the hydrogen in the oxide semiconductor layer 903 is moved to the insulating layer 904 by performing the heat treatment A, and the hydrogen concentration in the oxide semiconductor layer 903 is reduced. In particular, when the film formation temperature of the insulating layer 904 is low (profile 910C), it can be seen that the hydrogen concentration in the oxide semiconductor layer 903 is reduced to BGL.

The density of the insulating layer 904 (aluminum oxide layer) having a low film forming temperature is ^{about 2.9 g / cm 3} , and the density of the insulating layer 904 having a high film forming temperature is ^{about 3.3 g / cm 3} (implemented). See Example 2). It is presumed that the smaller the density, the larger the amount of hydrogen absorbed.

Profile 910E shown by a solid line in FIG. 30 (A) is a SIMS analysis result of sample 900E. Further, the profile 910F shown by the broken line in FIG. 30A is the SIMS analysis result of the sample 900F.

Similar to the profiles 910C and 910D shown in FIG. 29B, it can be seen that the hydrogen concentration in the oxide semiconductor layer 903 is significantly reduced in the profiles 910E and 910F as well. Further, it can be seen that the hydrogen concentration in the insulating layer 904 is greatly increased.

That is, it was found that the hydrogen in the oxide semiconductor layer 903 also moves to the insulating layer 904 by performing the heat treatment B, and the hydrogen concentration in the oxide semiconductor layer 903 is reduced. Further, in both profile 910E and profile 910F, the hydrogen concentration in the oxide semiconductor layer 903 is reduced to BGL. It can be seen that by performing the heat treatment B, the hydrogen concentration in the oxide semiconductor layer 903 can be significantly reduced regardless of the film formation temperature of the insulating layer 904.

Profile 910G shown by a solid line in FIG. 30B is a SIMS analysis result of sample 900G. Further, the profile 910H shown by the broken line in FIG. 30B is the SIMS analysis result of the sample 900H.

Compared with the profile 910A and the profile 910B shown in FIG. 29 (A), it can be seen that the hydrogen concentration in the oxide semiconductor layer 903 is significantly reduced in the profile 910C and the profile 910D.

On the other hand, when compared with the profiles 910C and 910D shown in FIG. 29 (B) and the profiles 910E and 910F shown in FIG. 30 (A), the profiles 910G and 910H are in the oxide semiconductor layer 903. It can be seen that the hydrogen concentration is high. That is, the hydrogen concentration in the oxide semiconductor layer 903 is higher when both the heat treatment A and the heat treatment B are performed than when either the heat treatment A or the heat treatment B is performed.

This phenomenon will be considered as follows. By performing the heat treatment A, hydrogen in the oxide semiconductor layer 903 moves into the insulating layer 904, and hydrogen in the insulating layer 904 increases. Further, since the insulating layer 905 is formed by the ALD method, it has a high hydrogen content. When the insulating layer 905 having a large amount of hydrogen is laminated and the heat treatment B is performed with the hydrogen in the insulating layer 904 increased, the hydrogen in the insulating layer 904 is an oxide semiconductor having a lower hydrogen concentration than the insulating layer 905. It is believed to diffuse into layer 903.

According to this embodiment, it can be seen that hydrogen in the oxide semiconductor can be reduced by forming a film by contacting the aluminum oxide layer having a low film formation temperature with the oxide semiconductor layer and then performing heat treatment. In particular, the aluminum oxide layer formed by the sputtering method and the aluminum oxide layer formed by the ALD method are laminated on the oxide semiconductor layer and then heat-treated to form the oxide semiconductor layer. It can be seen that hydrogen can be effectively reduced.

As described above, the configuration shown in this embodiment can be used in combination with other examples or other embodiments as appropriate.

In this example, the result of analyzing the density of aluminum oxide formed by the sputtering method by using the X-ray reflectivity analysis method (XRR) will be described. In this example, Sample 950A, Sample 950B, and Sample 950C were prepared, and the densities of each sample before and after heat treatment were measured.

<1. Composition of each sample and preparation method>
Samples 950A to 950C have a common laminated structure. FIG. 31 shows the laminated structure of Samples 950A to 950C. Each of the samples 950A to 950C has a substrate 952, an oxide semiconductor layer 954 on the substrate 952, and an insulating layer 956 on the oxide semiconductor layer 954.

Here, in the sample 950A, the substrate temperature at the time of film formation of the insulating layer 956 was set to RT. In the sample 950B, the substrate temperature at the time of film formation of the insulating layer 956 was set to 130 ° C. In the sample 950C, the substrate temperature at the time of film formation of the insulating layer 956 was set to 250 ° C.

Next, a method for producing each sample will be described.

First, a silicon substrate is prepared as the substrate 952. Subsequently, an oxide semiconductor layer 954 containing 100 nm In, Ga, and Zn was formed on the substrate 952 as the oxide semiconductor layer 954 by the DC sputtering method. The oxide semiconductor layer 954 uses an oxide containing In, Ga, and Zn (atomic number ratio In: Ga: Zn = 4: 2: 4.1) as a film-forming gas, and argon (Ar) having a flow rate of 30 sccm. ), And oxygen (O ₂ ) with a flow rate of 15 sccm was used. Further, the film formation pressure was 0.7 Pa, the film formation power was 500 W, the substrate temperature was 200 ° C., and the distance between the target and the substrate was 60 mm.

Subsequently, after heat treatment at 400 ° C. for 1 hour in a nitrogen atmosphere, the heat treatment was switched to an oxygen atmosphere, and heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere.

Next, 20 nm aluminum oxide was formed on the oxide semiconductor layer 954 as the insulating layer 956 by using the RF sputtering method. For the insulating layer 956, an Al ₂ O ₃ target was used, and as the film forming gas, argon (Ar) having a flow rate of 25 sccm and oxygen (O ₂ ) having a flow rate of 25 sccm were used. Further, the film formation pressure was 0.4 Pa, the film formation power was 2500 W, and the distance between the target and the substrate was 60 mm.

Here, the substrate temperature of the sample 950A was kept at RT without heating. The substrate temperature of sample 950B was set to 130 ° C. The substrate temperature of the sample 950C was set to 250 ° C.

By the above steps, Samples 1A to 1C of this example were prepared.

<2. Density measurement>
Next, for each of Samples 950A to 950C, the density of the insulating layer 956 before the heat treatment and the density of the insulating layer 956 after the heat treatment were measured.

First, the density of the insulating layer 956 before the heat treatment was measured by using an X-ray reflectivity analysis method (XRR: X-ray Reflectivity Analysis).

Subsequently, the samples 950A to 950C were heat-treated. Specifically, after heat treatment at 400 ° C. for 1 hour in a nitrogen atmosphere, the heat treatment was switched to an oxygen atmosphere and heat treatment was performed at 400 ° C. for 1 hour in an oxygen atmosphere. Then, the density of the insulating layer 956 was measured using XRR.

Table 2 and FIG. 31 (B) show the measurement results of the density.

The density of the insulating layer 956 in the sample 950A was ^{2.8 g / cm 3 both before and after the heat treatment.} The density of the insulating layer 956 in the sample 950B was ^{2.9 g / cm 3 both before and after the heat treatment.} The density of the insulating layer 956 in the sample 950C was ^{3.3 g / cm 3 both before and after the heat treatment.}

Therefore, it was found that the density of the insulating layer 956 tends to increase as the substrate temperature at the time of film formation increases. In addition, no change was observed in the density of the insulating layer 956 before and after the heat treatment performed after the film formation of the insulating layer 956.

The configuration shown in this embodiment can be used in combination with other examples or other embodiments as appropriate.

100 Transistor 101 Substrate 102 Electrode 103 Insulation layer 104 Insulation layer 105 Insulation layer 106 Oxide semiconductor layer 108 Insulation layer 109 Insulation layer 110 Insulation layer

Claims (7)

The process of forming the first gate electrode and
The step of forming the first gate insulating layer on the first gate electrode and
A step of forming an oxide semiconductor layer on the first gate insulating layer and
A step of forming a second gate insulating layer on the oxide semiconductor layer and
The second gate insulating layer, forming a second gate electrode,
After the step of forming the second gate electrode, the step of performing the first heat treatment and the step of performing the first heat treatment
After the step of performing the first heat treatment, the first gate insulating layer and the oxide semiconductor layer, forming a first insulating layer Ri by the sputtering method,
Including
The first insulating layer is made of aluminum oxide.
The density of the first insulating layer is 3.0 g / cm ³ or less, and is
The first heat treatment is performed in an inert atmosphere and then in an oxidizing atmosphere.
The method for manufacturing a row Uto transistor without exposing the step of performing the first heat treatment up to the step of forming the first insulating layer in the atmosphere. The formation temperature of the first insulating layer is room temperature or higher and 150 ° C. or lower .
The method for manufacturing a transistor according to claim 1. The process of forming the first gate electrode and
The step of forming the first gate insulating layer on the first gate electrode and
The step of forming the oxide semiconductor layer on the first gate insulating layer and
A step of forming a second gate insulating layer on the oxide semiconductor layer and
The second gate insulating layer, forming a second gate electrode,
After the step of forming the second gate electrode, the step of performing the first heat treatment and the step of performing the first heat treatment
After the step of performing the first heat treatment, a step of forming a metal layer on the first gate insulating layer and the oxide semiconductor layer, and a step of forming the metal layer.
The step of oxidizing the metal layer to form the first insulating layer and
Including
The metal layer contains aluminum and
The density of the first insulating layer is 3.0 g / cm ³ or less, and is
The first heat treatment is performed in an inert atmosphere and then in an oxidizing atmosphere.
The method for manufacturing a row Uto transistor without exposing the step of performing the first heat treatment up to the step of forming the first insulating layer in the atmosphere. The step of oxidizing the metal layer to form the first insulating layer is
Including a second heat treatment performed in an oxidizing atmosphere,
The method for manufacturing a transistor according to claim 3. The second heat treatment is performed at 200 ° C. or higher and 500 ° C. or lower .
The method for manufacturing a transistor according to claim 4. The step of oxidizing the metal layer to form the first insulating layer is
Including plasma treatment performed in an oxidizing atmosphere ,
The method for manufacturing a transistor according to claim 3. The first heat treatment is performed at 200 ° C. or higher and 500 ° C. or lower .
The method for manufacturing a transistor according to any one of claims 1 to 6.

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