JP6979981B2 - Switching power supply - Google Patents

Description

The present invention relates to a so-called double-ended isolated type (half-bridge type, full-bridge type, push-pull type, etc.) switching power supply device, and more particularly to a switching power supply device provided with a bridge type synchronous rectifier circuit.

Conventionally, for example, there has been a full-bridge type switching power supply device 10 shown in FIG. The switching power supply device 10 includes a series circuit of the first and second switching elements 12 (1) and 12 (2) and a series circuit of the third and fourth switching elements 12 (3) and 12 (4). These are connected in parallel to each other, and the input voltage Vi is supplied from the input power supply 14 to both ends thereof. In each series circuit, the first and third switching elements 12 (1) and 12 (3) are arranged on the high side side, respectively, and the second and fourth switching elements 12 (2) and 12 (4) are respectively arranged. It is located on the low side.

The switching elements 12 (1) to 12 (4) are composed of N-channel MOS type FETs, and in FIG. 6, each switching element 12 (1) to 12 (4) is a FET 16 in order to make it easy to imagine an actual operation. (1) to 16 (4) and parasitic diodes 18 (1) to 18 (4) are described separately. FETs 16 (1) to 16 (4) are turned on during the high level period and turned off during the low level period when the drive pulse input to the gate is turned on. The parasitic diodes 18 (1) to 18 (4) have a cathode connected to the drain and an anode connected to the source.

The transformer 20 has an input winding 20a and an output winding 20b, one end of which is connected to the midpoint of the first and second switching elements 12 (1) and 12 (2), and the other end of the input winding 20a. Is connected to the midpoint of the third and fourth switching elements 12 (3) and 12 (4). The dots attached to the input winding 20a and the output winding 20b indicate the polarity of each winding.

A bridge-type synchronous rectifier circuit is connected to the output winding 20b. The synchronous rectifier circuit includes a series circuit of the first and second synchronous rectifier elements 22 (1) and 22 (2) and a series circuit of the third and fourth synchronous rectifier elements 22 (3) and 22 (4). These are connected in parallel to each other. In each series circuit, the first and third synchronous rectifying elements 22 (1) and 22 (3) are arranged on the high side side, respectively, and the second and fourth synchronous rectifying elements 22 (2) and 22 (4) are arranged. Are arranged on the low side side respectively. One end of the output winding 20b is connected to the midpoint of the first and second synchronous rectifying elements 22 (1) and 22 (2), and the other end is connected to the third and fourth synchronous rectifying elements 22 (3), It is connected to the midpoint of 22 (4).

The synchronous rectifying elements 22 (1) to 22 (4) are composed of N-channel MOS type FETs, and the synchronous rectifying elements 22 (1) to 22 (4) are connected to the FETs 24 (1) to 24 (4) in the same manner as described above. ) And the parasitic diodes 26 (1) to 26 (4). The FETs 24 (1) to 24 (4) are turned on during the high level period and turned off during the low level period when the drive pulse input to the gate is turned on. The parasitic diodes 26 (1) to 26 (4) have a cathode connected to the drain and an anode connected to the source.

An output smoothing circuit 28 that smoothes the voltage rectified by the synchronous rectifying elements 22 (1) to 22 (4) by the output inductor 28a and the output capacitor 28b is connected to the output of the synchronous rectifier circuit. The output smoothing circuit 28 generates an output voltage Vo across the output capacitor 28b, and supplies the output voltage Vo and the output current Io to the load 30.

The switching control circuit 32 switches each switching element by outputting a predetermined drive pulse toward the switching elements 12 (1) to 12 (4). Specifically, the switching period is fixed, the FETs 16 (1) and 16 (4) are paired and turned on and off in the same phase, and the FETs 16 (2) and 16 (3) are paired and turned on and off in the same phase. , Controls to shift the on / off phase of each pair by 180 degrees. Then, in order to keep the output voltage Vo constant, control is performed to variably adjust the on-duty of each FET 16 (1) to 16 (4).

Further, the switching control circuit 32 generates on / off timing signals Si (A) and Si (B) of the FETs 16 (1) to 16 (4) and transmits them to the synchronous rectification control circuit 34 through an isolator (not shown). The timing signal Si (A) is, for example, a rectangular wavy voltage signal having a low level during the on period and a high level during the off period of the FETs 16 (2) and 16 (3). Further, the timing signal Si (B) is, for example, a rectangular wavy voltage signal having a low level during the on period and a high level during the off period of the FETs 16 (1) and 16 (4). When all the switching of each switching element is stopped and fixed to off, the timing signals Si (A) and Si (B) are held at the low level.

The synchronous rectification control circuit 34 generates a predetermined drive pulse based on the timing signals Si (A) and Si (B) received from the switching control circuit 32, and the synchronous rectification elements 22 (1) to 22 (4) generate a predetermined drive pulse. By outputting toward, each synchronous rectifying element is switched. Specifically, the FET 24 (1) and the FET 24 (4) are turned on during the period when the timing signal Si (A) is at a high level, and the FET 24 (1) and the FET 24 (4) are turned off during the period when the timing signal Si (A) is at a low level. Further, the FET 24 (2) and the FET 24 (3) are turned on during the high level period of the timing signal Si (B), and the FET 24 (2) and the FET 24 (3) are turned off during the low level period. When the switching of each switching element is stopped and fixed to off, the timing signals Si (A) and Si (B) are held at the low level, so that the FET 24 (1) to FET 24 (4) stop switching. And fixed off.

Next, the operation of the conventional switching power supply device 10 when there is no load (output current Io = 0A) will be described with reference to the time chart of FIG. When a sufficiently high input voltage Vi is supplied, the switching element FETs 16 (1) to 16 (4) are switched under the control of the switching control circuit 32, and along with this, the synchronous rectifying element FETs 24 (1) to 24 (4) switches and operates in the current continuous mode in which the output inductor current Ich flows in the positive and negative directions. The parasitic diodes 26 (1) to 26 (4) of the synchronous rectifying element hardly conduct.

Here, consider a case where the input power supply 14 is cut off (or a momentary power failure occurs) and the input voltage Vi begins to decrease. When the input voltage Vi begins to decrease, the FETs 16 (1) to 16 (4) and the FETs 24 (1) to 24 (4) perform the same switching operation as described above while changing the on-duty. As a result, an operation of regenerating electric power from the output side to the input side, that is, an electric power regeneration operation is performed. The power regeneration operation is likely to continue when the input voltage Vi drops quickly and the output voltage Vo drops slowly. For example, when there is no load (output current Io = 0A), a large-capacity capacitor is attached to both ends of the load 30. When attached, the load 30 continues for a long time, such as when the battery is used.

If the power regeneration operation continues for a long time, the output inductor current Ich is largely DC superimposed in the negative direction. Then, when the input voltage Vi drops to the switching element stop voltage Vst (voltage at which the switching control circuit 32 does not output the drive pulse of the switching elements 12 (1) to 12 (4)), the FETs 16 (1) to 16 (4) ) And FETs 24 (1) to 24 (4) stop switching almost at the same time and are fixed to off.

In FIG. 7, the input voltage Vi reaches the switching element stop voltage Vst at the timing when all the FETs 24 (1) to 24 (4) of the synchronous rectifying element are turned on, and the FETs 24 (1) to 24 (4) are turned off at the same time. Shows the case. In this case, the flow path of the inductor current Ich that was flowing in the negative direction until just before the turn-off suddenly disappears. This is because the inductor current Ich in the negative direction becomes a reverse current for the parasitic diodes 26 (1) to 26 (4) and cannot flow into the parasitic diodes 26 (1) to 26 (4). As a result, a large surge is generated in the voltage Va in the previous stage of the output inductor 28a due to the counter electromotive force that the output inductor 28a tries to keep the inductor current Ich flowing. This surge increases as the inductor current Ich (absolute value of the current in the negative direction) immediately before the FETs 24 (1) to 24 (4) turn off increases.

The voltage Va in the previous stage of the output inductor 28a can rise up to 2.BVdss. BVdss is the breakdown voltage of the synchronous rectifying elements 22 (1) to 22 (4), which are MOS type FETs.

When the synchronous rectifying elements 22 (1) to 22 (4) are turned off at the same time, the voltages Vds1 to Vds4 between the drain sources are almost equal to Va / 2. Since the MOS FET has a property of breaking down due to avalanche breakdown when the voltage between the drain sources reaches a predetermined value, the voltage between the drain sources is clamped to the breakdown voltage BVdss and does not rise any more. In other words, it can be said that the voltage Va / 2 can change in the range of zero to BVdss, and the voltage Va may rise to a very high value of 2 · BVdss at the maximum.

Since the voltage Va can be used for various controls and functions of the switching power supply device 10, there are cases where a network (not shown) is connected to the position of the voltage Va. Therefore, in order to prevent excessive voltage stress from being applied to this network, it is an issue to prevent the voltage Va from rising to a high value.

Conventionally, as a technique for solving this kind of problem, for example, as disclosed in Patent Document 1, a monitor circuit for monitoring an input voltage Vi is provided, and an input voltage Vi is a predetermined reference value Vth (> Vst). There was a switching power supply device that stopped the switching of the synchronous rectifying element when it detected that the voltage was lower than that.

Japanese Unexamined Patent Publication No. 2004-336908

When the technique disclosed in Patent Document 1 is applied to the conventional switching power supply device 10, the switching power supply device 36 shown in FIG. 8 can be configured. The switching power supply device 36 is a switching power supply device 10 to which an input voltage monitor circuit 38 is added. The input voltage monitor circuit 38 compares the input voltage Vi with the reference value Vth, and transmits the input voltage detection signal Si (Vi), which is the comparison result, to the synchronous rectification control circuit 34 through the photocoupler 38a or the like which is an insulating element. ..

The input voltage detection signal Si (Vi) becomes a high level when Vi> Vth and a low level when Vi ≦ Vth, for example. When the synchronous rectification control circuit 34 receives the low-level input voltage detection signal Si (Vi), the synchronous rectification element FETs 24 (1) to 24 regardless of the content of the timing signals Si (A) and Si (B). Forcibly stop the switching of (4) and fix it to off.

The operation of the switching power supply device 36 when there is no load (output current Io = 0A) can be represented as shown in the time chart of FIG. When a sufficiently high input voltage Vi is supplied, that is, when Vi> Vth, the operation is the same as that of the switching power supply device 10, and the FETs 24 (1) to 24 (4) of the synchronous rectifying element are switched and the output inductor is used. Operates in the current continuous mode in which the current Ich flows in the positive and negative directions. The parasitic diodes 26 (1) to 26 (4) of the synchronous rectifying element hardly conduct.

When the input power supply 14 is cut off (or a momentary power failure occurs) and the input voltage Vi begins to decrease, the on-duty of the FETs 16 (1) to 16 (4) and the FETs 24 (1) to 24 (4) changes. However, the same switching operation as described above is performed, and the operation of regenerating power from the output side to the input side is performed.

After that, before the output inductor current Ich is largely DC superimposed in the negative direction, the input voltage Vi reaches the reference value Vth, the input voltage detection signal Si (Vi) is inverted to the low level, and the FET 24 (1) of the synchronous rectifier element. ~ 24 (4) stops switching and is fixed off. Then, during Vi = Vth to Vst, the voltage of the output winding 20b is rectified by the parasitic diodes 26 (1) to 26 (4), and as the output voltage Vo decreases, the FETs 16 (1) to 16 (4) of the switching element are rectified. The on-duty of 4) becomes large, and the operation mode is switched to the operation mode in which the output inductor current Ich flows slightly only in the positive direction. Then, when the input voltage Vi drops to the switching element stop voltage Vst, the FETs 16 (1) to 16 (4) stop switching, and the parasitic diodes 26 (1) to 26 (4) also become non-conducting.

In the case of the switching power supply device 36, when the input voltage Vi reaches the switching element stop voltage Vst, that is, when the parasitic diodes 26 (1) to 26 (4) become non-conducting, the immediately preceding output inductor current Ich is always zero. Or, since it is in the positive direction, a large surge does not occur in the voltage Va, and the above-mentioned problem of the switching power supply device 10 is prevented. However, when the input voltage Vi reaches the reference value Vth and the FETs 24 (1) to 24 (4) of the synchronous rectifying element are stopped at the same time and fixed to off, a large surge may occur in the voltage Va.

Since the switching power supply device 36 operates with no load, the output inductor current Ich when Vi> Vth has a period in which it flows in the negative direction even if the direct current is not superimposed in the negative direction. Then, during this period, the input voltage Vi may reach the reference voltage Vth at the timing when all the FETs 24 (1) to 24 (4) of the synchronous rectifying element are turned on.

When the input voltage Vi reaches the reference voltage Vth at this timing, the FETs 24 (1) to 24 (4) of the synchronous rectifying element turn off at the same time, and the flow path of the inductor current Ich that was flowing in the negative direction until just before suddenly disappears. It ends up. Therefore, as shown in FIG. 9, a large surge is generated in the voltage Va due to the counter electromotive force that the output inductor 28a tries to keep the inductor current Ich flowing. Then, the FETs 24 (1) to 24 (4) break down due to the avalanche breakdown, and the voltage Va rises to a very high value of 2.BVdss and is clamped.

As described above, in both the conventional switching power supply devices 10 and 36, the voltage Va may rise to a high value, so that measures for ensuring the safety of the device have been required.

The present invention has been made in view of the above background technology, and is a double-ended isolated switching power supply capable of suppressing the surge generated by the back electromotive force of the output inductor to be smaller than before when the input voltage drops. The purpose is to provide.

The present invention includes a transformer having an input winding and an output winding, a plurality of switching elements connected to the input winding for switching, and a MOS that breaks down due to avalanche breakdown when a certain voltage or more is applied to both ends. It consists of a plurality of synchronous rectifying elements that are connected to the output winding and switch, a switching control circuit that switches the switching elements, and an on / off timing signal of the switching element is received from the switching control circuit. A synchronous rectification control circuit for switching the synchronous rectifying element based on this timing signal and an output smoothing circuit for smoothing the voltage rectified by the synchronous rectifying element with an output inductor and an output capacitor are provided, and an input voltage is output to a predetermined value. It is a double-ended isolated switching power supply that converts it into a voltage and outputs it.

The plurality of synchronous rectifying elements are composed of first and second synchronous rectifying elements connected in series with each other and third and fourth synchronous rectifying elements connected in series with each other, and the first and second synchronous rectifying elements. In the series circuit of the synchronous rectifying element, the first synchronous rectifying element is arranged on the high side side, both ends are connected to the input end of the output smoothing circuit, and the series circuit of the third and fourth synchronous rectifying elements is , The third synchronous rectifying element is arranged on the high side side, both ends are connected to the input end of the output smoothing circuit, and the middle point of the first and second synchronous rectifying elements and the third and fourth are. The output winding is connected to the midpoint of the synchronous rectifying element. Then, when the input voltage drops below the reference value, the synchronous rectification control circuit forcibly stops the switching of the first and third synchronous rectification elements regardless of the content of the timing signal, or the synchronous rectification control circuit. The switching of the second and fourth synchronous rectifying elements is forcibly stopped. The synchronous rectification control circuit is preferably configured to detect the input voltage by the generated voltage of the auxiliary winding provided in the transformer.

Further, the synchronous rectification control circuit detects the synchronous rectifier element drive unit that drives the synchronous rectifier element based on the timing signal, the input voltage or a voltage corresponding thereto, and the input voltage is equal to or lower than the reference value. The synchronous rectifying element driving unit has an input voltage detecting unit that transmits an input voltage drop signal to the synchronous rectifying element driving unit, and the synchronous rectifying element driving unit drives the first and third synchronous rectifying elements. It is composed of a high-side drive unit and a low-side drive unit that drives the second and fourth synchronous rectifying elements, and when the input drop signal is received from the front input voltage detection unit, it is related to the content of the timing signal. Instead, the operation of either the low-side drive unit or the high-side drive unit may be forcibly stopped.

The switching power supply device of the present invention has a synchronous rectifier circuit in which a plurality of synchronous rectifier elements composed of MOS type FETs are connected in a bridge type, and when the input voltage drops below the reference value, the high side synchronous rectifier element or the low side It has a unique configuration in which the switching of the synchronous rectifying element on the side is forcibly stopped. Therefore, the surge generated by the back electromotive force of the output inductor can be suppressed to be smaller than before.

It is a circuit diagram which shows one Embodiment of the switching power supply device of this invention. It is a circuit diagram which shows the internal structure of the synchronous rectification control circuit in FIG. 2 is a block diagram (a) showing an internal configuration of a high-side drive unit in FIG. 2, and a block diagram (b) showing an internal configuration of a low-side drive unit. It is a time chart which shows the operation of the switching power supply apparatus shown in FIG. It is a circuit diagram which shows the modification of the internal structure of the synchronous rectification control circuit in FIG. 1 (the modification of the input voltage detection unit). It is a circuit diagram which shows one form of the conventional switching power supply device. 6 is a time chart showing the operation of the switching power supply device shown in FIG. It is a circuit diagram which shows the other form of the conventional switching power supply device. It is a time chart which shows the operation of the switching power supply apparatus shown in FIG.

Hereinafter, an embodiment of the switching power supply device of the present invention will be described with reference to FIGS. 1 to 5. Here, the same configurations as those of the conventional switching power supplies 10 and 36 are designated by the same reference numerals, and the description thereof will be omitted.

The switching power supply device 40 of this embodiment is a full-bridge type switching power supply device provided with a bridge-type synchronous rectifier circuit, similarly to the conventional switching power supply device 10. As shown in FIG. 1, a characteristic feature is that a synchronous rectification control circuit 42 that performs a unique operation is provided in place of the synchronous rectification control circuit 34, and the other configurations are the same.

The synchronous rectification control circuit 42 includes a synchronous rectifying element drive unit 44 and an input voltage detection unit 46. As shown in FIG. 2, the synchronous rectifying element driving unit 44 includes a high-side side driving unit 48 for driving the first and third synchronous rectifying elements 22 (1) and 22 (3), and the second and fourth synchronous rectifying elements. It is provided with a low-side side drive unit 50 that drives the synchronous rectifying elements 22 (2) and 22 (4).

The high-side drive unit 48 generates a drive pulse of the synchronous rectifier element 22 (1) based on the timing signal Si (A) received from the switching control circuit 32, and the synchronous rectifier element 22 (1) located on the high-side side. ) Is output to the gate. Further, a drive pulse of the synchronous rectifying element 22 (3) is generated based on the timing signal Si (B) and output to the gate of the synchronous rectifying element 22 (3) located on the high side side. For example, as shown in FIG. 3A, the level shifter 48a (1) is used to shift the ground of the timing signal Si (A) to the high side side, and this is current-amplified by the buffer 48b (1) for synchronous rectification. The drive pulse of the element 22 (1) is generated. Similarly, the ground of the timing signal Si (B) is shifted to the high side side by using the level shifter 48a (3), and the current is amplified by the buffer 48b (3) to drive the pulse of the synchronous rectifying element 22 (3). To generate.

The low third side drive unit 50 generates a drive pulse of the synchronous rectifier element 22 (2) based on the timing signal Si (B) received from the switching control circuit 32, and the synchronous rectifier element 22 (2) located on the low side side. Output to the gate. Similarly, a drive pulse of the synchronous rectifying element 22 (4) is generated based on the timing signal Si (A) and output to the gate of the synchronous rectifying element 22 (4) located on the low side side. For example, as shown in FIG. 3B, the timing signal Si (B) is received at one input end of the AND gate 50a (2), and the output of the AND gate 50a (2) is current-amplified by the buffer 50b (2). As a result, the drive pulse of the synchronous rectifying element 22 (2) is generated. Therefore, when the other input end of the AND gate 50a (2) is at a high level, a drive pulse having the same phase as the timing signal Si (B) is output, and when the other input end is at a low level, the content of the timing signal Si (B) is included. Regardless, it outputs a drive pulse fixed at a low level. Similarly, the synchronous rectifying element 22 (4) receives the timing signal Si (A) at one input end of the AND gate 50a (4) and amplifies the output of the AND gate 50a (4) with the buffer 50b (4). ) Generate a drive pulse. Therefore, when the other input end of the AND gate 50a (4) is at a high level, a drive pulse having the same phase as the timing signal Si (A) is output, and when the other input end is at a low level, the content of the timing signal Si (B) is included. Regardless, it outputs a drive pulse fixed at a low level. What is input to the other input terminal of the AND gates 50a (2) and 50a (4) is the input voltage detection signal Si (Vi) output by the input voltage detection unit 46.

As shown in FIG. 2, the input voltage detection unit 46 includes an auxiliary winding 20c attached to the transformer 20, a diode 52 and a capacitor that rectify and smooth the voltage across the auxiliary winding 20c to generate a DC voltage Vb substantially proportional to the input voltage Vi. It is equipped with 54. It has resistors 56a and 56b that divide the voltage Vb generated in the capacitor 54, and the midpoint of the resistors 56a and 56b is connected to the base of the transistor 58. The transistor 58 is a PNP type bipolar transistor, and the emitter is connected to the power supply voltage Vcc.

The gate of the transistor 60 is connected to the collector of the transistor 58. The transistor 60 is an N-channel MOS FET, the drain is pulled up to the power supply voltage Vcc via the resistor 62, and the source is connected to the ground. A capacitor 64 and a resistor 66 are connected in parallel between the gate and the ground. The capacitor 64 is a capacitor for holding the voltage between the gate and source at a high level for a predetermined time when the transistor 58 is switched from conducting to non-conducting, and the resistor 66 is for lowering the voltage between the gate and source to a low level. Discharge resistance. Further, a noise removing capacitor 68 is connected between the drain and the ground.

The diode 70 connected between the base emitters of the transistor 58 is a protective diode that prevents an excessive reverse voltage from being applied between the base emitters of the transistor 58, and does not contribute to the operation of the present invention. ..

The input voltage detection unit 46 compares the voltage Vc at the midpoint of the resistors 56a and 56b with the voltage (Vcc-Vbe) obtained by subtracting the base-emitter voltage Vbe of the transistor 58 from the power supply voltage Vcc, and is the comparison result. The input voltage detection signal Si (Vi) is output from the position of the drain of the transistor 60. Here, the voltage Vc is a value corresponding to the input voltage Vi, and the voltage (Vcc-Vbe) is set to a value corresponding to the reference value Vth, and the input voltage Vi and the reference value Vth are substantially set. Will be compared.

When the input voltage Vi is higher than the reference value Vth, the voltage Vc becomes higher than the voltage (Vcc-Vbe), the transistor 58 becomes non-conducting, the transistor 60 is turned off, and the input voltage detection signal Si (Vi) is at a high level. become. On the other hand, when the input voltage Vi drops to the reference value Vth or less, the voltage Vc reaches the voltage (Vcc−Vbe), the transistor 58 conducts, the transistor 60 turns on, and the input voltage detection signal Si (Vi) becomes low. Become a level. Therefore, the low-level input voltage detection signal Si (Vi) becomes an input drop signal indicating that the input voltage Vi is equal to or less than the reference value Vth.

As described above, when the low-level input voltage detection signal Si (Vi) is input to the AND gates 50a (2) and 50a (4), the low-side drive unit 50 is the synchronous rectifying element 22 (2), 22. A drive pulse fixed at a low level is output toward (4). That is, when the low-side drive unit 50 receives the input drop signal from the input voltage detection unit 46, it outputs a drive pulse fixed to a low level regardless of the contents of the timing signals Si (A) and Si (B). , Performs an operation of forcibly stopping the switching of the synchronous rectifying elements 22 (2) and 22 (4).

Next, the operation of the switching power supply device 40 when there is no load (output current Io = 0A) will be described with reference to the time chart of FIG. When a sufficiently high input voltage Vi is supplied, that is, when Vi> Vth, the input voltage detection unit 46 outputs a high-level input voltage detection signal Si (Vi), so that it is the same as the switching power supply devices 10 and 36. In addition, the FETs 24 (1) to 24 (4) of the synchronous rectifying element are switched, and the output inductor current Ich operates in the current continuous mode in which the current Ich flows in the positive and negative directions. The parasitic diodes 26 (1) to 26 (4) of the synchronous rectifying element hardly conduct.

When the input power supply 14 is cut off (or a momentary power failure occurs) and the input voltage Vi begins to decrease, the on-duty of the FETs 16 (1) to 16 (4) and the FETs 24 (1) to 24 (4) changes. However, the same switching operation as described above is performed, and the operation of regenerating power from the output side to the input side is performed.

After that, the input voltage Vi reaches the reference value Vth and the input voltage detection signal Si (Vi) is inverted to the low level (outputs a low input signal) before the output inductor current Ich is largely DC superimposed in the negative direction. Then, the low-side drive unit forcibly stops the switching of the FETs 24 (2) to 24 (4) and fixes them to off. On the other hand, the FETs 24 (1) and 24 (3) on the high side continue switching. Then, between Vi = Vth and Vst, the voltage of the output winding 20b is rectified by the FETs 24 (1) and 24 (3) of the synchronous rectifying element and the parasitic diodes 26 (2) and 26 (4), and the output voltage Vo. As the voltage decreases, the on-duty of the FETs 16 (1) to 16 (4) of the switching element increases, and the mode is switched to the operation mode in which the output inductor current Ich slightly flows only in the positive direction.

Then, when the input voltage Vi drops to the switching element stop voltage Vst (voltage at which the switching control circuit 32 does not output the drive pulse of the switching element), the FETs 16 (1) to 16 (4) and the FETs 24 (1), 24 ( 3) stops switching almost at the same time, and the parasitic diodes 26 (2) and 26 (4) also become non-conducting.

Here, consider the time when the input voltage Vi reaches the reference value Vth, that is, the time when the FETs 24 (2) and 24 (4) of the synchronous rectifying element are stopped and turned off. In the case of the above switching power supply device 36, the input voltage Vi is the reference value at the timing when all the FETs 24 (1) to 24 (4) of the synchronous rectifying element are turned on during the period when the output inductor current Ich is flowing in the negative direction. When Vth is reached, all of FETs 24 (1) to 24 (4) turn off at the same time, and the back electromotive force of the output inductor 28 causes the voltage Va in the previous stage of the output inductor 28a to rise to a very high value of 2.BVdss. It ends up. On the other hand, in the case of the switching power supply device 40, only the FETs 24 (2) and 24 (4) among the four FETs 24 (1) to 24 (4) are turned off, and the FETs 24 (1) and 24 (3) are turned off. Is kept on, so that the back electromotive force of the output inductor 28 causes a surge in the voltage Va, but the value of the voltage Va is suppressed to the break voltage BVdss or less due to the avalanche breakdown of the FET 24 (2) or 24 (4). ..

Further, in the switching power supply device 40, when the input voltage Vi reaches the switching element stop voltage Vst, that is, the switching of the FETs 24 (1) and 24 (3) of the synchronous rectifying element is stopped and the parasitic diodes 26 (2) and 26 ( When 4) becomes non-conducting, the output inductor current Ich immediately before is always zero or in the positive direction, so that a large surge does not occur in the voltage Va as in the switching power supply 36, and the switching power supply 10 described above does not occur. Problem is also prevented.

As described above, the switching power supply device 40 has a synchronous rectifier circuit in which synchronous rectifier elements 22 (1) to 22 (4) made of MOS type FETs are connected in a bridge type, and the input voltage Vi is equal to or less than the reference value Vth. It has a unique configuration in which switching of the synchronous rectifying elements 22 (2) and 22 (4) on the low side is forcibly stopped when the voltage drops to. Therefore, the surge generated by the counter electromotive force of the output inductor 28a can be suppressed to be smaller than before. That is, the increase in the voltage Va in the previous stage of the output inductor 28a can be suppressed to be equal to or lower than the breakdown voltage BVdss of the MOS type FET (one).

Further, since the input voltage detection unit 46 of the synchronous rectification control circuit 42 detects the input voltage Vi through the auxiliary winding 20c attached to the transformer 20, it is an insulating element having a large outer shape such as the photocoupler 38a shown in FIG. It is not necessary to use the above, and the input drop signal can be transmitted to the synchronous rectifying element drive unit 44 in a compact circuit configuration.

Another feature is that the synchronous rectifying element drive unit 44 is composed of a high-side side drive unit 48 and a low-side side drive unit 50. There are roughly three types of 2-channel FET drivers that are widely available on the market. The first type has a driver that drives the high side side and a driver that drives the low side side in one IC package, and the second type has two drivers that drive the high side side. The third type, which is housed in an IC package, is a type in which two drivers for driving the low side are housed in one IC package. The internal circuit of the driver that drives the high side side is composed of the high side side circuit and the low side side circuit, and in order to secure sufficient insulation between each circuit, the external connection terminal leading to the high side side circuit and the low side It is necessary to lengthen the insulation distance between the external connection terminal leading to the side circuit to a certain level or more, and the outer shape of the IC package of the first and second types is relatively large. On the other hand, in the third type, the insulation distance between the external connection terminals can be shortened, so that the outer shape of the IC package can be reduced.

For example, if two first types are prepared, a synchronous rectifying element driving unit having the same function as the synchronous rectifying element driving unit 44 can be configured, but since there are two large IC packages, a large mounting space is available. Is required. On the other hand, the synchronous rectifying element drive unit 44 of this embodiment can be configured by preparing one second type and one third type, so that a small third type can be used. , There is an advantage that the mounting space can be narrowed. In addition, since the transmission destinations of the input voltage detection signal Si (Vi) are integrated into one IC package, there is an advantage that the wiring pattern of the printed circuit board can be easily designed.

The switching power supply device of the present invention is not limited to the above embodiment. When the input voltage Vi drops below the reference value Vth, the synchronous rectification control circuit 42 of the switching power supply 40 forcibly stops the switching of the synchronous rectifier elements 22 (2) and 22 (4) on the low side, and the high side. The configuration is such that the operation of the synchronous rectifying elements 22 (1) and 22 (3) on the side is continued, but the switching of the synchronous rectifying elements 22 (1) and 22 (3) on the high side is forcibly stopped. The configuration may be changed so that the operation of the synchronous rectifying elements 22 (2) and 22 (4) on the low side is continued, and the same effect can be obtained.

The switching control circuit and the synchronous rectification control circuit are not limited to the configurations of the switching control circuit 32 and the synchronous rectification control circuit 42 described above, and the internal configuration may be appropriately changed if the operation intended by the present invention is possible. can. For example, when a dead time is provided between the on / off of the switching element and the on / off of the synchronous rectifier element, the switching control circuit generates a timing signal including the dead time, and the synchronous rectifier control circuit is driven according to the timing signal. It can be configured to generate a pulse. Alternatively, the switching control circuit may generate a timing signal according to the on / off of the switching element, and the synchronous rectification control circuit may generate a drive pulse in consideration of the dead time. Further, the timing signal is not limited to the form of a rectangular wave-shaped voltage signal such as Si (A) and Si (B) described above, and for example, the timing signal becomes high level only for a short time at the timing when the switching element turns on and off. An impulse-shaped voltage signal may be transmitted.

The input voltage detection unit is not limited to the configuration of the input voltage detection unit 46 described above, and for example, the input voltage is not indirectly detected from the auxiliary winding of the transformer, but is indirectly detected at another location. Alternatively, it may be configured to directly detect the input voltage as in Patent Document 1. Further, in the case of the input voltage detection unit 46, the portion for comparing the voltage is composed of a plurality of discrete parts (transistors, resistors, diodes, etc.) with an emphasis on cost, but the input voltage detection unit 46x shown in FIG. As described above, the comparator element 72 or the like may be configured with an emphasis on reducing the number of parts. Further, the form of the input voltage detection signal (input drop signal) is not limited to the high level or low level voltage signal.

In addition, the inverter circuit may be a so-called double-ended isolated type, and can be applied to a half-bridge type or push-pull type inverter circuit in addition to the full-bridge type of the switching power supply 40, and the same effect can be obtained. Be done.

10, 36,40 Switching power supply device 12 (1) to 12 (4) First to fourth switching elements 16 (1) to 16 (4) FET (switching element)
18 (1) -18 (4) Parasitic diode (switching element)
20 Transformer 20a Input winding 20b Output winding 20c Auxiliary winding 22 (1) to 12 (4) First to fourth synchronous rectifying elements 24 (1) to 24 (4) FET (synchronous rectifying element)
26 (1) to 26 (4) Parasitic diode (synchronous rectifying element)
28 Output smoothing circuit 28a Output inductor 28b Output capacitor 32 Switching control circuit 34, 42 Synchronous rectifier control circuit 44 Synchronous rectifier element drive unit 46, 46x Input voltage detection unit 48 High side drive unit (synchronous rectifier element drive unit)
50 Low side drive unit (synchronous rectifier element drive unit)
Si (A), Si (B) timing signal
Si (Vi) Input voltage detection signal (input drop signal)
Vi input voltage
Vo output voltage
Vth reference value

Claims (3)

It consists of a transformer having an input winding and an output winding, a plurality of switching elements connected to the input winding for switching, and a MOS type FET that breaks down due to avalanche breakdown when a certain voltage or more is applied to both ends. A plurality of synchronous rectifying elements connected to and switched to the output winding, a switching control circuit for switching the switching element, and an on / off timing signal of the switching element are received from the switching control circuit and used as this timing signal. A synchronous rectification control circuit for switching the synchronous rectifying element based on the above, and an output smoothing circuit for smoothing the voltage rectified by the synchronous rectifying element with an output inductor and an output capacitor are provided, and an input voltage is converted into a predetermined output voltage. In a double-ended isolated switching power supply that outputs
The plurality of synchronous rectifying elements are composed of first and second synchronous rectifying elements connected in series with each other and third and fourth synchronous rectifying elements connected in series with each other, and the first and second synchronous rectifying elements. In the series circuit of the synchronous rectifying element, the first synchronous rectifying element is arranged on the high side side, both ends are connected to the input end of the output smoothing circuit, and the series circuit of the third and fourth synchronous rectifying elements is , The third synchronous rectifying element is arranged on the high side side, both ends are connected to the input end of the output smoothing circuit, and the middle point of the first and second synchronous rectifying elements and the third and fourth are. The output winding is connected to the midpoint of the synchronous rectifying element, and the output winding is connected.
When the input voltage drops below the reference value, the synchronous rectification control circuit forcibly stops the switching of the first and third synchronous rectifying elements regardless of the content of the timing signal, or the second. And a switching power supply device characterized by forcibly stopping the switching of the fourth synchronous rectifying element. The switching power supply device according to claim 1, wherein the synchronous rectification control circuit detects the input voltage by the generated voltage of the auxiliary winding provided in the transformer. The synchronous rectification control circuit detects the synchronous rectifier element drive unit that drives the synchronous rectifier element based on the timing signal, the input voltage or a voltage corresponding thereto, and the input voltage becomes equal to or less than the reference value. At that time, it has an input voltage detection unit that transmits an input reduction signal toward the synchronous rectifying element drive unit.
The synchronous rectifying element drive unit is composed of a high-side side driving unit that drives the first and third synchronous rectifying elements and a low-side side driving unit that drives the second and fourth synchronous rectifying elements. When the input drop signal is received from the front input voltage detection unit, the operation of either the low side drive unit or the high side drive unit is forcibly stopped regardless of the content of the timing signal. Or the switching power supply device according to 2.

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