JP6950187B2 - Circuit equipment, electronic devices and cable harnesses - Google Patents

Description

The present invention relates to circuit devices, electronic devices, cable harnesses, and the like.

Conventionally, a circuit device that realizes USB (Universal-Serial-Bus) data transfer control has been known. As a conventional technique of such a circuit device, for example, there is a technique disclosed in Patent Documents 1 and 2.

For example, Patent Document 1 discloses a technique for activating an enable control signal of a current source of a transmission circuit for HS (High Speed) mode at a timing prior to a packet transmission start timing. Patent Document 2 discloses a technique for disabling the self-propelled operation of the PLL that generates a high-speed clock for the HS mode when the HS mode is switched to the FS (Full Speed) mode.

Japanese Unexamined Patent Publication No. 2006-135397 Japanese Unexamined Patent Publication No. 2002-141911

In USB, the eye pattern is measured in the authentication test. Therefore, the transmission circuit for the USB HS mode needs to output a transmission signal that can pass the USB standard certification test for the eye pattern. However, since there is a parasitic capacitance and a parasitic resistance in the signal path of the transmission signal of the transmission circuit for the HS mode, it becomes difficult to pass the eye pattern authentication test due to the parasitic capacitance and the parasitic resistance. Things will happen. As an example, when the transmission signal from the transmission circuit of the main controller is output to the peripheral device via the cable harness or the like, if the cable is long or the protection circuit or the like is present in the signal path, proper signal transfer is performed. Cannot be realized and the certification test cannot be passed.

According to some aspects of the present invention, it is possible to provide a circuit device, an electronic device, a cable harness, and the like that can improve the deterioration of the signal characteristics of the USB signal.

One aspect of the present invention includes a first physical layer circuit to which the first bus of the USB standard is connected, a second physical layer circuit to which the second bus of the USB standard is connected, and the first physical layer circuit. A packet received from the bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and from the second bus via the second physical layer circuit. A processing circuit that performs a transfer process that transfers the received packet to the first bus via the first physical layer circuit, and a bus monitor circuit that monitors the first bus and the second bus. The present invention relates to a circuit device including a bus switch circuit for turning on or off the connection between the first bus and the second bus based on the monitoring result in the bus monitor circuit.

According to one aspect of the present invention, the first and second physical layer circuits to which the first and second buses of the USB standard are connected, the processing circuit that performs packet transfer processing, and the first and second A bus monitor circuit for monitoring the bus and a bus switch circuit are provided. Then, the bus switch circuit turns on or off the connection between the first bus and the second bus based on the monitoring result in the bus monitor circuit. In this way, the connection between the first bus and the second bus is turned on according to the monitoring results of the first and second buses, and the first device and the second device connected to the first bus are connected. It is possible to exchange signals with a second device connected to the bus. Further, a transfer process for transferring a packet from one of the first and second buses to the other of the first and second buses via the first and second physical layer circuits becomes possible, and the first and second buses can be transferred. Even if the signal characteristics of the signal of the bus 2 have deteriorated, this can be improved. Therefore, it becomes possible to provide a circuit device or the like that can improve the deterioration of the signal characteristics of the USB signal.

Further, in one aspect of the present invention, the period in which the bus switch circuit turns on the connection between the first bus and the second bus is set as the first period, and the bus switch circuit is the first bus and the said. When the period for turning off the connection of the second bus is set as the second period, the processing circuit may perform the transfer processing in the second period.

In this way, in the first period, by turning on the connection between the first bus and the second bus, the first device and the second bus connected to the first bus are connected. It becomes possible to exchange signals with the second device. Then, in the second period, the connection between the first bus and the second bus is turned off, and packets from one of the first and second buses are sent through the first and second physical layer circuits. The transfer process of transferring to the other of the first and second buses can be realized.

Further, in one aspect of the present invention, the bus monitor circuit turns on the connection between the first bus and the second bus by the bus switch circuit in the first period, and in the second period, the connection is turned on. The connection between the first bus and the second bus may be turned off by the bus switch circuit, and the transfer process may be performed by the processing circuit.

In this way, under the control of the bus monitor circuit, it becomes possible to realize the switch control of the bus switch circuit and the transfer processing of the processing circuit in the first and second periods.

Further, in one aspect of the present invention, in the first period, the bus monitor circuit is based on signals from one physical layer circuit of the first physical layer circuit and the second physical layer circuit. The monitoring operation may be performed, and the first physical layer circuit and the other physical layer circuit of the second physical layer circuit may be set to the operation off or the power saving mode.

In this way, the monitor operation in the bus monitor circuit can be realized by using the signal from one of the physical layer circuits of the first and second physical layer circuits. Then, by setting the other physical layer circuit that is not used for the monitor operation to the operation off or the power saving mode, the power consumption can be reduced.

Further, in one aspect of the present invention, in the first period, the transmission circuit for the HS mode of the first physical layer circuit and the second physical layer circuit may be set to the operation off or the power saving mode. ..

By doing so, by turning off the operation of the transmission circuit for HS mode or setting the power saving mode in the first period, it is possible to suppress unnecessary power consumption in the transmission circuit and reduce power consumption. You will be able to plan.

Further, in one aspect of the present invention, at least after the start timing of the device chirp K, the bus switch circuit switches the connection between the first bus and the second bus from on to off, and the processing circuit performs the transfer processing. May be started.

In this way, for example, it is possible to confirm with the device chirp K whether the device side supports the HS mode and start the transfer processing of the processing circuit.

Further, in one aspect of the present invention, at least after the end timing of the host chirp K / J, the bus switch circuit switches the connection between the first bus and the second bus from on to off, and the processing circuit performs the processing circuit. The transfer process may be started.

By doing so, for example, both the host side and the device side support the HS mode, and after the mode is completely switched to the HS mode, the transfer process of the processing circuit can be started properly.

Further, in one aspect of the present invention, when a reset or suspend is performed, the bus switch circuit switches the connection between the first bus and the second bus from off to on, and the processing circuit performs the transfer processing. May be stopped.

In this way, the transfer process of the processing circuit can be stopped when a reset or suspend is performed. Then, by turning on the connection between the first bus and the second bus, a signal between the first device connected to the first bus and the second device connected to the second bus Can be exchanged.

Further, in one aspect of the present invention, when the resume is performed after the suspend is performed, the bus switch circuit switches the connection between the first bus and the second bus from on to off, and the process is performed. The circuit may start the transfer process.

In this way, when the resume after suspension is performed, the transfer processing by the processing circuit can be restarted.

Further, in one aspect of the present invention, the processing circuit may perform packet bit resynchronization processing in the transfer processing.

By performing such packet bit resynchronization processing, even if the signal characteristics of the bus signal are deteriorated, the deterioration can be improved.

Further, in one aspect of the present invention, the bus switch circuit may turn on the connection between the third bus connected to the charging circuit and the second bus during the charging arbitration period.

In this way, during the charge arbitration period, the connection between the third bus and the second bus is turned on, and the charge arbitration or the like is performed between the charging circuit and the second device connected to the second bus. It becomes possible to exchange signals for the purpose.

Further, in one aspect of the present invention, the processing circuit may perform the transfer processing without changing the number of bits in the SYNC field and the number of bits in the EOP field of the packet.

In this way, packets from one of the first and second buses can be sent through the first and second physical layer circuits via the first and second physical layer circuits without changing the number of bits in the SYNC and EOP fields. It becomes possible to transfer to the other of the two buses.

Another aspect of the present invention relates to an electronic device including the circuit device according to any one of the above and a processing device connected to the first bus.

Further, another aspect of the present invention relates to a cable harness including the circuit device according to any one of the above and a cable.

Explanatory drawing about the problem of deterioration of the signal characteristic of a transmission signal. Explanatory drawing of eye pattern. Configuration example of the circuit device of this embodiment. Another configuration example of the circuit device of this embodiment. A detailed configuration example of the circuit device of this embodiment. An operation explanatory diagram of a circuit device. An operation explanatory diagram of a circuit device. An operation explanatory diagram of a circuit device. A signal waveform diagram illustrating a detailed operation of a circuit device. A signal waveform diagram illustrating a detailed operation of a circuit device. A signal waveform diagram illustrating a detailed operation of a circuit device. An explanatory diagram of the detailed operation of the bus monitor circuit. Detailed configuration example of the physical layer circuit. Explanatory drawing of the packet forwarding process in USB-HUB. Explanatory drawing of the packet forwarding process in USB-HUB. The explanatory view of the packet transfer processing in the circuit apparatus of this embodiment. The explanatory view of the packet transfer processing in the circuit apparatus of this embodiment. Explanatory drawing of packet bit resynchronization processing. Explanatory drawing of packet bit resynchronization processing. Configuration example of electronic equipment. Cable harness configuration example.

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as a means for solving the present invention. Not necessarily.

1. 1. Signal Characteristics of Transmission Signal Deterioration of signal characteristics of transmission signals by USB will be described with reference to FIG. FIG. 1 shows an example of an in-vehicle electronic device system, in which a USB-HUB210 is connected to a main controller 200 (host controller). For example, the upstream port of USB-HUB210 is connected to the main controller 200, and devices such as SD211 (SD card), BT212 (Bluetooth (registered trademark)), and DSRC213 (Dedicated Short Range Communications) are connected to the downstream port. NS.

A portable terminal device 250 such as a smartphone is connected to the USB receptacle 226 of the cable harness 220 having the cable 224. A charging circuit 221, an electrostatic protection circuit 222, a short-circuit protection circuit 223, and the like are provided between the main controller 200 and the USB receptacle 226.

In FIG. 1, since the cable 224 is wired in the vehicle while avoiding the interior, for example, the cable length becomes long, for example, 1 to 3 m, and parasitic capacitance or the like occurs. In addition, parasitic capacitance and the like caused by circuits such as the charging circuit 221 and the electrostatic protection circuit 222 and the short-circuit protection circuit 223 also occur. Due to these parasitic capacitances and the like, the signal characteristics of the transmission signal of the USB transmission circuit (HS) of the main controller 200 are deteriorated.

FIG. 2 is an explanatory diagram of an eye pattern in a USB authentication test. AR indicates a prohibited area of the waveform of the transmission signal, and this prohibited area AR is defined by the USB standard. The USB transmission circuit (HS) is required to prevent the waveform of the transmission signal (DP, DM) shown in A1 from overlapping with the prohibited area AR.

However, if the cable 224 routed in the vehicle becomes long in FIG. 1 or is caused by circuits such as the charging circuit 221 and the electrostatic protection circuit 222 and the short-circuit protection circuit 223, parasitic capacitance or the like occurs in FIG. The signal quality of the transmission signal shown in A1 of the above is deteriorated. Therefore, there is a problem that proper signal transfer cannot be realized and the eye pattern authentication test (for example, near-end authentication test) cannot be passed.

2. Circuit device FIG. 3 shows a configuration example of the circuit device 10 of the present embodiment that can solve the above problems. The circuit device 10 of the present embodiment includes physical layer circuits 11 and 12, a processing circuit 20, a bus monitor circuit 30, and a bus switch circuit 40. The circuit device 10 is not limited to the configuration shown in FIG. 3, and various modifications such as omitting some of these components or adding other components can be performed.

A USB standard bus BS1 (first bus) is connected to the physical layer circuit 11 (first physical layer circuit). A USB standard bus BS2 (second bus) is connected to the physical layer circuit 12 (second physical layer circuit). Each of the physical layer circuits 11 and 12 is composed of an analog circuit of the physical layer. The analog circuit of the physical layer is, for example, a transmission circuit for HS and FS, a reception circuit, various detection circuits, a pull-up resistor circuit, and the like. Note that the serial / parallel conversion circuit that converts serial data received via USB into parallel data, the parallel / serial conversion circuit that converts parallel data into serial data, and the circuit corresponding to the link layer such as the NRZI circuit are It is included in the processing circuit 20. For example, a circuit corresponding to a link layer or the like in a USB transceiver macro cell is included in the processing circuit 20, and analog circuits such as a transmission circuit, a reception circuit, and a detection circuit are included in the physical layer circuits 11 and 12.

The bus BS1 is, for example, a bus to which the main controller side is connected, and the bus BS2 is, for example, a bus to which the peripheral device side is connected. However, this embodiment is not limited to such a connection configuration. The buses BS1 and BS2 are USB standard (in a broad sense, a given data transfer standard) bus including signal lines such as signals DP and DM (first and second signals) constituting a differential signal. Buses BS1 and BS2 can include signal lines of power supply VBUS and GND.

The processing circuit 20 is a circuit that performs transfer processing and various control processing, and can be realized by a logic circuit or the like by automatic arrangement and wiring such as a gate array. The processing circuit 20 may be realized by a processor such as a CPU or MPU. The bus monitor circuit 30 is a circuit that performs a monitor operation for monitoring the states of the bus BS1 and the bus BS2 (at least one of BS1 and BS2). The bus switch circuit 40 is a circuit that performs a switch operation based on the monitor result. The bus switch circuit 40 includes, for example, a switch element configured by a transistor. This switch element can be realized by an analog switch such as a transfer gate.

Then, in the present embodiment, the processing circuit 20 transfers the packet received from the bus BS1 via the physical layer circuit 11 to the bus BS2 via the physical layer circuit 12, and receives the packet from the bus BS2 via the physical layer circuit 12. A transfer process is performed in which the packet is transferred to the bus BS1 via the physical layer circuit 11. For example, a packet is transferred from the bus BS1 side to the bus BS2 side, or from the bus BS2 side to the bus BS1 side without changing the packet format. At this time, the processing circuit 20 performs a packet bit resynchronization process in the transfer process. For example, when receiving a packet, each bit of the packet is sampled based on the clock signal generated by the circuit device 10. When transmitting the packet, each bit of the packet is transmitted in synchronization with the clock signal generated by the circuit device 10. Further, the bus monitor circuit 30 monitors the buses BS1 and BS2. For example, based on a signal from the physical layer circuit 11 or the physical layer circuit 12 (at least one physical layer circuit), a monitoring operation for monitoring the state of the bus BS1 or the bus BS2 (at least one bus) is performed. Then, the bus switch circuit 40 turns on or off the connection (electrical connection) between the bus BS1 and the bus BS2 based on the monitoring result in the bus monitor circuit 30. That is, the bus BS1 and the bus BS2 are electrically connected or electrically disconnected. Turning the connection between the bus BS1 and the bus BS2 on or off (electrically connecting or disconnecting) means, for example, between the signal line of the DP and DM of the bus BS1 and the signal line of the DP and DM of the bus BS2. This is to turn on or off the provided switch elements (first and second switch elements) and the like.

Specifically, as shown in FIG. 6 described later, the period during which the bus switch circuit 40 turns on the connection between the bus BS1 and the bus BS2 is defined as the period T1 (first period). That is, in the period T1, the switch element of the bus switch circuit 40 provided between the bus BS1 and the bus BS2 is turned on. As a result, the main controller 200 (first device in a broad sense) connected to the bus BS1 and the peripheral device 260 (second device in a broad sense) connected to the bus BS2 are directly USB by the USB bus. It becomes possible to perform the signal transfer of. Further, as shown in FIG. 7 described later, the period during which the bus switch circuit 40 turns off the connection between the bus BS1 and the bus BS2 is defined as the period T2 (second period). That is, in the period T2, the switch element of the bus switch circuit 40 provided between the bus BS1 and the bus BS2 is turned off. Then, the processing circuit 20 performs the above transfer processing in the period T2 (at least in a part of the period T2). That is, in the period T2, the processing circuit 20 transfers the packet received from the bus BS1 via the physical layer circuit 11 to the bus BS2 via the physical layer circuit 12, and receives the packet from the bus BS2 via the physical layer circuit 12. The transfer process of transferring to the bus BS1 via the physical layer circuit 11 is performed. As a result, packet bit resynchronization processing is performed, and high-quality signal transfer with improved deterioration of signal characteristics of the USB transmission signal can be realized.

Specifically, the bus monitor circuit 30 controls the switch of the bus switch circuit 40. That is, the bus monitor circuit 30 turns on the connection between the bus BS1 and the bus BS2 by the bus switch circuit 40 during the period T1. For example, the bus monitor circuit 30 activates the switching control signal of the switch element of the bus switch circuit 40 and turns on the switch element during the period T1. Further, in the period T2, the bus monitor circuit 30 turns off the connection between the bus BS1 and the bus BS2 by the bus switch circuit 40, and causes the processing circuit 20 to perform the transfer process. For example, the bus monitor circuit 30 deactivates the switching control signal of the switch element of the bus switch circuit 40 and turns off the switch element during the period T2. Further, the bus monitor circuit 30 activates an instruction signal (permission signal) for transfer processing to the processing circuit 20.

FIG. 4 is another configuration example of the circuit device 10 of the present embodiment. The charging circuit 221 is, for example, a circuit that operates in accordance with the USB BC1.2 specification (Battery Charging Specification Rev1.2). In BC1.2, the power supply limit of VBUS, which is, for example, 500 mA or less, is extended to, for example, 2 A or less. In FIG. 4, the charging circuit 221 has, for example, a regulator circuit or the like, and an external power source is supplied to supply power to the VBUS. Further, in the past, power could be supplied only from the master side to the slave side, but in BC1.2, power can be supplied from the slave side to the master side as well. For example, even when the peripheral device 260 plays the role of the master and the main controller 200 plays the role of the slave, the power of VBUS can be supplied from the slave main controller 200 to the master peripheral device 260.

In order to realize BC1.2, the charging circuit 221 needs to perform signal transfer using DP and DM with the peripheral device 260 during the charge arbitration period and execute the BC1.2 protocol. Therefore, as will be described later with reference to FIG. 9, the bus switch circuit 40 has a bus BS3 (third bus) and a bus connected to the charging circuit 221 during the charging arbitration period (execution period of the BC1.2 protocol). Turn on the connection of BS2 (second bus) (switch from off to on). That is, the bus BS3 and the bus BS2 are electrically connected. For example, the switch element provided between the bus BS3 and the bus BS2 is turned on so that the charging circuit 221 can execute signal transfer using DP and DM with the peripheral device. By doing so, it becomes possible to execute the BC1.2 protocol and perform the charge arbitration process during the charge arbitration period. For example, since the charging current can be set to an appropriate level, the charging speed can be increased.

FIG. 5 is a detailed configuration example of the circuit device 10. The circuit device 10 is not limited to the configuration shown in FIG. 5, and various modifications such as omitting some of these components or adding other components can be performed. In FIG. 5, the circuit device 10 further includes reference current circuits 13 and 14, clock signal generation circuit 50, and power supply circuit 60.

The reference current circuits 13 and 14 are circuits for generating the reference current used in the physical layer circuits 11 and 12, respectively, and generate the reference current by using the resistors RI and RE which are external components. The clock signal generation circuit 50 is a circuit that generates various clock signals used in the circuit device 10, and includes an oscillation circuit 52 and a PLL circuit 54. An oscillator XTAL and capacitors CC1 and CC2, which are external components, are connected to the oscillator circuit 52. The oscillator XTAL is realized by, for example, a crystal oscillator or the like. Then, the oscillation circuit 52 performs an oscillation operation of the oscillator XTAL to generate a clock signal based on the oscillation signal. The PLL circuit 54 generates a multi-phase clock signal as shown in FIG. 18 described later, based on the generated clock signal.

The power supply circuit 60 is supplied with an external power supply voltage to generate various power supply voltages used in the circuit device 10. Specifically, the regulator 62 of the power supply circuit 60 regulates the external power supply voltage, generates a power supply voltage lower than the external power supply voltage, and supplies the power supply voltage to each circuit block of the circuit device 10.

The processing circuit 20 includes a link layer circuit 22, a repeater logic circuit 24, and the like. The link layer circuit 22 is a circuit that performs processing corresponding to the link layer. The link layer circuit 22 has, for example, a serial / parallel conversion process for converting serial data received by USB into parallel data, a parallel / serial conversion process for converting parallel data into serial data for transmission, and NRZI coding and decoding. Perform processing for conversion. The repeater logic circuit 24 performs logic processing for transmitting the packet received from the bus BS1 side to the bus BS2 side and transmitting the packet received from the bus BS2 side to the bus BS1 side. For example, as will be described in detail in FIGS. 18 and 19 described later, each bit of the received packet is sampled using a clock signal, and the serial data obtained by sampling is converted into parallel data. Then, the parallel data after various logic processing such as NRZI is performed is converted into serial data and transmitted in synchronization with the clock signal in the circuit device 10. By doing so, the packet bit resynchronization process (resynchronization) is realized.

6, FIG. 7, and FIG. 8 are operation explanatory views of the circuit device 10 of the present embodiment. For example, in the present embodiment, the bus monitor circuit 30 monitors the buses BS1 and BS2. Specifically, as will be described in detail with reference to FIG. 13 described later, a monitor operation for monitoring the state of the buses BS1 and BS2 is performed based on the signals from the physical layer circuits 11 and 12. Then, the bus switch circuit 40 performs a switch operation for turning on / off the connection between the bus BS1 and the bus BS2 based on the result of monitoring the bus state in the bus monitor circuit 30.

Specifically, as shown in FIG. 6, during the period T1, the bus switch circuit 40 turns on the connection of the buses BS1 and BS2. For example, when the switching control signal from the bus monitor circuit 30 becomes active, the switch elements provided corresponding to each of the DP and DM signal lines are turned on, and the buses BS1 and BS2 are electrically connected. .. As a result, the main controller 200 connected to the bus BS1 and the peripheral device 260 connected to the bus BS2 (for example, the portable terminal device 250 in FIG. 1) have the bus BS1, the bus switch circuit 40, and the transfer path TR1 of the bus BS2. In, it becomes possible to perform USB signal transfer. That is, signal transfer using signals DP and DM becomes possible.

On the other hand, as shown in FIG. 7, in the period T2 after the period T1, the bus switch circuit 40 turns off the connection between the bus BS1 and the bus BS2. For example, when the switching control signal from the bus monitor circuit 30 becomes inactive, the switch elements provided corresponding to the signals DP and DM are turned off, and the buses BS1 and BS2 are electrically disconnected. .. Then, in this period T2 (at least a part of the period T2), the processing circuit 20 performs a transfer process for transferring packets between the buses BS1 and BS2 via the physical layer circuits 11 and 12. That is, the packet transfer process on the transfer path TR2 of FIG. 7 is performed. For example, in the period T2, when the instruction signal (permission signal) for the transfer process from the bus monitor circuit 30 becomes active, the processing circuit 20 starts the packet transfer process on the transfer path TR2. In this transfer process, the bit resynchronization process of the packet is performed, and the signal quality is improved.

FIG. 8 is an operation explanatory view of the circuit device 10 in the configuration example of FIG. In FIG. 8, the bus switch circuit 40 turns on the connection between the bus BS3 and the bus BS2 connected to the charging circuit 221 during the charging arbitration period. For example, a switch element provided between the bus BS3 and the bus BS2 corresponding to each of the signals DP and DM is turned on during the charge arbitration period, and the bus BS3 and the bus BS2 are electrically connected. As a result, for example, the BC1.2 protocol is executed between the charging circuit 221 and the peripheral device 260, and charging arbitration processing and the like are realized. Then, after this charge arbitration period (protocol execution period of BC1.2), the signal is transferred on the transfer path TR1 by switching to the period T1 of FIG. After that, the period is switched to T2 in FIG. 7, and the packet transfer process on the transfer path TR2 is performed.

As described above, in the present embodiment, the processing circuit 20 that transfers packets between the buses BS1 and BS2 via the physical layer circuits 11 and 12, the bus monitor circuit 30 that monitors the bus, and the bus BS1 based on the monitoring results, A bus switch circuit 40 for turning on / off the connection of BS2 is provided. By doing so, for example, even when the signal characteristics of the signals on the buses BS1 and BS2 are deteriorated, the deterioration of the signal characteristics is improved by the resynchronization process of the packet bits on the transfer path TR2 of FIG. become able to.

For example, if the cable 224 is long as shown in FIG. 1, or if a large parasitic capacitance or a parasitic resistance exists in the transfer path, the signal characteristics are significantly deteriorated, and there is a problem that proper signal transfer cannot be realized. .. In this respect, for example, if the circuit device 10 of the present embodiment is arranged between the main controller 200 and the portable terminal device 250 (peripheral device), the deteriorated signal characteristics can be improved. Therefore, proper signal transfer between the main controller 200 and the portable terminal device 250 can be realized.

Further, in the present embodiment, the state of the buses BS1 and BS2 is monitored by the bus monitor circuit 30, and the connection of the buses BS1 and BS2 is turned on and off by the bus switch circuit 40 based on the monitoring result. Therefore, for example, in the period T1 before the high-speed packet transfer in the HS mode is performed, the buses BS1 and BS2 can be electrically connected by the bus switch circuit 40 as shown in FIG. As a result, during this period T1, it becomes possible to perform signal transfer using the signals DP and DM between the main controller 200 and the peripheral device 260, and various types of signals are transferred in the stage before the packet transfer in the HS mode. Communication becomes possible. Then, in the period T2, as shown in FIG. 7, the connections of the buses BS1 and BS2 are turned off, and the HS mode packet transfer is performed on the transfer path TR2. Then, at the time of this packet transfer, the bits of the packet are resynchronized, so that it is possible to realize a high-quality packet transfer in which the deterioration of the signal characteristics as described with reference to FIG. 1 is improved.

The USB-HUB210 shown in FIG. 1 has a USB standard product ID and vendor ID. On the other hand, the circuit device 10 of the present embodiment does not have such a product ID or vendor ID, and the circuit device 10 of the present embodiment is different from the USB-HUB210 in this respect.

Further, as a comparative example of the present embodiment, there is also a circuit device called a redriver that adjusts the amplitude and aperture of the signals DP and DM by an analog circuit. However, since the redriver does not perform packet transfer as in the transfer path TR2 of FIG. 7, the signal characteristics of the deteriorated signal cannot be improved by the resynchronization process, and in this respect, the present embodiment It is different from the circuit device 10.

Further, the peripheral device 260 of FIGS. 6 to 8 may be a device such as CarPlay or USB OTG (On-The-GO) that can exchange the role of the master (host) and the role of the slave (device). .. For example, it is assumed that the portable terminal device 250 of FIG. 1 is a peripheral device 260 capable of performing CarPlay or the like. In this case, as a method of the comparative example of the present embodiment, a method of arranging a USB-HUB for improving the deterioration of signal characteristics between the main controller 200 and the peripheral device 260 (portable terminal device 250) is also considered. Be done. However, when the peripheral device 260 becomes the master, the master peripheral device 260 will be connected to the downstream port of the USB-HUB, and there is a problem that proper packet forwarding cannot be realized. ..

In this respect, the circuit device 10 of the present embodiment is different from the USB-HUB, and corresponds to, for example, even when the role of the peripheral device 260 connected to the bus BS2 of FIGS. 6 to 8 is switched to the master. There is an advantage that it can be done. For example, the switching process and the setting process for the roles of the master and the slave may be performed in the period T1. Then, after the role of the peripheral device 260 is determined to be the master or the slave, packet transfer may be performed on the transfer path TR2 as shown in FIG. 7 during the period T2. Therefore, according to the method of the present embodiment, even if the peripheral device 260 is a device such as CarPlay, there is an advantage that proper packet forwarding can be realized.

3. 3. Detailed operation example Next, a detailed operation example of the present embodiment will be described. FIG. 9 is a signal waveform diagram showing a USB operation sequence after cable attachment. FIG. 9 shows various states of the differential signals DP and DM, and on / off states of the switch element of the bus switch circuit 40.

In FIG. 9, the BC switch and the USB switch are switch elements provided in the bus switch circuit 40. Specifically, the BC switch is a switch element provided between the bus BS3 (charging circuit) and the bus BS2 (peripheral device) of FIG. 8 in the bus switch circuit 40. The USB switch is a switch element provided between the bus BS1 (main controller) and the bus BS2 (peripheral device) in the bus switch circuit 40. The off / on of the transfer process indicates the off / on of the transfer process on the transfer path TR2 in FIG. 7.

After the cable attach (timing t1), the BC1.2 protocol described above is executed. The period shown in B1 in which the BC1.2 protocol is executed is the charge arbitration period.

Next, when the device side (peripheral device) turns on the pull-up resistor, the voltage of the signal DP is pulled up and the mode shifts to the FS mode (t2). That is, it shifts to the FS idle, and if there is nothing for a certain period of time, it shifts to the suspend state.

Next, when the host side (main controller) starts resetting (t3), the voltage of the signal DP that has been pulled up becomes the L level. The device side detects this, and the device side sends out the device chirp K (t4). After that, when a certain period of time elapses, the device side stops the device chirp K (t5). Then, the host side executes the host chirp K / J (t6), and the device side recognizes that the host side supports the HS mode by detecting the host chirp K / J and turns on the HS termination. (T7). As a result, the amplitudes of the signals DP and DM are reduced to, for example, 400 mV, and the mode shifts to the HS mode. Then, when the host side finishes the reset (t8), it shifts to the HS idle, and the host side starts sending the SOF (t9).

In the present embodiment, it is possible to enable and disable the BC switch that connects the bus BS3 and the bus BS2. When the BC switch is enabled, during the charge arbitration period (protocol execution period of BC1.2) shown in period B1 of FIG. 9, the BC switch is turned on and the USB switch is turned off as shown in the state B2. become. For example, in FIG. 8, when the BC switch is turned on, the connection between the bus BS3 and the bus BS2 is turned on, and when the USB switch is turned off, the connection between the bus BS1 and the bus BS2 is turned off. As a result, signal processing for charge arbitration or the like using signals DP and DM becomes possible between the charging circuit 221 and the peripheral device 260.

When the mode shifts to the FS mode, the USB switch is turned on and the BC switch is turned off as shown in the state B3. When the USB switch is turned on, the connection between the bus BS1 and the bus BS2 is turned on, and when the BC switch is turned off, the connection between the bus BS3 and the bus BS2 is turned off. As a result, as shown in FIG. 6, the signal can be transferred between the main controller 200 and the peripheral device 260 on the transfer path TR1 using the signals DP and DM. At this time, as shown in the state B4, the transfer process on the transfer path TR2 in FIG. 7 is turned off.

Then, in the present embodiment, the on / off switching timing of the connection between the bus BS1 and the bus BS2 (switching timing of the periods T1 and T2) is set to a timing within the range shown in the period B5 of FIG. That is, at least after the start timing (t4) of the device chirp K, the connection between the bus BS1 and the bus BS2 is switched from on to off (the period T1 is switched to T2). Alternatively, at least after the end timing (t8) of the host chirp K / J, the connection between the bus BS1 and the bus BS2 is switched from on to off. For example, at least after the start timing (t4) of the device chirp K, for example, before the start timing (t9) of SOF transmission, the connection between the bus BS1 and the bus BS2 is switched from on to off, and the transfer path TR2 in FIG. The transfer process in is switched from off to on. That is, at the timing within the range shown in the period B5, as shown in the state B6, the USB switch connecting the bus BS1 and the bus BS2 is switched from on to off, and the transfer process in the transfer path TR2 is switched from off to on. When the BC switch is set to disable, the BC switch is not switched on and off as shown in states B2 and B3, and the BC switch remains off as shown in state B7. ..

As described above, in the present embodiment, during the period T1 (B3), the connection between the bus BS1 and the bus BS2 is turned on by turning on the USB switch. Then, signal transfer on the transfer path TR1 as shown in FIG. 6 is performed between, for example, the main controller 200 and the peripheral device 260. On the other hand, in the period T2 (B6), when the USB switch is turned off, the connection between the bus BS1 and the bus BS2 is turned off, and the transfer process of the processing circuit 20 is turned on, so that the transfer path shown in FIG. 7 is turned on. Packet transfer is performed on TR2. Since the switching timing is within the range of the period B5, in FIG. 9, the range of the USB switch on / off switching timing and the transfer processing on / off switching timing is shown by a dotted line.

Then, in the present embodiment, at least after the start timing (t4) of the device chirp K, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from on to off, and the processing circuit 20 is on the transfer path TR2 of FIG. Transfer processing is started. For example, after the start timing of the device chirp K, the USB switch is switched from on (B3) to off (B6), and the transfer processing of the processing circuit 20 is switched from off (B4) to on (B6).

That is, when the start of the device chirp K (t4) is detected, it can be determined that the device side corresponds to the HS mode. On the other hand, it is extremely rare that the host side does not support HS mode. Therefore, when the start of the device chirp K (t4) is detected, the USB switch is switched from on to off, and the HS mode transfer process by the processing circuit 20 is switched from off (disable) to on (enabled). be able to. Therefore, the switching timing within the period B5 may be at least the timing after the start timing (t4) of the device chirp K.

Alternatively, considering the possibility that the host side does not support the HS mode, for example, when the start (t6) of the host chirp K / J is detected, the USB switch is switched from on to off, and the HS by the processing circuit 20 is used. The mode transfer process may be switched from off to on.

For example, in the present embodiment, at least after the end timing (t8) of the host chirp K / J, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from on to off, and the processing circuit 20 sets the transfer path of FIG. The transfer process in TR2 may be started.

By doing so, for example, after it is determined that both the host side and the device side are compatible with the HS mode and it is determined that the mode is completely switched to the HS mode, the transfer process of the processing circuit 20 can be started properly. become.

As described above, the switching timing within the period B5 of FIG. 9 may be at least after the start timing of the device chirp K. However, it is also necessary to consider the adverse effect of the generation of glitches due to switching. Therefore, it is desirable that the switching timing is within a period set to a predetermined voltage level (for example, L level) of the signals DP and DM. For example, the period between timings t5 to t6 and the period between t8 and t9 in FIG. 9 and the like.

As described above, in the present embodiment, before the switching timing of the period B5 in FIG. 9, by turning on the USB switch as shown in the state B3, on the USB bus between the host side and the device side. Signals can be exchanged. The bus monitor circuit 30 monitors the exchange of signals on the USB bus. Then, for example, when it is determined that the HS mode transfer is possible by detecting the device chirp K or the host chirp K / J, the USB switch is switched from on to off, and the transfer process by the processing circuit 20 is switched from off to on. By doing so, after exchanging signals between the host side and the device side, it is possible to properly shift to the HS mode transfer process.

Further, in the charge arbitration period by the charging circuit 221 of FIG. 8 as shown in the period B1 of FIG. 9, the BC switch is turned on and the USB switch is turned off as shown in the state B2. By doing so, for example, in FIG. 8, it becomes possible to realize an appropriate charge arbitration process between the charging circuit 221 and the peripheral device 260.

FIG. 10 is a signal waveform diagram showing an operation sequence when a reset is performed in the transfer in HS mode. In the HS mode, the host side sends out SOF packets every 125 μs (t11, t12). When the host side starts resetting (t12), the mode shifts to FS mode, and when 3 ms or more have passed since the packets disappeared on the bus, the device side turns off the HS termination and turns on the pull-up resistor (t13). Then, since it is confirmed that the bus state is SE0 (t14), the device side determines that the reset has started and sends out the device chirp K. On the other hand, when the host side sends out the host chirp K / J, the mode shifts from the FS mode to the HS mode.

As shown in C1 of FIG. 10, in the present embodiment, when the host starts resetting, the USB switch is switched from off to on, and the transfer processing of the processing circuit 20 is switched from on to off. That is, when a reset is performed, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from off to on, and the processing circuit 20 stops the transfer processing.

In this way, for example, when a reset is performed during the transfer in HS mode, the buses BS1 and BS2 are electrically connected, and the signals DP and DM are connected between the main controller 200 and the peripheral device 260, for example. It becomes possible to perform signal transfer using. After that, for example, at the switching timing within the range shown in the period C2 of FIG. 10, the USB switch is switched from on to off, and the transfer processing of the processing circuit 20 is switched from off to on. This makes it possible to properly shift to the HS mode transfer process after exchanging signals between the host side and the device side.

FIG. 11 is a signal waveform diagram showing an operation sequence when shifting from HS mode transfer to suspend and resume. When the host side starts suspending (t22), the mode shifts to FS mode, and when 3 ms or more have passed since the packets disappeared on the bus, the device side turns off the HS termination and turns on the pull-up resistor (t23). Then, the device side determines that the suspend has been started because it is confirmed that the state of the bus is J (t24). Then, when the host side starts the resume (t25) and the resume ends (t26), the device side returns to the mode at the time of suspending at the same time as the resume ends. Then, the pull-up resistor is turned off, HS termination is turned on, and the mode returns to HS mode.

As shown in the state D1 of FIG. 11, in the present embodiment, the USB switch is switched from off to on and the transfer process of the processing circuit 20 is switched from on to off even when the host starts suspending. That is, when suspend is performed, the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from off to on, and the processing circuit 20 stops the transfer processing.

In this way, for example, when suspend is started during transfer in HS mode, buses BS1 and BS2 are electrically connected, and signals DP and DM are transmitted between the main controller 200 and the peripheral device 260, for example. It becomes possible to perform the signal transfer used.

Then, after suspending, the host side resumes, so that the USB switch is switched from on to off and the transfer processing of the processing circuit 20 is switched from off to on, as shown in the state D2 of FIG. That is, in the present embodiment, when the resume is performed after the suspend is performed (at the end timing of the resume), the bus switch circuit 40 switches the connection between the bus BS1 and the bus BS2 from on to off, and the processing circuit 20 Starts the transfer process. In this way, the resume after suspend enables the data transfer in HS mode to be resumed properly. The operation sequence of the transition from suspend to reset is the same as the operation sequence of entering reset from suspend after cable attach to FS idle.

FIG. 12 is an explanatory diagram of the detailed operation of the bus monitor circuit 30. The bus monitor circuit 30 performs a USB bus monitor operation, and this monitor operation is performed based on a signal from the physical layer circuit. Specifically, as shown in FIG. 12, during the period T1, the bus monitor circuit 30 performs a monitor operation based on a signal from one of the physical layer circuits 11 and 12. That is, the USB bus is monitored based on a signal (detection signal or the like) from one of the physical layer circuits, not both of the physical layer circuits 11 and 12. Then, in the period T1, the other physical layer circuits of the physical layer circuits 11 and 12 are set to the operation off or the power saving mode.

For example, when the bus monitor circuit 30 performs the bus monitor operation based on the signal from the physical layer circuit 11, the physical layer circuit 12 is set to the operation off or the power saving mode. Alternatively, when the bus monitor circuit 30 performs the bus monitor operation based on the signal from the physical layer circuit 12, the physical layer circuit 11 is set to the operation off or the power saving mode. The operation off or the power saving mode of the physical layer circuit 11 and the physical layer circuit 12 can be set based on, for example, a control signal from the bus monitor circuit 30. Alternatively, the operation of the physical layer circuit 11 or the physical layer circuit 12 may be turned off or the power saving mode may be set based on the control signal from the processing circuit 20.

Here, the operation off setting means, for example, disabling the operation of the analog circuits constituting the physical layer circuit. For example, the transistors that make up the analog circuit are turned off so that the current that consumes power does not flow. For example, the transmission circuit (HSD) for HS mode includes a current source provided between the power supply line of AVDD (high potential side power supply) and the first node, the signal line of the first node and DP, and the signal line of DM. , The first, second, and third transistors provided between the power lines of the AVSS (low potential side power supply) can be included. In this case, the setting of the operation off of the transmission circuit for the HS mode is, for example, to stop the current source (stop the current flowing through the current source). Further, the setting to the power saving mode is to limit the current flowing through the analog circuit (operational amplifier or the like) constituting the physical layer circuit to reduce the power consumption. For example, the current flowing through an analog circuit is limited to a current below a given threshold. For example, the current flowing through the above current source is limited to a current below a given threshold.

For example, in order to monitor the state of a bus (signal DP, DM) as shown in FIGS. 9 to 11, it is effective to use a signal from an analog circuit constituting a physical layer circuit. Therefore, it is necessary to operate these analog circuits when performing the monitor operation.

On the other hand, in the circuit device 10 of the present embodiment, two physical layer circuits 11 and 12 are provided, and operating both of these physical layer circuits 11 and 12 for monitor operation is in terms of power consumption. It's useless. Therefore, the monitor operation is performed based on the signal from one of the physical layer circuits 11 and 12, and the operation of the other physical layer circuit is set to off or the power saving mode. In this way, proper bus monitoring operation can be realized based on the signal from one physical layer circuit, and wasteful power can be obtained by setting the other physical layer circuit to operation off or power saving mode. It is possible to reduce power consumption and reduce power consumption.

Then, as shown in FIG. 7, during the period T2, both the operations of the physical layer circuits 11 and 12 are turned on. Then, packet transfer is performed between the buses BS1 and BS2 on the transfer path TR2 via the physical layer circuits 11 and 12.

The bus monitor circuit 30 can monitor not only one of the buses BS1 and BS2 but also both the buses BS1 and BS2. For example, the bus monitor circuit 30 performs a USB bus monitor operation based on signals (detection signals, etc.) from both the physical layer circuits 11 and 12. For example, in order to detect a bus reset, it is necessary to monitor the bus BS1 on the main controller 200 side, for example. Further, in order to detect the HS disconnection, it is necessary to monitor the bus BS2 on the peripheral device 260 side. Therefore, in order to detect these bus resets and HS disconnection, the bus monitor circuit 30 monitors both the buses BS1 and BS2. That is, the monitor operation is performed based on the signals from both the physical layer circuits 11 and 12.

FIG. 13 is a configuration example of the physical layer circuit (11, 12). This physical layer circuit includes a pull-up resistor Rpu, switch elements SW_Rpu, SW_Dm, and pull-down resistors Rpd1 and Rpd2. The switch element SW_Rpu is turned on or off based on the control signal Rpu_Enable. As a result, the pull-down operation is realized. The physical layer circuit also includes a transmission circuit HSD (current driver) for HS mode, a transmission circuit LSD (driver) for LS / FS mode, resistors Rs1 and Rs2. The physical layer circuit includes a differential receiving circuit HSR (data receiver) for HS mode, a squelch detection circuit SQL (transmission envelope detector), a differential receiving circuit LSR (data receiver) for LS / FS mode, and disconnection. Includes detection circuit DIS (disconnection envelope detector), single-ended receiving circuit DP_SER, DM_SER (receiver).

Then, in the present embodiment, the bus monitor operation of the bus monitor circuit 30 is performed based on the signal from the analog circuit constituting the physical layer circuit. Specifically, as shown in FIG. 13, for example, a differential receiving circuit HSR for HS mode, a detection circuit SQL for squelch, a differential receiving circuit LSR for LS / FS mode, a disconnection detection circuit DIS, or The bus monitor circuit 30 performs a bus monitoring operation based on the signals from the single-ended receiving circuits DP_SER and DM_SER. That is, based on the signals from these analog circuits, each state of the bus such as device chirp K, host chirp K / J, idle, reset, suspend, resume, SE0, J, K, bus reset, or HS disconnection is performed. , The bus monitor circuit 30 can be monitored. Then, the bus monitor circuit 30 controls to turn on or off the switch elements (USB switch, BC switch) of the bus switch circuit 40 as described with reference to FIGS. 9, 10 and 11 based on the monitor results. , Controls to turn on or off the transfer process of the processing circuit 20. By doing so, it becomes possible to realize appropriate switch control of the bus switch circuit 40 and transfer control of the processing circuit 20 in which the state of the bus is appropriately determined.

Further, in the present embodiment, as shown in FIG. 13, in the period T1, the transmission circuit HSD for the HS mode of the physical layer circuits 11 and 12 is set to the operation off or the power saving mode. That is, in the present embodiment, as shown in FIG. 12, during the period T1, the bus switch circuit 40 turns on the connection of the buses BS1 and BS2, and the direct controller 200 and the peripheral device 260 are directly connected to each other on the transfer path TR1. It enables the exchange of signals. Then, the bus monitor circuit 30 performs a bus monitoring operation based on a signal from one of the physical layer circuits 11 and 12.

In this case, the transmission circuit HSD for the HS mode of the physical layer circuits 11 and 12 does not need to operate because the HS transfer process is not performed. Therefore, in the period T1, for example, the bus monitor circuit 30 (or the processing circuit 20) sets the transmission circuit HSD for the HS mode to the operation off or the power saving mode. By doing so, it is possible to prevent unnecessary power consumption in the transmission circuit HSD for the HS mode, and it becomes possible to reduce the power consumption. The transmission circuit HSD for the HS mode is a current driver, and a large amount of current flows through it. Therefore, when the bus monitor circuit 30 (or the processing circuit 20) sets the transmission circuit HSD to the operation off or the power saving mode, the power consumption can be significantly reduced. In the period T1, the transmission circuit LSD for LS / FS may also be set to operation off or power saving mode. By doing so, it becomes possible to further reduce the power consumption.

4. Details of the transfer process Next, the details of the transfer process in the processing circuit 20 will be described. 14 and 15 are diagrams for explaining packet transfer processing when the USB-HUB210 is provided between the main controller 200 and the peripheral device 260. FIG. 15 shows the signal waveforms of the signal UPP on the upstream port side and the signal DWP on the downstream port side of the USB-HUB210 of FIG. These signal UPP and DWP packets have fields (regions) of SYNC, PID, FrameNumber, CRC, and EOP, taking the packet of SOF as an example. For example, SYNC is a synchronization field, PID is a packet ID field, FrameNumber is a frame number field, CRC is a cyclic redundancy check field, and EOP is a packet end field.

In this case, in the USB-HUB210 of FIG. 14, as shown in FIG. 15, in the packet of the signal DWP, the number of bits of the SYNC field is reduced to -3 bits, and the number of bits of the EOP field is +1 bit. The number of bits is increasing. As shown in FIG. 15, in the USB standard, the SYNC field is allowed up to -4 bits, and the EP field is allowed up to +4 bits.

16 and 17 are diagrams for explaining packet transfer processing when the circuit device 10 of the present embodiment is provided between the main controller 200 and the peripheral device 260.

FIG. 17 shows the signal waveforms of the signal INT on the bus BS1 side and the signal EXT on the bus BS2 side of the circuit device 10 of FIG. As shown in FIG. 17, the packet received from the bus BS1 side is transmitted to the bus BS2 side in the same format without changing the packet format. Note that FIGS. 16 and 17 show the case where the packet is transferred from the bus BS1 side to the bus BS2 side, but the same signal waveform is obtained when the packet is transferred from the bus BS2 side to the bus BS1 side. That is, the packet received from the bus BS2 side is transmitted to the bus BS1 side in the same format without changing the packet format.

In FIG. 17, unlike the case of FIG. 15, in the signal EXT, neither the number of bits in the SYNC field nor the number of bits in the EOP field is changed. That is, the packet received from the bus BS1 side is transmitted to the bus BS2 side as it is without changing the number of bits in the SYNC field and the number of bits in the EOP field. The same applies to the case where the packet received from the bus BS2 side is transmitted to the bus BS1 side.

That is, the USB-HUB210 shown in FIG. 14 has a USB product ID and a vendor ID, and transfers packets conforming to the USB HUB standard. In the USB standard, a change in the number of bits in the SYNC field is allowed up to -4 bits, and a change in the number of bits in the EOP field is allowed up to +4 bits. Therefore, in the waveform of the signal DWP of FIG. 15, the number of bits of SYNC and EOP is changed so as to conform to this standard.

On the other hand, the circuit device 10 of the present embodiment does not have a product ID or a vendor ID, and a change in the number of bits in the fields of SYNC and EOP as shown in FIG. 15 is not allowed. Therefore, in the present embodiment, the packet transfer process on the transfer path TR2 shown in FIG. 7 is performed without changing the number of bits in the SYNC field and the number of bits in the EOP field of the packet. By doing so, even if the circuit device 10 of the present embodiment is provided between the main controller 200 and the peripheral device 260 as shown in FIG. 16, it is possible to realize proper packet transfer conforming to the USB standard. That is, USB packets can be transferred between the main controller 200 and the peripheral device 260 as if no circuit device exists.

Further, in the present embodiment, in the transfer process in the processing circuit 20, the packet bit resynchronization process is performed. In the resynchronization process (resynchronization), for example, each bit of the received packet is sampled and captured by the clock signal of the circuit device, the packet composed of each captured bit is reconstructed, and the reconstructed packet is reconstructed. Is realized by outputting in synchronization with the clock signal of the circuit device.

18 and 19 are explanatory diagrams of packet resynchronization processing, and are explanatory diagrams of processing for sampling each bit of a packet. In FIG. 18, the PLL circuit 54 generates and outputs clock signals CLK0, CLK1, CLK2, CLK3, and CLK4 (in a broad sense, first to Nth clock signals) having the same frequency but different phases. For example, the PLL circuit 54 is a five (N) differential output comparator (in a broad sense, an odd-stage first to Nth inverting circuit) included in the VCO (oscillation means whose oscillation frequency is variably controlled). The output is used to generate and output clock signals CLK0 to CLK4.

The DLL circuit 25 includes an edge detection circuit 26 and a clock selection circuit 27. Then, the edge detection circuit 26 detects the edge of the serial data DIN received by the reception circuit of the physical layer circuit (11, 12), and outputs the edge detection information to the clock selection circuit 27. Specifically, as described with reference to FIG. 19, it is detected which of the edges (rising edge or falling edge) of the clock signals CLK0 to CLK4 from the PLL circuit 54 has an edge of the serial data DIN. Then, the edge detection information is output to the clock selection circuit 27. The clock selection circuit 27 selects one of the clock signals from the clock signals CLK0 to CLK4 based on the edge detection information, and outputs the selected clock signal as the sampling clock signal SCLK. By sampling serial data based on this sampling clock signal SCLK, sampling of each bit of the received packet can be realized.

FIG. 19 is a timing waveform diagram for explaining the circuit operation of FIG. As shown in FIG. 19, CLK0 to CLK4 are multi-phase clock signals having the same frequency (480 MHz). Further, when the period of the clock signal is T, the phase between each clock is shifted by T / 5 (T / N in a broad sense). Then, in FIG. 19, the edge ED of the serial data DIN to be sampled is detected by the edge detection circuit 26 of FIG. 18 between CLK0 and CLK1. Then, the clock signal CLK3 having the edge EC3 deviated from the edge ED of the serial data DIN by, for example, three (in a broad sense, a set number of M) is selected by the clock selection circuit 27 of FIG. 18, and the selected CLK3 is selected. , DIN is output as a sampling clock signal SCLK to the subsequent circuit.

By performing the processing described with reference to FIGS. 18 and 19, each bit of the packet received from the USB bus can be appropriately sampled. That is, each bit of the packet of the signal INT of FIG. 17 can be appropriately sampled. Then, the packet is reconstructed by each sampled bit and transmitted to the USB bus as a signal EXT packet as shown in FIG. At this time, for example, the packet is transmitted so that each bit of the packet is synchronized with the clock signal of the circuit device 10.

For example, if the cable length becomes long as described in FIG. 1, or if a large parasitic capacitance or parasitic resistance parasitizes on the transfer path, the signal quality deteriorates and the eye pattern authentication test of FIG. 2 cannot be passed. There is a problem that proper signal transfer cannot be realized.

In this regard, according to the present embodiment, for example, even when the signal quality of the packet signal (INT) from the bus BS1 side of FIG. 16 is deteriorated, the circuit device 10 performs the above-mentioned resynchronization process. As a result, the signal (EXT) of the packet whose signal quality is improved (purified) is transferred to the bus BS2 side. Similarly, even when the signal quality of the packet signal from the bus BS2 side is deteriorated, the packet signal whose signal quality is improved by performing the above-mentioned resynchronization process by the circuit device 10 can be obtained. It is transferred to the bus BS1 side. Therefore, it becomes possible to provide a circuit device capable of improving the deterioration of the signal characteristics of the USB signal.

Moreover, as shown in FIG. 6, the connection between the bus BS1 and the bus BS2 can be turned on by the bus switch circuit 40 in the pre-stage of such high-speed packet transfer in the HS mode. As a result, various signals as described with reference to FIGS. 9 to 11 can be exchanged between the main controller 200 connected to the bus BS1 and the peripheral device 260 connected to the bus BS2. Therefore, according to the USB standard, various processes are performed between the main controller 200 and the peripheral device 260 as if the circuit device 10 does not exist, and the USB standard is performed between the main controller 200 and the peripheral device 260. It becomes possible to execute proper transfer processing in accordance with.

5. Electronic device, cable harness FIG. 20 shows a configuration example of the electronic device 300 including the circuit device 10 of the present embodiment. The electronic device 300 includes the circuit device 10 of the present embodiment and the main controller 200 (in a broad sense, a processing device). The main controller 200 is connected to the bus BS1. For example, the main controller 200 and the circuit device 10 are connected via the bus BS1. Further, for example, a peripheral device 260 is connected to the bus BS2 of the circuit device 10.

The main controller 200 (processing device) is realized by a processor such as a CPU or an MPU, for example. Alternatively, the main controller 200 may be realized by various ASIC circuit devices. Further, the main controller 200 may be realized by a circuit board on which a plurality of circuit devices (ICs) and circuit components are mounted. As the peripheral device 260, for example, the portable terminal device 250 as shown in FIG. 1 can be assumed, but the peripheral device 260 is not limited thereto. The peripheral device 260 may be a wearable device or the like.

The electronic device 300 can further include a storage unit 310, an operation unit 320, and a display unit 330. The storage unit 310 stores data, and its function can be realized by a semiconductor memory such as RAM or ROM, an HDD (hard disk drive), or the like. The operation unit 320 is for the user to perform an input operation, and can be realized by an operation device such as an operation button or a touch panel display. The display unit 330 displays various types of information, and can be realized by a display such as a liquid crystal display or an organic EL. When a touch panel display is used as the operation unit 320, the touch panel display also functions as the operation unit 320 and the display unit 330.

The electronic device 300 realized by the present embodiment measures, for example, an in-vehicle device, a printing device, a projection device, a robot, a head-mounted display device, a biological information measuring device, a physical quantity such as a distance, a time, a flow velocity, or a flow rate. Various devices such as measuring devices, network-related devices such as base stations or routers, content providing devices for distributing content, and video devices such as digital cameras or video cameras can be assumed.

FIG. 21 shows a configuration example of the cable harness 350 including the circuit device 10 of the present embodiment. The cable harness 350 includes the circuit device 10 and the cable 360 of this embodiment. The cable 360 is a cable for USB. The cable harness 350 may also include a USB receptacle 370. Alternatively, the cable harness 350 may include the electrostatic protection circuit 222, the short-circuit protection circuit 223, and the like shown in FIG. The cable 360 is connected to, for example, the bus BS2 of the circuit device 10. For example, a main controller 200 (processing device) or the like is connected to the bus BS1 side of the circuit device 10. The cable harness 350 is used, for example, for routing wiring in a vehicle. The cable harness 350 may be a harness other than that for a car.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present invention are possible. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present invention. Further, the configuration / operation of the circuit device, the electronic device, and the cable harness, the bus monitor processing, the bus switch processing, the transfer processing, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

BS1, BS2 ... Buses (first and second buses),
10 ... Circuit device, 11, 12 ... Physical layer circuit (first and second physical layer circuits),
13, 14 ... Reference current circuit, 20 ... Processing circuit,
25 ... DLL circuit, 26 ... edge detection circuit, 27 ... clock selection circuit,
30 ... Bus monitor circuit, 40 ... Bus switch circuit, 50 ... Clock signal generation circuit,
52 ... Oscillation circuit, 54 ... PLL circuit, 60 ... Power supply circuit, 62 ... Regulator,
200 ... Main controller, 210 ... USB-HUB,
221 ... Charging circuit, 222 ... Static electricity protection circuit, 223 ... Short circuit protection circuit,
224 ... Cable, 226 ... USB Receptacle, 250 ... Portable Terminal Device,
300 ... Electronic equipment, 310 ... Storage unit, 320 ... Operation unit,
350 ... Cable harness, 360 ... Cable, 370 ... USB receptacle

Claims (13)

The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and the second bus is transferred to the second physical layer. A processing circuit that performs a transfer process that transfers a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus monitor circuit that monitors the first bus and the second bus,
A bus switch circuit that turns on or off the connection between the first bus and the second bus based on the monitoring result of the bus monitor circuit.
Including
The bus switch circuit switches the connection between the first bus and the second bus from on to off, at least after the start timing of the device chirp K, or at least after the end timing of the host chirp K / J. A circuit device characterized in that a processing circuit starts the transfer processing. In claim 1,
The period during which the bus switch circuit turns on the connection between the first bus and the second bus is set as the first period, and the bus switch circuit disconnects the connection between the first bus and the second bus. If the period to be set is the second period,
The processing circuit
A circuit device characterized in that the transfer process is performed in the second period. In claim 2,
The bus monitor circuit
In the first period
The connection between the first bus and the second bus is turned on by the bus switch circuit.
In the second period
A circuit device characterized in that the connection between the first bus and the second bus is turned off by the bus switch circuit, and the transfer process is performed by the processing circuit. The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and the second bus is transferred to the second physical layer. A processing circuit that performs a transfer process that transfers a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus monitor circuit that monitors the first bus and the second bus,
A bus switch circuit that turns on or off the connection between the first bus and the second bus based on the monitoring result of the bus monitor circuit.
Including
The bus monitor circuit
In the first period
The connection between the first bus and the second bus is turned on by the bus switch circuit.
In the second period
The connection between the first bus and the second bus is turned off by the bus switch circuit, and the transfer process is performed by the processing circuit.
In the first period
The bus monitor circuit
The monitor operation is performed based on the signal from one physical layer circuit of the first physical layer circuit and the second physical layer circuit.
The first physical layer circuit and the other physical layer circuit of the second physical layer circuit are
A circuit device characterized in that it is set to operation off or power saving mode. The first physical layer circuit to which the first bus of the USB standard is connected,
A second physical layer circuit to which the second bus of the USB standard is connected, and
A packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and the second bus is transferred to the second physical layer. A processing circuit that performs a transfer process that transfers a packet received via the layer circuit to the first bus via the first physical layer circuit, and a processing circuit that performs transfer processing.
A bus monitor circuit that monitors the first bus and the second bus,
A bus switch circuit that turns on or off the connection between the first bus and the second bus based on the monitoring result of the bus monitor circuit.
Including
The bus monitor circuit
In the first period
The connection between the first bus and the second bus is turned on by the bus switch circuit.
In the second period
The connection between the first bus and the second bus is turned off by the bus switch circuit, and the transfer process is performed by the processing circuit.
A circuit device characterized in that, in the first period, the transmission circuit for the HS mode of the first physical layer circuit and the second physical layer circuit is set to the operation off or the power saving mode. In any of claims 4 to 5 ,
The bus switch circuit switches the connection between the first bus and the second bus from on to off, at least after the start timing of the device chirp K, or at least after the end timing of the host chirp K / J. A circuit device characterized in that a processing circuit starts the transfer processing. In any of claims 1 to 6 ,
When a reset or suspend is performed, the bus switch circuit switches the connection between the first bus and the second bus from off to on, and the processing circuit stops the transfer processing. Circuit equipment. In any of claims 1 to 7 ,
When the resume is performed after the suspend is performed, the bus switch circuit switches the connection between the first bus and the second bus from on to off, and the processing circuit starts the transfer processing. A circuit device characterized by that. In any of claims 1 to 8 ,
The processing circuit
A circuit device characterized in that a packet bit resynchronization process is performed in the transfer process. In any of claims 1 to 9 ,
The bus switch circuit
A circuit device characterized in that during the charge arbitration period, the connection between the third bus connected to the charging circuit and the second bus is turned on. In any of claims 1 to 10 ,
The processing circuit
A circuit device characterized in that the transfer processing is performed without changing the number of bits in the SYNC field and the number of bits in the EOP field of the packet. The circuit device according to any one of claims 1 to 11.
The processing device connected to the first bus and
An electronic device characterized by including. The circuit device according to any one of claims 1 to 11.
With the cable
A cable harness characterized by including.

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