JP6821897B2 - Alignment by physical alignment mark and virtual alignment mark - Google Patents

Description

The present invention relates to methods, computer-readable media, and programs for aligning electrical devices in process.

The product functionality of component carriers with one or more electronic components is increasing. Such electronic components are becoming smaller and smaller, and the number of electronic components to be mounted on component carriers such as printed circuit boards is increasing. In this case, increasingly powerful array components or package components with several electronic components are being adopted. Such array parts or package parts have multiple contacts or connectors. The spacing between these contacts is constantly decreasing. Removing the heat generated by such electronic components and the component carriers themselves during operation becomes an increasingly prominent problem. Also, the component carrier should be mechanically stable and electrically reliable so that it can operate in harsh conditions.

In addition, proper alignment of component carriers is a problem during manufacturing. For example, in order to pattern the layer structure of the component carrier during manufacturing, proper alignment accuracy is important when exposing the dry film. Other electrical devices have similar alignment problems.

An object of the present invention is to make it possible to process an electric device with high spatial accuracy.

To achieve the above objectives, a method of performing alignment during processing of an electrical device, a computer-readable medium, and a program unit are provided.

According to one exemplary embodiment of the invention, there is provided a method of aligning an electrical device being machined (or while the electrical device is being machined). The method involves the following steps: setting multiple physical alignment marks on an electrical device and determining multiple virtual alignment marks based on the physical alignment marks (especially using mathematical algorithms). Multiple virtual alignment marks are calculated by physical alignment marks), at least a portion of the physical alignment marks (especially multiple physical alignment marks) or at least one of the virtual alignment marks for processing electrical devices. Align using at least one of the parts (especially multiple alignment marks).

According to another exemplary embodiment of the invention, one program unit (eg, source code or executable code form software routine) is provided. This process unit is suitable for controlling or executing a method having the above characteristics when executed by a processor (for example, a microprocessor or a CPU (Central Processing Unit)).

According to yet another exemplary embodiment of the invention, a computer-readable medium (eg, CD, DVD, flash drive, floppy disk, hard drive, etc.) is provided. It contains a computer program suitable for controlling or executing a method having the above characteristics when executed by a processor (eg, microprocessor or CPU).

Data processing that can be performed according to embodiments of the present invention is performed by computer programs or software, or by using one or more dedicated electronic optimization circuits or hardware, or by hybrids or software and hardware components. it can.

In the context of this application, the term "part carrier" specifically means any support structure capable of accommodating on or within one or more parts for providing mechanical support and / or electrical connections. To do. In other words, the component carrier can be configured as a mechanical and / or electronic carrier for the component. In particular, the component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) board. The component carrier may also be a hybrid panel that combines different component carriers within the above types of component carriers.

In the context of this application, the term "physical alignment mark" may specifically mean the structural or physical characteristics of an electrical device. This structural or physical feature can be detected on or within the surface area of electrical devices, especially component carriers such as printed circuit board preforms, and can be optically inspected or visually observed. be able to. Physical alignment marks can be used as the basis for the alignments performed, especially in the machining of electrical devices by machining machines that can be spatially oriented using physical alignment marks. For example, such a physical alignment mark may be a through hole or a blind hole in an electrical device that can be optically inspected. This allows the position and / or orientation of preforms (eg, panels) of electrical devices such as component carriers to be determined. For example, as an alignment mark, a plurality of such holes may be provided in the edge region of a rectangular electrical device such as a carrier board. Also, physical alignment marks (particularly four alignment marks on the four edges of each main surface) can be provided on both of the two opposing main surfaces of the electrical device.

In the context of this application, the term "virtual alignment mark" can specifically mean a feature that is not physically present in the electrical device. This feature cannot be detected, optically inspected or visually observed on or within the surface area of electrical devices, especially component carriers such as preforms of printed circuit boards. On the other hand, the virtual alignment mark can be a calculated position on the electrical device. This position is determined by an algorithm and is used in combination with a physical alignment mark for alignment purposes when machining electrical devices.

According to an exemplary embodiment of the present invention, the combination of a physical alignment mark and a plurality of virtual alignment marks realizes an alignment of electrical devices during processing. An algorithm for the physical alignment marks can be used to determine those multiple virtual alignment marks. Therefore, the physical alignment mark can be used as a starting point for calculating the virtual alignment mark. This process has great advantages. The virtual alignment mark can be virtually placed in any desired area of the electrical device, not physically, even in a functional area where the physical alignment mark cannot be formed. Physical alignment marks in this position can reduce functionality or damage the electrical device. This significantly increases the degree of freedom of alignment based on the alignment mark, and at least a part of the alignment mark is placed in any desired position of the electrical device (eg, within the area where the component carrier such as a PCB is located). Can be done. In addition, deriving a virtual alignment mark based on the physical alignment mark, which is the starting point of the real world, determines multiple virtual alignment marks at a meaningful position regarding the alignment function for proper processing of an electric device. Allows you to.

The alignment architecture described has significant advantages. First, the combination of physical and virtual alignment marks makes it possible to follow the contours of electrical devices (especially carrier boards) in a very advantageous and very balanced way. Moreover, in particular, the plurality of virtual alignment marks can be placed anywhere in the electrical device (eg, within the PCB area of the carrier board) without affecting utilization. This is because the virtual alignment mark does not actually exist as a structural feature of the electrical device. In addition to this, the alignment architecture described can be used for array alignment with rectangular scaling (eg, with respect to the assembly process). The described ideas can be easily implemented in existing software for controlling machining (eg, laser machining, optical machining and machining) in an efficient and accurate manner. By using one or more virtual alignment marks other than the physical alignment marks, alignment can be achieved quickly and easily in just one step (especially than when using the idea of repeating in one step). Is also fast). In addition, the described physical and virtual alignment mark arrays compensate for changes in the height of electrical devices, especially varying height panels, highly warped panels, or other electrical devices. To enable. Moreover, optimized carrier utilization can be achieved instead of inserting the actual alignment sample. This process is very fast as it can be achieved by detecting a small number of physical alignment points in just one step. Considering the multiple virtual alignment marks described, a very accurate alignment process can be guaranteed. Capacity can be saved for other processes (eg, X-ray, laser and optical processes). Therefore, both high accuracy and high carrier board utilization rate can be achieved at the same time. Compared to the actual target or physical alignment mark, the additionally used virtual alignment mark is for forming an active region in an electrical device (eg, a printed circuit board which is an example of a carrier board of an electrical device). It does not reach the surface loss.

The following describes further exemplary embodiments of methods, computer-readable media, and program units.

In a preferred embodiment, a shape function is used to perform a virtual alignment mark determination based on a physical alignment mark. In particular, the physical alignment marks can be placed along the outer frame of the rectangular electrical device. You can use shape functions to find and derive virtual alignment marks within a frame. In this case, the shape function may be a mathematical formula that is useful for interpolating anywhere without points to define a grid of alignment marks. The idea of calculating the device's internal virtual alignment mark based on the device's external physical alignment mark by using a shape function is powerful, fast and accurate to achieve the alignment for machining electrical devices. Proven to be a tool.

For example, the calculation of the virtual alignment mark inside the outer circumference can be performed based on the following formula. The perimeter is defined by multiple physical alignment marks using shape functions.

In the above equation, U and V are the coordinates of arbitrary points (x, y) on and inside the electrical device. Also, U _i and V _i are the coordinates of the physical alignment mark deformed. Shape function _N i (x, y) is expressed as.

In one embodiment, at least some, especially all, of the physical alignment marks are placed within (and away from) the inactive region of the electrical device. The "inactive region" can be a range of functional elements in the electrical device that do not contain the electrical device. Correspondingly, the "active region" can be the range of functional elements in the electrical device that house the electrical device. In the example of the carrier board for manufacturing a batch of component carriers, the carrier board region in which the component carriers are arranged is the active region, and the region not including the component carriers is the inactive region. Therefore, the physical alignment mark can be located outside the active region (eg, PCB) of the electrical device (eg, carrier board). This avoids the undesired effect of the presence of physical alignment marks on the function or capacity of the electrical device.

In one embodiment, at least a portion, especially all, of the physical alignment marks are located along the edges (particularly the periphery) of the electrical device and away from the central portion. In other words, the frame area or outer area extending along the edge of the electrical device can be provided with a plurality of physical alignment marks. In view of many cases, the physical alignment mark does not disturb the edge or frame region, given the fact that such an edge or frame region has no active region.

In one embodiment, at least a portion, in particular the entire, virtual alignment mark is placed within (and away from) the active region of the electrical device. Virtual alignment marks are virtually non-existent and are only used as virtual or mathematical data units to align electrical devices and correspondingly control the device's processing machines. Can be placed anywhere on the electrical device. The physical alignment mark is preferably placed in a functionally active area of the electrical device so as not to interfere with the function of the electrical device. On the other hand, in the case of virtual alignment mark, it is not necessary to consider this limitation.

In one embodiment, at least part of the virtual alignment mark, especially all of it, is located in the central region of the electrical device and away from the periphery. Therefore, the virtual alignment mark can appear properly, especially in the central region of the electrical device. This central region is often the region for functionally active structures such as printed circuit boards (PCBs) in the case of carrier board electrical devices. Therefore, high precision alignment of such active regions is achieved without losing the area of the functionally active structure or interfering with the functionally active structure by providing a physical alignment mark in such a central region. can do.

In one embodiment, the virtual alignment marks are placed on the electrical device in a matrix pattern, especially to define a rectangle. Each rectangle encloses the corresponding active region of the electrical device. At least a portion of the rectangle can be defined by four virtual alignment marks located at each of the four corners of the rectangle. In other words, the electrical device is divided into multiple compartments so that each compartment contains one active region of the electrical device, in particular an array of component carriers such as PCBs on a carrier board. Therefore, very preferably, a plurality of virtual alignment marks can be placed around the circumference of each active region, for example, at the four corners of a rectangular active region. The corresponding array alignment has the advantage of high capacity. This is because the active region can be aligned by a virtual alignment mark that is optionally combined with one or more physical alignment marks arranged around the outer circumference of the electrical device only within the active region.

In one embodiment, the method comprises dividing the electrical device into multiple compartments. The division is performed by determining at least one dividing line, in particular at least two orthogonal dividing lines. At least one dividing line is determined to extend outside the active region of the electrical device. By preventing the dividing line from extending through the functional area of the electrical device (eg, the PCB array on the carrier board), the function of the functional area of the electrical device is not affected by the alignment process.

In one embodiment, processing each compartment is associated with at least one physical alignment mark or at least one virtual associated with each compartment (particularly spatially related or spatially located therein). Performed using at least one of the target alignment marks. For example, the outer edge compartment of an electrical device can be aligned based on multiple physical alignment marks and at least one virtual alignment mark.

In one embodiment, at least one partition is aligned based only on the corresponding virtual alignment mark during processing. Thus, the internal compartments of an electrical device can be aligned based on more virtual alignment marks than physical alignment marks, especially based solely on virtual alignment marks.

In one embodiment, the processing of the electrical device is performed by performing the alignment using more virtual alignment marks than the physical alignment marks, especially by performing the alignment using only the virtual alignment marks. To. By taking this measure, the number of physical alignment marks required can be kept very low. This reduces the potential impact of physical alignment marks on the capacity of electrical devices. For example, there are no undue limits for the manufacture of the maximum number of component carriers.

In one embodiment, the determination of the virtual alignment mark based on the physical alignment mark is performed so that the gap or distance between the physical alignment marks is filled with the virtual alignment mark by insertion. Therefore, for example, evenly spaced virtual alignment marks (or evenly spaced physical alignment marks and virtual alignment marks) are formed. The set of virtual alignment marks forms a regular shape, such as a rectangle, or meets any other symmetry criterion.

In one embodiment, the electrical device is selected from the group consisting of carrier boards for manufacturing component carriers, wafers, and components machined by pick-and-place equipment. In the most preferred embodiment, the PCB carrier board can be processed with the idea of a physical alignment mark combined with one or more virtual alignment marks described. After that, the tendency of frequent warpage and deformation of the carrier board can be solved by properly combining the physical alignment mark and the virtual alignment mark. However, the alignment process described herein can also be advantageously applied to semiconductor wafers separated or fragmented into individual electronic chips. High accuracy is also advantageous for this method, which can be obtained by a combination of virtual and physical alignment marks. In yet another embodiment, the surface mount components are aligned and can be electrical devices in another embodiment of the invention. Such parts can be machined by pick-and-place equipment so that the location and orientation of such electrical devices can be accurately determined. The combination of physical alignment marks and virtual alignment marks is also an advantageous solution to the tasks described above. This virtual alignment mark is derived based on the physical alignment mark.

In one embodiment, processing the electrical device comprises at least one of a group consisting of image formation (particularly optical imaging), welding mask processing, screen printing, and mechanical processing of the electrical device (particularly during the assembly process). .. These and other processes require precise alignment of the electrical devices to be machined.

In one embodiment, the physical alignment marks are holes (such as blind holes and via holes), pads (consisting of a conductive material surrounded by other materials such as dielectrics), skiving marks, and corners. (For example, those of rectangular electrical devices), and can be laser targets. Typically, the physical alignment mark can be any reference point, i.e. any object located within the field of view of the imaging system. This object is displayed in the resulting image for use as a reference point or measurement. It can be any object placed in or on top of the imaged object. This physical alignment mark can be used to adjust the processing equipment to the electrical device to be processed.

The one or more parts may be surface mounted and / or embedded in and / or on the part carrier or its preform. At least one component is selected from the group consisting of non-conductive inlays, conductive inlays (such as metal inlays, preferably containing copper or aluminum), heat transfer units (such as heat pipes), electronic components, or combinations thereof. Can be done. For example, components include active electronic components, passive electronic components, electronic chips, storage devices (eg, DRAM or other data storage devices), filters, integrated circuits, signal processing components, power management components, optoelectronic interface components, voltage conversion ( Examples: DC / DC converters or AC / DC converters), encryption components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), micromachines, capacitors, resistors, inductors, batteries, It may be a switch, a camera, an antenna, a logic chip and an environmental power generation unit. However, other components can also be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnet element (eg, a ferromagnetic element, an antiferromagnetic element, or a ferrimagnetic element such as a ferrite-based structure), or may be a paramagnetic element. However, the component may be another component carrier, such as a panel configuration within a panel. The component may be surface mounted on the component carrier and / or embedded within the component carrier.

In one embodiment, the component carrier or preform thereof comprises a laminate of at least one electrically insulating layer structure and at least one conductive layer structure. For example, in the component carrier, the laminate of the electrically insulating layer structure and the conductive layer structure is formed particularly by applying mechanical pressure, and if desired, the forming process is supported by thermal energy. The laminate can provide a large mounting surface for other parts, but can nevertheless provide a plate-shaped part carrier that is very thin and compact. The term "layer structure" may specifically mean a continuous layer, a patterned layer, or multiple discontinuous islands in a common plane.

In one embodiment, the component carrier or preform thereof is formed as a panel. This facilitates compact designs where component carriers still provide large boards for mounting components. Further, since the bare wafer is thin, it is convenient to embed the bare wafer in a thin plate member such as a printed circuit board, as an example of an embedded electronic component.

In one embodiment, the component carrier being manufactured is configured as one of a group consisting of a printed circuit board (PCB) and a board (particularly an IC board).

In the context of this application, the term "printed circuit board" (PCB) specifically refers to a component carrier formed by laminating several conductive layer structures and several electrically insulating layer structures, which are plate-like (ie, planar). ), A three-dimensional curved surface (eg when manufactured using 3D printing), or it may have any other shape. The forming step is formed, for example, by applying pressure while supplying thermal energy as needed. As a preferred material for PCB technology, the conductive layer structure is made of copper. The electrically insulating layer structure may include resin and / or glass fiber, a so-called prepreg or FR4 material. A via hole as a via connector is formed by forming a through hole penetrating the laminate (for example, by laser perforation or mechanical perforation) and filling the through hole with a conductive material, particularly copper. The individual conductive layer structures can be connected to each other in any way. Except for one or more components that can be embedded in a printed circuit board, a printed circuit board is typically configured to accommodate one or more components on one or both opposite surfaces of a panel-shaped printed circuit board. .. They can be joined to the corresponding main surface by welding. The dielectric portion of the PCB can be made of a resin having reinforcing fibers such as glass fibers.

In the context of this application, the term "board" may specifically mean a widget carrier that has substantially the same dimensions as the components (especially electronic components) to be mounted on it. More specifically, the substrate is a carrier for an electrical connector or electrical network, and a component carrier that corresponds to a printed circuit board (PCB), but with a relatively high density of horizontal and / or vertical arrangements. Can be understood as a connector. The horizontal connector is, for example, a conductive path, and the vertical connector is, for example, a drill hole. These horizontal and / or vertical connectors are arranged within the substrate, for example, electrical connection and / or machine between a contained or uncontained component of an IC chip (eg, a bare wafer) and a printed circuit board or intermediate printed circuit board. Can be used to provide a connection. Therefore, the term "board" also includes "IC board". The dielectric portion of the substrate can be made of a resin having a reinforcing sphere such as a glass sphere.

In one embodiment, the at least one electrically insulating layer structure is a resin (reinforced or non-reinforced resin such as epoxy or bismaleimide-triazine resin, more specifically such as FR-4 or FR-5), cyanate ester, polyphenylene. Derivatives (polyphenylene sulfide), glass (especially glass fiber, multi-layer glass, glass material), prepreg material, polyimide, polyamide, liquid crystal polymer (LCP), epoxy-based build-up film (epoxy-based Built-Up Film), poly Includes at least one of the group consisting of tetrafluoroethylene (Teflon®), ceramics, and metal oxides. For example, reinforcing materials such as meshes, fibers or spheres made of glass (multilayer glass) can also be used. Prepreg or FR4 is generally preferred, but other materials may be used. For high frequency applications, high frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins can be implemented as an electrically insulating layer structure within the component carrier.

In one embodiment, the at least one conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten. Copper is generally preferred, but other materials or their coating forms, especially those coated with superconducting materials such as graphene, are also possible.

In one embodiment, the component carrier being manufactured is a laminated component carrier. In such an embodiment, the component carrier is a composite of multiple layers that are stacked and joined together by applying compressive forces while applying heat as needed.

The above and other aspects of the invention will become apparent from the examples of embodiments described below. The above aspects and other aspects of the present invention will then be described with reference to examples of these embodiments.
FIG. 1 shows a plan view of an electric device configured as a carrier board according to an exemplary embodiment of the present invention. This carrier board is used in the manufacture of component carriers. The plan view then shows the physical alignment marks and virtual environment marks obtained during the implementation of the method of aligning electrical devices during machining. FIG. 2 shows a plan view of an electrical device undergoing an alignment method during processing. FIG. 3 shows the idea of a shape function for deriving at least one virtual alignment mark based on a physical alignment mark, which is carried out according to an exemplary embodiment of the present invention. FIG. 4 shows the idea of a shape function for deriving at least one virtual alignment mark based on a physical alignment mark, which is carried out according to an exemplary embodiment of the present invention. FIG. 5 shows the idea of a shape function for deriving at least one virtual alignment mark based on a physical alignment mark, which is carried out according to an exemplary embodiment of the present invention.

The contents illustrated are schematic, and similar or identical elements are given the same reference numerals in different figures.

Before the exemplary embodiments are described in more detail with reference to the drawings, some basic considerations under which the exemplary embodiments of the present invention are developed will be outlined.

According to an exemplary embodiment of the invention, an electrical device alignment during machining using one or more physical alignment marks and / or one or more virtual alignment marks derived from the physical alignment marks. Can be carried out. In a preferred embodiment, the electrical device (such as a carrier board used in the manufacture of printed circuit boards) can also be divided into multiple compartments. Then, it is preferable to perform alignment in the partition layer by using the shape function and the virtual alignment point.

Moreover, the exemplary embodiment of the present invention can overcome the limitations of existing alignment methods. In fact, according to the method of the exemplary embodiment, the use of multiple compartments allows for higher accuracy than the global alignment method. And by using virtual internal points according to exemplary embodiments, faster speeds and better carrier board utilization than local alignment and purely real division methods are possible.

More specifically, the alignment method according to an exemplary embodiment of the present invention uses a plurality of points as physical alignment marks within a circumferential frame (particularly a carrier board frame) of an electrical device. This physical alignment mark is obtained by shooting with a mechanical camera. Based on these physical alignment marks, a plurality of virtual internal points are calculated as virtual alignment marks used for partition alignment. For example, even a small number of points can be calculated by a highly accurate shape function. In the case of four compartments, the center point can be calculated using, for example, other geometric methods.

Therefore, the actual mark on the electrical device can be used as a physical alignment mark obtained by shooting with a mechanical camera. Virtual alignment marks, on the other hand, do not exist as structural features on electrical devices and can be calculated by software or other computational resources. Then, for example, every four points can be used for scaling compartments or the arrays they form.

Functions that can be very advantageously used in this process is the shape function N _i. These shape functions allow each central point of an electrical device (eg, carrier board) to follow the same shape (especially linear or non-linear) as the frame, including both scaling and rotation.

The method according to an exemplary embodiment of the present invention can provide an accurate alignment of electrical equipment without the need for actual internal points. That is, no physical alignment mark is required in the active region of the electrical device. This method provides very high accuracy, especially higher than global alignment. Moreover, this method is very fast, especially faster than local alignments. In addition to this, efficient use of electrical devices can be achieved, especially with respect to better PCB-type carrier board utilization compared to compartments based solely on practice. Also, exemplary embodiments of the invention can be readily implemented in all alignment software for each device. It is very advantageous that the exemplary embodiments of the present invention can reduce waste due to poor alignment and improve alignment.

FIG. 1 shows a plan view of an electrical device 100 configured as a carrier board (eg, in a size of 24 x 18 square inches) according to an exemplary embodiment of the invention. This carrier board is used to manufacture component carriers such as printed circuit boards (PCBs). In this embodiment, the electrical device 100 has 22 physical alignment marks 102 and 20 virtual alignment marks 104. These physical alignment marks and virtual alignment marks are obtained during the implementation of the method of aligning the electrical device 100 during machining.

For example, it can happen that the PCB carrier board forming the electrical device 100 should be subjected to a welding mask process. For this purpose, it is very important that the machine performing the task of the welding mask knows exactly the current position of the electrical device 100 and its orientation, and as a result, the machining becomes very accurate. obtain. To achieve such an accurate alignment, exemplary embodiments of the invention use a plurality of physical alignment marks 102, which are structural features on the surface of the electrical device 100 that can be detected by a camera or the like. To do. For example, the physical alignment mark 102 located along the perimeter of a substantially rectangular electrical device 100 is a copper brazed pad or a laser hole. Therefore, the actual or physical alignment mark 102 can be detected by the optical measurement of the above camera or the like.

Thus, in a first process describing how to process (or in between) the electrical device 100, a plurality of (22, but other quantities are possible) physical alignment marks 102 are optically formed on the electrical device 100. Is detected. The corresponding image can undergo image processing. During this image processing, the position (particularly coordinates) of the physical alignment mark 102 is determined by a processor (not shown) and stored in a large-capacity storage device (hard disk or the like). As can be seen from FIG. 1, all physical alignment marks 102 can be placed away from the central region 112. The central region 112 accommodates a plurality of active regions of the electrical device 100 (see reference numeral 110 in FIG. 2). These active regions 110 of the electrical device 100 correspond to regions of the carrier board on which the printed circuit board is formed. In other words, each of the active regions 110 can be, for example, a printed circuit board or a printed circuit board array. By placing the physical alignment mark 102 away from the active region 110 and thus outside the printed circuit board, it is possible to perform the alignment process without undesirably affecting the capacitance of the printed circuit board. Become.

As can be seen from FIG. 1, in this case, the electrical device 100 is aligned during machining by using only 22 physical alignment marks 102. The internal or central region 112 of the electrical device 100 is not considered. For the above reasons, all the physical alignment marks 102 are aligned along the outer circumference or the edge 108 of the electrical device 100.

To overcome this limitation, exemplary embodiments of the invention, in addition to (or even replace) the physical alignment mark 102 described above, are used to align the electrical device 100 during machining. Determine the virtual alignment mark 104. It is very advantageous to calculate the virtual alignment mark 104 based on the defined physical alignment mark 102. In other words, the physical alignment mark 102 is used as the basis for calculating the position of the virtual alignment mark 104. This virtual alignment mark is for aligning the electrical device 100 in addition to (or even replacing) the physical alignment mark 102 during machining. Various alternatives for determining the virtual alignment mark 104 based on the physical alignment mark 102 can be applied. Advantageously, the shape function can be used to determine the virtual alignment mark 104.

U and V are the coordinates of arbitrary points (x, y) in the electrical device 100. _Also, U i, _{V i} are the coordinates of the physical alignment mark 102. Shape _function, N i _(x, y) is expressed as.

Therefore, the mathematical process of determining the virtual alignment mark 104 based on the previously detected and defined physical alignment mark 102 is performed using a shape function.

All physical alignment marks 102 are located along the edge 108 so that they are located in the inactive region of the electrical device 100 (see reference numeral 106 in FIG. 2). All virtual alignment marks 104 are located in the central region 112 (corresponding to the active region shown in FIG. 2) of the electrical device 100.

The physical alignment marks 102 are arranged in a ring shape. The virtual alignment marks 104 are arranged in a matrix on the electrical device 100, and all are arranged within the loop of the physical alignment marks 102.

The resulting array of physical alignment marks 102 and virtual alignment marks 104 can then be used as a source for alignment when machining the electrical device 100 by welding masking. For this purpose, for example, more virtual alignment marks 104 can be used than physical alignment marks 102. It is even possible to use only the virtual alignment mark 104 for alignment. Preferably, after the virtual alignment mark 104 is determined, the alignment can be performed partially using the physical alignment mark 102 and partially using the virtual alignment mark 104. The electrical device 100 is machined by a welding mask process.

FIG. 1 also shows that the electrical device 100 can be divided into a plurality of compartments 114. A separate and appropriate set of alignment marks 102, 104 can be selected to machine the corresponding compartment 114. For example, for the upper left section 114 of FIG. 1, three closest physical alignment marks 102 and one closest virtual alignment mark 104 can be used for alignment. For the compartment 114 that is directly horizontally adjacent to the compartment 114, the two closest physical alignment marks 102 and the two closest virtual alignment marks 104 can be used for alignment. For each of the internal compartments 114, the corresponding four closest virtual alignment marks 104 can be used for alignment.

In FIG. 1, all alignment marks 102, 104 are evenly spaced from their respective horizontal and vertical adjacent marks. Therefore, the alignment marks 102, 104 form a matrix array with rows and columns. The matrix array consists of a smaller central matrix array at the virtual alignment mark 104. This central matrix array is surrounded by an annular array of physical alignment marks 102.

FIG. 2 shows a plan view of an electrical device 100 that often uses methods for alignment during machining.

According to the embodiment of FIG. 2, a rectangular matrix arrangement is formed. Each rectangle surrounds each active region 110 of the electrical device 100. Further, the electric device 100 is divided into a plurality of compartments 114 arranged in rows and columns. Each of the rectangles corresponds to one of the compartments 114 and is defined by four virtual alignment marks 104 located at the four corners of the corresponding rectangle or compartment 114. The inactive region 106 is located within the peripheral edge 108 and within the intersecting horizontal and vertical channels defined by the regions between adjacent rectangles or compartments 114. Machining of each compartment 114 is performed using only the four closest virtual alignment marks 104 associated with each compartment 114. In other words, all compartments 114 shown in FIG. 2 are aligned based only on their respective virtual alignment marks 104 during machining. In FIG. 2, not all alignment marks 102, 104 are evenly spaced from their respective horizontal and vertical adjacent marks.

3 to 5 show the idea of a shape function for deriving at least one virtual alignment mark 104 based on the physical alignment mark 102, which is carried out according to an exemplary embodiment of the present invention.

FIG. 3 shows an embodiment of eight points 1, 2, 3 ... 8 on the corners and edges of a rectangle. When the idea of the shape function is applied in this embodiment, the following results are obtained.

Descriptively, the idea of a shape function is to apply the transformation of an element in real space to the space that normalizes the element.

The latter is shown in FIGS. 4 and 5. Among them, the elements from the actual space (see FIG. 4) are transformed for normalization (see FIG. 5).

Note that the term "contains" does not exclude other elements or steps, and the term "one" or "one" does not exclude more than one. The elements described in relation to different embodiments can also be combined.

It should also be noted that the reference numerals in the claims should not be construed as limiting the scope of the claims.

The practice of the present invention is not limited to the preferred embodiments shown in the drawings and described above. On the contrary, even in the case of radically different embodiments, various modifications can be made according to the principles of the present invention using the illustrated embodiments .
[Item 1]
A method of alignment in the processing of electrical devices
Set multiple physical alignment marks on the above electrical device
Determine multiple virtual alignment marks based on the above physical alignment marks,
Aligning is performed using at least a part of the physical alignment mark or at least one part of the virtual alignment mark in order to process the electric device.
How to include that.
[Item 2]
The method according to item 1, wherein the virtual alignment mark is determined based on the physical alignment mark by using a shape function.
[Item 3]
The shape function is used to determine the virtual alignment mark based on the physical alignment mark according to the following equation.
[Number 1]
Here, U and V are the coordinates of the point on the electrical devices (x, y), U _i and V _i are the coordinates of the physical alignment mark, N i _(x, y) is the shape function The method according to item 2.
[Item 4]
The method according to any one of items 1 to 3, wherein at least a part, particularly all of the physical alignment marks are located in the inactive region of the electrical device.
[Item 5]
The method according to any one of items 1 to 4, wherein at least a part, particularly all of the physical alignment marks are arranged along the edge, particularly the periphery of the electrical device.
[Item 6]
The method according to any one of items 1 to 5, wherein at least a part, particularly all of the virtual alignment marks are located within the active region of the electrical device.
[Item 7]
The method according to any one of items 1 to 6, wherein at least a part, particularly all of the virtual alignment marks, are located in the central region of the electrical device.
[Item 8]
The virtual alignment marks are arranged in a matrix pattern on the electrical device and are used specifically to define a rectangle, each of which surrounds each active region of the electrical device, items 1- The method according to any one of 7.
[Item 9]
Divide the above electrical device into multiple compartments
Process each corresponding compartment using at least one of the relevant physical alignment marks or at least one of the at least one virtual alignment mark associated with each compartment.
The method according to any one of items 1 to 8, including the above.
[Item 10]
9. The method of item 9, wherein at least one of the compartments is aligned so that it is processed, based only on the corresponding virtual alignment mark.
[Item 11]
Alignment is performed using the virtual alignment marks more than the physical alignment marks, and in particular, alignment is performed using only the virtual alignment marks, as in the processing of the electric device, item 1. The method according to any one of 10 to 10.
[Item 12]
The method according to any one of items 1 to 11, wherein the electrical device is selected from the group consisting of panels for manufacturing component carriers, wafers, and components machined by a pick-and-place device.
[Item 13]
Machining the electrical device means forming an image, especially optical imaging, welding masking, screen printing, and mechanically processing the electrical device, especially during the assembly process. The method according to any one of items 1 to 12, which comprises at least one of a group consisting of mechanical processing.
[Item 14]
The method according to any one of items 1 to 13, wherein the physical alignment mark is selected from the group consisting of holes, solder pads, cut marks, corners, and laser targets.
[Item 15]
A computer-readable medium that stores computer programs that align in the processing of electrical devices.
A computer-readable medium configured to perform or control the method according to any one of items 1-14 when the computer program is executed by one or more processors.
[Item 16]
A program that aligns in the processing of electrical devices
A program configured to perform or control the method according to any one of items 1-14 when the program is executed by one or more processors.

Claims (15)

A method of alignment in the processing of electrical devices
Set multiple physical alignment marks on the electrical device
Determining a plurality of virtual alignment mark based on the previous SL plurality of physical alignment mark,
To process said electrical device performs alignment using at least one of the at least part of or prior SL multiple virtual alignment mark before Symbol plurality of physical alignment mark,
Including that
At least a portion of the plurality of virtual alignment marks is located within the central region of the electrical device.
METHODS. A method of alignment in the processing of electrical devices
Set multiple physical alignment marks on the electrical device
A plurality of virtual alignment marks are determined based on the plurality of physical alignment marks, and a plurality of virtual alignment marks are determined.
Aligning is performed using at least a portion of the plurality of physical alignment marks or at least one portion of the plurality of virtual alignment marks in order to process the electrical device.
Including that
At least a portion of the plurality of virtual alignment marks is located within the active region of the electrical device.
Method. A method of alignment in the processing of electrical devices
Set multiple physical alignment marks on the electrical device
A plurality of virtual alignment marks are determined based on the plurality of physical alignment marks, and a plurality of virtual alignment marks are determined.
Aligning is performed using at least a portion of the plurality of physical alignment marks or at least one portion of the plurality of virtual alignment marks in order to process the electrical device.
Including that
The plurality of virtual alignment marks are arranged in a matrix pattern on the electrical device and are used to define a rectangle, each of which surrounds the respective active region of the electrical device.
Method. Using the shape function, before SL based on the plurality of physical alignment mark, determining a previous SL multiple virtual alignment marks A method according to any one of claims 1 to 3. The shape function is used to determine the virtual alignment mark before Symbol of the plurality based on the previous SL plurality of physical alignment marks according to the following equation,
Here, U and V are the coordinates of the point on the electrical devices (x, y), a _{U i} and _{V i} are pre SL plurality of physical alignment mark _coordinate, N i _(x, y) The method according to claim 4 , wherein is a shape function. At least part of the previous SL plurality of physical alignment marks, in particular all, located in the non-active area of the electrical device, the method according to any one of claims 1-5. Before SL least some of the plurality of physical alignment marks, in particular all edges of the electrical device are arranged in particular along the peripheral edge, the method according to any one of claims 1 to 6 .. The electrical device is divided into a plurality of compartments and
At least That other of said plurality of physical alignment mark that are related in correspondence to each ward image using one even without least of the at least one of said plurality of virtual alignment mark, respectively The method according to any one of claims 1 to 7 , which comprises processing the corresponding section of the above. As processed, based only on the virtual alignment mark before Symbol a plurality of corresponding, to the alignment of at least one of the previous SL plurality of wards image The method of claim 8. To implement the processing of the electrical device, before SL performs alignment using many prior SL multiple virtual alignment marks than the plurality of physical alignment mark, in particular before SL multiple virtual alignment The method according to any one of claims 1 to 9 , wherein the alignment is performed using only the mark. The method according to any one of claims 1 to 10, wherein the electrical device is selected from the group consisting of panels for manufacturing component carriers, wafers, and components machined by a pick-and-place device. Machining the electrical device means forming an image, especially optical imaging, welding masking, screen printing, and mechanically processing the electrical device, especially during the assembly process. The method according to any one of claims 1 to 11 , which comprises at least one of a group consisting of mechanical processing. Before SL plurality of physical alignment marks, holes, solder pads, incision marks, corners, and is selected from the group consisting of laser target, The method according to any one of claims 1 to 12. A computer-readable medium that stores computer programs that align in the processing of electrical devices.
When said computer program is executed by one or more processors configured to perform or control a method according to any one of claims 1 or et 13, computer-readable media. A program that aligns in the processing of electrical devices
Wherein when the program is executed by one or more processors configured to perform or control a method according to any one of claims 1 or et 13, program.