JP6724687B2 - Nanorod forming method and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method for forming a nanorod and a method for manufacturing a semiconductor device.

In the field of semiconductor elements such as electronic devices and optical devices, excellent elements have been realized by the development of semiconductor materials such as nitride semiconductors and the progress of manufacturing technology. In recent years, for example, efforts have been made to further reduce the size and increase the efficiency by improving the internal quantum efficiency by utilizing the quantum confinement effect and the strain relaxation effect by utilizing nanorods having a diameter or width of 100 nm or less.

Methods for forming the nanorods are roughly classified into a bottom-up type by crystal growth and a top-down type by etching. Patent Document 1 discloses a bottom-up type nanorod forming method for forming a nanorod made of GaN. The method for forming nanorods in Patent Document 1 is to grow GaN upward while suppressing lateral growth by adjusting crystal growth conditions such as temperature, pressure, and flow rates of Ga and N precursors. Further, Patent Document 2 discloses a top-down type nanorod forming method for forming a nanorod made of a nitride semiconductor. The method for forming nanorods of Patent Document 2 is a method of forming a nanorod made of a nitride semiconductor by forming a mask on the nitride semiconductor layer in an island shape and removing the nitride semiconductor between the masks. is there. In the method of forming nanorods of Patent Document 2, the nitride semiconductor mask has a two-layer structure of nickel and silicon oxide.

Special table 2008-544567 Special table 2014-509075

However, the bottom-up method using crystal growth has a problem that the shape of the nanorods formed is not stable due to fluctuations or variations in the setting of crystal growth conditions.
Further, the bottom-up type method by crystal growth is difficult to mass-produce because it is difficult to control the shape.

As a top-down method by etching, for example, as described in Patent Document 2, there is a method of forming a mask pattern corresponding to a nanorod shape in, for example, two layers. In this method, in order to pattern the first mask in a minute size, a metal layer which is automatically formed in a minute size by annealing is used as the second mask. However, such a method has a problem that the number of steps such as annealing, etching, and mask removal is large, so that it cannot be manufactured at low cost.
Further, the size of the nanorods described in Patent Document 2 is 100 to 1000 nm in diameter, and there is a problem that it is not easy to form nanorods having a small diameter.

Therefore, it is an object of the present invention to provide a nanorod forming method capable of forming a nanorod by controlling the shape in a simple process, and a semiconductor element manufacturing method using the nanorod forming method.

The method for forming nanorods according to the present invention is a method for forming semiconductor nanorods by dry etching using a reaction gas, wherein the etching rate by the chemical reaction with the reaction gas during dry etching is the semiconductor A preparatory step of setting a mask material made of a lower material and a substrate containing the semiconductor in a chamber, and the mask material scattered by etching adheres to the surface of the semiconductor with a predetermined dot density and a predetermined dot size. By setting the pressure in the chamber within a predetermined range as described above, a plurality of dot masks each containing the mask material are formed on the surface of the semiconductor, and the semiconductor exposed from the dot mask is removed by dry etching. A dry etching step.

According to the method for forming nanorods of the present invention, it is possible to form the nanorods by controlling the shape in a simple process.

It is a schematic diagram which shows the structure of the dry etching apparatus which enforces the semiconductor nanorod formation method of Embodiment 1 which concerns on this invention. FIG. 6 is a schematic cross-sectional view of a semiconductor element of Embodiment 3 according to the present invention. It is a typical sectional view which expands and shows a part of Drawing 2. FIG. 11 is a cross-sectional view showing a step of forming an active layer including nanorods in the semiconductor device of Embodiment 3. It is a schematic cross section of a semiconductor device of embodiment 4 concerning the present invention. FIG. 11 is a cross-sectional view showing a step of forming an active layer including nanorods including an n-side semiconductor rod portion, an active layer rod portion and a p-side semiconductor rod portion in the semiconductor device of Embodiment 3; It is a schematic cross section of a semiconductor device of embodiment 4 concerning the present invention. 3 is a photograph of the nanorods of Example 1 formed by setting the pressure during dry etching to 4 Pa. 9 is a photograph of the nanorods of Example 3 formed by setting the pressure during dry etching to 8 Pa. 9 is a photograph of the nanorods of Example 4 formed by setting the pressure during dry etching to 1 Pa. 7 is a photograph of the nanorods of Example 5 formed on the -C plane of the GaN substrate. 5 is a photograph of Comparative Example 1 in which a semiconductor wafer is set on a wafer table made of quartz and formation of nanorods is tried. 5 is a graph showing PL intensities before and after washing with nitric acid for the nanorods of Example 2.

The inventor of the present application has found that it is possible to form a mask on a semiconductor in a series of dry etching steps under a predetermined dry etching condition and etch the semiconductor using the mask. Further, as a result of diligent studies, the inventors of the present application have found that when the conditions during dry etching, particularly the pressure is changed, the shape of the nanorods can be changed according to the pressure value, and further the formation density of the nanorods changes. ..

The reason why the above phenomenon occurs is considered as follows.
First, under certain specific conditions, in the initial stage of dry etching, the chemical reaction between the reaction gas and the semiconductor is suppressed because the temperature of the semiconductor surface is low. As a result, in the initial stage of dry etching, the etching rate based on the chemical reaction is low, and the reaction products due to the chemical reaction between the reaction gas and the semiconductor are small. On the other hand, at the initial stage of dry etching, the number of collisions between the reaction gas particles in the plasma and the scattering objects is reduced due to the decrease in the scattering products such as reaction products, and the average freeness of the reaction gas particles is reduced. The journey becomes longer. As a result, the reaction gas in the plasma irradiates the semiconductor and the mask material while maintaining high kinetic energy, and physical etching proceeds. Therefore, in the initial stage of dry etching, physical etching becomes relatively active, and the mask material scattered by the physical etching adheres to the semiconductor surface to form a mask.

As the etching progresses, the temperature of the semiconductor rises due to the heat generated by the chemical reaction between the reaction gas and the semiconductor, and the etching rate due to the chemical reaction between the reaction gas and the semiconductor increases, as well as the reaction products associated with the chemical reaction. The amount of scattered material increases. On the other hand, when the amount of scattered products such as reaction products increases, the number of collisions between the particles of the reaction gas and the scattered particles increases, the mean free path of the particles of the reaction gas shortens, and the physical etching rate decreases. Therefore, at this stage, the etching due to the chemical reaction between the reaction gas and the semiconductor becomes dominant, and the mask material adhering to the semiconductor surface serves as a mask to remove the semiconductor except under the mask to form nanorods. It

According to the above consideration, in order to attach the masking material to the semiconductor surface in a dot shape as a nano-sized mask, the masking material is formed by physical etching into particles with a size of, for example, 10 nm to 200 nm. A material that scatters is good. On the other hand, it is necessary to function as a mask when the semiconductor is dry-etched by the reaction gas based on a chemical reaction. Therefore, the material for the mask needs to have an etching rate lower than that of the semiconductor based on the chemical reaction with the reaction gas. A material in which a chemical reaction by a reactive gas does not substantially occur, such as a mask remaining on the semiconductor surface after etching is more suitable.

The present invention has been made based on the above-mentioned findings uniquely obtained by the present inventor, and includes the following modes.

Embodiment 1.
The method for forming a semiconductor nanorod according to the first embodiment of the present invention forms a dot-shaped mask (dot mask) in the dry etching process without changing the initially set dry etching condition, and uses the mask. The semiconductor layer is etched to form nanorods. The method for forming a semiconductor nanorod according to the first embodiment can be performed using a general dry etching apparatus schematically shown in FIG. 1, and since it is not necessary to separately form a mask, the semiconductor nanorod can be manufactured at a low cost. It can be easily formed.
The dry etching apparatus 10 shown in FIG. 1 includes a chamber 12 in which an upper electrode 13, a lower electrode 15 and a wafer table 17 are provided, and a high frequency power source 19. The substrate 11 is placed on the wafer table 17. Placed.

Hereinafter, the method for forming the semiconductor nanorods according to the first embodiment will be described in detail.
The method for forming semiconductor nanorods according to the first embodiment includes the following steps.

Preparation Step Here, a mask material and a base body including a semiconductor (semiconductor layer) that becomes nanorods after etching are set in a chamber. Here, as the material for the mask, a material that can be physically etched and has an etching rate lower than that of the semiconductor by a chemical reaction with a reaction gas during dry etching is selected. It is preferable to select a material for the mask that hardly chemically reacts with a reaction gas generally used for dry etching of semiconductor materials. Materials that hardly chemically react with the reaction gas used for dry etching of semiconductor materials include yttria and zirconia. The mask material may be mounted around the base on the wafer table 17 on which the base is mounted, or the wafer table 17 itself may be made of the mask material. That is, a tray such as the wafer table 17 may be used as the supply source of the mask material. This eliminates the need to separately arrange the mask material in the chamber of the dry etching apparatus.

As the material of the semiconductor layer, various semiconductors such as group IV semiconductors such as Si and Ge, nitride semiconductors, group III-V semiconductors such as gallium arsenide-based semiconductors and gallium phosphide-based semiconductors can be used. For example, as the semiconductor layer, one or more semiconductor layers of GaN, AlGaN, or InGaN are used. In such a semiconductor layer, by using a chlorine-based gas such as Cl ₂ gas or SiCl ₄ gas as a reaction gas, the etching rate of dry etching can be increased more than that of yttria and zirconia.

Dry etching In a chamber in which a mask material and a substrate including a semiconductor layer are set, dry etching is performed using a reaction gas suitable for dry etching (reactive ion etching) of a semiconductor forming a semiconductor layer. The etching conditions are set so that the mask material scattered by the etching adheres to the surface of the semiconductor layer at a predetermined dot density and a predetermined dot size in the initial stage of the etching. The pressure in the chamber is a particularly important parameter for depositing the mask material on the surface of the semiconductor layer with a predetermined dot density and a predetermined dot size. For example, by setting the parameters other than the pressure to a value within a certain range and adjusting the pressure in the chamber, the mask material can be attached to the surface of the semiconductor layer with a desired dot density and a desired dot size. ..

For example, when the pressure in the chamber 12 is lowered, the size of the scattered mask material particles tends to increase. Therefore, in order to form a mask having a relatively large diameter, that is, to increase the diameter of the nanorods to be formed, the pressure inside the chamber 12 is lowered. On the contrary, in order to form a mask having a relatively small diameter, that is, to reduce the diameter of the nanorod to be formed, the pressure in the chamber 12 may be increased. Further, when the pressure in the chamber 12 is lowered, the number of scattered mask material particles is reduced, and the density of the mask formed on the semiconductor layer tends to be lowered. Considering the relationship between the pressure in the chamber 12 and the size of the scattered mask material particles and the number of scattered mask material particles, the mask material is applied to the semiconductor layer with a desired dot density and a desired dot size. The pressure in the chamber 12 is set so that it adheres to the surface.

The pressure in the chamber 12 is set, for example, in the range of 0.5 to 20 Pa, preferably in the range of more than 1 Pa and 10 Pa or less.

Further, it may be relatively difficult to adhere the mask material to the surface of the semiconductor layer with a desired dot density and a desired dot size only by setting the pressure in the chamber 12. In this case, in addition to the pressure, the mask material is attached to the surface of the semiconductor layer with a desired dot density and a desired dot size by changing other parameters such as the output and the flow rate of the reaction gas. You can
For example, increasing the power can reduce the size of the scattering mask material particles. This is because increasing the power enhances the kinetic energy of the particles of the reaction gas, and such particles of the reaction gas collide with the mask material particles.
For example, reducing the flow rate of the reactive gas can increase the number of deposited mask material particles on the surface of the semiconductor layer. This is because the flow rate of the reaction gas is reduced and the flow of the mask material particles around the semiconductor layer slows down, and the particles of the mask material easily deposit on the surface of the semiconductor layer.

The dry etching conditions are, for example,
Output: 10~1000W,
Pressure: 0.5-20Pa,
Reaction gas flow rate: 1 to 200 sccm,
To the range of
Preferably,
Output: 50~500W,
Pressure: 3-5Pa,
Reaction gas flow rate: 5 to 120 sccm
Set to the range.

In addition, when the nitride semiconductor nanorods are formed using a mixed gas of Cl ₂ and SiCl ₄ as a reaction gas, for example,
Cl ₂ flow rate: 1 to 50 sccm,
SiCl ₄ flow rate: 10 to 140 sccm,
To the range of
Preferably,
Cl ₂ flow rate: 5 to 20 sccm,
SiCl ₄ flow rate: 30 to 100 sccm
Set to the range.

The etching time is set so that the nanorods have a desired height.
When a nitride semiconductor nanorod is formed using a mixed gas of Cl ₂ and SiCl ₄ as a reaction gas, for example, when the output is 230 W, the pressure is ₄ Pa, the Cl ₂ flow rate is 10 sccm, and the SiCl ₄ flow rate is 70 sccm, the etching rate is set. : 43 nm/min. By using a mixed gas of Cl ₂ and SiCl ₄ as the reaction gas, the etching rate of the nitride semiconductor can be increased as compared with the case of using Cl ₂ . As a result, etching can be performed with a small bias power, so that plasma damage to the nitride semiconductor can be reduced.
Further, for example, when it is desired to form nanorods having a diameter of 50 nm to 300 nm, the pressure inside the chamber 12 is set to 2 Pa to 4 Pa, for example.

Mask removal step After completion of dry etching, the mask is removed. Here, for example, the mask is removed with an inorganic strong acid solution such as nitric acid. For example, when yttria is used as the mask material, nitric acid can remove the mask, and when zirconia is used as the mask material, sulfuric acid can remove the mask.

In the nanorod forming method of the first embodiment, when dry etching is continued without changing the etching conditions, as described above, from the initial stage where physical etching was active, to the stage where etching based on a chemical reaction is dominant. To autonomously transition to. After the transfer, dry etching of the semiconductor layer on which the mask is formed proceeds. At this stage, the three-dimensional shape of the nanorods formed by etching is mainly determined by the etching conditions. For example, when the pressure is high, that is, low vacuum, side etching progresses to form a columnar shape. When the pressure is low, that is, when the pressure is high, side etching is suppressed and the pyramidal nanorods are formed.

In the nanorod forming method of the first embodiment, the dry etching conditions are, for example, the pressure in the chamber 12 and the shape of the finally formed nanorods, which are created in advance for the selected semiconductor material, mask material and reaction gas. It can be set based on a database associated with density. This database is created by, for example, fixing the conditions other than the pressure in the chamber 12, sequentially changing the pressure in the chamber 12, and evaluating the shape and density of the nanorods when dry etching is performed at each pressure. This database is created by sequentially changing conditions other than the pressure in the chamber 12 and sequentially changing the pressure in the chamber 12 for each condition to evaluate the shape and density of the nanorods at each pressure. Good.

In the method for forming nanorods according to the first embodiment described above, the substrate including the semiconductor layer and the mask material are set in the chamber, the dry etching conditions are initially set so that the desired shape and density are obtained, and the mask is mainly formed. Nanorods are formed by autonomously changing from the initial stage to the stage where the semiconductor is mainly dry-etched.
Therefore, according to the nanorod forming method of the first embodiment, it is possible to form the nanorods by controlling the shape in a simple process.

Embodiment 2.
In the method for forming nanorods according to the first embodiment described above, a mask is formed in the dry etching process without changing the initially set dry etching conditions, and the semiconductor layer is etched using the mask to form nanorods. Said to do.
On the other hand, in the nanorod forming method according to the second embodiment, the dry etching condition is changed between the initial stage of forming the mask and the stage of dry etching the semiconductor layer after the mask is formed. Different from 1. Except for this point, the nanorod forming method of the second embodiment has the same configuration as the nanorod forming method of the first embodiment.

According to the nanorod forming method of the second embodiment configured as described above, it becomes possible to form a desired nanorod in response to more diverse requirements.
For example, as described above, when it is desired to form a mask having a relatively large diameter, that is, to increase the diameter of the nanorods to be formed, it is necessary to reduce the pressure inside the chamber 12. On the other hand, when the pressure is low, that is, high vacuum, side etching is suppressed and the shape tends to be conical. Therefore, it is not always easy to form pillar-shaped nanorods having a large diameter by the nanorod forming method of the first embodiment. However, according to the nanorod forming method of the second embodiment, the dry etching conditions are changed between the initial stage of forming the mask and the stage of dry etching the semiconductor layer after the mask is formed. Thereby, for example, a pillar-shaped nanorod having a large diameter can be easily formed. For example, the pressure in the chamber 12 may be reduced to form a mask having a large diameter, and then the pressure in the chamber 12 may be increased to etch the semiconductor layer into a pillar shape.

In the nanorod forming method according to the second embodiment, the etching conditions at the initial stage of forming the mask are, for example, the pressure in the chamber 12 and the mask scattered in advance for the selected semiconductor material, mask material and reaction gas. It can be set based on a database in which the size and distribution density of the mask formed by the working material on the semiconductor surface are related. This database, for example, fixes the conditions other than the pressure inside the chamber 12, changes the pressure inside the chamber 12 sequentially, and the size of the mask formed on the semiconductor surface by the scattered mask material when etching is performed at each pressure. And distribution density are evaluated and created. In this database, conditions other than the pressure in the chamber 12 are sequentially changed, the pressure in the chamber 12 is sequentially changed for each condition, and the size of the mask formed on the semiconductor surface by the mask material at each pressure is determined. It may be created by evaluating the distribution density.

In addition, after the mask is formed, when the semiconductor layer is dry-etched, the dry etching conditions are anisotropic with respect to the pressure in the chamber 12 which is created in advance for the selected semiconductor material, mask material and reaction gas. It can be set on the basis of a database in which a specific etching degree (ratio of etching in the depth direction and side etching) is associated. This database is created, for example, by fixing the conditions other than the pressure in the chamber 12 and sequentially changing the pressure in the chamber 12 and evaluating the anisotropic etching degree at each pressure. This database is also created by sequentially changing the conditions other than the pressure in the chamber 12 and sequentially changing the pressure in the chamber 12 for each condition to evaluate the anisotropic etching degree at each pressure. Good.

In the nanorod forming method of the second embodiment described above, the pressure in the chamber at the initial stage of etching for forming the mask and the pressure in the chamber when the semiconductor layer is etched using the mask are changed. Therefore, nanorods having a desired shape can be more easily formed to have a desired density.

In the method for forming nanorods according to the second embodiment described above, the pressure in the chamber at the initial stage of forming the mask and the pressure in the chamber when the semiconductor layer is etched using the mask are changed or the pressure in the chamber is changed. Without changing the etching conditions other than the pressure in the chamber in the initial stage of forming the mask and the dry etching conditions other than the pressure in the chamber when the semiconductor layer is etched using the mask. Good.

Embodiment 3.
FIG. 2 is a schematic cross-sectional view of a semiconductor element 20 manufactured using the method of Embodiment 3 according to the present invention. FIG. 3 is a schematic sectional view showing a part of FIG. 2 in an enlarged manner. The semiconductor element 20 is, for example, a laser element, and includes an n-side semiconductor layer 21 having an n-electrode 24 formed on its lower surface, a p-side semiconductor layer 23 having a p-electrode 25 formed on its upper surface, and an n-side semiconductor layer 21. and an active layer 22 provided between the p-side semiconductor layers 23. Here, in particular, as shown in FIG. 3, the active layer 22 includes a plurality of nanorods 22n in which barrier layers 22b and well layers 22w are alternately laminated, and an insulating member 22i embedded in a gap between the nanorods 22n. Including and The nanorods 22n are formed by the method for forming nanorods according to the first or second embodiment. The n-side semiconductor layer 21 includes an n-type semiconductor layer (first conductivity type semiconductor layer), and the p-side semiconductor layer 23 includes a p-type semiconductor layer (second conductivity type semiconductor layer).

In the active layer 22, the nanorods 22n include, for example, an n-side barrier layer having a thickness of 250 nm, a first well layer having a thickness of 3 nm, an intermediate barrier layer having a thickness of 2 nm, a second well layer having a thickness of 3 nm, and a p-side barrier layer having a thickness of 250 nm. Including and The lower end of the nanorod 22n may be located in the n-side barrier layer, and the height of the nanorod 22n may be, for example, about 260 to 510 nm. Further, in the active layer 22, the insulating member 22i can be made of, for example, an oxide such as SiO ₂ or a nitride such as AlN.

As described above, when the semiconductor device including the active layer 22 including the plurality of nanorods 22n is applied to, for example, a light emitting device, quantum confinement can improve the light emission efficiency.

Hereinafter, a method of manufacturing the semiconductor element 20 will be described.

First, the n-side semiconductor layer 21 and the active layer are epitaxially grown on the growth substrate. For example, when a nitride semiconductor light emitting device is manufactured as the semiconductor device 30, a sapphire substrate or an n-type GaN substrate can be used as the growth substrate. Further, n-side semiconductor layer 21 and the active layer, for example, the general formula _is represented by _{In x Al y Ga 1-x} -y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) It is formed using a nitride semiconductor.

Next, the nanorods are formed in the active layer by the method for forming nanorods according to the first or second embodiment, and the mask used during the formation of the nanorods (the mask material attached in the initial stage of dry etching) is removed by, for example, strong acid cleaning. To do. The height of the nanorods is approximately the same as the thickness of the active layer 22. Further, the lower end of the nanorod may be located in the n-side barrier layer in the active layer 22.

Next, the gap between the nanorods is filled with an insulating member.
Specifically, first, as shown in FIG. 4A, the insulating member 22i is formed so that the nanorods 22n are completely buried. The insulating member to be filled between the nanorods has excellent stability at high temperature in consideration of being exposed to high temperature during epitaxial growth of the p-side semiconductor layer which is a later step, for example, SiO ₂ , AlN, etc. It is preferable to use the insulating inorganic material. For example, as a method of forming or filling a gap between the nanorods with an insulating inorganic material such as SiO ₂ or AlN, sputtering, CVD (chemical vapor deposition method), or ECR (electron cyclotron resonance) can be mentioned. When SiO ₂ is used, a liquid SiO ₂ material called spin-on-glass (SOG) may be used to fill the space between the nanorods.

Next, as shown in FIG. 4B, a part of the insulating member 22i is removed so that the top and the vicinity of the nanorod 22n are exposed. The step of removing a part of the insulating member 22i is a step of exposing the top and the vicinity of the nanorod 22n, and it is preferable to remove the insulating member 22i while suppressing removal of the nanorod 22n as much as possible. The insulating member 22i can be removed by, for example, dry etching or wet etching, but the reaction gas in dry etching and the etching solution in wet etching are appropriately selected so that substantially only the insulating member 22i is removed. .. For example, when SiO ₂ is used as the insulating member, the insulating member can be removed by dry etching using a reaction gas such as CHF ₃ or CF ₄ . When AlN is used as the insulating member, the insulating member can be removed by wet etching using an etching solution such as KOH or NaOH. By using such a condition that substantially only the insulating member 22i is removed, the upper portion of the nanorod is exposed from the insulating member 22i as shown in FIG. 4B. The upper length of the nanorod exposed from the insulating member 22i is, for example, about 5 nm or less.

Then, the p-side semiconductor layer is epitaxially grown on the nanorods 22n and the insulating member 22i. In the case of manufacturing the nitride semiconductor light emitting device, p-side semiconductor layer, for example, general _{formula, In x Al y Ga 1-} x-y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y It is formed using a nitride semiconductor represented by ≦1). This growth of the p-side semiconductor layer is referred to as regrowth because after epitaxially growing the n-side semiconductor layer 21 and the active layer, the epitaxial growth is temporarily suspended and restarted to form the nanorods 22n and the insulating member 22i. To be done.

Finally, the p electrode 35 and the n electrode 34 are formed.
The semiconductor element 20 is manufactured as described above.
When the semiconductor element 20 is manufactured as a laser element, for example, a ridge having a longitudinal direction orthogonal to the height direction of the nanorods is formed, and reflective films made of, for example, a dielectric multilayer film are formed on both ends of the ridge. To do.

Embodiment 4.
FIG. 5 is a schematic cross-sectional view of a semiconductor element 30 manufactured by using the method of Embodiment 4 according to the present invention.
The semiconductor element 30 of the fourth embodiment is, for example, a laser element, and includes an n-side semiconductor layer 31 having an n-electrode 34 formed on the lower surface, a p-side semiconductor layer 33 having a p-electrode 35 formed on the upper surface, and an n-side. An active layer 32 provided between the semiconductor layer 31 and the p-side semiconductor layer 33 is included. Here, in particular, in the semiconductor device of Embodiment 4, as shown in FIG. 6A, the nanorod 37n includes the n-side semiconductor rod portion 31n, the active layer rod portion 32n, and the p-side semiconductor rod portion 33n. The semiconductor device 20 is different from the semiconductor device 20 of the third embodiment and is manufactured as follows.

In the manufacturing method of the fourth embodiment, first, the n-side semiconductor layer 31, the active layer 32, and the p-side semiconductor layer 33 are epitaxially grown on a growth substrate (for example, an n-type GaN substrate).
Next, the nanorod 37n including a part of the p-side semiconductor layer 33, the active layer 32, and the n-side semiconductor layer 31 is formed by the nanorod forming method of the first or second embodiment. After forming the nanorods 37n, the mask used for forming the nanorods (the mask material attached in the initial stage of dry etching) is removed by, for example, strong acid cleaning.

Next, the gap between the nanorods 37n is filled with an insulating member.
Specifically, first, as shown in FIG. 6A, the insulating member 36i is formed so that the nanorods 37n are completely buried. As the insulating member 36i filled between the nanorods 37n, an insulating inorganic material such as SiO ₂ or AlN can be used. Further, in the manufacturing method of the fourth embodiment, unlike the third embodiment, the p-side semiconductor layer is already epitaxially grown, so that the insulating resin can be used without being exposed to high temperature. In the fourth embodiment, unlike the third embodiment, the nanorod 37n includes the p-side semiconductor layer 33 and the n-side semiconductor layer 31 in addition to the active layer 32, and the length of the nanorod 37n becomes long. Therefore, in the fourth embodiment, it is preferable to use an insulating resin that is easier to fill the space between the nanorods 37n than the inorganic material. As the insulating resin, for example, paraxylylene resin can be used.

Next, as shown in FIG. 6B, a part of the insulating member 36i is removed so that the top and the vicinity of the nanorod 37n are exposed. In the step of removing a part of the insulating member 36i, when an insulating inorganic material such as SiO ₂ or AlN is used, it can be removed by the same method as in the third embodiment. When an insulating resin is used, it can be removed by dry etching using a gas such as O ₂ . The length of the upper portion of the nanorod 37n exposed from the insulating member is preferably longer than that of the third embodiment in order to reduce the contact resistance with the p electrode, and is exposed to, for example, about 30 nm.

Then, as shown in FIG. 6C, the p-electrode 35 is formed so as to be in contact with and cover the nanorod 37n and the insulating member 36i.
Finally, the n-electrode 34 is formed.
The semiconductor element 30 is manufactured as described above.
When the semiconductor device 30 is manufactured as a laser device, for example, a p-electrode having a longitudinal direction orthogonal to the height direction of the nanorods is formed to define a waveguide region, and both ends of the waveguide region are defined, for example. A reflective film made of a dielectric multilayer film is formed.

In the semiconductor device 30 manufactured as described above, as shown in FIG. 5, the n-side semiconductor layer 31 has the second n-side semiconductor layer 31b on the n-electrode 34 side and the first n-side semiconductor layer 31a on the active layer 32 side. Including and The first n-side semiconductor layer 31a, the active layer 32, and the p-side semiconductor layer 33 are insulated from the n-side semiconductor rod portion 31n and the insulating member 36i, the active layer rod portion 32n and the insulating member 36i, and the p-side semiconductor rod portion 33n. And a member 36i.

In the semiconductor device 30 of the fourth embodiment configured as described above, since the active layer 32 includes the nano-sized active layer rod portion 32n, for example, when applied to a light emitting device, quantum confinement improves the light emitting efficiency. Can be made.

Embodiment 5.
FIG. 7 is a schematic cross-sectional view of a semiconductor device 40 manufactured using the method of Embodiment 5 according to the present invention. The semiconductor element 40 is, for example, a light emitting diode, and includes a support substrate 47, and a semiconductor laminated structure 42 provided on the support substrate 47 via a conductive layer 48. The semiconductor laminated structure 42 includes, for example, a p-side semiconductor layer 42a, an active layer 42b, and an n-side semiconductor layer 42c from the support substrate 47 side. In the semiconductor element 40, the n-electrode 46 is provided on a part of the upper surface of the semiconductor laminated structure 42 so as to be in contact with the n-side semiconductor layer 42c. The p electrode 43 is provided on the lower surface of the semiconductor laminated structure 42 on the support substrate 47 side so as to be in contact with the p side semiconductor layer 42a.
In the semiconductor element 40, the lower surface of the semiconductor laminated structure 42 is bonded to the support substrate 47 via the conductive layer 48, the reflective film 45, and the protective film 44. Specifically, the conductive layer 48 has a convex portion 48p, and the upper surface of the convex portion 48p is joined to the lower surface of the p electrode 43. A reflective film 45 and a protective film 44 are provided from the conductive layer 48 side between the conductive layer 48 and the semiconductor laminated structure 42 except for the convex portion 48p. The reflective film 45 may be omitted. Further, the protective film 44 may be omitted and the p electrode 43 may be provided on almost the entire lower surface of the p-side semiconductor layer 42a.

Here, in particular, in the semiconductor element 40, the upper surface (the surface of the n-side semiconductor layer 42c) of the semiconductor laminated structure 42 on which the n-electrode 46 is formed is an uneven surface including a plurality of nanorods.

In the semiconductor element 40 of the fifth embodiment configured as described above, the surface of the n-side semiconductor layer 42c, which is the main light emitting surface, is an uneven surface (rough surface) containing nanorods, and therefore the light extraction efficiency is high. can do.

In the semiconductor element 40 of the fifth embodiment, the surface of the n-side semiconductor layer 42c has nanorods formed on the surface of the n-side semiconductor layer 42c by the nanorod forming method of the first or second embodiment before forming the n-electrode 46. It can be roughened by forming it.

Examples of the present invention will be described below.
Example 1.
First, a GaN layer having a thickness of about 5 μm was formed on the +C surface of the GaN substrate.
Next, the semiconductor wafer was set on a wafer table made of yttria and dry-etched using an RIE device. Cl ₂ and SiCl ₄ were used as the reaction gas, and the etching conditions were output: 230 W, pressure: ₄ Pa, Cl ₂ flow rate: 10 sccm, and SiCl ₄ flow rate: 70 sccm. The etching time was 16 minutes, and nanorods having a diameter of about 70 nm and a height of about 700 nm were formed.
Then, in order to remove the yttria deposited as a mask on the nanorods, the wafer was immersed in nitric acid for 5 minutes, washed with water and dried.
The obtained nanorod is shown in FIG. FIG. 8 is an SEM image photographed using a scanning electron microscope (SEM).
As shown in FIG. 8, in Example 1, columnar nanorods suitable for forming the nanorods including the active layer described in Embodiment 3 or 4 were formed.

Example 2.
As Example 2, nanorods were formed in the same manner as in Example 1, except that the semiconductor wafer was obtained by sequentially stacking an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the +C surface of a GaN substrate. .. That is, in Example 2, the nanorods were formed in the p-type semiconductor layer. The p-type semiconductor layer includes a Mg-doped GaN/AlGaN superlattice cladding layer and a Mg-doped GaN contact layer. The n-type semiconductor layer includes a Si-doped AlGaN cladding layer, and the active layer includes an n-side barrier layer having a thickness of about 250 nm, a first well layer having a thickness of about 3 nm, and an intermediate barrier having a thickness of about 2 nm. A layer, a second well layer having a thickness of about 3 nm, and a p-side barrier layer having a thickness of about 250 nm. The first well layer and the second well layer had a composition capable of emitting blue light having a wavelength of about 455 nm.
Also in Example 2, a nanorod having the same shape as in Example 1 was obtained. In Example 2, the PL (photoluminescence) intensity before and after washing with nitric acid was evaluated for the sample on which the nanorods were formed. As a result, as shown in FIG. 13, it was confirmed that the PL intensity was low in the state where the nitric acid was not washed, and was high after the nitric acid washes. This shows that the yttria deposited on the surface of the semiconductor layer remains after the nanorod formation and before the nitric acid cleaning, and indicates that the yttria deposited on the surface of the semiconductor layer functions as a mask.

Example 3.
As Example 3, nanorods were formed in the same manner as in Example 1 except that the pressure during dry etching was 8 Pa.
The obtained nanorod is shown in the SEM image of FIG.
As shown in FIG. 9, in Example 3, needle-shaped nanorods are formed, and the nanorods can be used, for example, in forming the uneven surface for improving the light extraction efficiency shown in Embodiment 5.

Example 4.
As Example 4, a nanorod was formed in the same manner as in Example 1 except that the pressure during dry etching was set to 1 Pa.
The obtained nanorod is shown in the SEM image of FIG.

Example 5.
As Example 5, nanorods were formed in the same manner as in Example 1 except that a GaN layer was formed on the -C plane of the GaN substrate to produce a semiconductor wafer.
The obtained nanorod is shown in the SEM image of FIG.
As shown in FIG. 11, in Example 5, a cone-shaped nanorod is formed, and this nanorod can be used, for example, for forming the uneven surface for improving the light extraction efficiency shown in Embodiment 5. Incidentally, in the SEM image shown in FIG. 11, the nanorods seem to be inclined, but this is due to the SEM image capturing conditions, and in reality, the shape was a pyramidal shape that was nearly symmetrical.

Comparative Example 1.
In Comparative Example 1, formation of nanorods was attempted in the same manner as in Example 1 except that the semiconductor wafer was set on a wafer table made of quartz and dry-etched.
However, in Comparative Example 1, the nanorod could not be formed as shown in FIG.

Example 6.
As Example 6, a laser device including nanorods produced in the same manner as in Example 1 is produced.
Specifically, first, an n-type semiconductor layer and an active layer are sequentially formed on the +C surface of a GaN substrate to manufacture a semiconductor wafer. In Example 6, the n-type semiconductor layer includes a Si-doped AlGaN cladding layer, and the active layer has an n-side barrier layer having a thickness of about 250 nm, a first well layer having a thickness of about 3 nm, and a thickness of about 2 nm. Intermediate barrier layer, a second well layer having a thickness of about 3 nm, and a p-side barrier layer having a thickness of about 250 nm.
Next, nanorods are formed on the semiconductor wafer in the same manner as in Example 1. At this time, the lower end of the nanorod is in the n-side barrier layer.
Then, on the semiconductor wafer on which the nanorods are formed, AlN that is an insulator is formed for the purpose of insulating between the p-type semiconductor layer and the n-type semiconductor layer, and AlN is wet-etched using KOH so that the upper part of the nanorods is exposed. .. That is, the gap between the nanorods is filled with AlN to the extent that the entire active layer is not completely filled.
After that, the p-type semiconductor layer is crystal-grown to form a stripe-shaped ridge, an electrode, and the like to obtain a laser element. The p-type semiconductor layer includes a Mg-doped GaN/AlGaN superlattice cladding layer and a Mg-doped GaN contact layer.

Example 7.
As Example 7, a laser device including nanorods produced in the same manner as in Example 1 is produced.
Specifically, first, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially formed on the +C surface of a GaN substrate to manufacture a semiconductor wafer. The n-type semiconductor layer, the active layer, and the p-type semiconductor layer are the same as those in the sixth embodiment.
Next, nanorods are formed on the semiconductor wafer in the same manner as in Example 1. At this time, the lower end of the nanorod is in the n-type semiconductor layer.
Then, the semiconductor wafer on which the nanorods are formed is coated with paraxylylene resin, which is an insulator, for the purpose of insulating between the p-type semiconductor layer and the n-type semiconductor layer, so that the upper part of the nanorods is exposed, that is, the p-type semiconductor layer is entirely exposed. The gaps between the nanorods are filled to the extent that the nanorods are not completely filled and the surface is flattened.
After that, a stripe-shaped ridge, electrodes, and the like are formed to obtain a laser element.

Example 8.
The LED element of Example 8 is manufactured as follows.
First, an n-side semiconductor layer 42c is formed by growing a GaN layer and an n-type contact layer made of Si-doped n-type AlGaN on a growth substrate made of sapphire (C plane) via a buffer layer. Form.

Next, a barrier layer made of undoped AlGaN and a well layer made of undoped InGaN are alternately grown to form an active layer 42b which is a light emitting layer.
Next, a p-type AlGaN layer doped with Mg and a p-type contact layer made of p-type AlGaN doped with Mg are grown to form the p-side semiconductor layer 42c.
As described above, the semiconductor laminated structure 42 is formed.

Next, the p electrode 43 is formed on a part of the surface of the p-type contact layer of the semiconductor laminated structure 42.
SiO ₂ as a protective film 44 is formed on a portion of the surface of the p-type contact layer where the p electrode 43 is not formed, and a reflective film 45 made of Al is formed on the protective film 44.
Then, a bonding metal layer is formed so as to cover the p-electrode 43 and the reflective film 45.

Separately, a supporting substrate 47 made of CuW and having a thickness of 200 μm is prepared. A bonding metal layer is formed on the surface of the support substrate 47.

Next, the joining metal layer of the semiconductor laminated structure 42 and the joining metal layer of the support substrate 47 are joined. After the bonding, the bonding metal layer of the semiconductor laminated structure 42 and the bonding metal layer of the support substrate 47 are integrated to form the conductive layer 48 containing AuSn.
Then, the growth substrate and the buffer layer on the opposite side of the support substrate 47 are removed, and the surface of the n-type contact layer made of n-type AlGaN is exposed above the p-side semiconductor layer 42c.

The exposed surface of the n-type contact layer is dry-etched using Cl ₂ and SiCl ₄ as a reaction gas using an RIE apparatus. The etching conditions are: output: 230 W, pressure: ₄ Pa, Cl ₂ flow rate: 10 sccm, SiCl ₄ flow rate: 70 sccm. The etching time is 16 min. As a result, nanorods having a height of about 700 nm are formed on the surface of the n-type contact layer.
Then, in order to remove the yttria deposited as a mask on the nanorods, it is immersed in nitric acid for 5 minutes, washed with water and dried.
Next, the n electrode 46 is formed on a part of the surface of the n-type contact layer on which the nanorods are formed.

In the LED element of Example 8 manufactured as described above, since the nanorods are formed on the surface of the n-type contact layer that is the main light emitting surface, the luminous efficiency can be higher than that in the case where the nanorods are not provided.

10 dry etching apparatus 11 substrate 13 upper electrode 15 lower electrode 17 wafer table 12 chamber 19 high frequency power supply 20, 30, 40 semiconductor element 21, 31, 42c n side semiconductor layer 22, 32, 42b active layer 22b barrier layer 22w well layer 22n , 37n nanorod 22i insulating member 23, 33, 42a p-side semiconductor layer 24, 34, 46 n-electrode 25, 35, 43 p-electrode 31a first n-side semiconductor layer 31b second n-side semiconductor layer 31n n-side semiconductor rod portion 32n active layer Rod part 33n p side semiconductor rod part 42 Semiconductor laminated structure 44 Protective film 45 Reflective film 47 Support substrate 48 Conductive layer

Claims (8)

A method for forming semiconductor nanorods by dry etching using a reaction gas, comprising:
In the chamber, a masking material made of a material having an etching rate lower than that of the semiconductor by a chemical reaction with the reaction gas during dry etching, and a preparatory step of setting the substrate containing the semiconductor in the chamber,
By setting the pressure in the chamber within a predetermined range so that the mask material scattered by etching adheres to the surface of the semiconductor with a predetermined dot density and a predetermined dot size, a plurality of mask materials containing the mask material, respectively, can be obtained. A dry etching step of forming a dot mask on the surface of the semiconductor, and removing the semiconductor exposed from the dot mask by dry etching;
And a mask removal step of removing the dot mask, only including,
The method for forming a nanorod , wherein the mask material is yttria or zirconia . The method for forming nanorods according to claim 1, wherein the semiconductor is a nitride semiconductor. The method of forming a nanorod according to claim 2, wherein a surface on which the semiconductor dot mask is formed is a +C plane. Wherein in the dry etching step, the method of forming the nanorods according to any one of claims 1 to 3, which comprises changing the pressure in the chamber. The method comprising placing the substrate on a tray comprising said masking material, the formation of nanorods according to any one of claims 1-4 wherein the tray is the source of the mask material Method. The method of manufacturing a semiconductor device including a method for forming nanorods according to any one of claims 1-5. The semiconductor includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer different from the first conductivity type in this order,
The semiconductor device according to claim 6 , wherein in the dry etching step, the dot mask is formed on the first conductive type semiconductor layer, and at least a part of the first conductive type semiconductor layer is removed to form nanorods. Production method. The method of manufacturing a semiconductor device according to claim 7 , further comprising forming an electrode in contact with the first conductive type semiconductor layer on the surface on which the nanorods are formed.

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