JP6711679B2 - Synchronous rectification circuit of wireless power receiving device, control circuit thereof, control method, wireless power receiving device and power receiving control circuit, electronic device - Google Patents

Description

The present invention relates to a synchronous rectification circuit for a wireless power receiving device.

FIG. 1 is a block diagram of a wireless power supply system 900. The wireless power feeding system 900 includes a wireless power transmitting device 902 and a wireless power receiving device 910. The wireless power transmission device 902 transmits the power signal S1 from the transmission coil 904. The wireless power receiving device 910 receives the power signal S1 at the receiving coil 912. The full bridge circuit 914 rectifies the current I _AC flowing through the receiving coil 912. The controller 918 performs switching control of the full bridge circuit 914 in synchronization with the waveform of the current I _AC .

The current rectified by the full bridge circuit 914 is smoothed by the smoothing capacitor 916. The voltage V _RECT generated in the smoothing capacitor 916 is made into a constant voltage by the regulator (for example, LDO) 920. The full bridge circuit 914, the controller 918, the regulator 920, etc. are integrated in a power reception control IC (Integrated Circuit) 930.

The power transmitting device 902 and the power receiving device 910 can communicate with each other, and a feedback loop is formed to keep the rectified voltage V _RECT at a target value (DP: Desired Point). However, if the coupling degree between the transmitting coil 904 and the receiving coil 912 changes or the load of the regulator 920 suddenly changes at a speed exceeding the feedback response speed, the rectified voltage V _RECT jumps up. When the rectified voltage V _RECT becomes an overvoltage, there is a possibility that the withstand voltage of the transistors forming the full bridge circuit 914 and the regulator 920 may be exceeded.

A comparator 932 is provided to detect an overvoltage of the rectified voltage V _RECT . When V _RECT >V _{OVP and the} overvoltage condition is detected, the switches SW91 and SW92 are turned on. As a result, the capacitors C91 and C92 are connected in parallel to the reception antenna 934, the resonance frequency of the reception antenna 934 changes, and the reception power decreases. As a result, the rise of the rectified voltage V _RECT is suppressed and overvoltage protection is applied.

US Pat. No. 8,278,889

The overvoltage protection of FIG. 1 requires external capacitors C91 and C92 in order to change the resonance frequency, which causes an increase in cost and an increase in mounting area. Particularly, in the wireless power receiving device, in addition to the capacitors C91 and C92, capacitors C93 and C94 for setting the resonance frequency, a modulation capacitor (not shown), and the like are externally attached, so that the number of capacitors can be reduced. It makes sense if possible.

Further, in this overvoltage protection, since the resonance frequency of the receiving antenna 934 is changed, a delay may occur before the protection is applied, and it may take time until the rectified voltage V _RECT decreases.

The present invention has been made in view of the above problems, and one of the exemplary objects of an aspect thereof is to provide a synchronous rectification circuit having an overvoltage protection function different from the conventional one.

An aspect of the present invention relates to a control circuit that constitutes a synchronous rectification circuit together with a full bridge circuit. The control circuit compares at least one of the voltages of the first AC input and the second AC input to which the full bridge circuit is connected with a threshold voltage, and generates at least one detection signal indicating the comparison result. And a control logic for generating four control signals for instructing on/off of four transistors forming the full bridge circuit according to at least one detection signal, and a voltage of a rectification line of the full bridge circuit is an overvoltage. An overvoltage detection comparator that asserts an overvoltage detection signal when the threshold voltage is exceeded, and a timing control that changes at least one switching timing of four transistors in response to the assertion of the overvoltage detection signal from the timing instructed by the control signal. And a section.

According to this aspect, in the overvoltage state, by shifting the switching timing from the optimum point indicated by the control signal, the phase of the current waveform with respect to the voltage waveform is shifted, and by controlling the power factor, the rectifier circuit can be protected from the overvoltage state. Moreover, an overvoltage state can be suppressed.

The timing control unit may change the switching timing of at least the two transistors on the low side in response to the assertion of the overvoltage detection signal. The timing control unit may change the switching timing of the four transistors in response to the assertion of the overvoltage detection signal.

The timing controller may include a delay circuit that delays at least one of the four control signals in response to the assertion of the overvoltage detection signal.

The delay amount of the delay circuit may depend on the set value of the register. By allowing the amount of delay to be adjusted externally, optimal overvoltage protection for the system can be achieved.

The amount of delay when the overvoltage detection signal is asserted may depend on the slope of the voltage of the rectification line. By increasing the delay amount as the voltage gradient increases, adaptive overvoltage protection can be realized.

The amount of delay when the overvoltage detection signal is asserted may depend on the voltage level of the rectification line. By increasing the delay amount as the voltage level increases, adaptive overvoltage protection can be realized.

The control circuit may be integrated on one semiconductor substrate. "Integrated integration" includes the case where all the components of the circuit are formed on the semiconductor substrate and the case where the main components of the circuit are integrated, and some of them are used for adjusting the circuit constants. A resistor or a capacitor may be provided outside the semiconductor substrate.

Another aspect of the present invention relates to a synchronous rectification circuit. The synchronous rectification circuit may include a full-bridge circuit and any one of the control circuits described above that controls the full-bridge circuit.

The synchronous rectification circuit may be used in a wireless power receiving device to rectify the current of the receiving coil.

Another aspect of the present invention relates to a power reception control circuit used in a wireless power receiving device. The power reception control circuit is one of the control circuits described above that controls the full-bridge circuit connected to the receiving coil, a regulator that stabilizes the rectified voltage generated by the full-bridge circuit, and data to be transmitted to the wireless power transmission device. And a modulator that modulates the data and superimposes it on the receiving coil.

Another aspect of the present invention relates to a wireless power receiving device. The wireless power receiving device stabilizes the rectification voltage generated in the receiving coil, the full bridge circuit connected to the receiving coil, the smoothing capacitor connected to the full bridge circuit, the control circuit controlling the full bridge circuit, and the smoothing capacitor. And a regulator that operates.

Another aspect of the present invention relates to an electronic device. The electronic device includes a wireless power receiving device.

It should be noted that any combination of the above constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced among methods, devices, systems, etc. are also effective as an aspect of the present invention.

According to one aspect of the present invention, the synchronous rectification circuit can be protected from an overvoltage condition.

It is a block diagram of a wireless power feeding system. 3 is a circuit diagram of a synchronous rectification circuit including the control circuit according to the embodiment. FIG. FIG. 3 is an operation waveform diagram of the synchronous rectification circuit of FIG. 2 when normal. It is an operation waveform diagram in an overvoltage state. FIG. 3 is a block diagram of a wireless power receiving device including the synchronous rectification circuit of FIG. 2. It is a figure which shows the electronic device provided with a wireless power receiving apparatus.

Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplicated description will be omitted as appropriate. Further, the embodiments are merely examples and do not limit the invention, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In the present specification, “the state in which the member A is connected to the member B” means that the members A and B are electrically connected to each other in addition to the case where the members A and B are physically directly connected. It also includes the case of being indirectly connected via another member that does not substantially affect the general connection state or does not impair the function and effect exerted by their connection.

Similarly, "the state in which the member C is provided between the member A and the member B" means that the members A and C or the members B and C are directly connected and their electrical It also includes the case of being indirectly connected via another member that does not substantially affect the general connection state or does not impair the function and effect exerted by their connection.

FIG. 2 is a circuit diagram of the synchronous rectification circuit 100 including the control circuit 200 according to the embodiment. The synchronous rectification circuit 100 includes a full bridge circuit 102 and a control circuit 200. The control circuit 200 is an IC (Integrated Circuit) integrated with a full bridge circuit 102 on one semiconductor substrate. In a high power application, the power transistor forming the full bridge circuit 102 may be a discrete element.

The synchronous rectification circuit 100 has an AC1 terminal (first AC input), an AC2 terminal (second AC input), a RECT terminal, and a GND terminal. A power supply, a coil, and an antenna that generate an AC signal are connected to the AC1 terminal and the AC2 terminal. The smoothing capacitor 104 is connected to the RECT terminal, and the GND terminal is grounded. The full bridge circuit 102 is connected to the rectification line 106 and the RECT terminal, and connected to the GND terminal via the ground line 108.

The full bridge circuit 102 includes a first transistor M1 to a fourth transistor M4 connected in an H bridge form. In the present embodiment, the first transistor M1 to the fourth transistor M4 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, GaN (gallium nitride) FETs, etc. may be used. Good. Further, P-channel (or PNP type) may be used for the first transistor M1 and the second transistor M2 on the high side.

A flywheel diode is provided in parallel with each of the first transistor M1 to the fourth transistor M4, but not shown. The free wheel diode may be a body diode of a MOSFET or a discrete element.

The control circuit 200 performs so-called zero current switching in the normal state, and repeats the following states φ1 to φ4.
・First state φ1
First transistor M1=OFF
Second transistor M2=ON
Third transistor M3=ON
Fourth transistor M4=OFF
・Second state φ2
First transistor M1=OFF
Second transistor M2=OFF
Third transistor M3=OFF
Fourth transistor M4=OFF
・Third state φ3
First transistor M1=ON
Second transistor M2=OFF
Third transistor M3=OFF
Fourth transistor M4=ON
・Fourth state φ4
First transistor M1=OFF
Second transistor M2=OFF
Third transistor M3=OFF
Fourth transistor M4=OFF

The control circuit 200 includes a zero current detection circuit 202, control logic 204, and a driver 208 for zero current switching.

The zero current detection circuit 202 compares at least one of the voltages V _AC1 and V _AC2 at the AC1 terminal and the AC2 terminal with a threshold voltage, and generates at least one detection signal ZC_DET1 and ZC_DET2 indicating the comparison result. The ZC_DET1 signal changes its level at each zero-cross timing of the current I _AC1 . The ZC_DET2 signal changes its level at each zero-cross timing of the current I _AC2 . Note that the zero-cross timing indicated by the ZC_DET1 signal and the ZC_DET2 signal may not indicate a strict current zero-cross point in consideration of the delay time of the circuit, but may indicate a time earlier in time than that.

The control logic 204 generates four control signals SG1 to SG4 instructing on and off of the four transistors M1 to M4 forming the full bridge circuit 102 based on the ZC_DET1 signal and the ZC_DET2 signal.

The configurations of the zero current detection circuit 202 and the control logic 204 are not particularly limited, and a known technique may be used.

In the present embodiment, the zero current detection circuit 202 includes a first comparator ZC_COMP1 and a second comparator ZC_COMP2. First comparator ZC_COMP1 the voltage _{V AC1} in AC1 terminal is compared with the threshold value voltage _{V ZC1,} it generates a ZC_DET1 signal. The second comparator ZC_COMP2 compares the voltage V _AC2 at the AC2 terminal with the threshold voltage V _ZC2 and generates the ZC_DET2 signal.

Threshold voltage _{V ZC1} and _{V ZC2} is set to near zero, typically slightly lower voltage range than zero - is set to (number mV~- tens mV). As the threshold value voltage V _ZC1, V _ZC2 low, zero current detection is earlier in time, higher, zero current detection is delayed temporally. Therefore the threshold voltage _{V ZC1, V ZC2} is determined in consideration of the propagation delay, etc. of the response speed and signal of the comparator.

The ZC_DET1 signal becomes the first level (high level in the present embodiment) when V _AC1 >V _ZC and the second level (low level) when it is low. First comparator ZC_COMP1 is hysteresis _comparator, V AC1 _<when a _{V ZC1,} the threshold voltage _{V ZC1} is set to a high _value, V _AC1> when a _{V ZC1,} the threshold voltage _{V ZC1} is low (For convenience, referred to as V _ZC3 ) is set.

The ZC_DET2 signal becomes the first level (high level) when V _AC2 >V _ZC2 and the second level (low level) when V _AC2 <V _ZC2 . The second comparator ZC_COMP2 is also composed of a hysteresis comparator, and the threshold voltage V _ZC2 is set to a high value when V _AC2 <V _ZC2 , and the threshold voltage V _ZC2 is low when V _AC2 >V _ZC2. It is set to a value (referred to as V _ZC4 for convenience).

The zero current detection circuit 202 may include a mask circuit for removing noise of the first comparator ZC_COMP1 and the second comparator ZC_COMP2.

The control logic 204 is
(1) When the ZC_DET1 signal becomes the first level (high level), the full bridge circuit 102 is transited from the first state φ1 to the second state φ2,
(2) When the ZC_DET2 signal becomes the second level (low level), the full bridge circuit 102 is transited from the second state φ2 to the third state φ3,
(3) When the ZC_DET2 signal becomes the first level (high level), the full bridge circuit 102 is transited from the third state φ3 to the fourth state φ4,
(4) When the ZC_DET1 signal becomes the second level (low level), the full bridge circuit 102 is transited from the fourth state φ4 to the first state φ1.

The control logic 204 may be a state machine. The control logic 204 generates control signals SG1 to SG4 for instructing on and off of the first transistor M1 to the fourth transistor M4, respectively. The driver 208 switches ON/OFF of the first transistor M1 to the fourth transistor M4 according to the gate signals SG1 to SG4. When the high-side transistors M1 and M2 are N-channel, the driver 208 is configured by using a bootstrap circuit, but the bootstrap capacitor and the like are omitted here.

With the above configuration, the full bridge circuit 102 is zero-current switched in a normal state, and high-efficiency operation is realized. Next, overvoltage protection will be described.

The control circuit 200 includes a timing control unit 206 and an overvoltage detection comparator (OVP comparator) 210 for overvoltage protection.

The OVP comparator 210 asserts an overvoltage detection signal (OVP signal) S _OVP (for example, high level) when the voltage V _RECT of the rectification line 106 of the full bridge circuit 102 exceeds the overvoltage threshold voltage V _OVP .

The timing control unit 206 is inserted, for example, between the control logic 204 and the driver 208, incorporated in the control logic 204, or incorporated in the driver 208.

The timing control unit 206 makes the switching timing of at least one of the four transistors M1 to M4 different from the timing instructed by the control signals SG1 to SG4 in response to the assertion of the OVP signal S _OVP . In the present embodiment, the timing of all four control signals SG1 to SG4 is shifted from the optimum timing for zero current switching indicated by the control signals SG1 to SG4.

The timing control unit 206 includes, for example, a plurality of delay circuits 212. Each delay circuit 212 can be switched between enable and disable in accordance with the OVP signal S _OVP , gives a delay τ _OVP to the corresponding control signal SG in the enabled state, and passes the control signal SG through in the disabled state. The delay amount τ _OVP can be about several ns to several tens of ns.

The delay amount of the delay circuit 212 is preferably adjustable according to the set value stored in the register. An external microcomputer or the like can write the set value of the delay amount in the register.

The above is the configuration of the synchronous rectification circuit 100. Next, the operation will be described. FIG. 3 is an operation waveform diagram of the synchronous rectification circuit 100 of FIG. 2 in a normal state. M1 to M4 represent gate signals.

Before the time t0, the state is the first state φ1. At time t0, when the first voltage _{V AC1} in AC1 terminal exceeds a first threshold voltage _{V ZC1,} ZC_DET1 signal is the first level (high level), the control circuit 200, the transition to the second state φ2 Give instructions. Note that for ease of understanding, ZC_DET1 signal _is shown as being at the same time the level transitions when the V AC1 _{= V ZC1,} actually the response delay of the comparator transitions ZC_DET1 signal is delayed from time t0. The same applies to the ZC_DET2 signal. After that, at time t1 after the lapse of the control delay τ1, the gate signals SG2 and SC3 of the second transistor M2 and the third transistor M3 become low level, and they are turned off. The control delay τ1 includes a detection delay of the zero current detection circuit (comparator) 202, a calculation delay of the control logic 204, a propagation delay of the driver 208, and the like. This control delay τ1 (τ2 to τ4) does not include the delay time τ _OVP added in the above-mentioned overvoltage state.

At time t2, when the second voltage V _AC2 at the AC2 terminal falls below the threshold voltage V _ZC4 , the ZC_DET2 signal becomes the second level (low level), and the control circuit 200 instructs the transition to the third state φ3. .. Thereafter, the fourth transistor M4 is turned on at time t3 after the control delay τ2 has elapsed, and the first transistor M1 is turned on at time t4 which is delayed.

At time t5, when the second voltage V _AC2 of the AC2 terminal exceeds the second threshold voltage V _ZC2 , the ZC_DET2 signal becomes the first level (high level), and the control circuit 200 makes a transition to the fourth state φ4. Give instructions. After that, at time t6 after the elapse of the control delay τ3, the gate signals SG1 and SG4 of the first transistor M1 and the fourth transistor M4 become low level, and the first transistor M1 and the fourth transistor M4 are turned off.

At time t7, when the first voltage V _AC1 of the AC1 terminal falls below the threshold voltage V _ZC3 , the ZC_DET1 signal becomes the second level (low level), and the control circuit 200 instructs the transition to the first state φ1. .. After that, the third transistor M3 is turned on at time t8 after the control delay τ4 has elapsed, and the second transistor M2 is turned on at time t9 after the delay.

The states (actual transistor states) φ1′ to φ4′ of the full-bridge circuit 102 transit with a delay from the corresponding states φ1 to φ4 of the control circuit 200. The first threshold voltage _{V ZC1} ~ fourth threshold voltage _{V ZC4} of the control circuit 200, delayed state of the full bridge circuit 102 φ1'~φ4 'has a zero-cross point of the actual current _{I AC1, I AC2} Determined to match.

Attention is paid to the transition from the first state φ1 to the second state φ2.
The first voltage V _AC1 in the first state φ1 is given by I _AC1 ×R _ON3 . R _ON3 is the on-resistance of the third transistor M3. The threshold voltage V _ZC1 may be set so that an actual current zero current (I _AC1 =0) is generated after a delay time τ1 has passed after V _AC1 crosses V _ZC1 .

If the slope of the current I _AC1 is α(A/s), the slope of the first voltage V _AC1 is α×R _ON3 (V/s). Therefore, by setting the threshold voltage V _ZC1 so as to satisfy the expression (1), ideal zero current switching can be realized.
V _ZC1 =α×R _ON3 ×τ1 (1)

Next, the operation in the overvoltage state will be described. FIG. 4 is an operation waveform diagram in the overvoltage state. The alternate long and short dash line shows the waveform in the zero current switching of FIG. 3 for reference. The gate signals of the first transistor M1 to the fourth transistor M4 are delayed by the delay time τ _OVP as compared with the waveform diagram of FIG. Due to this delay time τ _OVP , the current is inverted while the voltage is crossing, and a reactive power section is generated. In this section, the load in the latter stage of the synchronous rectification circuit 100 looks high impedance as seen from the power transmitting device, and thus power is not supplied to the load. As a result, the current supplied to the smoothing capacitor 104 and the rectification line 106 decreases, and the overvoltage state can be suppressed.

The above is the operation of the synchronous rectification circuit 100. According to this synchronous rectification circuit 100, an overvoltage state can be suppressed.

Since the capacitors C91 and C92 shown in FIG. 1 are not required, the cost can be reduced, the number of IC pins can be reduced, and the circuit mounting area can be reduced.

Further, when the resonance frequency is shifted by the capacitors C91 and C92, the overvoltage protection is gradually enabled over several cycles of the power signal S1. On the other hand, according to the present embodiment, the OVP comparator 210 and the timing control unit 206 can generate the reactive power section on a cycle-by-cycle basis, so that high-speed overvoltage protection can be realized.

Further, since the rise of the rectified voltage V _RECT can be suppressed more than ever, the breakdown voltage required for the circuit can be lowered in some cases.

(Use)
Next, a preferred application of the synchronous rectification circuit 100 will be described. FIG. 5 is a block diagram of a wireless power receiving apparatus 300 including the synchronous rectification circuit 100 of FIG. The wireless power receiving device 300 includes a receiving coil L _RX , resonance capacitors Cs and Cd, a smoothing capacitor C _RECT (104), and a power reception control IC 400. The synchronous rectification circuit 100 is integrated in the power reception control IC 400. The power reception control IC 400 includes a regulator 310, a controller 312, and a modulator 314 in addition to the synchronous rectification circuit 100. The synchronous rectifying circuit 100 rectifies the current flowing through the receiving coil 302.

The regulator 310 stabilizes the rectified voltage V _RECT generated by the full bridge circuit 102 and the smoothing capacitor 104, and outputs the rectified voltage V _RECT from the output (OUT) pin to the outside.

The controller 312 controls the entire power reception control IC 400 as a whole, and also generates data to be transmitted to the wireless power transmission device 902. This data may include a control error packet indicating the error between the rectified voltage V _RECT and the target value DP thereof, a packet indicating the power received by the wireless power receiving apparatus 300, and the like. The modulator 314 modulates the data (packet) from the controller 312 and superimposes it on the reception coil 302 via the COMM1 and COMM2 terminals.

The wireless power receiving device 300 may be adopted in either an electromagnetic induction system or a magnetic resonance system. Examples of the former include the Qi standard established by WPC (Wireless power consortium) and the Air-Fuel Alliance standard. The magnetic resonance method adopted by the Air-Fuel Alliance standard uses a frequency band (for example, 6.78 MHz) higher than the electromagnetic induction method of 150 kHz to 200 kHz. Therefore, with respect to overvoltage protection as well, higher-speed responsiveness is required, and there is a possibility that the advantages of the synchronous rectification circuit 100 according to the embodiment can be further enjoyed. Alternatively, it can be used for non-contact power transmission (also referred to as non-contact power transmission or wireless power supply) used for electric shavers, electric toothbrushes, cordless phones, game machine controllers, electric tools, and the like.

The wireless power receiving device 300 is mounted on the electronic device 500. FIG. 6 is a diagram showing an electronic device 500 including the wireless power receiving apparatus 300. The electronic device 500 may be a mobile phone terminal, a tablet terminal, a notebook PC, a digital camera, a digital video camera, a portable audio device, a portable game device, or the like.

The housing 502 of the electronic device 500 accommodates a charging circuit 504 and a secondary battery 506 in addition to the reception coil L _RX and the power reception control IC 400. The charging circuit 504 receives the output voltage V _OUT of the power reception control IC 400 and charges the secondary battery 506. The layout of these components is not particularly limited.

The present invention has been described above based on the embodiment. It is understood by those skilled in the art that these embodiments are exemplifications, that various modifications can be made to the combinations of their respective constituent elements and respective processing processes, and that such modifications are also within the scope of the present invention. By the way. Hereinafter, such modified examples will be described.

(First modification)
In the embodiment, all gate signals of the first transistor M1 to the fourth transistor M4 are delayed in the overvoltage state, but the present invention is not limited to this. For example, the timing control unit 206 may delay the gate signals of the two low-side transistors M3 and M4. Furthermore, at least one gate signal may be delayed because it is sufficient to move away from the ideal zero current switching in the overvoltage state.

Alternatively, the timing control unit 206 may advance the switching timing of each transistor in the overvoltage state compared to the ideal timing of zero current switching.

(Second modified example)
The change amount of the switching timing when the overvoltage detection signal S _OVP is asserted, for example, the delay amount τ _OVP may be according to the slope of the voltage V _RECT of the rectification line 106. The larger the slope of the voltage V _RECT, the larger the delay amount τ _OVP , so that adaptive overvoltage protection can be realized. The slope of the voltage V _RECT may be detected by using a high-pass filter (differential circuit) or may be calculated from a digital value captured by the A/D converter.

(Third modification)
The change amount of the switching timing when the overvoltage detection signal S _OVP is asserted, for example, the delay amount τ _OVP may be according to the voltage level V _RECT of the rectification line 106. By increasing the delay amount τ _OVP as the rectified voltage V _RECT is higher, adaptive overvoltage protection can be realized. The voltage level of the rectified voltage V _RECT may be captured by an A/D converter, or may be detected by using a plurality of OVP comparators having different thresholds together.

(Fourth modification)
In the embodiment, the case where the full bridge circuit 102 is integrated in the same IC as the control circuit 200 has been described, but in high power applications, discrete elements may be used as the transistors M1 to M4 of the full bridge circuit 102. Good.

(Fifth Modification)
In the embodiment, the threshold voltage _V ZC1 _{~V ZC4} was near zero, may be set to the rectified voltage _{V RECT} side.

(Sixth Modification)
The synchronous rectification circuit 100 according to the embodiment can be suitably used as a wireless power supply rectification circuit in which the frequency of the power signal is higher than that of commercial AC. Note that the application of the synchronous rectification circuit 100 is not limited to this, and can be used for various applications such as an AC/DC converter.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments are defined in the claims. Many modifications and changes in arrangement are possible without departing from the concept of the present invention.

100... Synchronous rectification circuit, 102... Full bridge circuit, 104... Smoothing capacitor, 106... Rectification line, 108... Ground line, 200... Control circuit, 202... Zero current detection circuit, 204... Control logic, 206... Timing control section, 208... Driver, 210... OVP comparator, 300... Wireless power receiving device, L _RX ... Receiving coil, Cs, Cd... Resonant capacitor, 310... Regulator, 312... Controller, 314... Modulator, 400... Power receiving control IC, 500... Electronic Equipment, 502... Casing, 504... Charging circuit, 506... Secondary battery, M1... First transistor, M2... Second transistor, M3... Third transistor, M4... Fourth transistor.

Claims (13)

A control circuit that is used in a wireless power receiving device and forms a synchronous rectification circuit together with a full bridge circuit,
The wireless power receiving apparatus can transmit information indicating an error between a rectified voltage generated by the full bridge circuit and a target value to the wireless power transmitting apparatus, and the wireless power transmitting apparatus adjusts transmission power based on the information. Consists of
The full bridge circuit is
A first AC input and a second AC input connected to the receiving antenna;
An upper first transistor connected to the first AC input;
An upper second transistor connected to the second AC input;
A lower third transistor connected to the first AC input;
A lower fourth transistor connected to the second AC input;
Including,
The control circuit is
A zero-current detection circuit that compares at least one of the voltages of the first AC input and the second AC input to which the full bridge circuit is connected with a threshold voltage, and generates at least one detection signal indicating the comparison result;
A control logic for generating four control signals for instructing on/off of the fourth transistor from the first transistor forming the full-bridge circuit according to the at least one detection signal;
An overvoltage detection comparator that asserts an overvoltage detection signal when the voltage of the rectification line of the full bridge circuit exceeds an overvoltage threshold voltage,
A timing control unit that makes the switching timing of at least one of the four transistors different from the timing instructed by the control signal in response to the assertion of the overvoltage detection signal;
Equipped with
The control logic, in a normal state, in synchronization with the at least one detection signal,
(I) a first state in which the first transistor is off, the second transistor is on, the third transistor is on, and the fourth transistor is off,
(Ii) a second state in which the first transistor to the fourth transistor are off,
(Iii) a third state in which the first transistor is on, the second transistor is off, the third transistor is off, and the fourth transistor is on,
(Iv) A zero-current switching circuit that repeats the fourth state in which the first transistor is off, the second transistor is off, the third transistor is off, and the fourth transistor is off. .. The control circuit according to claim 1, wherein the timing control unit changes at least the switching timing of the third transistor and the fourth transistor in response to the assertion of the overvoltage detection signal. The control circuit according to claim 1, wherein the timing control unit changes a switching timing of the first transistor to the fourth transistor in response to assertion of the overvoltage detection signal. 4. The control according to claim 1, wherein the timing control unit includes a delay circuit that delays at least one of the four control signals in response to assertion of the overvoltage detection signal. circuit. The control circuit according to claim 4, wherein the delay amount of the delay circuit depends on a set value of a register. The control circuit according to claim 4, wherein a delay amount when the overvoltage detection signal is asserted is in accordance with a slope of a voltage of the rectification line. 5. The control circuit according to claim 4, wherein the delay amount when the overvoltage detection signal is asserted depends on the voltage level of the rectification line. The control circuit according to any one of claims 1 to 7, wherein the control circuit is integrated on one semiconductor substrate. Full bridge circuit,
The control circuit according to claim 1, which controls the full-bridge circuit,
And a rectifying circuit for rectifying a current of a receiving coil. A power receiving control circuit used in a wireless power receiving device,
The control circuit according to claim 1, which controls a full bridge circuit connected to the receiving coil,
A regulator that stabilizes the rectified voltage generated by the full bridge circuit,
A controller for generating data to be transmitted to the wireless power transmission device,
A modulator that modulates the data and superimposes it on the receiving coil;
A power reception control circuit comprising: A receiving coil,
A full bridge circuit connected to the receiving coil,
A smoothing capacitor connected to the full bridge circuit,
The control circuit according to claim 1, which controls the full-bridge circuit,
A regulator for stabilizing the rectified voltage generated in the smoothing capacitor,
A wireless power receiving device comprising: An electronic device comprising the wireless power receiving device according to claim 11. A method for controlling a full bridge circuit for rectifying a current flowing through a receiving coil of a wireless power receiving device,
Generating four control signals that transit at a timing at which the full bridge circuit can be soft-switched based on the voltages of the first AC input and the second AC input of the full bridge circuit;
Driving the full bridge circuit based on the four control signals;
When the rectified voltage, which is the output of the full bridge circuit, exceeds an overvoltage threshold voltage, delaying at least one of the four control signals to cause the full bridge circuit to perform a non-soft switching operation,
Equipped with
The full bridge circuit is
An upper first transistor connected to the first AC input;
An upper second transistor connected to the second AC input;
A lower third transistor connected to the first AC input;
A lower fourth transistor connected to the second AC input;
Including,
The full bridge circuit, in a normal state,
(I) a first state in which the first transistor is off, the second transistor is on, the third transistor is on, and the fourth transistor is off,
(Ii) a second state in which the first transistor to the fourth transistor are off,
(Iii) a third state in which the first transistor is on, the second transistor is off, the third transistor is off, and the fourth transistor is on,
(Iv) A control method comprising repeating the fourth state in which the first transistor is off, the second transistor is off, the third transistor is off, and the fourth transistor is off .

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