JP6703053B2 - Photoelectric conversion device, photoelectric conversion system - Google Patents

Description

The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Patent Document 1 describes a photoelectric conversion device including a photoelectric conversion unit, a capacitive element, a transfer transistor, and an amplifier. The photoelectric conversion unit includes a first electrode, a second electrode provided on the substrate side with respect to the first electrode, and a photoelectric conversion layer arranged between the first electrode and the second electrode. Have. Then, the capacitive element accumulates the signal output from the second electrode. The transfer transistor outputs the signal accumulated in the capacitive element to the amplifier.

JP-A-2002-350551

In the photoelectric conversion device of Patent Document 1, one capacitance element is provided for one photoelectric conversion unit. Therefore, there is a problem that the circuit area of the photoelectric conversion device increases.

The present invention has been made in view of the above problems, and in one aspect, a photoelectric conversion device having a pixel region in which a plurality of cells each including a plurality of photoelectric conversion units and an amplification unit are arranged. In the photoelectric conversion layer, each of the plurality of photoelectric conversion units is arranged between a first electrode, a second electrode, and the first electrode and the second electrode, and stores a signal charge. And an insulating layer disposed between the photoelectric conversion layer and the second electrode, wherein the amplification unit outputs an optical signal based on the signal charges accumulated in each of the photoelectric conversion units, Further, the photoelectric conversion device includes a capacitive element having a first node and a second node, and the first node includes the second electrode of each of the plurality of photoelectric conversion units and the amplifier. And a plurality of electric potentials having different values from each other are selectively supplied to the second node.

According to the present invention, the circuit area of the photoelectric conversion device can be reduced.

Diagram showing an example of the configuration of a photoelectric conversion device Diagram showing an example of the operation of the photoelectric conversion unit Diagram showing an example of the operation of the photoelectric conversion device Diagram showing an example of the operation of the photoelectric conversion device The figure which showed an example of the structure of a capacity drive part Diagram showing an example of the operation of the photoelectric conversion device Diagram showing an example of the operation of the photoelectric conversion device Diagram showing an example of the configuration of a photoelectric conversion device Diagram showing an example of the configuration of the photoelectric conversion system

Hereinafter, the photoelectric conversion device of each embodiment will be described with reference to the drawings.

(Example 1)
FIG. 1 is a diagram showing an example of the configuration of the photoelectric conversion device of the present invention.

The photoelectric conversion device 10 illustrated in FIG. 1 includes a pixel cell 1000, a capacitance drive unit 12, a vertical signal line 17, a current source 18, and a column amplification unit 19. The photoelectric conversion device 10 also includes a power supply unit 30a and a power supply unit 30b.

The pixel cell 1000 includes a unit pixel 10a, a unit pixel 10b, a reset unit 14, and a pixel output unit 16.

The unit pixel 10a has a photoelectric conversion unit 101a and a transfer transistor 15a. Further, the unit pixel 10b has a photoelectric conversion unit 101b and a transfer transistor 15b. The photoelectric conversion unit 101a includes a first electrode 201, a blocking layer 203, a photoelectric conversion layer 205, an insulating layer 207, and a second electrode 209. The blocking layer 203 is provided between the first electrode 201 and the photoelectric conversion layer 205, and the photoelectric conversion layer 205 is provided between the blocking layer 203 and the insulating layer 207. The insulating layer 207 is provided between the photoelectric conversion layer 205 and the second electrode 209. The photoelectric conversion unit 101b can have the same configuration as the photoelectric conversion unit 101a. In the following description, the photoelectric conversion unit 101a will be described. Is the same as. Each of the transfer transistors 15a and 15b is provided corresponding to each of the plurality of photoelectric conversion units 101a and 101b. Each of the transfer transistors 15a and 15b is a transfer unit that transfers the optical signal of each of the plurality of photoelectric conversion units 101a and 101b to the amplification transistor 16a that is an amplification unit.

The first electrode 201 is composed of a conductive member having a high transmittance of light in a wavelength range in which the photoelectric conversion layer 205 has sensitivity. For example, a compound containing indium and/or tin such as ITO (Indium Tin Oxide) or a compound such as ZnO is used as the material of the first electrode 201. As a result, the photoelectric conversion layer 205 of the present embodiment can capture more light than in the case where an opaque electrode such as copper is used as the first electrode 201. As another example, the first electrode 201 of this embodiment may be formed of polysilicon or metal having a thinness enough to transmit a predetermined amount of light.

The blocking layer 203 reduces injection of charges having the same polarity as the signal charges accumulated in the photoelectric conversion layer 205 from the first electrode 201 into the photoelectric conversion layer 205. The photoelectric conversion layer 205 is depleted due to the potential difference between the potential Vs applied to the first electrode 201 and the potential of the second electrode 209. Further, the potential gradient of the photoelectric conversion layer 205 is inverted depending on the relationship between the potential Vs applied to the first electrode 201 and the potential of the second electrode 209. With such a structure, the photoelectric conversion layer 205 can accumulate signal charges and discharge the accumulated signal charges. The operation of the photoelectric conversion unit 101a will be described later.

In this embodiment, the power supply voltage supplied to the first electrode 201 is the potential Vs supplied from the power supply units 30a and 30b.

The photoelectric conversion layer 205 is formed of intrinsic amorphous silicon (hereinafter a-Si), low-concentration P-type a-Si, low-concentration N-type a-Si, or the like. Alternatively, the photoelectric conversion layer 205 may be formed of a compound semiconductor. Examples thereof include III-V group compound semiconductors such as BN, GaAs, GaP, AlSb, and GaAlAsP, II-VI group compound semiconductors such as CdSe, ZnS, and HdTe, and IV-VI group compound semiconductors such as PbS, PbTe, and CuO. .. Alternatively, the photoelectric conversion layer 205 may be formed of an organic material. For example, fullerene, coumarin 6 (C6), rhodamine 6G (R6G), zinc phthalocyanine (ZnPc), quinacridone, phthalocyanine compound, naphthalocyanine compound and the like can be used. Further, as the photoelectric conversion layer 205, a quantum dot film including the above compound semiconductor can be used.

When the photoelectric conversion layer 205 is formed of a semiconductor, the impurity concentration of the semiconductor may be low or the semiconductor may be intrinsic. With such a configuration, the depletion layer can be sufficiently widened in the photoelectric conversion layer 205, so that effects such as high sensitivity and noise reduction can be obtained.

For the blocking layer 203, an N-type or P-type semiconductor that is the same material as the semiconductor used for the photoelectric conversion layer 205 and has a higher impurity concentration than the semiconductor used for the photoelectric conversion layer 205 can be used. For example, when a-Si is used for the photoelectric conversion layer 205, N-type a-Si doped with impurities or P-type a-Si doped with impurities is used for the blocking layer 203. Since the position of the Fermi level differs depending on the difference in impurity concentration, the blocking layer 203 functions as a potential barrier for only one of electrons and holes.

When the photoelectric conversion layer 205 includes a quantum dot film, a blocking layer 203 having the same material as the semiconductor used for the quantum dot film and having a conductivity type opposite to that of the quantum dot film may be provided. For example, when the quantum dot film is P-type PbS, the blocking layer 203 may be N-type PbS. Further, even if the blocking layer 203 is made of the same material as the quantum dot film and has the same conductivity type, the impurity concentration may be different between the quantum dot film and the blocking layer 203.

Alternatively, the blocking layer 203 can be made of a material different from that of the photoelectric conversion layer 205. With this structure, a heterojunction is formed. Since the bandgap differs depending on the material, the potential barrier can be formed only for one of the electron and the hole. When the photoelectric conversion layer 205 includes a quantum dot film, for example, PbS may be used as the quantum dot film and ZnO may be used for the blocking layer 203.

The insulating layer 207 is provided between the photoelectric conversion layer 205 and the second electrode 209. For example, as the material of the insulating layer 207, amorphous silicon oxide (hereinafter a-SiO), amorphous silicon nitride (a-SiN), or organic material is used. The thickness of the insulating layer 207 is preferably set such that signal charges are not transmitted due to a tunnel effect. With such a configuration, the leak current can be reduced, and thus noise can be reduced. Specifically, the thickness of the insulating layer 207 is preferably 50 nm or more.

When an amorphous film is used for the blocking layer 203, the photoelectric conversion layer 205, and the insulating layer 207, hydrogenation treatment may be performed to terminate the dangling bond with hydrogen. With such a configuration, noise can be reduced.

The second electrode 209 is made of a conductive material such as metal. The second electrode 209 is made of the same material as the conductive member that forms the wiring or the conductive member that forms the pad electrode for connecting to the outside. With such a configuration, the photoelectric conversion unit 101a of the present embodiment can simultaneously form the second electrode 209 and the conductive member forming the wiring or the pad electrode. Therefore, the photoelectric conversion unit 101a of the present embodiment can be manufactured by a simplified manufacturing process as compared with the case where the second electrode 209 is made of a material different from that of the conductive member or the pad electrode forming the wiring. ..

The first electrode 201 of the photoelectric conversion unit 101a is electrically connected to the power supply unit 30a. The power supply unit 30a supplies the potential Vs to the first electrode 201. The first electrode of the photoelectric conversion unit 101b is electrically connected to the power supply unit 30b. The power supply unit 30b supplies the potential Vs to the first electrode of the photoelectric conversion unit 101b.

The transfer transistor 15a is electrically connected to the second electrode 209 of the photoelectric conversion unit 101a. The transfer transistor 15b is electrically connected to the second electrode of the photoelectric conversion unit 101b. A signal φT1 is input to the gate of the transfer transistor 15a from a vertical scanning circuit (not shown). The signal φT2 is input to the gate of the transfer transistor 15b from a vertical scanning circuit (not shown).

The reset unit 14 has a reset transistor 14a. The reset potential Vres is supplied to one of a source and a drain of the reset transistor 14a, and the other of the source and the drain is electrically connected to the node FD. The reset potential Vres is a potential smaller than the potential Vs. In this embodiment, the potential Vs is 5V and the reset potential Vres is 2V. A signal φRES is input to the gate of the reset transistor 14a from a vertical scanning circuit (not shown).

The capacitance drive unit 12 has a buffer circuit 12a and a capacitance element 12b. A first node, which is one node of the capacitor 12b, is electrically connected to the node FD. Further, the first node of the capacitive element 12b is electrically connected in common to each of the photoelectric conversion units 101a and 101b via each of the transfer transistors 15a and 15b that are the transfer units. The second node, which is the other node of the capacitor 12b, is electrically connected to the buffer circuit 12a. A signal φVp is input to the buffer circuit 12a from a timing generator (not shown) provided separately from the vertical scanning circuit. The buffer circuit 12a supplies the potential obtained by buffering the potential of the signal φVp to the capacitive element 12b. The timing generator (not shown) is a potential supply unit that supplies signals φVp having different potentials to the capacitive element 12b via the buffer circuit 12a.

The capacitive element 12b is electrically connected to the node FD. The capacitive element 12b includes, for example, two electrodes facing each other. The two electrodes are made of a material such as polysilicon or metal. Alternatively, the capacitive element 12b is configured to include a semiconductor region and a polysilicon electrode arranged on the semiconductor region. With the configuration in which the capacitive element 12b is connected to the node FD, noise can be reduced when the optical signal is read from the photoelectric conversion unit 101a. This noise reduction operation will be described.

In the photoelectric conversion device of this embodiment, the potential of the node FD is controlled. The potential of the second electrode 209 of the photoelectric conversion unit 101a is the capacitance value of the node FD (the gate capacitance of the amplification transistor 16a) and the capacitance value of the capacitance component between the first electrode 201 and the second electrode 209 ( Hereafter, the capacitance value of the photoelectric conversion unit 101a). This is because the node FD and the photoelectric conversion unit 101a can be regarded as two capacitors connected in series.

In the photoelectric conversion device of this embodiment, the potential of the node FD is controlled. The potential of the second electrode 209 of the photoelectric conversion portion 101a includes a capacitance element 12b, a gate capacitance of the amplification transistor 16a connected to the node FD, and a capacitance component between the first electrode 201 and the second electrode 209. Of the photoelectric conversion unit 101a and the combined capacitance value thereof (hereinafter, referred to as the capacitance value of the photoelectric conversion unit 101a). This is because the capacitive element 12b and the combined capacitance can be regarded as two capacitors connected in series.

In the photoelectric conversion device of this embodiment, the larger the capacitance value of the capacitive element 12b, the larger the amount of change in the potential of the second electrode 209 when the signal φVp is changed.

According to this embodiment, the capacitive element 12b is electrically connected to the node FD. A node of the capacitor 12b to which the potential of the signal φVp is input and the node FD are electrically separated from each other.

Therefore, when the potential of the second electrode 209 is controlled to read the optical signal from the photoelectric conversion unit 101a, a large potential difference can be applied between the first electrode 201 and the second electrode 209. As a result, the photoelectric conversion device of this embodiment can easily deplete the photoelectric conversion layer 205. This improves the sensitivity of the photoelectric conversion unit 101a to the incident light. In addition, noise included in the optical signal can be reduced by setting the potential at the time of starting the accumulation of the signal charge based on the incident light of the photoelectric conversion layer 205 to be a substantially constant potential.

The pixel output unit 16 has an amplification transistor 16a and a selection transistor 16b. The gate of the amplification transistor 16a is electrically connected to the node FD. The potential Vdd is input to one of the source and the drain of the amplification transistor 16a, and the other of the source and the drain is electrically connected to one of the source and the drain of the selection transistor 16b. The other of the source and the drain of the selection transistor 16b is electrically connected to the vertical signal line 17. The signal φSEL is input to the gate of the selection transistor 16b from a vertical scanning circuit (not shown). The amplification transistor 16a, which is the amplification unit, outputs a signal obtained by amplifying the signal output from the second electrode 209.

The current source 18 is electrically connected to the selection transistor 16b via the vertical signal line 17. When the selection transistor 16b is turned on, the amplification transistor 16a and the current source 18 form a source follower circuit.

The input node of the column amplification unit 19 is electrically connected to the vertical signal line 17. The output node of the column amplification unit 19 is electrically connected to a signal holding unit (not shown). The signal holding unit (not shown) is electrically connected to the output unit (not shown). The signal output by the output unit (not shown) is a signal output by the photoelectric conversion device to the outside of the photoelectric conversion device.

In the photoelectric conversion device illustrated in FIG. 1, one capacitance element 12b and one amplification transistor 16a are provided for the photoelectric conversion units 101a and 101b, which are a plurality of photoelectric conversion units. That is, one capacitance element 12b and one amplification transistor 16a are shared by the photoelectric conversion unit 101a and the photoelectric conversion unit 101b.

Although only one pixel cell 1000 is shown in FIG. 1, a plurality of pixel cells are actually arranged in thousands rows and thousands columns. Further, each of the vertical signal line 17, the current source 18, and the column amplification unit 19 is provided in a plurality of columns corresponding to the column in which the plurality of pixel cells 1000 are arranged. The plurality of pixel cells 1000 are provided in the pixel area. The column amplification unit 19 is provided in the peripheral circuit area provided outside the pixel area. The peripheral circuit region is, for example, a region outside the orthogonal projection of the first electrode 201 provided commonly to the plurality of photoelectric conversion units 101.

Next, the operation of the photoelectric conversion unit 101a in this embodiment will be described. Each of FIGS. 2A to 2D schematically shows an energy band in the photoelectric conversion unit 101a. In each of FIGS. 2A to 2D, energy bands of the first electrode 201, the blocking layer 203, the photoelectric conversion layer 205, the insulating layer 207, and the second electrode 209 are shown. The vertical axis of FIG. 2 represents the potential for electrons. The higher towards the top of FIG. 2, the higher the potential for electrons. Therefore, the potential becomes lower toward the bottom of FIG. The Fermi level is shown for the first electrode 201 and the second electrode 209. For the blocking layer 203 and the photoelectric conversion layer 205, the band gap between the energy level of the conduction band and the energy level of the valence band is shown.

As the operation of the photoelectric conversion unit 101a, the following steps (1) to (5) are repeated. (1) resetting the input node of the amplifier, (2) reading a noise signal, (3) transferring signal charges from the photoelectric converter, (4) reading optical signals, and (5) accumulating signal charges. Each step will be described below.

FIG. 2A shows the state of the photoelectric conversion unit 101a from step (1) to step (2). The potential Vs is supplied to the first electrode 201. The first potential Vs is, for example, 3V. Holes indicated by white circles are accumulated in the photoelectric conversion layer 205 as signal charges generated during the exposure period. The surface potential of the photoelectric conversion layer 205 on the insulating layer 207 side changes depending on the amount of accumulated holes. Further, the buffer circuit 12a supplies the first potential Vd1 to the capacitive element 12b. The first potential Vd1 is, for example, 0V.

In this state, the reset transistor 14a is turned on. Thus, the potential of the node including the second electrode 209, that is, the node FD is reset to the reset potential Vres. The reset potential Vres is, for example, 1V. Since the node FD is connected to the gate of the amplification transistor 16a, the node FD is an input node of the amplification section. Therefore, the input node of the amplifier is reset.

Then, the reset transistor 14a is turned off. As a result, the node FD becomes electrically floating. At this time, reset noise (noise kTC1 in FIG. 2) due to the reset transistor 14a may occur. At this time, the holes of the signal charge are still accumulated in the photoelectric conversion layer 205.

When the selection transistor 105 is turned on, the amplification transistor 16a outputs a noise signal including reset noise.

2B and 2C show the state of the photoelectric conversion unit 101a in step (3). First, the buffer circuit 12a supplies the second potential Vd2 to the capacitive element 12b. Since holes are used as signal charges, the second potential Vd2 is higher than the first potential Vd1. The second potential Vd2 is, for example, 5V.

At this time, the potential of the second electrode 209 (node FD) changes in the same direction as the change in the potential supplied by the buffer circuit 12a. The amount of change dVB in the potential of the second electrode 209 is determined according to the ratio between the capacitance value C1 of the capacitance element 12b electrically connected to the node FD and the capacitance value C2 of the photoelectric conversion unit 101a. dVB is
dVB=(Vd2-Vd1)*C1/(C1+C2) (1)
Is expressed as In the following description, for simplification of description, it is assumed that the capacitance value C1 and the capacitance value C2 are equal. Therefore, the change amount dVB is
dVB=(Vd2-Vd1)×(1/2) (2)
Is expressed as In this embodiment, the capacitance value of the photoelectric conversion unit 101b is also equal to the capacitance value C2 of the photoelectric conversion unit 101b.

In this embodiment, the change amount dVB of the potential of the second electrode 209 is sufficiently larger than the difference (Vs−Vres) between the potential Vs of the first electrode 209 and the reset potential Vres. Therefore, the potential of the second electrode 209 becomes lower than the potential of the first electrode 201, and the slope of the potential of the photoelectric conversion layer 205 is inverted. As a result, electrons indicated by black circles are injected from the first electrode 209 to the photoelectric conversion layer 205. Further, some or all of the holes accumulated in the photoelectric conversion layer 205 as signal charges move toward the blocking layer 203. The moved holes are recombined with majority carriers of the blocking layer 203 and disappear. As a result, holes in the photoelectric conversion layer 205 are discharged from the photoelectric conversion layer 205. When the entire photoelectric conversion layer 205 is depleted, all the holes accumulated as signal charges are discharged.

Next, in the state shown in FIG. 2C, the buffer circuit 12a supplies the first potential Vd1 to the capacitive element 12b. As a result, the slope of the potential of the photoelectric conversion layer 205 is inverted again. Therefore, the electrons injected into the photoelectric conversion layer 205 in the state of FIG. 2B are discharged from the photoelectric conversion layer 205. On the other hand, the blocking layer 203 reduces injection of holes from the first electrode 201 into the photoelectric conversion layer 205. Therefore, the potential of the node FD changes from the reset state by the potential Vsig according to the amount of the disappeared holes. That is, the potential Vsig corresponding to the amount of holes accumulated as signal charge appears at the node FD. The potential Vsig corresponding to the amount of accumulated holes is called an optical signal component.

Here, in the state shown in FIG. 2C, the selection transistor 16b is turned on. As a result, the amplification transistor 16a outputs an optical signal. The difference between the noise signal read in step (2) and the optical signal read in step (4) is a signal based on the potential Vsig corresponding to the accumulated signal charge.

FIG. 2D shows the state of the photoelectric conversion unit 101a in step (5). The potential Vs is supplied to the first electrode 201 and the reset potential Vres is supplied to the node FD. Since the reset potential Vres is lower than the potential Vs of the first electrode 201, the electrons of the photoelectric conversion layer 205 are discharged to the first electrode 201. On the other hand, the holes in the photoelectric conversion layer 205 move toward the interface between the photoelectric conversion layer 205 and the insulating layer 207. However, the holes cannot be moved to the insulating layer 207 and thus are accumulated in the photoelectric conversion layer 205. In addition, as described above, the blocking layer 203 reduces injection of holes into the photoelectric conversion layer 205. Therefore, when light enters the photoelectric conversion layer 205 in this state, only holes out of electron hole pairs generated by photoelectric conversion are accumulated in the photoelectric conversion layer 205 as signal charges. The potential Vch is a potential at which the second electrode 209 changes based on holes accumulated in the photoelectric conversion layer 205.

When the signal charge is an electron, the second potential Vd2 may be lower than the first potential Vd1. Further, the conductivity type of the blocking layer 203 may be opposite to that of the blocking layer 203 of this embodiment. Therefore, the inclination of the potential in FIGS. 2A to 2D is inverted. Other operations are the same.

Next, a timing chart of the photoelectric conversion device shown in FIG. 1 will be described with reference to FIG.

FIG. 3A shows an operation of individually outputting signals from the photoelectric conversion units 101a and 101b to the node FD. On the other hand, FIG. 3B shows an operation in which a signal obtained by adding optical signals generated by the photoelectric conversion units 101a and 101b is output to the node FD. The signals shown in FIGS. 3A and 3B correspond to the signals shown in FIG. With respect to the signal φS/H shown in FIGS. 3A and 3B, a timing generator (not shown) controls the sampling operation of a signal holding unit (not shown) provided in the subsequent stage of the column amplification unit 19. It is a signal. The signal holding unit holds the signal output from the column amplification unit 19 when the signal level of the signal φS/H changes from the Hi level (hereinafter, Hi) to the Lo level (hereinafter, Lo).

First, the operation shown in FIG. 3A will be described. The operation in the period T0-1 shown in FIG. 3A is the operation relating to the photoelectric conversion unit 101a. Further, the operation in the period T0-2 is the operation relating to the photoelectric conversion portion 101b.

At time t1, the vertical scanning circuit (not shown) changes the signal levels of the signal φRES and the signal φT1 from the Lo level (hereinafter, referred to as Lo) to the Hi level (hereinafter, referred to as Hi). The reset transistor 14a whose gate receives the Hi signal φRES is turned on. As a result, the potential of the node FD is reset to the potential Vd1. Further, the transfer transistor 15a to which the Hi signal φT1 is input to the gate is turned on. Accordingly, the electric path between the second electrode 209 of the photoelectric conversion unit 101a and the node FD is changed from the non-conduction state to the conduction state, so that the potential of the second electrode 209 is reset to the potential Vd1. Further, the vertical scanning circuit sets the signal φSEL to Hi. As a result, the selection transistor 16b is turned on. Therefore, the amplification transistor 16a outputs a signal based on the potential of the node FD to the vertical signal line 17.

At time t2, the vertical scanning circuit (not shown) changes the signal φRES from Hi to Lo. As a result, the reset of the node FD is released. The operation in the period T1-1 from the time t1 to the time t2 is the operation corresponding to step (2) described above.

After that, the timing generator (not shown) changes the signal level of the signal φS/H from Lo to Hi and then sets it to Lo again. The signal holding unit holds the signal output from the column amplification unit 19 when the signal level of the signal φS/H changes from Hi to Lo. At this time, the signal output from the column amplification unit 19 is a noise signal. This operation corresponds to step (2) described above. In FIG. 3A, the operation related to the holding of the noise signal by the signal holding unit is represented by N.

Note that in the period until the time t3 is reached, the buffer circuit 12a supplies the first potential Vd1 to the capacitive element 12b based on the Lo signal φVp. The signal φVp of Lo is 0V in this embodiment. The buffer circuit 12a supplies the first potential Vd1, which is 0 V, to the capacitive element 12b.

At time t3, the timing generator changes the signal level of the signal φVp from 0V which is Lo to 10V which is Hi. Further, based on the Hi signal φVp, the buffer circuit 12a supplies the second potential Vd2 of 10 V to the capacitive element 12b. The change amount dVB of the potential of the second electrode 209 is dVB=(10−0)×(1/2)=5(V) according to the above equation (2). Therefore, the potential of the second electrode 209 is a potential obtained by applying 5 V to the reset potential Vres.

By inputting the Hi signal φVp, the holes of the photoelectric conversion layer 205 are refreshed as shown in FIG. After that, the timing generator sets the signal φVp to Lo. As a result, an optical signal is output to the second electrode 209 as shown in FIG. This operation corresponds to step (3) described above. Since the transfer transistor 15a is turned on, the electrical path between the second electrode 209 of the photoelectric conversion unit 101a and the amplification transistor 16a is in a conductive state. Therefore, the amplification transistor 16a outputs a signal based on the optical signal to the vertical signal line 17. This operation corresponds to step (4) described above. The column amplification unit 19 outputs a signal obtained by amplifying a signal based on the optical signal output by the amplification transistor 16a (hereinafter referred to as an amplified optical signal).

After that, the timing generator sets the signal φS/H to Hi and then to Lo. As a result, the signal holding unit holds the amplified optical signal output by the column amplification unit 19. In FIG. 3A, the operation related to holding the amplified optical signal of the signal holding unit is denoted by S.

Next, in the period from time t5 to time t6, the residual charge of the lower electrode of the photoelectric conversion unit 101a is reset. As a result, the photoelectric conversion unit 101a is ready to perform accumulation of signal charges based on light again, as shown in FIG. This operation is a preparation operation for performing the operation of step (5).

At time t6, the vertical scanning circuit sets the signal φT1 to Lo. Further, the vertical scanning circuit sets the signal φSEL to Lo. As a result, the selection transistor 16b is turned off. As a result, the output of the signal based on the signal charges accumulated in the photoelectric conversion unit 101a to the vertical signal line 17 is completed.

By obtaining the difference between the noise signal and the amplified optical signal held by the signal holding unit, it is possible to obtain a signal in which the noise component included in the amplified optical signal is reduced.

After that, also in the photoelectric conversion unit 101b, by performing the same operation as that performed using the photoelectric conversion unit 101a, a signal based on the signal charge accumulated in the photoelectric conversion unit 101b is output to the vertical signal line 17.

Next, the operation shown in FIG. 3B will be described. In the following description, the points different from the operation described with reference to FIG. The operation illustrated in FIG. 3B is an operation of adding the optical signals of the photoelectric conversion unit 101a and the photoelectric conversion unit 101b at the node FD.

At time t10, the vertical scanning circuit changes the signal levels of both the signal φT1 and the signal φT2 from Lo to Hi. As a result, both the transfer transistor 15a and the transfer transistor 15b are turned on. Further, the signal φRES is set to Hi. Accordingly, the potentials of the second electrodes 209 of both the photoelectric conversion units 101a and 101b and the potential of the node FD are reset based on the reset potential Vres.

At time t11, the vertical scanning circuit sets the signal φRES to Lo.

After that, the timing generator sets the signal φS/H to Hi and then to Lo. As a result, the signal holding unit holds the noise signal.

At time t12, the timing generator changes the signal level of the signal φVp from 0V which is Lo to 15V which is Hi. Here, the point that the signal level of the Hi signal φVp is set to 15V will be described. The change amount dVB of the potential of the second electrode 209 expressed by the above formula (1) is set to C3 when the capacitance value of the photoelectric conversion unit 101b is C3 in the operation shown in FIG. 3B.
dVB=(Vd2-Vd1)*C1/(C1+C2+C3) (3)
Becomes In the present embodiment, since C1=C2=C3 is set as described above, the formula (3) is
dVB=(Vd2-Vd1)×(1/3) (4)
Can be rewritten as In order to set the amount of change dVB of the potential of the second electrode 209 of each of the photoelectric conversion unit 101a and the photoelectric conversion unit 101b to 5V as in the operation of FIG. 3A, Vd1=0 (V) is satisfied. , Vd2=15 (V). Therefore, the signal φVp is set to 15V. As shown in FIG. 3A, the signal level of Hi of the signal φVp is 3/2 times that when the optical signals are individually read from the photoelectric conversion units 101a and 101b.

The signal φVp is changed from Hi to Lo. Further, since both the transfer transistors 15a and 15b are turned on, the electrical path between the second electrode 209 of the photoelectric conversion units 101a and 101b and the amplification transistor 16a is in a conductive state. Therefore, optical signals are output to the node FD from the second electrodes 209 of the photoelectric conversion units 101a and 101b. The potential of the node FD is the potential of the signal obtained by adding the optical signals of the photoelectric conversion unit 101a and the photoelectric conversion unit 101b.

After that, the timing generator sets the signal φS/H to Hi and then to Lo. As a result, the signal holding unit holds the signal obtained by sequentially amplifying the optical signals of the photoelectric conversion unit 101a and the photoelectric conversion unit 101b by the amplification transistor 16a and the column amplification unit 19.

As described above, the photoelectric conversion device according to the present embodiment can individually read the optical signal of each of the plurality of photoelectric conversion units in the operation illustrated in FIG. Further, in the operation shown in FIG. 3B, the photoelectric conversion apparatus of the present embodiment adds the signals obtained by adding the optical signals of the plurality of photoelectric conversion units at the node FD that is the input node of the amplification unit, Can be read.

Further, in the photoelectric conversion device of this embodiment, one capacitance element 12b and one amplification transistor 16a are shared by the plurality of photoelectric conversion units 101a and 101b. As a result, the circuit area of the pixel cell can be reduced as compared with the case where one capacitance element 12b and one amplification transistor 16a are individually provided for each of the plurality of photoelectric conversion units 101a and 101b. it can.

In some cases, RGB color filters are provided in a Bayer array, and a plurality of photoelectric conversion units are provided for each color. In this case, one capacitance element 12b and one amplification transistor 16a may be shared by a plurality of photoelectric conversion units in which color filters of the same color are arranged.

Further, the signal φVp was input from the timing generator to the capacitive element 12b via the buffer 12a. As another example, as shown in FIG. 8, the signal φVp may be input from the timing generator to the capacitive element 12b without passing through the buffer 12a.

In addition, in this embodiment, the configuration in which one amplification transistor 16a is shared by the plurality of photoelectric conversion units 101a and 101b has been described. As another example, as shown in FIG. 8, each of the plurality of photoelectric conversion units 101a and 101b may be provided with each of the plurality of amplification transistors 16a. For example, in the case of a configuration in which a plurality of pixel cells 1000 are arranged in a matrix, each of the plurality of pixel cells 1000 has the same number of amplification transistors 16 as the number of photoelectric conversion units included in each pixel cell 1000. The pixel cells 1000 belonging to the same row may share one capacitive element 12a. In the configuration in which the plurality of capacitance elements 12b are provided, it is preferable that each of the plurality of buffer circuits 12a be provided corresponding to each of the plurality of capacitance elements 12b. Since the buffer circuit 12a is provided corresponding to the capacitive element 12b in this way, the load on the potential supply unit can be reduced.

In this embodiment, the configuration in which the two photoelectric conversion units 101a and 101b share one capacitance element 12b and one amplification transistor 16a has been described. A plurality of photoelectric conversion units may share one capacitance element 12b and one amplification transistor 16a. In addition, in the plurality of photoelectric conversion units 101 that are electrically connected to the node FD in common, the number of optical signals read out to the node FD at the same time is N (N is an integer of 1 or more). In the case of M, which is larger than the number, the signal level of Hi of the signal φVp is increased. This is a case where the optical signal output from the photoelectric conversion unit 101 has holes as signal charges accumulated by the photoelectric conversion unit 101. When the signal charges accumulated in the photoelectric conversion unit 101 are electrons, the number of optical signals read out to the node FD at the same time is N (N is an integer of 1 or more), and M is more than N. In this case, the signal level of Hi of the signal φVp is made smaller.

In addition, the photoelectric conversion device of the present embodiment has the operation of individually reading an optical signal from each of the plurality of photoelectric conversion units illustrated in FIG. 3A and the plurality of photoelectric conversions illustrated in FIG. The operation of reading out a signal obtained by adding the optical signals of the other units may be combined. An example of such an operation is shown in FIG.

A period from time t21 to time t26 is a period in which operations related to reading the noise signal and the optical signal of the photoelectric conversion unit 101a are performed. A period from time t27 to time t31 is a period in which an operation relating to reading of a signal obtained by adding optical signals of the photoelectric conversion unit 101a and the photoelectric conversion unit 101b is performed. By this operation, the signal holding unit holds the optical signal of the photoelectric conversion unit 101a at time t26, that is, the A signal which is the signal amplified by the amplification transistor 16a and the column amplification unit 19. At time t29, the signal holding unit holds the signal A+B which is the signal obtained by amplifying the signal obtained by adding the optical signals of the photoelectric conversion units 101a and 101b to each other by the amplification transistor 16a and the column amplification unit 19. .. The photoelectric conversion device outputs the A signal and the A+B signal to the outside of the photoelectric conversion device, respectively.

Here, an example of a photoelectric conversion system including a photoelectric conversion device and an output signal processing unit which processes a signal output from the photoelectric conversion device will be described. The output signal processing unit provided outside the photoelectric conversion device can obtain the B signal by subtracting the A signal from the A+B signal. The B signal generated by the output signal processing unit is a signal corresponding to a signal obtained by amplifying the optical signal of the photoelectric conversion unit 101b by the amplification transistor 16a and the column amplification unit 19. The photoelectric conversion device may further include a microlens array provided with a plurality of microlenses, and one microlens may be provided for one photoelectric conversion unit 101a or 101b. In this case, light emitted from different exit pupils of the optical system that guides light to the photoelectric conversion device enters each of the plurality of photoelectric conversion units 191a and 101b. In the case of this configuration, the output signal processing unit uses the B signal generated by the output signal processing unit and the A signal output by the photoelectric conversion device to cause the light incident on the photoelectric conversion unit 101a and the photoelectric conversion unit 101b. The phase difference with the incident light can be detected. Accordingly, the photoelectric conversion system including the photoelectric conversion device and the output signal processing unit can perform focus detection by the phase difference detection method. The output signal processing unit can also generate an image using the A+B signal output from the photoelectric conversion device.

In this example, the potential of the second electrode 209 was controlled when reading the optical signal based on the signal charge of the photoelectric conversion unit 101. As another example, the photoelectric conversion device of the present embodiment may control the first electrode 201 when reading an optical signal based on the signal charge of the photoelectric conversion unit 101. In this case, the node of the capacitive element 12b electrically connected to the buffer circuit 12a in the present embodiment may be supplied with a fixed potential such as the ground potential.

Although the pixel cell 1000 is provided with the transfer transistor 15 in this embodiment, the transfer transistor 15 may not be provided. That is, the first node, which is one node of the capacitor 12b, may be directly connected to the second electrodes 209 of the photoelectric conversion units 101a and 101b. In this case, the first electrode 201 of the photoelectric conversion unit 101 that does not output an optical signal is set in a floating state during a period in which the signal level of the signal φVp is Hi. On the other hand, the potential Vs is supplied to the first electrode 201 of the photoelectric conversion unit 101 which outputs an optical signal. Thereby, even when the transfer transistor 15 is not provided in the pixel cell 1000, the optical signal is selectively read from the plurality of photoelectric conversion units 101 electrically connected to the node FD to the amplification transistor 16a. You can

The photoelectric conversion unit 101 of this embodiment may be a Schottky photoelectric conversion unit.

The photoelectric conversion device of this embodiment includes a plurality of photoelectric conversion units 10a and 10b and an amplifier 16a. Each of the plurality of photoelectric conversion units 10a and 10b includes a first electrode 201, a second electrode 209, a photoelectric conversion layer 205 that accumulates signal charges, and an insulating layer 207. The first node of the capacitive element 12b is electrically connected to the second electrode 209 of each of the photoelectric conversion units 10a and 10b and the amplification unit 16a. A plurality of potentials having different values are selectively input to the second node of the capacitor 12b. With this configuration, since the capacitive element 12b is shared by the plurality of photoelectric conversion units 12a and 12b, the capacitance of the capacitive element 12b is larger than that of the case where one photoelectric conversion unit has one capacitive element 12b. The number can be reduced. The photoelectric conversion device of the present embodiment can reduce the circuit area of the photoelectric conversion device by reducing the number of the capacitive elements 12b.

(Example 2)
Another example of the capacitance drive unit 12 will be described with reference to the configuration diagram of FIG. 5 and the timing diagrams of FIGS. 6A and 6B.

In the capacitance drive unit 12b of this embodiment, the switches connected in series to the capacitance element C11 and the capacitance element C12 are configured in parallel.

The switch is controlled by the pulse φCsel.

FIG. 6A shows the operation of individually reading the optical signals of the photoelectric conversion units 101a and 101b. In the operation of FIG. 6A, the timing generator sets the signal φCsel to Lo. As a result, the photoelectric conversion units 101a and 101b are individually driven by using the capacitive element C11 without using the capacitive element C12. The operation shown in FIG. 6A is the same as the operation shown in FIG. 3A except for the signal φCsel. The Hi signal level of the signal φVp is also 10 V in the operation shown in FIG. 6A, which is the same as that in FIG. 3A.

FIG. 6B shows an operation of reading a signal obtained by adding optical signals of the plurality of photoelectric conversion units 101a and 101b at the node FD.

In the operation of FIG. 6B, the timing generator sets the signal φCsel to Hi. Therefore, the two photoelectric conversion units 101a and 101b are driven by the combined capacitance of the capacitive element C11 and the capacitive element C12. In this embodiment, the capacitance value of the capacitive element C12 is the same as the capacitance value of the capacitive element C11. As a result, the potential of the second electrode 209 of the two photoelectric conversion units 101a and 101b can be maintained without changing the signal level of the Hi signal φVp from the same signal level of 10 V as in the case of the operation shown in FIG. 6A. Can be a potential obtained by applying 5 V to the reset potential Vres. The capacitance drive unit 12 according to the present exemplary embodiment separately outputs the signal φVp when reading the optical signals of the plurality of photoelectric conversion units 101a and 101b individually and when adding and reading the optical signals of the plurality of photoelectric conversion units 101a and 101b. Can be operated without changing the Hi signal level. As a result, the configuration of the circuit that supplies the signal φVp can be simplified in the photoelectric conversion device of the present embodiment as compared with the photoelectric conversion device of the first embodiment.

In the operation of FIG. 6B of this embodiment, the number of photoelectric conversion units that add optical signals is two, but it may be three or more. The number of capacitance elements provided in parallel with the capacitance element C11 of the capacitance drive unit 12 is the optical signal in the mode in which the number of photoelectric conversion units that add the optical signals is maximum in the operation mode of the photoelectric conversion device. Is preferably the same as the number of photoelectric conversion units to which is added.

In this embodiment, a plurality of photoelectric conversion units 101a and 101b share one amplification unit. As a result, the photoelectric conversion device of the present embodiment can reduce the circuit area of the pixel cell in comparison with the configuration in which each of the plurality of amplification units is provided for each of the plurality of photoelectric conversion units 101a and 101b.

In addition, in the present embodiment, the capacitance drive unit 12 is shared by the plurality of photoelectric conversion units 101a and 101b. As a result, the photoelectric conversion device according to the present embodiment can reduce the circuit area of the pixel cell 1000 as compared with the case where the capacitance driving unit 12 is provided in each of the plurality of photoelectric conversion units 101a and 101b.

Also in the photoelectric conversion device of this embodiment, a plurality of amplification transistors 16 may be provided for each of the plurality of photoelectric conversion units 101a and 101b. For example, in the case of a configuration in which a plurality of pixel cells 1000 are arranged in a matrix, each of the plurality of pixel cells 1000 has the same number of amplification transistors 16 as the number of photoelectric conversion units included in each pixel cell 1000. The pixel cells 1000 belonging to the same row may share one capacitance driving unit 12.

(Example 3)
The photoelectric conversion device of the present embodiment will be described focusing on the differences from the first embodiment.

FIG. 7 is a diagram showing a layout of a plurality of stacked photoelectric conversion units and a circuit showing an element related to reading of an optical signal of the plurality of photoelectric conversion units. In the photoelectric conversion device of this example, a plurality of photoelectric conversion units 1010B, 1010G, and 1010R are stacked in the depth direction on a semiconductor substrate provided with the unit cell 1000. That is, the photoelectric conversion device of the present embodiment is provided with a plurality of photoelectric conversion units 1010B, 1010G, and 1010R in order from the side into which incident light is inserted. The photoelectric conversion unit 1010B stores signal charges based on blue light. Further, the photoelectric conversion unit 1010G accumulates signal charges based on green light. Further, the photoelectric conversion unit 1010R accumulates signal charges based on red light.

The photoelectric conversion unit 1010B includes a first electrode 201B, a blocking layer 203B, a photoelectric conversion layer 205B, an insulating layer 207B, and a second electrode 209B. These configurations are the same as the configurations of the photoelectric conversion unit 101a described in the first embodiment. Each of the photoelectric conversion unit 1010G and the photoelectric conversion unit 1010R has the same configuration as the photoelectric conversion unit 1010B.

The plurality of transfer transistors 15B, 15G, and 15R are electrically connected in sequence to the plurality of photoelectric conversion units 1010B, 1010G, and 1010R, respectively. The plurality of transfer transistors 15B, 15G, 15R are electrically connected in common to the node FD.

The configurations of the capacitance drive unit 12, the reset unit 14, the pixel output unit 16, the vertical signal line 17, the current source 18, and the column amplification unit 19 are the same as those of the photoelectric conversion device of the first embodiment.

In the photoelectric conversion device of this embodiment, three photoelectric conversion units 1010B, 1010G, and 1010R share one capacitance drive unit 12. Thereby, one capacitance drive unit 12 can drive each of the three photoelectric conversion units 1010B, 1010G, and 1010R. Therefore, the circuit area of the pixel cell 1000 can be reduced as compared with the configuration in which one capacitance drive unit 12 is provided for each of the three photoelectric conversion units 1010B, 1010G, and 1010R.

(Example 4)
The photoelectric conversion devices described in Embodiments 1 to 3 above can be applied to various photoelectric conversion systems. Examples of photoelectric conversion systems include digital still cameras, digital camcorders, and surveillance cameras. FIG. 9 shows a schematic diagram of a photoelectric conversion system in which the photoelectric conversion device according to any one of the first to third embodiments of the present invention is applied to a digital still camera as an example of the photoelectric conversion system.

The photoelectric conversion system illustrated in FIG. 9 makes a photoelectric conversion device 154, a barrier 151 for protecting a lens, a lens 152 for forming an optical image of a subject on the photoelectric conversion device 154, and a variable light amount passing through the lens 152. It has a diaphragm 153 for. The lens 152 and the diaphragm 153 are an optical system that guides light to the photoelectric conversion device 154. In addition, the photoelectric conversion system illustrated in FIG. 9 includes an output signal processing unit 155 that processes an output signal output from the photoelectric conversion device 154.

The output signal processing unit 155 performs AD conversion for converting an analog signal output by the photoelectric conversion device 154 into a digital signal. In addition, the output signal processing unit 155 also performs an operation of performing various corrections and compressions as necessary to output image data.

The photoelectric conversion system illustrated in FIG. 9 further includes a buffer memory unit 156 for temporarily storing image data and an external interface unit (external I/F unit) 157 for communicating with an external computer or the like. Further, in the photoelectric conversion system, a recording medium 159 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I/F unit) 158 for recording or reading on the recording medium 159. Have. The recording medium 159 may be built in the photoelectric conversion system or may be removable.

Further, the photoelectric conversion system has an overall control/calculation unit 1510 for controlling various calculations and the entire digital still camera, a timing generation unit 1511 for outputting various timing signals to the photoelectric conversion device 154 and the output signal processing unit 155. Here, the timing signal or the like may be input from the outside, and the photoelectric conversion system may include at least the photoelectric conversion device 154 and the output signal processing unit 155 that processes the output signal output from the photoelectric conversion device 154. .. As described above, the photoelectric conversion system according to the present embodiment can perform the image pickup operation by applying the photoelectric conversion device 154.

In addition, the output signal processing unit 155 may detect the phase difference using the signal output by the photoelectric conversion device 154, as described in the first embodiment.

It should be noted that each of the above-described embodiments is merely an example of an embodiment in carrying out the present invention, and the technical scope of the present invention should not be limitedly interpreted by these exemplifications. That is, the present invention can be implemented in various modes without departing from the technical idea or the main features thereof. In addition, various embodiments described so far can be implemented in various combinations.

10 unit pixel 12 capacitance drive unit 12a buffer circuit 12b capacitance element 14 reset unit 14a reset transistor 15 transfer transistor 16 pixel output unit 16a amplification transistor 16b selection transistor 17 vertical signal line 18 current source 19 column amplification unit 30 power supply unit 101 photoelectric conversion unit 1000 pixel cell

Claims (23)

In a photoelectric conversion device having a pixel region in which a plurality of cells each having a plurality of photoelectric conversion units and an amplification unit are arranged ,
Each of the plurality of photoelectric conversion units has a first electrode, a second electrode, and a photoelectric conversion layer that is disposed between the first electrode and the second electrode and that accumulates signal charges. An insulating layer disposed between the photoelectric conversion layer and the second electrode,
An optical signal based on the signal charges accumulated in each of the photoelectric conversion units is output to the amplification unit,
Further, the photoelectric conversion device includes a capacitive element having a first node and a second node, and the first node includes the second electrode of each of the plurality of photoelectric conversion units and the amplifier. Electrically connected to the
A photoelectric conversion device, wherein a plurality of potentials having different values are selectively supplied to the second node. The photoelectric conversion device according to claim 1, wherein the amplification unit includes a transistor having a gate connected to the first node. The photoelectric conversion device according to claim 2, wherein the transistor is a part of a source follower circuit. Each of the plurality of cells further includes a plurality of transfer units,
4. Each of the plurality of transfer units switches between conduction and non-conduction of an electrical path between the second electrode of the photoelectric conversion unit and the amplification unit. The photoelectric conversion device according to 1. The capacitance value of the capacitive element is variable,
When the signal charges are discharged from the photoelectric conversion layer, only some of the plurality of transfer units are turned on so that the electrical path between the photoelectric conversion unit and the amplification unit becomes conductive. The capacitance value of the capacitive element is the first capacitance value,
When the signal charges are discharged from the photoelectric conversion layer, the plurality of transfer units are turned on together so that each of the electrical paths between the plurality of photoelectric conversion units and the amplification unit is electrically connected. When it exists, the capacitance value of the capacitance element is a second capacitance value larger than the first capacitance value, and the photoelectric conversion device according to claim 4. The photoelectric conversion device has a first switch and a second switch,
The first node is electrically connected to one of the photoelectric conversion units of the plurality of photoelectric conversion units via the first switch,
The first node is electrically connected to the other photoelectric conversion unit of the plurality of photoelectric conversion units via the second switch. The photoelectric conversion device according to any one of 1. The photoelectric conversion device has a plurality of the amplification units,
The one photoelectric conversion unit is electrically connected to one of the plurality of amplification units,
The photoelectric conversion device according to claim 6, wherein the other photoelectric conversion unit is electrically connected to another amplification unit of the plurality of amplification units. For the previous SL plurality of photoelectric conversion unit, photoelectric conversion device according to claim 1, wherein the amplifying unit one is provided. The photoelectric conversion device according to claim 1, wherein the second node is electrically connected to a potential supply unit that supplies the plurality of potentials. The photoelectric conversion device,
A plurality of the capacitive elements,
A plurality of buffer circuits, each of which is provided corresponding to each of the plurality of capacitance elements, and each of which supplies the plurality of potentials from the potential supply unit to each of the plurality of capacitance elements. The photoelectric conversion device according to claim 9. When the potential supply unit supplies the first potential to the second node, the photoelectric conversion layer accumulates the signal charge,
11. The signal charge is discharged from the photoelectric conversion layer by the potential supply unit supplying a potential different from the first potential to the second node. Photoelectric conversion device. When the electrical path between the N photoelectric conversion units (N is a number of 1 or more) of the plurality of photoelectric conversion units and the amplification unit is in a conductive state, the potential supply unit is connected to the capacitor. Supplying the second potential of the different potential to the second node of the element to discharge the signal charge from the photoelectric conversion layer of each of the N photoelectric conversion units,
When the electrical paths between the M photoelectric conversion units, the number of which is greater than N of the plurality of photoelectric conversion units, and the amplification unit are both conductive, the potential supply is performed. Section supplies the third potential of the different potential to the second node of the capacitive element to discharge the signal charge from the photoelectric conversion layer of each of the M photoelectric conversion sections,
The photoelectric conversion device according to claim 9, wherein the signal charge is a hole, and the third potential is a potential having a larger value than the second potential. When the electrical path between the N photoelectric conversion units (N is a number of 1 or more) of the plurality of photoelectric conversion units and the amplification unit is in a conductive state, the potential supply unit is connected to the capacitor. Supplying the second potential of the different potential to the second node of the element to discharge the signal charge from the photoelectric conversion layer of each of the N photoelectric conversion units,
When the electrical paths between the M photoelectric conversion units, the number of which is greater than N of the plurality of photoelectric conversion units, and the amplification unit are both conductive, the potential supply is performed. Section supplies the third potential of the different potential to the second node of the capacitive element to discharge the signal charge from the photoelectric conversion layer of each of the M photoelectric conversion sections,
The photoelectric conversion device according to claim 11, wherein the signal charge is an electron, and the third potential is a potential whose value is smaller than that of the second potential. One microlens is provided for each of the plurality of cells ,
In each of the plurality of cells,
Since only some of the plurality of photoelectric conversion units have electrical paths between the photoelectric conversion units and the amplification unit, the second electrodes of the some photoelectric conversion units are connected to each other. After the optical signal is output to the amplifier,
Since the electrical paths between all the photoelectric conversion units and the amplification unit of the plurality of photoelectric conversion units are in a conductive state together, the amplification unit, the photoelectric conversion unit of each of the photoelectric conversion unit The photoelectric conversion device according to claim 1, wherein a signal obtained by adding the optical signals output from the second electrode is output. Light enters the photoelectric conversion device from an optical system,
Light emitted from different exit pupils of the optical system enters each of the plurality of photoelectric conversion units,
Since only some of the plurality of photoelectric conversion units have electrical paths between the photoelectric conversion units and the amplification unit, the second electrodes of the some photoelectric conversion units are connected to each other. After the optical signal is output to the amplifier,
Since the electrical paths between all the photoelectric conversion units and the amplification unit of the plurality of photoelectric conversion units are in a conductive state together, the amplification unit, the photoelectric conversion unit of each of the photoelectric conversion unit The photoelectric conversion device according to claim 1, wherein a signal obtained by adding the optical signals output from the second electrode is output. The plurality of photoelectric conversion units are provided on a semiconductor substrate,
16. The photoelectric conversion device according to claim 1, wherein the plurality of photoelectric conversion units are stacked in a depth direction of the semiconductor substrate. The capacitive element has two electrodes facing each other,
One electrode of the two electrodes is the first node of the capacitive element,
The other electrode of the two electrodes is the second node of the capacitive element, The photoelectric conversion device according to claim 1. The capacitive element is provided on a semiconductor substrate,
The first node of the capacitive element is one of a semiconductor region and a gate arranged on the semiconductor region,
17. The photoelectric conversion device according to claim 1, wherein the second node is electrically connected to the other of the semiconductor region and the gate arranged on the semiconductor region. The power supply voltage is supplied to the 1st electrode, The photoelectric conversion apparatus in any one of Claims 1-18 characterized by the above-mentioned. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion layer includes quantum dots. A blocking layer that reduces injection of charges having the same polarity as the signal charges from the first electrode into the photoelectric conversion layer is provided between the first electrode and the photoelectric conversion layer. The photoelectric conversion device according to claim 1. A photoelectric conversion device according to any one of claims 1 to 21,
An output signal processing unit that generates an image by processing a signal based on the optical signal output by the photoelectric conversion device,
A photoelectric conversion system comprising: A photoelectric conversion system comprising the photoelectric conversion device according to claim 14 or 15, and an output signal processing unit,
The photoelectric conversion device,
A first signal based on the optical signal output from only a part of the photoelectric conversion units of the plurality of photoelectric conversion units;
And outputting a second signal based on the optical signals output from all the photoelectric conversion units of the plurality of photoelectric conversion units to the output signal processing unit,
Detecting a phase difference using the difference between the first signal and the second signal,
A photoelectric conversion system, wherein an image is generated using the second signal.

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