JP6796776B2 - Voltage supply circuit - Google Patents

Description

The present application relates to an image pickup apparatus, and more particularly to an image pickup apparatus having a photoelectric conversion unit laminated on a semiconductor substrate.

Conventionally, digital cameras (digital video cameras or digital still cameras) have been used in various fields. CCD (Charge Coupled Device) type solid-state image sensor and CMOS (Complementary Metal Oxide Semiconductor) type solid-state image sensor are used in these digital cameras. As is well known, these solid-state image pickup devices have a photodiode formed on a semiconductor substrate as a light receiving unit.

As a light receiving unit, a laminated image pickup device having a photoelectric conversion film laminated on the outermost surface of a semiconductor substrate is also known (for example, Patent Document 1). In a stacked image pickup device, charges generated by photoelectric conversion in a photoelectric conversion film are accumulated in a charge storage region (referred to as "floating diffusion"). The accumulated charge is read out in the semiconductor substrate via a CCD circuit or a CMOS circuit. The stacked image pickup device has an advantage that a larger number of pixels can be realized because it is relatively easy to secure the area of the light receiving portion even if the pixel size is reduced. For reference, the entire disclosure of International Publication No. 2012/137445 is incorporated herein by reference.

International Publication No. 2012/137445

In the field of imaging devices, noise reduction is desired.

According to some non-limiting exemplary embodiments of the present application, the following are provided.

A first capacitive element connected between a gradient voltage generation circuit, a first amplifier, the gradient voltage generation circuit, and the first amplifier, and a first that negatively feeds back the output of the first amplifier. A voltage supply circuit comprising a feedback circuit, wherein the first feedback circuit includes a switch that selectively forms a feedback loop.

According to one aspect of the present disclosure, it is possible to supply a low noise gradient voltage to a unit pixel cell, and an imaging device capable of further reducing the influence of noise is provided.

FIG. 1 is a schematic diagram of an exemplary configuration of an imaging device according to the first embodiment of the present disclosure. FIG. 2 is a diagram showing an exemplary circuit configuration of the unit pixel cell 10A. FIG. 3 is a diagram showing a typical example of the connection relationship between the unit pixel cell 10A and the peripheral circuit. FIG. 4 is an exemplary timing chart for explaining the operation in the voltage supply circuit 50A. FIG. 5 is another exemplary timing chart for illustrating operation in the voltage supply circuit 50A. FIG. 6 is an exemplary timing chart for explaining the operation of the image pickup apparatus 100 when reading a signal. FIG. 7 is a diagram showing a circuit configuration of the unit pixel cell 10B. FIG. 8 is a schematic diagram of an exemplary configuration of the imaging device according to the second embodiment of the present disclosure. FIG. 9 is a diagram showing an example of a circuit configuration applicable as the control circuit 64. FIG. 10 is a diagram showing an exemplary circuit configuration of the unit pixel cell 10C according to the third embodiment of the present disclosure. FIG. 11 is an exemplary timing chart for explaining a signal reading operation using the unit pixel cell 10C. FIG. 12 is a diagram showing another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 13 is a diagram showing still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 14 is a diagram showing still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 15 is a diagram showing still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 16 is a diagram showing an example of the circuit configuration of the inverting amplifier 62 and the amplifier 80 in the voltage supply circuit 50E shown in FIG. FIG. 17 is a schematic diagram of another exemplary configuration of the imaging device according to the embodiment of the present disclosure. FIG. 18 is a block diagram showing an exemplary configuration of a gradient voltage generating circuit applicable to the voltage supply circuit of the present disclosure. FIG. 19 is a diagram showing an example of the circuit configuration of the gradient voltage generation circuit 52. FIG. 20 is a timing chart showing an example of the relationship between the input clocks CK and CKD and each control signal. FIG. 21 is a diagram showing an example of a clock generation circuit that generates the control signals Φ1, Φ2, Φ1d, and Φ2d shown in FIG. FIG. 22 is a diagram showing another example of the circuit configuration of the gradient voltage generation circuit. FIG. 23 is a diagram showing an exemplary connection relationship between a unit pixel cell and peripheral circuits in the image pickup apparatus according to the fourth embodiment of the present disclosure. FIG. 24 is a diagram showing an exemplary circuit configuration of the unit pixel cell 10D. FIG. 25 is a diagram showing a modified example of the unit pixel cell in the fourth embodiment. FIG. 26 is a diagram schematically showing a configuration example of a camera system according to a fifth embodiment of the present disclosure.

Prior to explaining the embodiments of the present disclosure, the findings of the present inventor will be described.

The above-mentioned Patent Document 1 discloses a circuit configuration in which a feedback amplifier and a control circuit for controlling an input level (gate voltage) for a reset transistor are provided for each row in the pixel array. In this circuit configuration, the reset is executed with the output fed back through the feedback amplifier. The noise that appears at the output is canceled by being fed back to the input.

Patent Document 1 further proposes that the gate voltage of the reset transistor is linearly reduced at the end of reset in such a circuit configuration. Patent Document 1 describes that by linearly reducing the gate voltage of the reset transistor, the band in the feedback loop is limited and a high noise reduction effect can be obtained.

However, if the input to the reset transistor (here, the gate voltage that decreases linearly) itself contains noise, the influence of the noise may affect the pixels and the image quality may deteriorate. Therefore, it is beneficial that the input to the transistor, which limits the band in the feedback loop, is low noise.

The present inventor has focused on the above points and conceived the imaging apparatus of the present disclosure.

The outline of one aspect of the present disclosure will be described below. In the present specification, a voltage having a waveform that generally increases or decreases with the passage of time may be referred to as a “ramp voltage”. The “gradient voltage” in the present specification is not limited to a voltage that increases or decreases linearly, and broadly includes a voltage having a stepped waveform, a voltage having a waveform that increases or decreases with vibration, and the like. Further, the "waveform" in the present specification is not limited to a shape showing a periodic or quasi-periodic change.

[Item 1]
A unit pixel cell including a photoelectric conversion unit that photoelectrically converts incident light, a signal detection circuit that detects a signal generated by the photoelectric conversion unit, and a voltage supply circuit that supplies a gradient voltage to the unit pixel cell are provided with a voltage. The supply circuit includes a gradient voltage generation circuit, a first amplifier, a capacitive element connected between the gradient voltage generation circuit and the first amplifier, and a first feedback circuit that negatively feeds back the output of the first amplifier. The first feedback circuit comprises a switch that selectively forms a feedback loop.

According to the configuration of item 1, it is possible to supply a gradient voltage to the unit pixel cell in which the influence of the input / output offset caused by the variation of the threshold voltage in the first amplifier is removed. Therefore, the influence of noise caused by the variation of the threshold voltage in the first amplifier can be reduced.

[Item 2]
The imaging apparatus according to item 1, further comprising a reset circuit for initializing a signal of a photoelectric conversion unit.

According to the configuration of item 2, the signal of the photoelectric conversion unit can be initialized.

[Item 3]
The imaging device according to item 2, further comprising a second feedback circuit that negatively feeds back the output of the signal detection circuit, wherein the reset circuit constitutes a part of the feedback loop of the second feedback circuit.

According to the configuration of item 3, thermal noise can be suppressed.

[Item 4]
The image pickup apparatus according to item 3, wherein the reset circuit includes a first transistor whose source or drain is connected to a photoelectric conversion unit, and a gradient voltage is applied to the gate of the first transistor.

According to the configuration of item 4, noise in the transistor in the unit pixel cell can be suppressed by using the gradient voltage. Further, the number of transistors in the unit pixel cell can be reduced.

[Item 5]
A second feedback circuit for negatively feeding back the output of the signal detection circuit is further provided, and the second feedback circuit is a first transistor forming a part of the feedback loop of the second feedback circuit, and a gradient voltage is applied to the gate thereof. The imaging apparatus according to item 2, wherein the reset circuit includes a second transistor whose source or drain is connected to a photoelectric conversion unit.

According to the configuration of item 5, noise in the transistor in the unit pixel cell can be suppressed by using the gradient voltage. It is also possible to apply an arbitrary voltage to the charge storage node as a reference voltage for resetting.

[Item 6]
Item 4. The imaging according to item 4 or 5, further comprising a control circuit that detects fluctuations in the threshold voltage of the first transistor and applies a reference voltage corresponding to the threshold voltage to the non-inverting input terminal of the second amplifier. apparatus.

According to the configuration of item 6, the initial voltage at the start of application of the gradient voltage can be flexibly changed according to the fluctuation of the threshold voltage of the first transistor. Therefore, it is possible to shorten the time required for noise reduction.

[Item 7]
The imaging apparatus according to any one of items 1 to 6, wherein the first amplifier has a source follower, and the output voltage of the gradient voltage generation circuit is input to the source follower via a capacitive element.

According to the configuration of item 7, when the switch in the first feedback circuit is turned off, the capacitance element can hold a potential that makes the output voltage of the voltage supply circuit equal to a predetermined voltage.

[Item 8]
The imaging apparatus according to any one of items 1 to 7, wherein the first feedback circuit includes a second amplifier which is an inverting amplifier, and the output of the first amplifier is input to the inverting input terminal of the second amplifier.

According to the configuration of item 8, the initial voltage at the start of application of the gradient voltage can be set to an arbitrary voltage.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In addition, all of the embodiments described below show comprehensive or specific examples. Numerical values, shapes, materials, components, arrangement and connection forms of components, steps, step order, etc. shown in the following embodiments are examples, and are not intended to limit the present disclosure. The various aspects described herein can be combined with each other as long as there is no conflict. Further, among the components in the following embodiments, the components not described in the independent claims indicating the highest level concept are described as arbitrary components. In the following description, components having substantially the same function are indicated by common reference numerals, and the description may be omitted.

(First Embodiment)
FIG. 1 outlines an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. The image pickup apparatus 100 shown in FIG. 1 has a pixel array PA and peripheral circuits. The pixel array PA includes a plurality of unit pixel cells 10A. As will be described later, each of the unit pixel cells 10A has a photoelectric conversion unit that photoelectrically converts incident light and a signal detection circuit that detects a signal generated by the photoelectric conversion unit. In the illustrated example, the unit pixel cells 10A are arranged in the row direction and the column direction. Since the unit pixel cell 10A has a two-dimensional arrangement, a photosensitive region (pixel region) is formed. As used herein, the row direction and the column direction mean the directions in which the rows and columns extend, respectively, the vertical direction is the column direction, and the horizontal direction is the row direction. The plurality of unit pixel cells 10A may be arranged one-dimensionally. In other words, the image pickup apparatus 100 may be a line sensor.

The image pickup apparatus 100 includes a voltage supply circuit 50A and a vertical scanning circuit (also referred to as a “row scanning circuit”) 16 connected to the voltage supply circuit 50A. As schematically shown in FIG. 1, the vertical scanning circuit 16 is connected to each of the unit pixel cells 10A via a feedback control line 28. The voltage supply circuit 50A and the vertical scanning circuit 16 form a part of peripheral circuits.

The voltage supply circuit 50A generates a gradient voltage for supplying to each of the unit pixel cells 10A. As will be described later, here, the supply of the gradient voltage to the unit pixel cell 10A is selectively executed via the vertical scanning circuit 16. Details of the structure and operation of the voltage supply circuit 50A will be described later.

In the configuration illustrated in FIG. 1, the voltage supply circuit 50A includes a gradient voltage generation circuit 52, a capacitance element 56, and an amplifier 54. The capacitive element 56 is connected between the gradient voltage generation circuit 52 and the amplifier 54. In addition, in this specification, a "capacitor" means a structure in which a dielectric material such as an insulating film is sandwiched between electrodes. The term "electrode" as used herein is not limited to an electrode formed of a metal, and is construed as broadly including a polysilicon layer and the like. The "electrode" in the present specification can be a part of a semiconductor substrate.

The gradient voltage generation circuit 52 converts, for example, an input voltage into a gradient voltage and outputs it. The configuration of the gradient voltage generation circuit 52 is not limited to a specific circuit configuration as long as the gradient voltage can be output. A specific example of the configuration of the gradient voltage generation circuit 52 will be described later. The output voltage (gradient voltage) Vgen of the gradient voltage generation circuit 52 is input to the amplifier 54 via the capacitive element 56. The amplifier 54 is arranged between the gradient voltage generation circuit 52 and the pixel array PA, and buffers the output voltage Vgen of the gradient voltage generation circuit 52. The amplifier 54 typically includes a source follower.

From the viewpoint of applying a low noise gradient voltage to each unit pixel cell 10A, it is beneficial that the amplifier 54 as a buffer has low noise. In order to reduce the noise of the buffer, it is effective to reduce the number of transistors that are noise sources and increase the size of the transistors. When arranging the buffer in a certain area, the size of the transistor in the buffer can be increased if the number of transistors required for the buffer configuration is small. The source follower can be configured with a relatively small number of transistors, and it is advantageous in terms of noise reduction if a circuit having a source follower is adopted as a buffer.

However, the output voltage of the source follower shifts with respect to the input voltage by the threshold voltage of the transistor of the source follower. In general, the characteristics of transistors are not constant due to variations during manufacturing. In addition, the threshold voltage of the source follower transistor fluctuates under the influence of temperature. It is beneficial to be able to reduce the variation in the threshold voltage for each transistor and the influence of the fluctuation of the threshold voltage because a desired voltage (gradient voltage) can be applied to the unit pixel cell 10A.

As shown in FIG. 1, the voltage supply circuit 50A according to the embodiment of the present disclosure includes a feedback circuit 58 that negatively feeds back the output of the amplifier 54. By negatively feeding back the output of the amplifier 54 using the feedback circuit 58, it is possible to reduce the variation in the threshold voltage for each transistor of the source follower and the influence of the fluctuation of the threshold voltage. In the configuration illustrated in FIG. 1, the feedback circuit 58 includes a switch 60. The feedback loop can be selectively formed by switching the switch 60 on / off. A typical example of a "switch" in the present specification is a switching element such as a field effect transistor (FET).

In the illustrated example, the feedback circuit 58 includes an inverting amplifier 62. The output of the amplifier 54 is applied to the inverting input terminal of the inverting amplifier 62. On the other hand, a predetermined reference voltage Vsrt is applied to the non-inverting input terminal of the inverting amplifier 62. This reference voltage Vsrt does not have to be a fixed single voltage. Here, the switch 60 described above is connected between the output terminal of the inverting amplifier 62 and the input terminal of the amplifier 54. The switch 60 switches whether or not to input the output Vamp of the inverting amplifier 62 to the amplifier 54. The operation of the inverting amplifier 62 will be described later.

FIG. 2 shows an exemplary circuit configuration of the unit pixel cell 10A. As shown in FIG. 2, the unit pixel cell 10A includes a photoelectric conversion unit 15 and a signal detection circuit SC including an amplification transistor 34.

The photoelectric conversion unit 15 typically has a photoelectric conversion film 15b laminated on a semiconductor substrate on which a unit pixel cell 10A is formed, a first electrode 15a, and a second electrode (pixel electrode) 15c. The photoelectric conversion film 15b is formed of an organic material or an inorganic material such as amorphous silicon. The "semiconductor substrate" in the present specification is not limited to a substrate whose entire structure is a semiconductor, and may be an insulating substrate in which a semiconductor layer is provided on the surface on the side where a photosensitive region is formed.

As schematically shown in FIG. 2, the photoelectric conversion film 15b is sandwiched between the first electrode 15a and the second electrode (pixel electrode) 15c. The first electrode 15a is provided on the light receiving surface side of the photoelectric conversion film 15b. The first electrode 15a is formed of a transparent conductive material such as ITO. The second electrode 15c is provided on the side facing the first electrode 15a via the photoelectric conversion film 15b. The second electrode 15c collects the electric charge generated by the photoelectric conversion in the photoelectric conversion film 15b. The second electrode 15c is formed of a metal such as aluminum or copper, or polysilicon that has been imparted with conductivity by doping with impurities.

The first electrode 15a is connected to the storage control line 17, and the second electrode 15c is connected to a charge storage node (also referred to as a “floating diffusion node”) 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, one of the holes and electrons among the hole-electron pairs generated by the photoelectric conversion can be collected by the second electrode 15c. it can. When holes are used as signal charges, the potential of the first electrode 15a may be higher than that of the second electrode 15c. In the following, a case where holes are used as signal charges will be illustrated. For example, a voltage of about 10 V is applied to the first electrode 15a via the storage control line 17. As a result, the signal charge is accumulated in the charge storage node 44. Of course, electrons may be used as signal charges.

The signal generated by the photoelectric conversion unit 15 is amplified by the amplification transistor 34. The gate of the amplification transistor 34 of the signal detection circuit SC is connected to the charge storage node 44. In other words, the gate of the amplification transistor 34 has an electrical connection with the second electrode 15c. One of the source and drain of the amplification transistor 34 (drain in the case of N-channel MOS) is connected to the voltage switching circuit 7 via the power supply wiring 22. The voltage switching circuit 7 includes a first switch SW1 and a second switch SW2, and a first voltage source VS1 and a second voltage source VS2. One of the source and drain of the amplification transistor 34 and the first voltage source VS1 are connected in series via the first switch SW1. Further, one of the source and drain of the amplification transistor 34 and the second voltage source VS2 are connected in series via the second switch SW2. By controlling the on / off of each of the first switch SW1 and the second switch SW2, either the first voltage V1 or the second voltage V2 is applied to one of the source and drain of the amplification transistor 34. Can be switched. The first voltage V1 is, for example, 0V (ground), and the second voltage V2 is, for example, VDD (power supply voltage). The voltage switching circuit 7 may be shared among a plurality of pixels, or may be provided for each pixel.

The other side of the source and drain of the amplification transistor 34 (or the source if it is an N-channel MOS) is connected to the signal readout line 18 and the constant current source 6 via the address transistor 40. The signal readout line 18 may be shared between two or more pixels. An address signal line 30 is connected to the gate of the address transistor 40. The state of the address transistor 40 is determined by the potential of the address signal line 30. When the potential of the address signal line 30 is high, the address transistor 40 is turned on, and the address transistor 40, the amplification transistor 34, and the constant current source 6 form a source follower. As a result, a signal corresponding to the charge stored in the charge storage node 44 is output to the signal reading line 18. When the potential of the address signal line 30 is low level, the address transistor 40 is turned off, and the amplification transistor 34 and the signal read line 18 are electrically separated.

In the configuration illustrated in FIG. 2, the amplification transistor 34 and the voltage switching circuit 7 constitute the amplifier 2. Further, the address transistor 40 constitutes the output selection unit 5S. The signal of the photoelectric conversion unit 15 in each of the unit pixel cells 10A is amplified by the amplifier 2 and selectively read out via the output selection unit 5S and the signal reading line 18. The constant current source 6 may be shared among a plurality of pixels, or may be provided for each pixel.

In the configuration illustrated in FIG. 2, the unit pixel cell 10A has a feedback circuit 48 that negatively feeds back the output of the signal detection circuit SC. A part of the signal amplified by the amplifier 2 is input to the band control unit 3SA. The feedback circuit 48 shown in FIG. 2 includes a feedback transistor 38 and a band control circuit 3 having capacitive elements 41 and 42. The band control circuit 3 limits the output signal of the amplifier 2 and outputs it to the charge storage node 44. That is, in the configuration illustrated in FIG. 2, the signal read from the charge storage node 44 is amplified by the amplifier 2, band-limited by the band control circuit 3, and then returned to the charge storage node 44.

In the illustrated example, one of the source and drain of the feedback transistor 38 is connected to the photoelectric conversion unit 15 via the capacitive element 41. The other side of the source and drain of the feedback transistor 38 is connected to the side of the source and drain of the amplification transistor 34 that is not connected to the voltage switching circuit 7 and the source and drain of the address transistor 40 to the signal read line 18. It is connected to the side that is not.

The gate of the feedback transistor 38 is connected to the feedback control line 28. The feedback control line 28 is connected to the voltage supply circuit 50A via the switch SW _i . The switch SW _i is typically provided corresponding to each row of the unit pixel cell 10A. Here, the subscript i is an index that specifies each row of the unit pixel cell 10A in the pixel array PA, and is a feedback control line 28 and a voltage supply circuit connected to a plurality of unit pixel cells 10A belonging to the i-th row. The switch arranged between 50A and 50A is referred to as switch SW _i . The switch SW _i is, for example, a switching element provided in the vertical scanning circuit 16. When the switch SW _i is turned on, an electrical connection is established between the unit pixel cell 10A in the i-th row and the voltage supply circuit 50A. By turning on the switch SW _i , the output voltage Vout of the voltage supply circuit 50A is applied to the feedback control line 28. That is, by switching the switch SW _i on / off, the gradient voltage can be selectively applied as the band control signal Tpr to the gate of the feedback transistor 38 of the unit pixel cell 10A in the desired row.

The state of the feedback transistor 38 is determined by the potential of the feedback control line 28. Here, when the switch SW _i is on, the feedback control line 28 in the unit pixel cell 10A on the i-th row and the voltage supply circuit 50A are electrically connected. Therefore, it is possible to control the state of the feedback transistor 38 by using the output voltage of the voltage supply circuit 50A. When the output voltage of the voltage supply circuit 50A is high, the feedback transistor 38 is turned on. As a result, a feedback loop including the charge storage node 44, the amplification transistor 34, the feedback transistor 38, and the capacitive element 41 in the path is formed. When the output voltage of the voltage supply circuit 50A decreases, the resistance of the feedback transistor 38 increases. When the resistance of the feedback transistor 38 increases, the band of the feedback transistor 38 becomes narrower, and the frequency domain of the feedback signal becomes narrower. When the feedback loop is formed (it may be said that the feedback transistor 38 is not off), the signal output by the feedback transistor 38 is attenuated by the parasitic capacitance of the capacitance element 41 and the charge storage node 44. Attenuated in the circuit. Assuming that the capacitance value of the capacitance element 41 is C1 and the capacitance value of the parasitic capacitance of the charge storage node 44 is Cfd, the attenuation factor B is expressed as B = C1 / (C1 + Cfd). When the output voltage of the voltage supply circuit 50A drops and reaches a low level, the feedback transistor 38 is turned off. That is, no feedback loop is formed.

In the configuration illustrated in FIG. 2, one of the source and drain of the feedback transistor 38 is connected to the charge storage node 44 via the capacitance element 41. The capacitance element 41 arranged between the feedback transistor 38 and the second electrode 15c of the photoelectric conversion unit 15 has a relatively small capacitance value. Hereinafter, the node including the connection point between the feedback transistor 38 and the capacitance element 41 may be referred to as a reset drain node 46. Further, here, the capacitance element 42 having a capacitance value larger than that of the capacitance element 41 is connected to the reset drain node 46. Of the electrodes of the capacitive element 42, the electrode that is not connected to the reset drain node 46 is connected to the sensitivity adjustment line 32, and the reference voltage VR1 (for example, 0V) is supplied. An RC filter circuit is formed from the capacitive element 42 and the feedback transistor 38. The potential of the sensitivity adjustment line 32 does not have to be fixed during the operation of the image pickup apparatus 100. For example, a pulse voltage may be supplied to the sensitivity adjustment line 32. The sensitivity adjustment line 32 can be used to control the potential of the charge storage node 44.

Further, in the configuration illustrated in FIG. 2, the band control unit 3SA includes a reset circuit 4A that initializes the signal of the photoelectric conversion unit 15. The reset circuit 4A includes a reset transistor 36 in which one of the source and the drain is connected to the charge storage node 44. The other of the source and drain of the reset transistor 36 is connected to the reset voltage line 25, and a predetermined voltage VR2 is applied via the reset voltage line 25. The voltage VR2 is a reference voltage at the time of reset in the configuration illustrated in FIG. As shown in FIG. 2, the gate of the reset transistor 36 is connected to the reset control line 26. The state of the reset transistor 36 is determined by the potential of the reset control line 26. When the potential of the reset control line 26 is high, the reset transistor 36 is turned on and the charge storage node 44 is reset.

The reset circuit 4A may be provided in each of the unit pixel cells 10A, or may be shared between two or more unit pixel cells 10A. As used herein, the "reset circuit" means a portion of the charge storage node 44 that includes a switching element that switches between application and non-application of a reference voltage during reset, and whose output is connected to the charge storage node 44. The "reset circuit" may include a circuit outside the unit pixel cell as a part thereof.

Each of the amplification transistor 34, the reset transistor 36, the feedback transistor 38, and the address transistor 40 may be an N-channel MOS or a P-channel MOS. Not all of these need to be unified into either N-channel MOS or P-channel MOS. In the following, unless otherwise specified, the transistor will be described as an N-channel MOS.

FIG. 3 shows a typical example of the connection relationship between the unit pixel cell 10A and the peripheral circuit. In FIG. 3, four unit pixel cells 10A are shown. However, this is just an example, and the number of unit pixel cells included in the pixel array PA is not limited to four.

Each of the unit pixel cells 10A is connected to the power supply wiring 22 and the reset voltage line 25. A predetermined power supply voltage (here, a first voltage V1 or a second voltage V2) is supplied to the unit pixel cell 10A via the power supply wiring 22. Further, the reference voltage VR2 for resetting is supplied via the reset voltage line 25. The reference voltage VR2 at reset may be supplied from the vertical scanning circuit 16 to the unit pixel cell 10A via the reset voltage line 25. Further, each of the unit pixel cells 10A is connected to a storage control line 17 that applies a constant voltage to the first electrode 15a (see FIG. 2) of the photoelectric conversion unit 15. In the illustrated example, a common voltage is applied to each of the unit pixel cells 10A. However, it is not necessary to apply a common voltage to all of the unit pixel cells 10A. For example, a different voltage may be supplied to each pixel block composed of several unit pixel cells 10A. By supplying a different voltage to each pixel block, the sensitivity of each pixel can be made variable.

In the configuration illustrated in FIG. 3, each of the unit pixel cells 10A is connected to the reset control line 26, the feedback control line 28, and the address signal line 30. The reset control line 26, the feedback control line 28, and the address signal line 30 are connected to the vertical scanning circuit 16. That is, in the illustrated example, the reset signal for reset operation control, the band control signal (gradient voltage), and the address signal are supplied from the vertical scanning circuit 16 to the unit pixel cell 10A. For example, the vertical scanning circuit 16 selects the unit pixel cell 10A in units of rows by applying a predetermined voltage to the address signal line 30. As a result, the signal voltage of the selected unit pixel cell 10A can be read out and reset. In the configuration illustrated in FIG. 3, one voltage supply circuit 50A is connected to the vertical scanning circuit 16. However, this is just an example, and two or more voltage supply circuits may be connected to the vertical scanning circuit 16.

The unit pixel cell 10A is connected to the signal reading line 18 for each column. A constant current source 19 and a column signal processing circuit (also referred to as a “row signal storage circuit”) 20 are connected to the signal reading line 18 corresponding to each column. The column signal processing circuit 20 performs noise suppression signal processing represented by correlated double sampling, analog-to-digital conversion (A / D conversion), and the like. A horizontal signal reading circuit (also referred to as a “column scanning circuit”) 21 is connected to the column signal processing circuit 20 provided corresponding to the row of the unit pixel cells 10A. The horizontal signal reading circuit 21 sequentially reads signals from the column signal processing circuit 20 to the horizontal common signal line 23.

(Operation in voltage supply circuit)
Next, an example of the operation in the voltage supply circuit 50A will be described with reference to FIGS. 1, 2, 4, and 5. In the embodiment of the present disclosure, a gradient voltage is applied to the gate of the feedback transistor 38 of the unit pixel cell 10A. The voltage supply circuit 50A supplies a gradient voltage applied to the gate of the feedback transistor 38. Here, a case where the amplifier 54 includes a source follower will be described as an example.

FIG. 4 shows an exemplary timing chart for explaining the operation in the voltage supply circuit 50A. The graph in FIG. 4 shows, in order from the top, the on / off state of the switch 60, the output voltage Vout of the voltage supply circuit 50A, and the output voltage Vgen of the gradient voltage generation circuit 52, respectively. The horizontal axis of each graph indicates time T. As shown in FIG. 4, in this example, the gradient voltage generation circuit 52 generates a constant voltage in the period from time t0 to time t3. Further, the gradient voltage generation circuit 52 generates a voltage that decreases monotonically between the time t3 and the time t4.

First, at time t1, the switch 60 is turned on. As a result, a feedback loop (feedback circuit 58) that negatively feeds back the output of the amplifier 54 is formed.

As described above, the output voltage of the source follower shifts with respect to the input voltage by the threshold voltage of the transistor of the source follower. Therefore, when the switch 60 is off in the voltage supply circuit 50A, the output voltage VOUT of the source follower is VOUT = VIN if the input voltage of the source follower and the threshold voltage of the transistor of the source follower are VIN and VTs, respectively. Expressed as −VTs. Since the threshold voltage VTs are affected by manufacturing variations and temperature, they are not constant among individual transistors and vary even in the same transistor. Therefore, in general, the output of the source follower is not uniquely determined.

However, in the embodiment of the present disclosure, a feedback loop (feedback circuit 58) that negatively feeds back the output of the amplifier 54 is formed by turning on the switch 60. Since the output of the amplifier 54 is negatively fed back, according to the embodiment of the present disclosure, the variation in the threshold voltage of the transistor of the amplifier 54 (here, the source follower) and the fluctuation of the threshold voltage are canceled. Is possible.

Further, in the configuration illustrated in FIG. 1, the feedback circuit 58 includes an inverting amplifier 62 in the feedback loop. In the illustrated example, the output of the amplifier 54 is connected to the inverting input terminal of the inverting amplifier 62. The connection form may be such that the output of the switch SW _i (see FIG. 2) is input to the inverting input terminal of the inverting amplifier 62.

On the other hand, a voltage source (not shown) is connected to the non-inverting input terminal of the inverting amplifier 62, and a voltage Vsrt is applied to the non-inverting input terminal of the inverting amplifier 62. This voltage Vsrt can be set arbitrarily. When the inverting amplifier 62 operates so that the voltage of the inverting input terminal and the voltage of the non-inverting input terminal become equal to each other, the output voltage Vout of the voltage supply circuit 50A becomes the amplifier 54 (here, the source follower) after a while from the time t1. ) Is equal to the voltage Vsrt regardless of the magnitude of the threshold voltage of the transistor (time t2). The switch 60 is turned off at the time t2 when the output voltage Vout is sufficiently close to the voltage Vsrt.

Then, at time t3, the gradient voltage generation circuit 52 starts to decrease the output voltage Vgen. At this time, the input voltage of the amplifier 54 changes via the capacitive element 56. As the voltage Vgen decreases, so does the input voltage Vin (see FIG. 1) of the amplifier 54. As the input voltage Vin of the amplifier 54 decreases, the output voltage Vout of the voltage supply circuit 50A decreases.

What should be noted here is that, in the configuration illustrated in FIG. 1, the capacitive element 56 is connected between the gradient voltage generation circuit 52 and the amplifier 54. When the switch 60 is off, the capacitance element 56 holds a potential that makes the output voltage Vout of the voltage supply circuit 50A equal to an arbitrarily set voltage Vsrt. Therefore, as shown in FIG. 4, the output voltage Vout of the voltage supply circuit 50A changes from the voltage Vsrt as the starting point. As described above, according to the embodiment of the present disclosure, the voltage at the start of the change that lowers (or increases) the output voltage Vout of the voltage supply circuit 50A (hereinafter, may be referred to as “initial voltage”) is arbitrary. The voltage can be set to Vsrt. In other words, the voltage Vsrt can be used to determine the initial voltage at the start of application of the gradient voltage.

As will be described in detail later, in the embodiment of the present disclosure, the potential of the feedback control line 28 is changed so as to straddle the threshold voltage of the feedback transistor 38. That is, if the threshold voltage of the feedback transistor 38 and the voltage at the end of the voltage change at the gradient voltage are VTf and Vend, respectively, the threshold voltage VTf becomes the voltage between the voltage Vsrt and the voltage Vend. Set the voltage Vsrt. The change in the potential of the feedback control line 28 may be a change from a high level to a low level, or may be a change from a low level to a high level.

The threshold voltage of the feedback transistor 38 is affected by manufacturing variations, similar to the threshold voltage of the transistor of the amplifier 54 (here, the source follower). Therefore, the appropriate initial voltage value may vary from individual unit pixel cell 10A. According to the embodiment of the present disclosure, by appropriately setting the voltage Vsrt input to the non-inverting input terminal of the inverting amplifier 62, the initial voltage of the gradient voltage without adding a special function to the gradient voltage generation circuit 52. Can be set to a voltage corresponding to the threshold voltage of the feedback transistor 38 of each unit pixel cell 10A.

As described above, according to the embodiment of the present disclosure, the influence of the variation in the threshold value of the transistor of the source follower can be canceled. Therefore, it is possible to supply a low noise gradient voltage to the unit pixel cell 10A. Further, at the same time as canceling the variation in the threshold value, it is easy to shift the output voltage Vout of the voltage supply circuit 50A to an arbitrary voltage range. Therefore, it is possible to supply a gradient voltage starting from an initial voltage suitable for each unit pixel cell 10A. By setting the range of voltage fluctuation in the gradient voltage to an appropriate range according to the variation of the threshold voltage of the feedback transistor 38 in the unit pixel cell 10A, the time required from the time t3 to the time t4 shown in FIG. 4 can be shortened. It is possible. Therefore, high-speed noise suppression can be realized.

The waveform of the gradient voltage is not limited to the waveform in which the voltage drops. Depending on the application, a gradient voltage such that the voltage increases may be supplied to the unit pixel cell 10A as shown in FIG.

Next, an exemplary operation of the image pickup apparatus 100 when reading a signal will be described.

(Operation in the imaging device)
FIG. 6 shows an exemplary timing chart for explaining the operation of the image pickup apparatus 100 when reading a signal. In FIG. 6, the horizontal axis of each graph indicates time T. The vertical axis of the graph shown in FIG. 6 is, in order from the top, the voltage level Vr of the reset control line 26, the voltage level Vf of the feedback control line 28, the voltage level Va of the address signal line 30, and the drain and source of the amplification transistor 34. Of these, the voltage levels Vs on the side (typically drain) connected to the voltage switching circuit 7 are shown. The voltage VTf shown in the graph is the threshold voltage of the feedback transistor 38.

(reset)
First, at time t11, the potential of the address signal line 30 is set to a low level. As a result, the address transistor 40 is turned off, and the amplification transistor 34 and the signal readout line 18 are electrically separated. Also, the potential of the feedback control line 28 is raised to a high level, and the feedback transistor 38 is turned on. As a result, a feedback loop is formed in the unit pixel cell 10A (see FIG. 2). The amplification factor at this time is expressed as (-A x B), where the amplification factor of the amplifier 2 is (-A) ("x" represents multiplication). The designer can design the amplification factor to be the optimum value for the circuit system. Usually, A is larger than 1, and can be set to a numerical value of several tens to several hundreds. At this time, the first switch SW1 and the second switch SW2 of the voltage switching circuit 7 are turned on and off, respectively, and the first voltage V1 (typically GND) is connected to the drain (or source) of the amplification transistor 34. Is applied. Further, the potential of the reset control line 26 is raised to a high level, and the reset transistor 36 is turned on. By turning on the reset transistor 36, the charge storage node 44 is reset. In other words, the potential of the charge storage node 44 becomes the reference potential VR2 at reset.

(First noise suppression period)
Next, at time t12, the potential of the reset control line 26 is lowered to a low level, and the reset transistor 36 is turned off. As the reset transistor 36 is turned off, kTC noise is generated. However, when the reset transistor 36 is off, a feedback loop having an amplification factor of (−A × B) is formed in the unit pixel cell 10A. Therefore, in the period from time t12 to time t13, the kTC noise of the charge storage node 44 generated when the reset transistor 36 is turned off is suppressed 1 / (1 + A × B) times. At this time, if the potential of the feedback control line 28 is set so that the operating band of the feedback transistor 38 becomes the first band having a wide band, noise can be suppressed at high speed. The first band means a band corresponding to a high level gate potential. Here, since the potential of the feedback control line 28 is set to a high level, noise suppression is high speed.

(Second noise suppression period)
Next, in the period from time t13 to time t14, the potential of the feedback control line 28 is changed so that the feedback transistor 38 gradually changes from the on state to the off state. That is, the potential of the feedback control line 28 is gradually lowered from the high level to the low level so as to cross the threshold voltage VTf of the feedback transistor 38. At this time, the potential of the feedback control line 28 is controlled so that the operating band of the feedback transistor 38 becomes a second band narrower than the first band. The second band means a band corresponding to an intermediate level gate potential.

Here, at time t13, the potential of the feedback control line 28 is lowered to the potential V3 between the high level and the low level. Further, the potential of the feedback control line 28 is continuously lowered to the potential V4 between the time t13 and the time t14. Further, here, after the potential of the feedback control line 28 is lowered to the potential V4, the potential of the feedback control line 28 is changed to a low level at time t15. The potential V4 is lower than the potential V3 and higher than the low level. Of course, the potential of the feedback control line 28 may be continuously changed from the high level to the low level.

It is not necessary for the voltage supply circuit 50A to generate all of the voltage applied to the feedback control line 28 (voltage level Vf shown in FIG. 4). For example, a voltage having a rectangular waveform (for example, a voltage at times t11 to t13 shown in FIG. 6 and a voltage at times t14 to t15) is generated by the vertical scanning circuit 16 and a gradient voltage portion (time t13 to t14 shown in FIG. 6) is generated. The voltage) may be generated by the voltage supply circuit 50A (see FIG. 1).

Although the time for sufficiently suppressing noise (time from time t13 to time t14) is long, noise suppression is performed by setting the second band to a band sufficiently lower than the operating band of the amplification transistor 34. The effect can be improved. However, since the noise suppression effect can be obtained even if the second band is higher than the operating band of the amplification transistor 34, the designer arbitrarily selects the second band according to the time that can be tolerated as the period from time t13 to time t14. It should be designed to. Hereinafter, the second band will be described as a band sufficiently lower than the operating band of the amplification transistor 34.

When the second band is lower than the operating band of the amplification transistor 34, the thermal noise generated in the feedback transistor 38 is suppressed by the feedback circuit 48 by 1 / (1 + A × B) ^1/2 times. In a state where the second band is lower than the operating band of the amplification transistor 34, the potential of the feedback control line 28 is lowered at time t15, and the feedback transistor 38 is turned off. The kTC noise remaining in the charge storage node 44 when the feedback transistor 38 is off is represented by the square root of the sum of squares of the kTC noise caused by the reset transistor 36 and the kTC noise caused by the feedback transistor 38.

Further, assuming that the capacitance value of the capacitance element 42 is C2, the kTC noise of the feedback transistor 38 generated in the state without suppression by feedback is the kTC noise (Cfd / C2) of the reset transistor 36 generated in the state without suppression by feedback. ) ^1/2 times. Considering this point, the kTC noise when there is feedback is (1+ (1 + A × B) × (Cfd / (C2 × B ² ))) ^1/2 / (1 + A ×) as compared with the case where there is no feedback. B) It is suppressed twice.

(Exposure / Read period)
Next, at time t16, the potential of the address signal line 30 is raised to a high level, and the address transistor 40 is turned on. Further, the first switch SW1 and the second switch SW2 of the voltage switching circuit 7 are turned off and on, respectively, and a second voltage V2 (typically VDD) is applied to the drain (or source) of the amplification transistor 34. .. In this state, the amplification transistor 34 and the constant current source 6 form a source follower circuit. The potential of the signal readout line 18 becomes a potential corresponding to the signal charge accumulated in the charge storage node 44. The amplification factor of this source follower circuit is set to, for example, about 1.

The voltage of the charge storage node 44 at time t16 changes from the reference voltage (voltage VR2) at reset by the amount corresponding to the electric signal generated by the photoelectric conversion unit 15 during the period from time t15 to time t16. .. The voltage of the charge storage node 44 is amplified by the amplifier 2 (in this example, the amplification factor is about 1) and output to the signal readout line 18 (time t17).

Random noise means fluctuation of the output when the electric signal generated by the photoelectric conversion in the photoelectric conversion unit 15 is 0, that is, kTC noise. In the embodiment of the present disclosure, the kTC noise is suppressed by (1+ (1 + A × B) × (Cfd / (C2 × B ² ))) ^1/2 / (1 + A × B) times during the noise suppression period. Further, the amplification factor in the exposure / readout period is about 1. Therefore, it is possible to read a signal in which random noise is suppressed from the signal read line 18. As a result, good image data in which random noise is suppressed can be acquired.

The circuit configuration of the unit pixel cell is not limited to the configuration shown in FIG. For example, the circuit configuration shown in FIG. 7 is also applicable. In the unit pixel cell 10B shown in FIG. 7, of the source and drain of the reset transistor 36 in the reset circuit 4B in the band control unit 3SB, the side not connected to the charge storage node 44 is the source and drain of the feedback transistor 38. , Is connected to the side that is not connected to the reset drain node 46.

In the configuration illustrated in FIG. 7, the output of the amplification transistor 34 is used as a reference voltage at reset. Therefore, in the unit pixel cell 10B shown in FIG. 7, the reset voltage line 25 is omitted. According to such a configuration, the change in the voltage of the charge storage node 44 before and after turning off the reset transistor 36 can be reduced. Therefore, faster noise suppression is possible. The operation timing of each transistor in the configuration illustrated in FIG. 7 may be the same as in the case of the unit pixel cell 10A.

(Second Embodiment)
FIG. 8 shows an outline of an exemplary configuration of an imaging device according to a second embodiment of the present disclosure. The difference between the image pickup device 100 described above and the image pickup device 200 shown in FIG. 8 is that the image pickup device 200 is a control circuit that detects fluctuations in the threshold voltage of the feedback transistor 38 (see FIG. 2) of the unit pixel cell 10A. To have 64.

The control circuit 64 has an electrical connection with a transistor that is a target for detecting fluctuations in the threshold voltage. The transistor for which the fluctuation of the threshold voltage is detected is typically a dummy pixel transistor provided on a substrate on which a pixel array PA is formed. When it is considered that the variation between the transistors on the same substrate is small, the threshold voltage of the dummy transistor can be regarded as the threshold voltage of the feedback transistor 38 of the unit pixel cell 10A included in the pixel array PA. it can.

The control circuit 64 detects the fluctuation of the threshold voltage of the feedback transistor 38 and generates a voltage Vsrt corresponding to the fluctuation of the threshold voltage of the feedback transistor 38. As shown in FIG. 8, the control circuit 64 is connected to the non-inverting input terminal of the inverting amplifier 64. The control circuit 64 applies a reference voltage corresponding to the fluctuation of the threshold voltage of the feedback transistor 38 to the non-inverting input terminal of the inverting amplifier 64.

FIG. 9 shows an example of a circuit configuration applicable as the control circuit 64. In the circuit shown in FIG. 9, a source follower is formed by using the transistor 68 to be detected. A constant current source 66 is connected to the drain of the transistor 68, and the potential of the source is fixed. In the configuration illustrated in FIG. 9, a feedback amplifier 65 is connected to the source of the transistor 68. The output of this source follower is taken out via buffer 67.

The specific configuration of the control circuit 64 is not limited to the configuration shown in FIG. Various known circuits can be applied as the control circuit 64. A circuit configuration that monitors the threshold voltage of a transistor and generates a voltage according to a detection result is well known. For example, Japanese Patent Application Laid-Open No. 2010-152995 and Japanese Patent Application Laid-Open No. 2011-55459 disclose such a circuit. For reference, all of the disclosure contents of JP2010-152995A and JP2011-55459A are incorporated herein by reference.

As already described with reference to FIG. 4 and the like, according to the circuit configuration illustrated in FIG. 1, the initial voltage at the gradient voltage output from the voltage supply circuit 50A is applied to the non-inverting input terminal of the inverting amplifier 64. It can be determined by the voltage. That is, the initial voltage at the gradient voltage can be shifted to the voltage Vsrt by applying the voltage Vsrt corresponding to the fluctuation of the threshold voltage of the feedback transistor 38 to the non-inverting input terminal of the inverting amplifier 64. In the configuration illustrated in FIG. 8, as the voltage applied to the non-inverting input terminal of the inverting amplifier 64, the voltage Vsrt generated by the control circuit 64 configured to detect the fluctuation of the threshold voltage of the feedback transistor 38 is used. I am using it. Therefore, the fluctuation of the voltage in the gradient voltage can be shifted to an appropriate range according to the fluctuation of the threshold voltage of the feedback transistor 38.

In this example, the gradient voltage has a waveform starting from the initial voltage reflecting the fluctuation of the threshold voltage of the feedback transistor 38. As a result, a gradient voltage that straddles the threshold voltage of the feedback transistor 38 can be more reliably supplied to the unit pixel cell 10A. In addition, the voltage sweep time can be shortened. As described above, according to the embodiment of the present disclosure, it is possible to cancel the variation in the threshold voltage of the amplifier 54 itself as a buffer and shift the gradient voltage according to the threshold voltage of the feedback transistor 38. Is.

(Third Embodiment)
FIG. 10 shows an exemplary circuit configuration of the unit pixel cell 10C according to the third embodiment of the present disclosure. The feedback circuit 49 shown in FIG. 10 negatively feeds back the output of the signal detection circuit SC, similarly to the feedback circuit 48 described with reference to FIG. The feedback circuit 49 includes a band control circuit 3C having a feedback transistor 38. The band control circuit 3C limits the output signal of the amplifier 2 and outputs it to the charge storage node 44. In the configuration illustrated in FIG. 10, the reset circuit 4C in the band control unit 3SC is provided in the feedback loop of the feedback circuit 49. The reset circuit 4C includes a feedback transistor 38. The feedback transistor 38 is connected between the output of the amplification transistor 34 and the charge storage node 44. In this example, one of the source and drain of the feedback transistor 38 is connected to the photoelectric conversion unit 15 without going through a capacitive element. The feedback transistor 38 forms part of the feedback loop.

In the configuration illustrated in FIG. 10, the feedback transistor 38 forms a part of the reset circuit 4C that initializes the signal of the photoelectric conversion unit 15, and the reference voltage is applied / not applied to the charge storage node 44 in the reset. Functions as a switching element that switches between. That is, in the configuration illustrated in FIG. 10, the feedback transistor 38 also has the function of the reset transistor 36 in the unit pixel cell 10A shown in FIG. 2 and the unit pixel cell 10B shown in FIG. 7. According to the circuit configuration as illustrated in FIG. 10, the number of transistors in the unit pixel cell can be reduced as compared with the unit pixel cell 10A shown in FIG. 2 and the unit pixel cell 10B shown in FIG. 7.

FIG. 11 is an exemplary timing chart for explaining a signal reading operation using the unit pixel cell 10C. In FIG. 11, the horizontal axis of each graph indicates time T. The vertical axis of the graph shown in FIG. 11 is connected to the voltage switching circuit 7 among the voltage level Vf of the feedback control line 28, the voltage level Va of the address signal line 30, and the drain and source of the amplification transistor 34 in order from the top. The voltage level Vs on the side (typically the drain) is shown. The voltage VTf shown in the graph is the threshold voltage of the feedback transistor 38. Hereinafter, the outline of the signal reading operation will be described with reference to FIG.

(reset)
First, at time t11, the potential of the address signal line 30 is lowered and the address transistor 40 is turned off. Also, the potential of the feedback control line 28 is raised to a high level, and the feedback transistor 38 is turned on. At this time, the first switch SW1 and the second switch SW2 of the voltage switching circuit 20 are turned on and off, respectively, and the first voltage V1 (typically GND) is applied to the drain (or source) of the amplification transistor 34. To do. These operations reset the charge storage node 44. The reference voltage at reset is the output of the amplification transistor 34. The operating band of the feedback transistor 38 at this time is the first band.

(Noise suppression period)
Next, in the period from time t13 to time t14, the potential of the feedback control line 28 is changed so that the feedback transistor 38 gradually changes from the on state to the off state. That is, the potential of the feedback control line 28 is changed from the high level to the low level so as to straddle the threshold voltage VTf of the feedback transistor 38. At this time, the potential of the feedback control line 28 is controlled so that the operating band of the feedback transistor 38 becomes a second band narrower than the first band. Here, at time t13, the potential of the feedback control line 28 is lowered to the potential V3 between the high level and the low level. Further, the potential of the feedback control line 28 is continuously lowered to the potential V4 between the time t13 and the time t14. Further, here, after the potential of the feedback control line 28 is lowered to the potential V4, the potential of the feedback control line 28 is changed to a low level at time t15. The potential V4 is lower than the potential V3 and higher than the low level. Of course, the potential of the feedback control line 28 may be continuously changed from the high level to the low level.

In a state where the second band is lower than the operating band of the amplification transistor 34, the thermal noise generated in the feedback transistor 38 is suppressed by the feedback circuit 49 by 1 / (1 + A) ^1/2 times. When the potential of the feedback control line 28 is lowered at time t15 and the feedback transistor 38 is turned off while the second band is lower than the operating band of the amplification transistor 34, the kTC noise remaining in the charge storage node 44 is also fed back. It is suppressed to 1 / (1 + A) ^1/2 times as much as the case without.

(Exposure / Read period)
Next, at time t16, the potential of the address signal line 30 is raised to a high level, and the address transistor 40 is turned on. Further, the first switch SW1 and the second switch SW2 of the voltage switching circuit 7 are turned off and on, respectively, and a second voltage V2 (typically VDD) is applied to the drain (or source) of the amplification transistor 34. .. In this state, the amplification transistor 34 and the constant current source 6 form a source follower circuit. The potential of the signal readout line 18 becomes a potential corresponding to the signal charge accumulated in the charge storage node 44. The amplification factor of this source follower circuit is set to, for example, about 1. The voltage of the charge storage node 44 is amplified by the amplifier 2 (in this example, the amplification factor is about 1) and output to the signal readout line 18 (time t17).

(Other modifications)
Hereinafter, other modifications will be described with reference to the drawings.

FIG. 12 shows another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. The voltage supply circuit 50B shown in FIG. 12 has a capacitance element 70 connected to a node including a connection point between the capacitance element 56 and the input of the amplifier 54. Of the electrodes of the capacitive element 70, the potential of the electrode on the side not connected to the input of the amplifier 54 is fixed.

In such a circuit configuration, the potential (Vin) of the node including the connection point between the capacitance element 56 and the input of the amplifier 54 is inclined if the capacitance values of the capacitance element 56 and the capacitance element 70 are C3 and C4, respectively. It is (C3 / (C3 + C4)) times the potential at the output of the voltage generation circuit 52. Since C3 / (C3 + C4) <1, the noise included in the output of the gradient voltage generation circuit 52 can be reduced by the ratio of (C3 / (C3 + C4)). In this way, by connecting the capacitance element 70 having a fixed potential at one end to the node including the connection point between the capacitance element 56 and the input of the amplifier 54, the noise included in the output of the gradient voltage generation circuit 52 is reduced. It is possible.

FIG. 13 shows yet another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. The voltage supply circuit 50C shown in FIG. 13 has an amplifier 54S configured as a so-called super source follower.

The amplifier 54S shown in FIG. 13 includes an input transistor 55, a MOSFET current source 57P including a P-channel MOS transistor, an NMOS current source 57N including an N-channel MOS transistor, and a feedback transistor 59. The input voltage of the amplifier 54S is applied to the gate of the input transistor 55. The source (or drain) of the MOSFET current source 57P is connected to the power supply, and the drain (or source) of the NMOS current source 57P is connected to the drain (or source) of the input transistor. The source (or drain) of the input transistor is connected to the drain (or source) of the NMOS current source 57N, and the source (or drain) of the NMOS current source 57N is grounded. The source (or drain) of the feedback transistor 59 is connected to a power source, and the drain (or source) of the feedback transistor 59 is connected to the connection point of the input transistor 55 and the NMOS current source 57N. The gate of the feedback transistor 59 is connected to the connection point of the MOSFET current source 57P and the input transistor 55.

In such a configuration, the loop formed by the feedback transistor 59 acts to suppress output runout. Therefore, the amount of output current is controlled according to the output voltage. In addition, the output impedance reduction effect of the amplifier 54S can also be obtained.

FIG. 14 shows yet another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. The feedback circuit 58D in the voltage supply circuit 50D shown in FIG. 14 has a switch 61 connected between the output of the amplifier 54 and the inverting input of the inverting amplifier 62. Further, the feedback circuit 58D has capacitive elements 71 and 72 having a fixed potential at one end. Of the two electrodes of the capacitive element 71, the ungrounded electrode is connected between the output of the amplifier 54 and the inverting input of the inverting amplifier 62. Of the two electrodes of the capacitive element 72, the ungrounded electrode is connected between the output of the inverting amplifier 62 and the input of the amplifier 54.

As can be seen from the operation described with reference to FIG. 4 and the like, in the embodiment of the present disclosure, the gradient voltage is sequentially supplied to the unit pixel cell. That is, every time the unit pixel cell to which the gradient voltage is supplied is switched, the switch 60 is turned on / off, and the formation / cancellation of the feedback loop is repeated. As can be seen from the graph of the output voltage Vout in FIG. 4, the output voltage after supplying the gradient voltage to a certain unit pixel cell is the voltage Vend. Next, when a gradient voltage is supplied to another unit pixel cell, the output voltage rises again from the voltage Vend to the voltage Vsrt due to the formation of the feedback loop. That is, when the switch 60 returns from off to on, the output voltage Vout fluctuates greatly in the process of reconstructing the feedback loop.

In the configuration illustrated in FIG. 14, the capacitive element 71 holds the voltage of the inverting input terminal of the inverting amplifier 62 before the switch 61 is turned off. Further, the capacitive element 72 holds the voltage of the output terminal of the inverting amplifier 62 before the switch 61 is turned off. By this operation, even when the feedback loop is not formed, the potential information on the input side and the output side of the inverting amplifier 62 in the state where the feedback loop is formed can be retained. Therefore, the starting point of the voltage change when the feedback loop is formed can be a voltage close to the voltage Vsrt. As a result, it is possible to suppress a large fluctuation in the output voltage when the feedback loop is formed again after the feedback loop is released. Moreover, high-speed convergence can be realized.

FIG. 15 shows yet another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. The feedback circuit 58E in the voltage supply circuit 50E shown in FIG. 15 has an amplifier 80 connected between the output of the inverting amplifier 62 and the input of the amplifier 54. The amplifier 80 is connected between the inverting amplifier 62 and the switch 60.

FIG. 16 shows an example of the circuit configuration of the inverting amplifier 62 and the amplifier 80 in the voltage supply circuit 50E shown in FIG. In the configuration illustrated in FIG. 16, the inverting amplifier 62 includes transistors 73, input transistors 74 and 75, transistors 76 and 77, and current source transistors 78 and 79. The gate of the input transistor 74 is connected to the inverting input terminal 62n. A transistor 76 is connected to the drain of the input transistor 74, and a current source transistor 78 is cascode-connected to the transistor 76. The gate of the input transistor 75 is connected to the non-inverting input terminal 62p. A transistor 77 is connected to the drain of the input transistor 75, and a current source transistor 79 is cascode-connected to the transistor 77. The transistor 73 forms a so-called tail current source and supplies the current used for the operation of the transistors 74 to 79. A mirror primary transistor 82, a current source transistor 83, and a diode connection transistor 84 are connected between the power supply terminal on the positive side and the power supply terminal on the negative side of the inverting amplifier 62.

In the configuration illustrated in FIG. 16, the transistor 76 and the current source transistor 78 are cascode-connected, and the transistor 77 and the current source transistor 79 are cascode-connected. Therefore, as compared with the case where such a cascade connection is not provided, even if the potential difference between the potential of the connection point of the input transistor 74 and the transistor 76 and the connection point of the input transistor 75 and the transistor 77 is large, the inverting input is performed. The current distributed to the side and the non-inverting input side is kept so as not to be unbalanced. That is, the occurrence of systematic offset in the inverting amplifier 62 can be suppressed.

However, in such a circuit configuration, since the transistor 76 and the current source transistor 78 are cascode-connected, and the transistor 77 and the current source transistor 79 are cascode-connected, the voltage range at the output (Vamp1) of the inverting amplifier 62. Is difficult to increase.

In the configurations illustrated in FIGS. 15 and 16, the amplifier 80 is connected to the output side of the inverting amplifier 62. The amplifier 80 shown in FIG. 16 has an amplifier input transistor 85 and a current source transistor 86. The output Vamp 1 of the inverting amplifier 62 is applied to the gate of the amplifier input transistor 85 via the connection line 89. A current source transistor 86 is connected to the amplifier input transistor 85. In this example, a resistor 87 and a capacitance element 88 (not shown in FIG. 15) are connected in series between the inverting amplifier 62 and the amplifier 80.

By providing the amplifier 80 having a gain on the output side of the inverting amplifier 62 in this way, even if the output of the inverting amplifier 62 has a small amplitude, the amplitude of the output Vamp 2 of the amplifier 80 can be expanded. According to the configurations shown in FIGS. 15 and 16, the input offset in the inverting amplifier 62 can be suppressed to set the input of the amplifier 54 with high accuracy, and the voltage range at the input of the amplifier 54 can be widened.

FIG. 17 outlines another exemplary configuration of the imaging apparatus according to the embodiments of the present disclosure. The image pickup apparatus 300 shown in FIG. 17 has two voltage supply circuits 50Fa and 50Fb. The voltage supply circuit 50F includes a gradient voltage generation circuit 52a, a capacitance element 56a, a switch 60a, an inverting amplifier circuit 62a, an amplifier 54a, and a capacitance element 90a. The voltage supply circuit 50Fb has the same configuration as the voltage supply circuit 50Fa. The voltage supply circuit 50Fb includes a gradient voltage generation circuit 52b, a capacitance element 56b, a switch 60b, an inverting amplifier circuit 62b, an amplifier 54b, and a capacitance element 90b. The voltage supply circuits 50Fa and 50Fb are electrically connected to each other via the capacitive elements 90a and 90b.

As illustrated in FIG. 17, two or more voltage supply circuits may be provided in the image pickup apparatus. As described with reference to FIGS. 2 and 3, the gradient voltage generated by the voltage supply circuit is gated in the feedback transistor 38 of the selected unit pixel cell via the switch SW _i in the vertical scanning circuit 16. Is applied to. The number of rows of a unit pixel cell included in the pixel array PA may reach several thousand rows. In such a case, due to the difference in wiring length, a delay may occur in the voltage applied to the unit pixel cell far from the voltage supply circuit as compared with the unit pixel cell closer to the voltage supply circuit. ..

In the configuration illustrated in FIG. 17, the output voltage Vouta (here, the gradient voltage) of the voltage supply circuit 50Fa and the output voltage Voutb (here, the gradient voltage) of the voltage supply circuit 50Fb are both applied to the common signal line 24. The voltage applied to the common signal line 24 is supplied to the unit pixel cell 10A belonging to the row corresponding to each switch via the switch SW _i in the vertical scanning circuit 16. Thereby, the influence of the voltage drop due to the difference in the wiring length between the voltage supply circuit and the unit pixel cell can be suppressed.

However, if a plurality of voltage supply circuits are simply provided, variations due to differences in characteristics between the gradient voltage generation circuits will occur among the gradient voltages. In the illustrated example, one of the electrodes of the capacitance element 90a is connected to a node to which the capacitance element 56a of the voltage supply circuit 50Fa and the amplifier 54a are connected, and the other is connected to the gradient voltage generation circuit 52b of the voltage supply circuit 50Fb and the capacitance. The element 56b is connected to the connected node. Further, one of the electrodes of the capacitance element 90b is connected to a node to which the capacitance element 56b of the voltage supply circuit 50Fb and the amplifier 54b are connected, and the other is connected to the gradient voltage generation circuit 52a of the voltage supply circuit 50Fa and the capacitance element. It is connected to the node to which 56a is connected. Therefore, the variation between the gradient voltage (Vgena) generated by the gradient voltage generation circuit 52a and the gradient voltage (Vgenb) generated by the gradient voltage generation circuit 52b can be averaged. Further, the noise included in the gradient voltage generated by the gradient voltage generation circuit 52a and the noise included in the gradient voltage generated by the gradient voltage generation circuit 52b are also averaged according to the capacitance ratio.

With the configuration as illustrated in FIG. 17, it is possible to supply a low noise gradient voltage to each unit pixel cell while suppressing variation in the gradient voltage among the plurality of gradient voltage generation circuits.

Next, the details of the configuration of the gradient voltage generation circuit applicable to the voltage supply circuit of the present disclosure will be described with reference to FIGS. 18 to 22.

As described with reference to FIGS. 4 and 5, in the embodiments of the present disclosure, the gradient voltage generator 52 (see, eg, FIG. 1) generates a voltage having a waveform that monotonically decreases (or increases). (See the graph of output voltage Vgen shown in FIGS. 4 and 5). When generating a voltage having a waveform that decreases (or increases) monotonically, it is common to perform filtering after generating a voltage having a stepped waveform. In generating a voltage having a stepped waveform, it is beneficial to have a large number of bits in the digital / analog conversion circuit. However, it may be difficult to increase the number of bits due to the limitation of the area of the substrate (semiconductor substrate). When a digital / analog conversion circuit having a small number of bits is used, high-frequency noise (hereinafter referred to as “spike noise”) may occur in the vicinity of the switching point. It is difficult to remove spike noise by filtering.

In the example described below, a plurality of sample / hold circuits are provided in the gradient voltage generation circuit, and spike noise is removed by using these sample / hold circuits. Bit accuracy is improved by inputting the output from which spike noise has been removed to the smoothing circuit.

FIG. 18 outlines an exemplary configuration of a gradient voltage generator applicable to the voltage supply circuits of the present disclosure. In the configuration illustrated in FIG. 18, the gradient voltage generation circuit 52 includes a digital / analog conversion circuit 92 (D / A conversion circuit 92) and sample / hold circuits 94a and 94b (first S / H circuits 94a and second). S / H circuit 94b) and a smoothing circuit 96. In the configuration illustrated in FIG. 18, the output Dout of the D / A conversion circuit 92 is input to each of the two S / H circuits 94a and 94b. The output SHouts of the two S / H circuits 94a and 94b are input to the smoothing circuit 96, and the output of the smoothing circuit 96 is output to the outside of the gradient voltage generation circuit 52. The output of the smoothing circuit 96 (voltage generated by the gradient voltage generating circuit 52) is input to the amplifier 54 in the feedback circuit 58 via the capacitive element 56 and output to the unit pixel cell 10A (see FIG. 1). ). Hereinafter, the circuit block provided between the gradient voltage generation circuit 52 and the vertical scanning circuit 16 may be referred to as a gradient voltage output unit.

FIG. 19 shows an example of the circuit configuration of the gradient voltage generation circuit 52. In the configuration illustrated in FIG. 19, the gradient voltage generation circuit 52 is smoothed by the polarity switching circuit 91, the D / A conversion circuit 92, the first S / H circuit 94a, and the second S / H circuit 94b. It has a circuit 96 and a gradient voltage output unit 98. In the illustrated example, the gradient voltage output unit 98 includes a capacitive element 56, a feedback circuit including an amplifier 54, an inverting amplifier 62, and a switch 60, and a capacitive element 70 having a fixed potential at one end. That is, here, the voltage supply circuit 50B shown in FIG. 12 will be described as an example.

In the configuration illustrated in FIG. 19, the D / A transform circuit 92 is a bilinear switched capacitor integrator. However, this is only an example, and the D / A conversion circuit 92 is not limited to the bilinear switched capacitor integrator. The D / A conversion circuit 92 includes switches SW8 to SW17, capacitive elements C7 to C10, and an integrating amplifier 99. One of the top voltage VTOP and the bottom voltage VBTM is applied to the first node N1, and the other of the top voltage VTOP and the bottom voltage VBTM is applied to the second node N2. The top voltage VTOP and the bottom voltage VBTM are sampled by the capacitive element C7 and the capacitive element C8 by a so-called crawl type switched capacitor operation, and transferred to the integrating capacitive element C10.

Switches SW8 and SW9 are used for the sampling operation to the capacitive element C7. Switches SW12 and SW13 are used for sampling to the capacitive element C8. The switches SW10 and SW11 are used for the transfer from the capacitance element C7 to the integration capacitance element C10 and the reset operation. Switches SW14 and SW15 are used for the transfer from the capacitance element C8 to the integration capacitance element C10 and the reset operation. Note that "Φ1" and "Φ2" in FIG. 19 indicate control signals of switches SW8 to SW15. The initialization of the integrating capacitance element C10 is performed by applying the control signal Φini1 to the switch SW17. The operating point of the integrator amplifier 99 is set by sampling the common voltage VCM to the capacitive element C9 via the switch SW16. By turning off the switch SW16 when the gradient voltage is generated, it is possible to block the propagation of noise superimposed on the common voltage VCM.

In the configuration illustrated in FIG. 19, a polarity switching circuit 91 is provided between the input terminal of the top voltage VTOP and the input terminal of the bottom voltage VBTM and the D / A conversion circuit 92. The polarity switching circuit 91 has four switches SW4 to SW7. The switches SW4 and SW5 are not turned on at the same time, one is on and the other is off. Similarly, switches SW6 and SW7 are not turned on at the same time, one is on and the other is off. Therefore, the top voltage VTOP can be applied to one of the first node and the second node N2, and the bottom voltage VBTM can be applied to the other of the first node N1 and the second node N2. Both the top voltage VTOP and the bottom voltage VBTM are not applied to the first node N1 at the same time, and both the top voltage VTOP and the bottom voltage VBTM are not applied to the second node N2 at the same time.

By switching on and off in each of the switches SW4 to SW7, it is possible to switch whether the top voltage VTOP and the bottom voltage VBTM are applied to the first node N1 or the second node N2, respectively. By providing the polarity switching circuit 91, it is possible to realize the generation of the falling voltage Vgen as shown in FIG. 4 and the generation of the rising voltage Vgen as shown in FIG. 5 by a simple configuration.

In the configuration illustrated in FIG. 19, the first S / H circuit 94a includes switches SW18 and SW19, resistors R2 to R4, and a hold capacitance element C11. The second S / H circuit 94b includes switches SW20 and SW21, resistors R5 to R7, and a hold capacitance element C12. It is useful to lay out the first S / H circuit 94a and the second S / H circuit 94b so that the characteristics are substantially the same. In the illustrated example, the first S / H circuit 94a and the second S / H circuit 94b are arranged symmetrically with respect to the smoothing circuit 96. The number of S / H circuits connected to the output side of the D / A conversion circuit 92 may be 3 or more.

“Φ1d” and “Φ2d” in FIG. 19 indicate control signals of switches SW18 to SW21. The sample / hold operation will be described with a focus on the first S / H circuit 94a. By controlling the switch SW18 using the control signal Φ1d, the output of the D / A conversion circuit 92 is transmitted to the node SHA having a connection with the hold capacitance element C11 via the resistor R2 at a timing that avoids spike noise. And sample. Then, using the control signal Φ2d, the output is transferred to the midpoint node VMID of the smoothing circuit 96 via the switch SW19 and the resistor R4.

In the illustrated example, the smoothing circuit 96 includes capacitive elements C13 and C14 and resistors R8 and R9. The midpoint node VMID of the smoothing circuit 96 is initialized to the reference potential Vini in advance. The initialization of the midpoint node VMID is performed by applying the control signal Φini2 to the switch SW22. The reference potential Vini is held by the capacitance element C13 via the switch SW22. The potential at the midpoint node VMID changes depending on the charge held in the capacitive element C13, the output of the first S / H circuit 94a, and the output of the second S / H circuit 94b. The gradient voltage generation circuit 52 outputs a voltage smoothed by the resistors R8 and R9 and the capacitance element C14. According to the configuration shown in FIG. 19, smoothing can also be performed during the sampling period, so that the output delay can be alleviated.

FIG. 20 is a timing chart showing an example of the relationship between the input clocks CK and CKD and each control signal. In FIG. 20, the horizontal axis of each graph indicates time T. In FIG. 20, in order from the top, input clock CK, input clock CKD, control signal Φ1, control signal Φ2, output Dout of D / A conversion circuit 92, control signal Φ1d, control signal Φ2d, first S / H circuit 94a. The potential of the node SHA and the potential of the node SHB of the second S / H circuit 94b (see FIG. 19), and the output voltage Vgen of the gradient voltage generation circuit 52 are shown. In FIG. 20, the potential of the node SHA is indicated by a solid line LA, and the potential of the node SHB is indicated by a broken line LB.

The input clock CKD is, for example, a signal shifted by several nanoseconds with respect to the input clock CK. The control signals Φ1, Φ2, Φ1d and Φ2d are generated by using the input clock CK and the input clock CKD.

FIG. 21 shows an example of a clock generation circuit that generates the control signals Φ1, Φ2, Φ1d, and Φ2d shown in FIG. The clock generation circuit 160 shown in FIG. 21 includes a plurality of logic gates 135 to 152.

The D / A conversion circuit 92 operates based on the control signals Φ1 and Φ2 generated from the input clocks CK and CKD, and outputs a stepped waveform (output Dout in FIG. 20). The output Dout contains spike noise in the vicinity of the step. The output Dout is sampled while avoiding spike noise by using the control signals Φ1d and Φ2d. The first S / H circuit 94a and the second S / H circuit 94b output waveforms LA and LB as shown in FIG. 20, respectively. The two waveforms are superimposed and smoothed at the midpoint node VMID in the smoothing circuit 96. In this way, the first S / H circuit 94a, the second S / H circuit 94b, and the smoothing circuit 96 generate a gradient voltage having a substantially smooth gradient from the stepped output Dout. , It is output from the gradient voltage generation circuit 52. According to the configuration as illustrated in FIG. 19, the noise reduction of the gradient voltage generation circuit 52 and the accuracy higher than the bit accuracy of the D / A conversion circuit 92 can be realized.

FIG. 22 shows another example of the circuit configuration of the gradient voltage generation circuit. The difference between the gradient voltage generation circuit 52B shown in FIG. 22 and the gradient voltage generation circuit 52 shown in FIG. 19 is that the gradient voltage generation circuit 52B replaces the resistors R3, R4, R6 and R7 with transistors 154 to 157. Is to have. In the configuration illustrated in FIG. 19, the control circuit 153 is connected to the gates of the transistors 154 to 157. The control circuit 153 generates a gate voltage to be supplied to the transistors 154 to 157.

In the configuration illustrated in FIG. 22, P-channel MOS transistors are used as the transistors 154 to 157. In this example, a P-channel MOS transistor is used as a resistor with variable resistance. That is, in this example, the source-drain voltage dependence in the linear region of the MOS transistor is used. According to the configuration illustrated in FIG. 22, the resistance in the transistors 154 to 157 can be changed by adjusting the gate voltage supplied from the control circuit 153. By changing the gate voltage supplied from the control circuit 153, it is possible to actively change the time constant in the first S / H circuit 94a and the time constant in the second S / H circuit 94b. is there.

As shown in FIG. 20, the graph showing the potential of the node SHA and the graph showing the potential of the node SHB generally show a curvilinear change at the rising and falling edges of the voltage. This is because the current flowing through the switch SW19 of the first S / H circuit 94a and the current flowing through the switch SW21 of the second S / H circuit 94b change depending on the potential difference between both ends of the resistor in the transient state of averaging. Due to the fact that

In this example, the transistor 154 uses a voltage that adjusts the time constant according to the slope of the gradient voltage so that the current flowing through the switch SW19 and the current flowing through the switch SW21 are constant even in the transient state of averaging. Apply to ~ 157. This makes it possible to obtain an appropriate time constant according to the slope at the slope voltage.

An N-channel MOS transistor may be used instead of the P-channel MOS transistor. Further, in the illustrated example, the voltages applied to the gates of the transistors 154 to 157 may be different from each other, and a common voltage is selectively applied to some of the transistors 154 to 157. You may. As the gate voltage, a gradient voltage generated by using the output of a gradient voltage generation circuit or the like may be applied.

(Fourth Embodiment)
FIG. 23 shows an exemplary connection relationship between a unit pixel cell and peripheral circuits in the image pickup apparatus according to the fourth embodiment of the present disclosure. The image pickup apparatus 400 shown in FIG. 23 has a voltage supply circuit 50A and a pixel array PA connected to the voltage supply circuit 50A via the vertical scanning circuit 16. In the configuration illustrated in FIG. 23, the pixel array PA includes four unit pixel cells 10D. Of course, the number of unit pixel cells 10D included in the pixel array PA is not limited to four. Instead of the voltage supply circuit 50A, any of the voltage supply circuits 50B to 50E described above, or a set of the voltage supply circuits 50Fa and 50Fb may be used.

The image pickup apparatus 400 has a vertical scanning circuit 16, a load circuit 27, a column signal processing circuit 20, a horizontal signal readout circuit 21, and an inverting amplifier 29 as peripheral circuits. The column signal processing circuit 20, the load circuit 27, and the inverting amplifier 29 are arranged for each row of unit pixel cells 10D arranged in two dimensions. The negative input terminal of the inverting amplifier 29 is connected to the corresponding signal readout line 18. A predetermined voltage (for example, 1V or a positive voltage in the vicinity of 1V) Vref is supplied to the input terminal on the positive side of the inverting amplifier 29. This voltage Vref is used as a reference voltage in reset. The output terminal of the inverting amplifier 29 is connected to a plurality of unit pixel cells 10D having a connection with the negative input terminal of the inverting amplifier 29 via a feedback line 31 provided corresponding to each row. ..

In the configuration illustrated in FIG. 23, the feedback control line 28 is connected to the vertical scanning circuit 16. As will be described later, when the vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, a feedback loop is formed in which the output of the unit pixel cell 10D is negatively fed back. The inverting amplifier 29 constitutes a part of a feedback circuit that negatively feeds back the output from the unit pixel cell 10D. The inverting amplifier 29 may be called a feedback amplifier. The inverting amplifier 29 may have a gain adjusting terminal 29a for changing the inverting amplification gain. The gain of the inverting amplifier 29 changes according to the potential of the gain adjusting terminal 29a. Since the product of the gain G and the band B is constant in the inverting amplifier 29, for example, when the gain G is lowered, the band B becomes wider (the cutoff frequency becomes higher).

FIG. 24 shows an exemplary circuit configuration of the unit pixel cell 10D. In FIG. 24, the voltage supply circuit 50A and the switch SW _i in the vertical scanning circuit 16 are not shown.
In the configuration illustrated in FIG. 24, the gate of the amplification transistor 34 is connected to the charge storage node 44. One of the source and drain of the amplification transistor 34 (drain in the case of N-channel MOS) is connected to the power supply wiring (source follower power supply) 22. The amplification transistor 34 amplifies the signal generated by the photoelectric conversion unit 15. In the configuration illustrated in FIG. 24, the voltage switching circuit 7 described with reference to FIG. 2 is unnecessary.

By applying a predetermined voltage to the feedback control line 28, a feedback circuit 47 that negatively feeds back the output of the signal detection circuit SC can be formed. The feedback circuit 47 is a negative feedback amplifier circuit including an amplifier transistor 34, an inverting amplifier 29, and a feedback transistor 38. Assuming that the gain of the feedback circuit 47 is A, the kTC noise is canceled to a magnitude of 1 / (1 + A) by the formation of the feedback circuit 47.

In this example, the formation of the feedback circuit 47 is performed on one of a plurality of unit pixel cells 10D that share the feedback line 31. In this way, the feedback circuit may be formed for each row of the pixel array PA.

The voltage applied to the feedback control line 28 may be a gradient voltage. By using the gradient voltage as the gate voltage, it is possible to avoid sudden on / off of the transistor. As a result, it is possible to reduce the noise generated by turning the transistor on and off. A gradient voltage may be applied to the gain adjusting terminal 29a of the inverting amplifier 29.

FIG. 25 shows a modified example of the unit pixel cell in the fourth embodiment. In the unit pixel cell 10E shown in FIG. 25, one of the source and drain of the reset transistor 36 is connected to the charge storage node 44, and the other is connected to the reset drain node 46. That is, in this example, the reset transistor 36 is connected in parallel with the capacitive element 41. Such a circuit configuration is also applicable. In the circuit configuration shown in FIG. 25, similarly to the circuit configuration shown in FIG. 24, the formation of the feedback circuit 47 is executed for one of the plurality of unit pixel cells 10E sharing the feedback line 31.

(Fifth Embodiment)
FIG. 26 schematically shows a configuration example of the camera system according to the fifth embodiment of the present disclosure. The camera system 600 shown in FIG. 26 includes a lens optical system 601, an image pickup device 100, a system controller 603, and a camera signal processing unit 604.

The lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens optical system 601 collects light on the imaging surface of the imaging device 100.

The system controller 603 controls the entire camera system 600. The system controller 603 can be realized, for example, by a microcomputer.

The camera signal processing unit 604 functions as a signal processing circuit that processes an output signal from the image pickup apparatus 100. The camera signal processing unit 604 performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance. The camera signal processing unit 604 can be realized by, for example, a DSP (Digital Signal Processor) or the like.

The image pickup device 100 in the camera system according to the embodiment of the present disclosure has reduced the influence of noise. As a result, the electric charge can be accurately read out and a good image can be obtained. Further, since the variation in the threshold voltage of the transistor in the amplifier 54 can be canceled, it is possible to supply a low noise gradient voltage to the band transistor 38 of the unit pixel cell 10A. Further, since the initial voltage of the gradient voltage can be arbitrarily set, an appropriate initial voltage can be used according to the variation in the threshold voltage of the band transistor 38, and efficient noise suppression can be performed. Instead of the image pickup device 100, any of the image pickup device 200 described with reference to FIG. 8, the image pickup device 300 described with reference to FIG. 17, and the image pickup device 400 described with reference to FIG. 23 may be used. Good.

According to the embodiments of the present disclosure, the influence of noise can be reduced. The imaging device according to the present disclosure can be applied to various camera systems and sensor systems such as digital still cameras, medical cameras, surveillance cameras, in-vehicle cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras.

2 Amplifier 3, 3C Band control circuit 3SA, 3SB, 3SC Band control unit 4A, 4B, 4C Reset circuit 5S Output selection unit 6 Constant current source 7 Voltage switching circuit 10A to 10E Unit pixel cell 15 Photoelectric conversion unit 15a First electrode 15b Photoelectric conversion film 15c 2nd electrode 16 Vertical scanning circuit 17 Storage control line 18 Signal readout line 19 Constant current source 20 Column signal processing circuit 21 Horizontal signal readout circuit 22 Power supply wiring 23 Horizontal common signal line 24 Common signal line 25 Reset voltage line 26 Reset control line 27 Load circuit 28 Feedback control line 29 Inverting amplifier 29a Gain adjustment terminal 30 Address signal line 31 Feedback line 32 Sensitivity adjustment line 34 Amplification transistor 36 Reset transistor (second transistor)
38 Feedback transistor (first transistor)
40 Address transistor 41, 42 Capacitive element 44 Charge storage node 46 Reset drain node 47, 48, 49 Feedback circuit (second feedback circuit)
50A-50E, 50Fa, 50Fb Voltage supply circuit 52, 52a, 52b, 52B Gradient voltage generation circuit 54, 54a, 54b, 54S amplifier (first amplifier)
55 Input transistor 56, 56a, 56b Capacitive element 57N NMOS current source 57P MOSFET current source 58, 58D, 58E Feedback circuit (first feedback circuit)
59 Feedback transistor 60, 60a, 60b, 61 Switch 62, 62a, 62b Inverting amplifier (second amplifier)
62n Inverted input terminal 62p Non-inverting input terminal 64 Control circuit 65 Feedback amplifier 66 Constant current source 67 Buffer 68 Transistor for detecting threshold voltage 70, 71, 72 Capacitive element 73 Transistor 74, 75 Input transistor 76, 77 Transistor 78 , 79 Current source transistor 80 Amplifier 82 Mirror primary transistor 83 Current source transistor 84 Diode connection transistor 85 Amplifier input transistor 86 Current source transistor 87 Resistor 88 Capacitive element 89 Connection line 90a, 90b Capacitive element 92 Digital / analog conversion circuit 94a, 94b Sample / Hold circuit 96 Smoothing circuit 100, 200, 300, 400 Imaging device 600 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing unit PA Pixel array SW1, SW2, SW _i switch VS1 First voltage source VS2 First 2 voltage sources

Claims (9)

Gradient voltage generation circuit and
With the first amplifier
A first capacitive element connected between the gradient voltage generation circuit and the first amplifier,
A first feedback circuit for negatively feeding back the output of the first amplifier is provided.
The first feedback circuit is a voltage supply circuit including a switch that selectively forms a feedback loop. The voltage supply circuit according to claim 1, wherein the first amplifier has a source follower, and the output voltage of the gradient voltage generation circuit is input to the source follower via the first capacitive element. The first feedback circuit includes a second amplifier which is an inverting amplifier.
The voltage supply circuit according to claim 1 or 2, wherein the output of the first amplifier is input to the inverting input terminal of the second amplifier. The voltage supply circuit according to claim 3, wherein the switch includes a first switch connected between an output terminal of the second amplifier and an input terminal of the first amplifier. The voltage supply circuit according to any one of claims 1 to 4, further comprising a second capacitive element having one end connected to an input terminal of the first amplifier. A second capacitive element whose one end is connected to the inverting input terminal of the second amplifier,
A third capacitive element whose one end is connected to the output terminal of the second amplifier, and
With more
The voltage supply circuit according to claim 4, wherein the switch includes a second switch connected between an output terminal of the first amplifier and an inverting input terminal of the second amplifier. The voltage supply circuit according to claim 3 or 4, further comprising a third amplifier connected between the output terminal of the second amplifier and the input terminal of the first amplifier. The gradient voltage generation circuit is
D / A conversion circuit and
Smoothing circuit and
It includes a first sample / hold circuit and a second sample / hold circuit connected in parallel to each other between the D / A conversion circuit and the smoothing circuit.
The voltage supply circuit according to any one of claims 1 to 7, wherein the output of the smoothing circuit is input to the first amplifier via the first capacitive element. The D / A conversion circuit
A first sample circuit including a fourth capacitive element and
Includes a second sample circuit that includes a fifth capacitive element,
The signal sampled by the fourth capacitive element is input to the first sample / hold circuit and is input to the first sample / hold circuit.
The voltage supply circuit according to claim 8, wherein the signal sampled by the fifth capacitive element is input to the second sample / hold circuit.

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