JP6793222B2 - Electronics - Google Patents

Description

The present invention relates to a product, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light emitting device, a storage device, an information processing device, a method for driving them, or a method for manufacturing them. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light emitting device, a power storage device, a storage device, a method for driving them, or a method for manufacturing them.

The configuration of the active matrix type display device using a light emitting element differs depending on the manufacturer, but usually at least the light emitting element and the transistor (switching transistor) that controls the input of the video signal to the pixel. And a transistor (driving transistor) for controlling the current value supplied to the light emitting element are provided in each pixel.

By setting all the transistors provided in the pixels to have the same polarity, it is possible to partially omit steps such as adding an impurity element that imparts one conductivity to the semiconductor film in the transistor manufacturing process. The following Patent Document 1 describes a light emitting element type display in which pixels are composed of only n-channel transistors.

Japanese Unexamined Patent Publication No. 2003-195810

By the way, in the light emitting device, since the drain current of the driving transistor is supplied to the light emitting element, if the threshold voltage of the driving transistor varies between pixels, the variation is reflected in the brightness of the light emitting element. Therefore, the proposal of a pixel configuration capable of correcting the current value of the drive transistor in anticipation of the variation in the threshold voltage is an important issue in improving the image quality of the light emitting device.

Based on the above-mentioned technical background, one of the problems is to provide a light emitting device capable of suppressing the variation in brightness between pixels due to the variation in the threshold voltage of the drive transistor.

One aspect of the present invention is to provide a new semiconductor device or the like as one of the problems. The description of these issues does not prevent the existence of other issues. One aspect of the present invention is
It is not always necessary to solve all of these issues. Issues other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract issues other than these from the description of the description, drawings, claims, etc. Is.

A light emitting device according to an aspect of the present invention includes a transistor having a first gate and a second gate that overlap each other via a semiconductor film, one of the source and drain of the transistor, and the first gate. A first capacitive element that holds a potential difference between the two, a second capacitive element that holds a potential difference between one of the source and drain of the transistor and the second gate, and a second gate of the transistor. And the switch that controls the continuity between the wiring and
It includes a light emitting element to which the drain current of the transistor is supplied.

According to one aspect of the present invention, it is possible to provide a light emitting device capable of suppressing variations in brightness between pixels due to variations in the threshold voltage of a transistor.

In addition, according to one aspect of the present invention, a novel semiconductor device or the like can be provided. The description of these effects does not preclude the existence of other effects. One aspect of the present invention is
It is not always necessary to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. A timing chart showing the operation of pixels. The figure which shows the operation of a pixel. The figure which shows the operation of a pixel. A timing chart showing the operation of pixels. The figure which shows the relationship between Vbg and Vth. The figure which shows the structure of the pixel part. The figure which shows the structure of a pixel part and a selection circuit. The circuit diagram of the monitor circuit. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. A timing chart showing the operation of pixels. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The cross-sectional view explaining the manufacturing method of a light emitting device. The cross-sectional view explaining the manufacturing method of a light emitting device. The cross-sectional view explaining the manufacturing method of a light emitting device. Sectional view of the light emitting device. Perspective view of the panel. Diagram of electronic equipment. The figure which shows the appearance of a circuit board. The figure which shows the structure of the information processing apparatus using a light emitting device. Top view showing the structure of a transistor. Sectional drawing which shows the structure of a transistor. Top view showing the structure of a transistor. Sectional drawing which shows the structure of a transistor. Top view showing the structure of a transistor. Sectional drawing which shows the structure of a transistor. The figure which shows the composition of a pixel. Sectional drawing which shows the structure of a transistor. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the composition of a pixel. The figure which shows the structure of the pixel part. The figure which shows the structure of the pixel part. The figure which shows the characteristic of a transistor. The figure which shows the composition and operation of a pixel. The figure which shows the structure of the display device. The figure which shows the display photograph of a display device. The figure which shows the characteristic of a transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

In the present specification, the light emitting device refers to a panel in which a light emitting element is formed in each pixel and a module in which an IC or the like including a drive circuit or a controller is mounted on the panel.
Included in that category. Further, the light emitting device according to one aspect of the present invention includes an element substrate corresponding to one form before the light emitting element is completed in the process of manufacturing the light emitting device, and the element substrate includes a transistor and a transistor. Each of the plurality of pixels is provided with a pixel electrode to which a voltage is supplied via a transistor.

Further, the source of the transistor means a source region that is a part of a semiconductor film that functions as an active layer, or a source electrode that is electrically connected to the semiconductor film. Similarly, the drain of a transistor means a drain region that is a part of the semiconductor membrane, or a drain electrode that is electrically connected to the semiconductor membrane. Further, the gate means a gate electrode.

The names of the source and drain of a transistor change depending on the conductive type of the transistor and the high and low potentials given to each terminal. Generally, in an n-channel transistor, a terminal to which a low potential is given is called a source, and a terminal to which a high potential is given is called a drain. Further, in a p-channel transistor, a terminal to which a low potential is given is called a drain, and a terminal to which a high potential is given is called a source. In this specification, for convenience,
The connection relationship between transistors may be described on the assumption that the source and drain are fixed, but in reality, the names of source and drain are interchanged according to the above potential relationship.

Further, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like.
Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text.
Other than the connection relationships shown in the figure or text, it shall be described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. Elements (eg, switches, transistors, capacitive elements, inductors) that allow an electrical connection between X and Y when the element, light emitting element, load, etc. are not connected between X and Y. , A resistance element, a diode, a display element, a light emitting element, a load, etc.), and X and Y are connected to each other.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows. Alternatively, the switch has a function of selecting and switching the path through which the current flows. It should be noted that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion) Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.)
, Voltage source, current source, switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc. ) Can be connected to one or more between X and Y. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do. In addition, X and Y
When and are functionally connected, when X and Y are directly connected, and when X and Y are connected.
It shall include the case where and is electrically connected.

When it is explicitly stated that X and Y are electrically connected, it is different when X and Y are electrically connected (that is, between X and Y). When X and Y are functionally connected (that is, when they are connected by sandwiching another circuit between X and Y) and when they are functionally connected by sandwiching another circuit between X and Y. (That is, when X and Y are directly connected (that is, when another element or another circuit is not sandwiched between X and Y)). It shall be disclosed in documents, etc. That is, when it is explicitly stated that it is electrically connected, the same contents as when it is explicitly stated that it is simply connected are disclosed in the present specification and the like. It is assumed that it has been done.

<Pixel configuration example>
FIG. 1 shows the configuration of the pixel 10 of the light emitting device according to one aspect of the present invention as an example. The pixel 10 shown in FIG. 1 includes a transistor 11, a switch 16, a capacitance element 13, a capacitance element 18, and a light emitting element 14.

The light emitting element 14 includes an LED (Light Emitting Diode) or an OLED (O).
The category includes elements whose brightness is controlled by a current or a voltage, such as an rganic Light Emitting Diode). For example, the OLED has an EL layer and
It has at least an anode and a cathode. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and at least a light emitting layer containing a luminescent substance is contained in these layers. In the EL layer, electroluminescence is obtained by the current supplied when the potential difference between the cathode and the anode becomes equal to or higher than the threshold voltage Vthe of the light emitting element 14. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphory light) when returning from the triplet excited state to the ground state.

Further, one of the anode and the cathode of the light emitting element 14 functions as a pixel electrode, and the other functions as a common electrode. FIG. 1 illustrates the configuration of a pixel 10 in which the anode of the light emitting element 14 is used as a pixel electrode and the cathode of the light emitting element 14 is used as a common electrode.

In addition to the normal gate (first gate), the transistor 11 has a second gate that overlaps with the first gate with a semiconductor film in between. In FIG. 1, the first gate is shown as G1 and the second gate is shown as G2.

Further, the potential of the first gate of the transistor 11 is controlled according to the image signal supplied from the wiring SL. The switch 16 has a wiring B to the second gate of the transistor 11.
It has a function of controlling the supply of the potential of L.

The switch 16 can be configured by using one or a plurality of transistors. Alternatively, the switch 16 may use a capacitive element in addition to the single or a plurality of transistors.

The capacitive element 13 has a function of holding a potential difference between the second gate of the transistor 11 and one of the source and drain of the transistor 11. The capacitive element 18 has a function of holding a potential difference between the first gate of the transistor 11 and one of the source and drain of the transistor 11.

FIG. 1 illustrates a case where the transistor 11 is an n-channel type. In this case, one of the source and the drain of the transistor 11 is electrically connected to the anode of the light emitting element 14. The other of the source and drain of the transistor 11 is electrically connected to the wiring VL, and the cathode of the light emitting element 14 is electrically connected to the wiring CL.
Further, the potential of the wiring VL is higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 14 and the threshold voltage Vth of the transistor 11 to the potential of the wiring CL. Therefore, when the value of the drain current of the transistor 11 is determined according to the image signal, the drain current is supplied to the light emitting element 14, so that the light emitting element 14 is in a light emitting state.

When the transistor 11 is a p-channel type, as shown in FIG. 35, the transistor 11
One of the source and the drain of the light emitting element 14 is electrically connected to the cathode of the light emitting element 14. The other of the source and drain of the transistor 11 is electrically connected to the wiring VL, and the anode of the light emitting element 14 is electrically connected to the wiring CL. Further, the potential of the wiring CL is higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 14 and the threshold voltage Vth of the transistor 11 to the potential of the wiring VL. Then, as in the case where the transistor 11 is an n-channel type, even when the transistor 11 is a p-channel type, when the value of the drain current of the transistor 11 is determined according to the image signal, the drain current is supplied to the light emitting element 14. As a result, the light emitting element 14 is in a light emitting state.

Then, in one aspect of the present invention, the voltage Vbg between one of the source and drain of the transistor 11 and the second gate is controlled before determining the value of the drain current of the transistor 11 according to the image signal. The threshold voltage Vth of the transistor 11 is corrected to prevent the threshold voltage Vth of the transistor 11 from being varied among the pixels 10.

Specifically, the transistor 11 is normalized by supplying the potential of the wiring BL to the second gate of the transistor 11 via the switch 16. For example, when the transistor 11 is an n-channel type, when the voltage Vbg is increased, the threshold voltage Vth shifts in the negative direction, and the transistor 11 becomes normal. Further, when the transistor 11 is a p-channel type, when the voltage Vbg is lowered, the threshold voltage Vth shifts in the positive direction, and the transistor 11 becomes a normalion.

FIG. 9 shows the relationship between the voltage Vbg and the threshold voltage Vth when the transistor 11 is an n-channel type. Let Vth0 be the threshold voltage Vth of the transistor 11 when the voltage Vbg is 0. Then, when the voltage Vbg is shifted from 0 in the positive direction to Vbg1, the threshold voltage Vth shifts from Vth0 in the negative direction and becomes Vth1 (Vth1 <0).

Then, when the transistor 11 is in a normalized state, the gate voltage Vgs, which is the potential difference between the first gate of the transistor 11 and one of the source and drain, is maintained at a constant value, and the drain current of the transistor 11 is the transistor 11. Second gate and capacitive element 1
It is configured to flow to 3.

With the above configuration, the electric charge stored in the second gate of the transistor 11 and the capacitive element 13 moves, and the potentials of one of the source and the drain of the transistor 11 shift. Then, as the potential of one of the source and drain of the transistor 11 shifts, the voltage Vb
Since g changes, the threshold voltage of the transistor 11 shifts in the direction of normalization off. For example, when the transistor 11 is an n-channel type, the voltage Vbg shifts in the negative direction, so that the threshold voltage Vth shifts in the positive direction. Further, when the transistor 11 is a p-channel type, the voltage Vbg shifts in the positive direction, so that the threshold voltage Vth shifts in the negative direction.

Finally, when the threshold voltage Vth of the transistor 11 approaches the gate voltage Vgs maintained at a constant value as much as possible, the drain current converges to 0 and the transistor 11 is turned off. At this time, the threshold voltage Vth of the transistor 11 is set to Vth2. As shown in FIG. 9, when the voltage Vbg becomes Vbg2, the drain current of the transistor 11 whose gate voltage Vgs is kept at a constant value converges to 0. As a result, the threshold voltage Vth is corrected to Vth2. The potential difference ΔV0 is held by the capacitance element 13.

In one aspect of the present invention, the above configuration can prevent the variation in the threshold voltage of the transistor 11 that occurs between the pixels 10 from affecting the value of the drain current of the transistor 11. As a result, it is possible to suppress variations in brightness between pixels.

Note that FIG. 1 shows a configuration of a pixel 10 capable of correcting the threshold voltage Vth of the transistor 11 by controlling the voltage Vbg between one of the source and drain of the transistor 11 and the second gate. However, by controlling the voltage Vgs between one of the source and drain of the transistor 11 and the first gate, the threshold voltage Vt of the transistor 11 is controlled.
It may be possible to correct h.

FIG. 33 shows, as an example, the configuration of the pixel 10 capable of correcting the threshold voltage Vth of the transistor 11 by controlling the voltage Vgs. In the pixel 10 shown in FIG. 33, the potential of the second gate of the transistor 11 is controlled according to the image signal supplied from the wiring SL. The switch 16 has a function of controlling the supply of the potential of the wiring BL to the first gate of the transistor 11. The capacitive element 13 includes the first gate of the transistor 11 and the transistor 11.
It has a function of holding a potential difference between one of the source and the drain of the above. The capacitive element 18 has a function of holding a potential difference between the second gate of the transistor 11 and one of the source and drain of the transistor 11. In one aspect of the present invention, according to the above configuration, the voltage Vgs between one of the source and drain of the transistor 11 and the first gate is controlled before the value of the drain current of the transistor 11 is determined according to the image signal. Therefore, the threshold voltage Vth of the transistor 11 can be corrected, and it is possible to prevent the threshold voltage Vth of the transistor 11 from being varied among the pixels 10.

<Specific configuration example 1 of pixels>
FIG. 2A shows a specific configuration of the pixel 10 shown in FIG. 1 as an example.

The pixel 10 shown in FIG. 2A has a switch 15 to a switch 17 and a capacitance element 18 in addition to the transistor 11, the switch 12, the capacitance element 13, and the light emitting element 14.

Specifically, in the pixel 10 shown in FIG. 2A, the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. Further, the wiring SL is electrically connected to the pixel electrode of the light emitting element 14 via the switch 15 and the switch 12. In the transistor 11, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element 14, and the other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light emitting element 14 is electrically connected to the wiring IL via the switch 17. One of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14.
One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. Light emitting element 1
The common electrode of 4 is electrically connected to the wiring CL.

Next, FIG. 2B shows another specific configuration of the pixel 10 shown in FIG. 1 as an example.

The pixel 10 shown in FIG. 2 (B) is different in configuration from the pixel 10 shown in FIG. 2 (A) in that it further has a switch 19.

Specifically, in the pixel 10 shown in FIG. 2B, the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. The wiring SL is the switch 15,
It is electrically connected to the pixel electrode of the light emitting element 14 via the switch 12 and the switch 19. In the transistor 11, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element 14 via the switch 19, and the other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light emitting element 14 is electrically connected to the wiring IL via the switch 17 and the switch 19. One of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14 via the switch 19. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14 via the switch 19. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, in the pixel 10 shown in FIG. 2A, a configuration example of the pixel when a transistor is used for each switch will be described. FIG. 3A shows a configuration example of the pixel 10 of the pixel 10 shown in FIG. 2A when a transistor is used as the switch 12 and the switches 15 to 17 respectively.

The pixels 10 shown in FIG. 3A are a transistor 11, a transistor 12t having a function as a switch 12, a transistor 15t to a transistor 17t having a function as a switch 15 to a switch 17, respectively, a capacitive element 13, and a capacitive element. It has 18 and a light emitting element 14.

Specifically, in the transistor 15t, the gate is electrically connected to the wiring GLa, one of the source and drain is electrically connected to the wiring SL, and the other of the source and drain is electrically connected to the first gate of the transistor 11. In the transistor 12t, the gate is the wiring GLb, one of the source and the drain is the pixel electrode of the light emitting element 14, and the other of the source and the drain is the transistor 1.
Each of them is electrically connected to the first gate of 1. In the transistor 11, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element 14, and the other of the source and the drain is electrically connected to the wiring VL. In the transistor 16t, the gate is electrically connected to the wiring GLb, one of the source and the drain is electrically connected to the wiring BL, and the other of the source and the drain is electrically connected to the second gate of the transistor 11. In the transistor 17t, the gate is electrically connected to the wiring GLd, one of the source and drain is electrically connected to the wiring IL, and the other of the source and drain is electrically connected to the pixel electrode of the light emitting element 14.

Further, one of the pair of electrodes of the capacitance element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, in the pixel 10 shown in FIG. 2B, a configuration example of the pixel when a transistor is used for each switch will be described. FIG. 3 (B) shows a configuration example of the pixel 10 when a transistor is used as the switch 12, the switch 15 to the switch 17, and the switch 19 of the pixel 10 shown in FIG. 2 (B).

The pixel 10 shown in FIG. 3B has a transistor 11, a transistor 12t having a function as a switch 12, a transistor 15t to a transistor 17t having a function as a switch 15 to a switch 17, and a function as a switch 19. It has a transistor 19t, a capacitance element 13, a capacitance element 18, and a light emitting element 14.

Specifically, in the transistor 15t, the gate is electrically connected to the wiring GLa, one of the source and drain is electrically connected to the wiring SL, and the other of the source and drain is electrically connected to the first gate of the transistor 11. In the transistor 12t, the gate is electrically connected to the wiring GLb, one of the source and drain is electrically connected to one of the source and drain of the transistor 19t, and the other of the source and drain is electrically connected to the first gate of the transistor 11. In the transistor 11, one of the source and the drain is electrically connected to one of the source and the drain of the transistor 19t, and the other of the source and the drain is electrically connected to the wiring VL. In the transistor 16t, the gate is connected to the wiring GLb, and one of the source and drain is connected to the wiring BL.
The other of the source and drain is electrically connected to the second gate of the transistor 11, respectively. In the transistor 17t, the gate is electrically connected to the wiring GLd, one of the source and drain is electrically connected to the wiring IL, and the other of the source and drain is electrically connected to one of the source and drain of the transistor 19t. The gate of the transistor 19t is GLc.
In addition, the other of the source and the drain is electrically connected to the pixel electrode of the light emitting element 14, respectively.

Further, one of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t. One of the pair of electrodes of the capacitive element 18 is the first transistor 11.
It is electrically connected to the gate of the transistor, and the other is electrically connected to one of the source and drain of the transistor 19t. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, the switch 12 and the switches 15 to 17 of the pixel 10 shown in FIG. 2B are shown.
FIG. 4A shows another configuration example of the pixel 10 when each transistor is used.

The pixel 10 shown in FIG. 4A is the pixel 1 shown in FIG. 3B in that one of the source and drain of the transistor 16t is electrically connected to the wiring VL instead of the wiring BL.
The configuration is different from 0.

Next, the switch 12 and the switches 15 to 17 of the pixel 10 shown in FIG. 2B are shown.
4 (B) shows another configuration example of the pixel 10 when a transistor is used as the switch 19.

The pixel 10 shown in FIG. 4B differs from the pixel 10 shown in FIG. 3B in that the gate of the transistor 17t is electrically connected to the wiring GLa instead of the wiring GLd.

<Specific operation example 1 of pixels>
Next, the operation of the pixels of the light emitting device according to one aspect of the present invention will be described by taking the pixel 10 shown in FIG. 3B as an example.

FIG. 5 shows a timing chart of the potential input to the wiring GLa to the wiring GLd and the wiring SL.
The timing chart of the potential of the image signal Vdata input to is shown. In the timing chart shown in FIG. 5, all the transistors included in the pixel 10 shown in FIG. 3B are n.
The case of the channel type is illustrated. Further, FIGS. 6 and 7 schematically show the operation of the pixel 10 in each period. However, in FIGS. 6 and 7, a transistor other than the transistor 11 is shown as a switch in order to show the operation of the pixel 10 in an easy-to-understand manner.

First, in the period t1, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, the wiring GLc is given a low-level potential, and the wiring GLd is given a high-level potential. Therefore, as shown in FIG. 6A, the transistor 12t, the transistor 16t, and the transistor 17t are turned on, and the transistor 15t and the transistor 19t are turned off.

Further, the potential Vano is given to the wiring VL, the potential V0 is given to the wiring BL, the potential V1 is given to the wiring IL, and the potential Vcat is given to the wiring CL electrically connected to the common electrode of the light emitting element 14. ing. Therefore, the potential V1 is given to the first gate (denoted by node A) of the transistor 11, the potential V0 is given to the second gate (denoted by node B) of the transistor 11, and the source and drain of the transistor 11 are given. One (denoted as node C) has the potential V1
Is given.

The potential Vano is the potential Vcat, the threshold voltage Vthe of the light emitting element 14, and the transistor 11.
It is desirable that the potential is higher than the potential obtained by adding the threshold voltage Vth of. And the potential V0
Node C to the extent that the threshold voltage Vth of the transistor 11 is shifted in the negative direction.
It is desirable that the potential is sufficiently high. Specifically, as shown in FIG. 9, the voltage Vb
Assuming that the threshold voltage Vth of the transistor 11 when g is 0 is Vth0, node B
Let Vbg1 be the voltage Vbg corresponding to the potential difference between the node C and the node C. As a result, in the period t1, the threshold voltage Vth of the transistor 11 becomes Vth1. Since the transistor 11 is normalized by the above configuration, the transistor 11 can be turned on even if the potential difference between the node A and the node C, that is, the gate voltage of the transistor 11 is 0.

When the transistor 11 is a p-channel type, it is desirable that the potential V0 is sufficiently low with respect to the node C so as to shift the threshold voltage Vth of the transistor 11 in the positive direction. Since the transistor 11 is normalized by the above configuration, the transistor 11 can be turned on even if the potential difference between the node A and the node C, that is, the gate voltage of the transistor 11 is 0.

Then, in the period t2, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, the wiring GLc is given a low-level potential, and the wiring GLd is given a low-level potential. Therefore, as shown in FIG. 6B, the transistor 12t and the transistor 16t are turned on, and the transistor 15t, the transistor 17t, and the transistor 19t are turned off.

Further, a potential Vano is given to the wiring VL, and a potential V0 is given to the wiring BL. Therefore, the state in which the potential V0 is given to the node B is maintained, and the threshold voltage Vth of the transistor 11 remains shifted to Vth1 in the negative direction at the start of the period t2, so that the transistor 11 is on. Then, in the period t2, the current path between the wiring VL and the wiring IL is cut off by the switch 17, so that the potentials of the nodes A and C start to rise due to the drain current of the transistor 11. When the potential of node C rises, node B
And the voltage Vbg corresponding to the potential difference of the node C becomes low, and the threshold voltage Vt of the transistor 11
h shifts in the positive direction. Finally, the threshold voltage Vt of the transistor 11
When h approaches 0 as much as possible, the transistor 11 is turned off. When the threshold voltage Vth of the transistor 11 is 0, the potential difference between the node B and the node C is V0-V2.

That is, the threshold voltage Vth of the transistor 11 is corrected to 0 so that the drain current converges to 0 with respect to the gate voltage 0 when the potential difference between the node B and the node C is V0-V2. Become. The potential difference V0-V2 between the node B and the node C is applied to the capacitive element 13.

Then, in the period t3, the wiring GLa is given a high level potential, the wiring GLb is given a low level potential, the wiring GLc is given a low level potential, and the wiring GLd is given a high level potential. Therefore, as shown in FIG. 7A, the transistor 15t and the transistor 17t are turned on, and the transistor 12t, the transistor 16t, and the transistor 19t are turned off.

Further, the wiring VL contains the potential Vano, and the wiring SL contains the potential Vdata containing image information.
However, the electric potential V1 is given to each of the wiring ILs. Since the node B is in a floating state, the capacitance element 13 is changed by changing the node C from the potential V2 to the potential V1.
As a result, the node B changes from the potential V0 to the potential V0 + V1-V2. Then, the capacitance element 13
Since the potential difference V0-V2 is held in the transistor 11, the threshold voltage Vth of the transistor 11 is maintained at 0. Further, the potential Vdata is given to the node A, and the gate voltage of the transistor 11 becomes Vdata-V1.

Then, in the period t4, the wiring GLa is given a low-level potential, the wiring GLb is given a low-level potential, the wiring GLc is given a high-level potential, and the wiring GLd is given a low-level potential. Therefore, as shown in FIG. 7B, the transistor 19t is turned on, and the transistor 12t, the transistor 15t, the transistor 16t, and the transistor 17t are turned off.

Further, a potential Vano is given to the wiring VL, and a potential Vcat is given to the wiring CL electrically connected to the common electrode of the light emitting element 14. In the period t4, the transistor 19t
When is turned on, the potential of node C fluctuates, and when the potential becomes V3, node A has potential Vd.
Ata + V3-V1 and node B have potentials V0-V2 + V3. Even if the potentials of the nodes A, B, and C change, the capacitance element 13 retains the potential difference V0-V2.
The capacitance element 18 holds a potential difference Vdata-V1. And wiring VL and wiring C
A drain current having a value corresponding to the gate voltage of the transistor 11 flows between L. The brightness of the light emitting element 14 is determined according to the value of the drain current.

In the light emitting device having the pixel 10 shown in FIG. 3B, the other of the source and drain of the transistor 11 and the second gate of the transistor 11 are electrically separated from each other.
Each potential can be controlled individually. Therefore, when the transistor 11 is normalized, that is, when the original threshold voltage Vth0 of the transistor 11 has a negative value, the potential of one of the source and the drain of the transistor 11 is second in the period t2. Charges can be stored in the capacitive element 13 until it is higher than the gate potential V0. Therefore, in the light emitting device according to one aspect of the present invention, even if the transistor 11 is a normalion, its threshold voltage Vth is set to 0 so that the drain current converges to 0 with respect to the gate voltage 0 in the period t2. It can be corrected.

Therefore, the other of the source and drain of the transistor 11 and the second of the transistor 11
Pixel 1 shown in FIGS. 3 (A), 3 (B), and 4 (B), which is electrically separated from the gate of
In the light emitting device having 0, for example, when an oxide semiconductor is used for the semiconductor film of the transistor 11, even if the transistor 11 becomes a normalion, display unevenness can be reduced and high image quality can be displayed.

Although FIGS. 2 (A) and 2 (B) are shown as examples of the circuit configuration, one aspect of the present invention is not limited thereto. For example, the switch can be placed in various places. For example, in the case of FIG. 6 (A), the configuration is as shown in FIG. 36 (A), and in the case of FIG. 6 (B), the configuration is as shown in FIG. 36 (B). In the case of FIG. 7 (A), the configuration may be as shown in FIG. 37 (A), and in the case of FIG. 7 (B), the configuration may be as shown in FIG. In each case, the switch may be placed in an appropriate place so as to have such a configuration.

The above is the pixel 1 including the correction of the threshold voltage in the pixel 10 (hereinafter, referred to as an internal correction).
Corresponds to the operation example of 0. Next, in addition to the internal correction, the operation of the pixel 10 when the variation in the brightness between the pixels 10 due to the variation in the threshold voltage is suppressed by the correction of the image signal (hereinafter referred to as the external correction) will be described.

Taking the pixel 10 shown in FIG. 3B as an example, the timing chart of the potential input to the wiring GLa to the wiring GLd and the image signal input to the wiring SL when the external correction is performed in addition to the internal correction. A timing chart of the potential of Vdata is shown in FIG. The timing chart shown in FIG. 8 illustrates a case where all the transistors included in the pixel 10 shown in FIG. 3 (B) are of the n-channel type.

First, from the period t1 to the period t4, the pixel 10 operates according to the above description in the same manner as the timing chart shown in FIG.

Then, in the period t5, the wiring GLa is given a low-level potential, the wiring GLb is given a low-level potential, the wiring GLc is given a low-level potential, and the wiring GLd is given a high-level potential. Therefore, the transistor 17t is turned on, and the transistor 12
t, the transistor 15t, the transistor 16t, and the transistor 19t are turned off.

Further, a potential Vano is given to the wiring VL, and a potential V1 is given to the wiring IL.
Further, the wiring IL is electrically connected to the monitor circuit.

By the above operation, the drain current of the transistor 11 is reduced to the transistor 17t and the wiring IL.
It is supplied to the monitor circuit via. The monitor circuit uses the drain current flowing through the wiring IL to generate a signal including the value of the drain current as information. Then, in the light emitting device according to one aspect of the present invention, the potential V of the image signal supplied to the pixel 10 is used by using the above signal.
The value of data can be corrected.

The operation of the external correction performed in the period t5 does not always have to be performed after the period t4. For example, in the light emitting device, the operation of the period t1 to the period t4 may be repeated a plurality of times, and then the operation of the period t5 may be performed. Further, after performing the operation for the period t5 on the pixel 10 in one line, the image signal corresponding to the minimum gradation value 0 is written to the pixel 10 in the line on which the operation is performed, so that the light emitting element 14 is not emitted. After the state is set, the operation for the period t5 may be performed in the pixel 10 in the next row.

Even when the external correction is performed without performing the internal correction, not only the variation of the threshold voltage of the transistor 11 existing between the pixels 10 but also the variation of the electrical characteristics of the transistor 11 other than the threshold voltage such as mobility. It can be corrected. However, when the internal correction is performed in addition to the external correction, the negative shift or positive shift correction of the threshold voltage is performed by the internal correction. Therefore, in the external correction, variations in electrical characteristics other than the threshold voltage in the transistor 11 such as mobility may be corrected. Therefore, when the internal correction is performed in addition to the external correction, the amplitude of the potential of the image signal after the correction is increased as compared with the case where only the external correction is performed.
It can be kept small. Therefore, since the amplitude of the potential of the image signal is too large, the potential difference of the image signal between the gradation values becomes large, and it becomes difficult to express the change in brightness in the image with a smooth gradation. It is possible to prevent the image quality from being deteriorated.

In the case of the pixel 10 shown in FIG. 3 (A), the wiring GLa and the wiring GL shown in FIG. 5 or 8 are also used.
It can be operated in the same manner according to the timing chart of the potential given to b, the wiring GLd, and the wiring SL. However, in the case of the pixel 10 shown in FIG. 3A, the potential V0 is set to the threshold voltage Vthe of the light emitting element 14 and the threshold of the transistor 15t so that the drain current of the transistor 11 does not flow to the light emitting element 14 during the period t2. Voltage Vth, potential Vca
It is desirable that the potential is lower than the potential added to t.

Further, also in the case of the pixel 10 shown in FIG. 4 (A), the wiring GLa and the wiring GL shown in FIG. 5 or 8
b, the wiring GLc, the wiring GLd, and the potential timing chart given to the wiring SL can be operated in the same manner.

Further, also in the case of the pixel 10 shown in FIG. 4 (B), the wiring GLa and the wiring GL shown in FIG. 5 or 8
It can be operated in the same manner according to the timing chart of the potential given to b, the wiring GLc, and the wiring SL.

In addition, for example, when the external correction is not performed, the wiring IL may be connected to the wiring CL. Alternatively, the wiring IL may be omitted by combining the wiring IL and the wiring CL into one. As a result, the number of wires can be reduced. As an example, FIG. 38 (A) shows an example in which the wiring IL is omitted in FIG. 2 (A). Similarly, an example when applied to FIG. 2 (B) is shown in FIG. 38 (B). It can be applied in the same manner in other drawings.

<Configuration example of pixel section and selection circuit>
Next, FIG. 10 shows, as an example, the configuration of the pixel portion of the light emitting device according to one aspect of the present invention.
In FIG. 10, the pixel unit 40 has a plurality of pixels 10 arranged in a matrix. Further, the pixel unit 40 includes wiring GL, wiring SL, wiring VL, wiring BL, wiring IL, and wiring CL.
Have at least (not shown). Each of the plurality of pixels 10 is electrically connected to at least one of the wiring GL, at least one of the wiring SL, at least one of the wiring VL, at least one of the wiring BL, at least one of the wiring IL, and the wiring CL, respectively. It is connected to the.

The type and number of the wirings can be determined by the configuration, number and arrangement of the pixels 10. Specifically, in the case of the pixel unit 40 shown in FIG. 10, the pixels 10 in the x-column × y-row are electrically connected in a matrix. Then, a plurality of wiring GLs represented by wiring GL1 to wiring GLy
, A plurality of wiring SLs indicated by wiring SL1 to SLx, a plurality of wiring VLs indicated by wiring VL1 to VLx, a plurality of wiring BLs indicated by wiring BL1 to BLx, and a plurality of wirings IL1 to ILx. The case where the wiring IL and one wiring CL are arranged in the pixel portion 40 is illustrated.

Then, each wiring GL shown in FIG. 10 includes all or a plurality of wiring GLa, wiring GLb, wiring GLc, or wiring GLd.

As shown in FIG. 10, when the pixels 10 are connected in a matrix, operations such as FIGS. 6 (A), 6 (B), and 7 (B) are performed in a certain line. If so, the operation of FIG. 7A can be performed, for example, in another line. Therefore, FIG. 6 (A)
And the operations shown in FIG. 6B can be performed for a sufficiently long period of time. Therefore, it can be corrected with high accuracy.

If the operations shown in FIGS. 6 (A) and 6 (B) and the operations shown in FIG. 7 (A) are not performed at the same time on different lines, for example, the wiring BL is connected to the wiring SL. You may. Alternatively, for example, the wiring BL may be omitted by combining the wiring BL and the wiring SL into one. As a result, the number of wires can be reduced. As an example, FIG. 39 (A) shows an example in which the wiring BL is omitted in FIG. 2 (A). Similarly, an example when applied to FIG. 2 (B) is shown.
It is shown in FIG. 39 (B). It can be applied in the same manner in other drawings.

Further, in FIG. 7A and the like, during the period in which the potential Vdata of the image signal is input, the operation of applying the potential difference V0-V2 between the node B and the node C to the capacitance element 13 as shown in FIG. 6B is performed. Therefore, in FIG. 7A and the like, the potential Vdata of the image signal can be input to the pixels in point order. An example in that case is shown in FIG. The switch 60A, the switch 60B, the switch 60C, and the like are turned on in order while being controlled by the circuit 61. As a result, point-sequential driving can be performed. Here, the circuit 61 has a function of being able to output waveforms shifted one by one. For example, the circuit 61 has a function as a shift register. Therefore, switch 60A, switch 60B, switch 6
It can also be said that 0C and the circuit 61 have a function as a source line drive circuit.

Alternatively, as another example, in a plurality of wiring SLs represented by wiring SL1 to wiring SLx, one of the wirings is selected in the plurality of wirings, and the potential Vdata of the image signal is input. You may. For example, wiring SL1 and wiring SL2 are selected by switch 62A and switch 62B, and wiring SL3 and wiring SL4 are selected by switch 62C and switch 6.
An example of the case of selecting in 2D is shown in FIG. In FIG. 41, when the wiring 63A is selected, the switch 62A and the switch 62C are turned on, and when the wiring 63B is selected, the switch 62B and the switch 62D are turned on. Here, an example in which one of the two wiring SLs is selected is shown, but one aspect of the present invention is not limited to this. One may be selected from a larger number of wiring SLs.

Next, FIG. 11 shows an example of the connection configuration of the pixel unit 40 and the selection circuit 41 of the light emitting device having the function of performing external correction. The selection circuit 41 has a function of selecting either the wiring 42 to which the potential V1 is given and the connection terminal TER with the monitor circuit. A conductive state can be established between either one of the selected wiring 42 and the connection terminal TER and the wiring IL.

Specifically, the selection circuit 41 shown in FIG. 11 determines the conduction state between the switch 43 that controls the supply of the potential V1 of the wiring 42 to the one wiring IL, the one wiring IL, and the connection terminal TER. It has a switch 44 to control.

<Example of monitor circuit configuration>
Next, a configuration example of the monitor circuit 45 is shown in FIG. The monitor circuit 45 shown in FIG. 12 is
It has an operational amplifier 46, a capacitive element 47, and a switch 48.

One of the pair of electrodes of the capacitive element 47 is connected to the inverting input terminal (−) of the operational amplifier 46, and the other of the pair of electrodes of the capacitive element 47 is connected to the output terminal of the operational amplifier 46. The switch 48 has a function of discharging the electric charge accumulated in the capacitance element 47, and specifically, has a function of controlling an electrical conduction state between a pair of electrodes of the capacitance element 47. The non-inverting input terminal (+) of the operational amplifier 46 is connected to the wiring 49, and the potential V1 is supplied to the wiring 49.

In one aspect of the present invention, the monitor circuit 45 functions as a voltage follower when the potential V1 is supplied to the wiring IL of the pixel 10 in order to perform internal correction. Specifically, by turning on the switch 48, the potential V1 supplied to the wiring 49 can be supplied to the wiring IL via the monitor circuit 45.

Further, when extracting a current from the pixel 10 via the wiring IL in order to perform external correction, first, the monitor circuit 45 is made to function as a voltage follower, so that the wiring IL has a potential V.
After supplying 1, the monitor circuit 45 functions as an integrator circuit to convert the current extracted from the pixel 10 into a voltage. Specifically, by turning on the switch 48, the wiring 4
The potential V1 supplied to 9 is supplied to the wiring IL via the monitor circuit 45, and then the switch 48 is turned off. When the drain current taken out from the pixel 10 is supplied to the wiring TER while the switch 48 is off, an electric charge is accumulated in the capacitance element 47 and a voltage is generated between the pair of electrodes of the capacitance element 47. Since the voltage is proportional to the total amount of drain current supplied to the wiring TER, the wiring OUT connected to the output terminal of the operational amplifier 46 is provided with a potential corresponding to the total amount of drain current within a predetermined period. ..

<Specific configuration example 2 of pixels>
FIG. 13A shows a specific configuration of the pixel 10 shown in FIG. 1 as an example.

The pixel 10 shown in FIG. 13A has a switch 15 to a switch 17 and a capacitance element 18 in addition to the transistor 11, the capacitance element 13, and the light emitting element 14.

Specifically, in the pixel 10 shown in FIG. 13A, the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. In the transistor 11, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element 14, and the other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light emitting element 14 is electrically connected to the wiring IL via the switch 17. One of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, FIG. 13B shows another specific configuration of the pixel 10 shown in FIG. 1 as an example.

The pixel 10 shown in FIG. 13 (B) further has a switch 19 in FIG. 13 (A).
The configuration is different from the pixel 10 shown in.

Specifically, in the pixel 10 shown in FIG. 13B, the wiring SL is electrically connected to the first gate of the transistor 11 via the switch 15. In the transistor 11, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element 14 via the switch 19, and the other of the source and the drain is electrically connected to the wiring VL. The second gate of the transistor 11 is electrically connected to the wiring BL via the switch 16. The pixel electrode of the light emitting element 14 is electrically connected to the wiring IL via the switch 17 and the switch 19. One of the pair of electrodes of the capacitive element 13 is the second electrode of the transistor 11.
The other is electrically connected to the pixel electrode of the light emitting element 14 via the switch 19. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is a light emitting element 1 via a switch 19.
It is electrically connected to the pixel electrode of 4. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, in the pixel 10 shown in FIG. 13 (A), a configuration example of the pixel when a transistor is used for each switch will be described. 14 (A) shows a configuration example of the pixel 10 in the case where a transistor is used as the switch 15 to the switch 17 of the pixel 10 shown in FIG. 13 (A).
Shown in A).

The pixels 10 shown in FIG. 14A are a transistor 11, a transistor 15t to a transistor 17t having a function as a switch 15 to a switch 17, respectively, and a capacitive element 1.
3. It has a capacitance element 18 and a light emitting element 14.

Specifically, in the transistor 15t, the gate is electrically connected to the wiring GLa, one of the source and drain is electrically connected to the wiring SL, and the other of the source and drain is electrically connected to the first gate of the transistor 11. In the transistor 11, one of the source and the drain is a light emitting element 1.
The other of the source and drain is electrically connected to the pixel electrode of No. 4 and to the wiring VL, respectively. In the transistor 16t, the gate is electrically connected to the wiring GLb, one of the source and drain is electrically connected to the wiring BL, and the other of the source and drain is electrically connected to the second gate of the transistor 11. In the transistor 17t, the gate is electrically connected to the wiring GLd, one of the source and drain is electrically connected to the wiring IL, and the other of the source and drain is electrically connected to the pixel electrode of the light emitting element 14.

Further, one of the pair of electrodes of the capacitance element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. One of the pair of electrodes of the capacitive element 18 is electrically connected to the first gate of the transistor 11, and the other is electrically connected to the pixel electrode of the light emitting element 14. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, in the pixel 10 shown in FIG. 13B, a configuration example of the pixel when a transistor is used for each switch will be described. Pixel 10 of the pixel 10 shown in FIG. 13 (B) when a transistor is used as the switch 15 to the switch 17 and the switch 19 respectively.
A configuration example of is shown in FIG. 14 (B).

The pixels 10 shown in FIG. 14B are a transistor 11, a transistor 15t to a transistor 17t having a function as a switch 15 to a switch 17, respectively, and a switch 1.
It has a transistor 19t having a function as 9, a capacitance element 13, a capacitance element 18, and a light emitting element 14.

Specifically, in the transistor 15t, the gate is electrically connected to the wiring GLa, one of the source and drain is electrically connected to the wiring SL, and the other of the source and drain is electrically connected to the first gate of the transistor 11. In the transistor 11, one of the source and the drain is electrically connected to one of the source and the drain of the transistor 19t, and the other of the source and the drain is electrically connected to the wiring VL. In the transistor 16t, the gate is electrically connected to the wiring GLb, one of the source and drain is electrically connected to the wiring BL, and the other of the source and drain is electrically connected to the second gate of the transistor 11. The gate of the transistor 17t is GL.
One of the source and the drain is electrically connected to the wiring IL, and the other of the source and the drain is electrically connected to one of the source and the drain of the transistor 19t. In the transistor 19t, the gate is electrically connected to the wiring GLc, and the other of the source and drain is electrically connected to the pixel electrode of the light emitting element 14.

Further, one of the pair of electrodes of the capacitive element 13 is electrically connected to the second gate of the transistor 11, and the other is electrically connected to one of the source and drain of the transistor 19t. One of the pair of electrodes of the capacitive element 18 is the first transistor 11.
It is electrically connected to the gate of the transistor, and the other is electrically connected to one of the source and drain of the transistor 19t. The common electrode of the light emitting element 14 is electrically connected to the wiring CL.

Next, another configuration example of the pixel 10 shown in FIG. 13 (B) when a transistor is used as the switch 15 to the switch 17 is shown in FIG. 15 (A).

The pixel 10 shown in FIG. 15 (A) is configured with the pixel 10 shown in FIG. 14 (B) in that one of the source and drain of the transistor 16t is electrically connected to the wiring VL instead of the wiring BL. Is different.

Next, switches 15 to 17 and switch 1 of the pixel 10 shown in FIG. 13 (B).
FIG. 15B shows another configuration example of the pixel 10 when a transistor is used as the 9th.
Shown in.

In the pixel 10 shown in FIG. 15B, the gate of the transistor 17t is not the wiring GLd, but
The configuration is different from that of the pixel 10 shown in FIG. 14B in that it is electrically connected to the wiring GLa.

<Specific operation example 2 of pixels>
Next, the operation of the pixels of the light emitting device according to one aspect of the present invention will be described by taking the pixel 10 shown in FIG. 14B as an example.

FIG. 16 shows a timing chart of the potential input to the wiring GLa to the wiring GLd and the wiring S.
The timing chart of the potential of the image signal Vdata input to L is shown. In addition, FIG.
The timing chart shown in 6 illustrates a case where all the transistors included in the pixel 10 shown in FIG. 14B are of the n-channel type.

First, in the period t1, the wiring GLa is given a high-level potential, the wiring GLb is given a high-level potential, the wiring GLc is given a low-level potential, and the wiring GLd is given a high-level potential. Therefore, the transistor 15t, the transistor 16t, and the transistor 17t are turned on, and the transistor 19t is turned off.

Further, the potential V4 is connected to the wiring SL, the potential Vano is connected to the wiring VL, the potential V0 is connected to the wiring BL, and the potential V1 is connected to the wiring IL to the wiring CL electrically connected to the common electrode of the light emitting element 14. Is given the potential Vcat, respectively. Therefore, the first gate of the transistor 11 (
The potential V4 is given to the node A (denoted as node A), and the second gate (node B) of the transistor 11 is given.
(Shown) is given a potential V0, and one of the source and drain of the transistor 11 (denoted as node C) is given a potential V1.

The potential Vano is the potential Vcat, the threshold voltage Vthe of the light emitting element 14, and the transistor 11.
It is desirable that the potential is higher than the potential obtained by adding the threshold voltage Vth of. And the potential V0
Node C to the extent that the threshold voltage Vth of the transistor 11 is shifted in the negative direction.
It is desirable that the potential is sufficiently high. Specifically, as shown in FIG. 9, the voltage Vb
Assuming that the threshold voltage Vth of the transistor 11 when g is 0 is Vth0, in the period t1, the voltage Vbg corresponding to the potential difference between the node B and the node C is set to Vbg1, thereby setting the threshold voltage Vth of the transistor 11 Let it be Vth1. Since the transistor 11 is normalized by the above configuration, the transistor 11 can be turned on even if the potential difference between the node A and the node C, that is, the gate voltage of the transistor 11 is V4-V1.

When the transistor 11 is a p-channel type, it is desirable that the potential V0 is sufficiently low with respect to the node C so as to shift the threshold voltage Vth of the transistor 11 in the positive direction. Since the transistor 11 is normalized by the above configuration, the transistor 11 can be turned on even if the potential difference between the node A and the node C, that is, the gate voltage of the transistor 11 is V4-V1.

Then, in the period t2, the wiring GLa is given a low-level potential, the wiring GLb is given a high-level potential, the wiring GLc is given a low-level potential, and the wiring GLd is given a low-level potential. Therefore, the transistor 16t is turned on, and the transistor 15
t, the transistor 17t, and the transistor 19t are turned off.

Further, a potential Vano is given to the wiring VL, and a potential V0 is given to the wiring BL. Therefore, the state in which the potential V0 is given to the node B is maintained, and the threshold voltage Vth of the transistor 11 remains shifted to Vth1 in the negative direction at the start of the period t2, so that the transistor 11 is on. Then, in the period t2, the current path between the wiring VL and the wiring IL is cut off by the switch 17, so that the potentials of the nodes A and C start to rise due to the drain current of the transistor 11. When the potential of node C rises, node B
And the voltage Vbg corresponding to the potential difference of the node C becomes low, and the threshold voltage Vt of the transistor 11
h shifts in the positive direction. Finally, the threshold voltage Vt of the transistor 11
When h approaches the gate voltage V4-V1 of the transistor 11 as close as possible, the transistor 11 is turned off. When the threshold voltage Vth of the transistor 11 is V4-V1, the potential difference between the node B and the node C is V0-V2.

That is, when the potential difference between the node B and the node C is V0-V2, the transistor 11 has a threshold voltage Vt so that the drain current converges to 0 with respect to the gate voltage V4-V1.
h will be corrected to V4-V1. The potential difference V0-V2 between the node B and the node C is applied to the capacitive element 13.

Then, in the period t3, the wiring GLa is given a high level potential, the wiring GLb is given a low level potential, the wiring GLc is given a low level potential, and the wiring GLd is given a high level potential. Therefore, the transistor 15t and the transistor 17t are turned on, and the transistor 16t and the transistor 19t are turned off.

Further, the wiring VL contains the potential Vano, and the wiring SL contains the potential Vdata containing image information.
However, the electric potential V1 is given to each of the wiring ILs. Since the node B is in a floating state, the capacitance element 13 is changed by changing the node C from the potential V2 to the potential V1.
As a result, the node B changes from the potential V0 to the potential V0 + V1-V2. Then, the capacitance element 13
Since the potential difference V0-V2 is held in the transistor 11, the threshold voltage Vth of the transistor 11 is V4.
It is maintained at -V1. Further, the potential Vdata is given to the node A, and the transistor 1
The gate voltage of 1 is Vdata-V1.

Then, in the period t4, the wiring GLa is given a low-level potential, the wiring GLb is given a low-level potential, the wiring GLc is given a high-level potential, and the wiring GLd is given a low-level potential. Therefore, the transistor 19t is turned on, and the transistor 15
t, the transistor 16t, and the transistor 17t are turned off.

Further, a potential Vano is given to the wiring VL, and a potential Vcat is given to the wiring CL electrically connected to the common electrode of the light emitting element 14. In the period t4, the transistor 19t
When is turned on, the potential of node C fluctuates, and when the potential becomes V3, node A has potential Vd.
Ata + V3-V1 and node B have potentials V0-V2 + V3. Even if the potentials of the nodes A, B, and C change, the capacitance element 13 retains the potential difference V0-V2.
The capacitance element 18 holds a potential difference Vdata-V1. And wiring VL and wiring C
A drain current having a value corresponding to the gate voltage of the transistor 11 flows between L. The brightness of the light emitting element 14 is determined according to the value of the drain current.

In the light emitting device having the pixel 10 shown in FIG. 14B, the other of the source and drain of the transistor 11 and the second gate of the transistor 11 are electrically separated, so that the respective potentials are set. It can be controlled individually. Therefore, when the transistor 11 is normalized, that is, when the original threshold voltage Vth0 of the transistor 11 has a negative value, the potential of one of the source and the drain of the transistor 11 is second in the period t2. Charges can be stored in the capacitive element 13 until it is higher than the gate potential V0. Therefore, in the light emitting device according to one aspect of the present invention, even if the transistor 11 is a normalion, the threshold voltage Vth is set so that the drain current converges to 0 with respect to the gate voltage V4-V1 in the period t2. It can be corrected to V4-V1.

Therefore, the other of the source and drain of the transistor 11 and the second of the transistor 11
In the light emitting device having the pixel 10 shown in FIGS. 14 (A), 14 (B), and 15 (B), which is electrically separated from the gate of the transistor 11, for example, an oxide semiconductor is formed on the semiconductor film of the transistor 11. Even if the transistor 11 becomes a normalion when it is used, display unevenness can be reduced and high image quality can be displayed.

The above corresponds to an operation example of the pixel 10 including the internal correction. Then, in addition to the internal correction,
The operation of the pixel 10 when the variation in the brightness between the pixels 10 due to the variation in the threshold voltage is suppressed by an external correction will be described.

Taking the pixel 10 shown in FIG. 14B as an example, when the external correction is performed in addition to the internal correction, the pixels 10 are described in the same manner as in the timing chart shown in FIG. 16 from the period t1 to the period t4. Works.

Then, in the period t5 after the period t4, a low level potential is applied to the wiring GLa, and the wiring G
A low level potential is given to Lb, a low level potential is given to the wiring GLc, and the wiring G
A high level potential is given to Ld. Therefore, the transistor 17t is turned on, and the transistor 15t, the transistor 16t, and the transistor 19t are turned off.

Further, a potential Vano is given to the wiring VL, and a potential V1 is given to the wiring IL.
Further, the wiring IL is electrically connected to the monitor circuit.

By the above operation, the drain current of the transistor 11 is reduced to the transistor 17t and the wiring IL.
It is supplied to the monitor circuit via. The monitor circuit uses the drain current flowing through the wiring IL to generate a signal including the value of the drain current as information. Then, in the light emitting device according to one aspect of the present invention, the potential V of the image signal supplied to the pixel 10 is used by using the above signal.
The value of data can be corrected.

The operation of the external correction performed in the period t5 does not always have to be performed after the period t4. For example, in the light emitting device, the operation of the period t1 to the period t4 may be repeated a plurality of times, and then the operation of the period t5 may be performed. Further, after performing the operation for the period t5 on the pixel 10 in one line, the image signal corresponding to the minimum gradation value 0 is written to the pixel 10 in the line on which the operation is performed, so that the light emitting element 14 is not emitted. After the state is set, the operation for the period t5 may be performed in the pixel 10 in the next row.

In the case of the pixel 10 shown in FIG. 14A, the same operation can be performed according to the timing chart of the potentials given to the wiring GLa, the wiring GLb, the wiring GLd, and the wiring SL shown in FIG. Further, the operation of the external correction can be performed in the same manner as the pixels shown in FIG. 14 (B). However, in the case of the pixel 10 shown in FIG. 14A, the potential V0 is set to the threshold voltage Vthe of the light emitting element 14 and the threshold of the transistor 15t so that the drain current of the transistor 11 does not flow to the light emitting element 14 during the period t2. It is desirable that the voltage Vth be lower than the potential added to the potential Vcat.

Further, also in the case of the pixel 10 shown in FIG. 15 (A), according to the timing chart of the potentials given to the wiring GLa, the wiring GLb, the wiring GLc, the wiring GLd, and the wiring SL shown in FIG.
It can be operated in the same way. Further, the operation of the external correction can be performed in the same manner as the pixels shown in FIG. 14 (B).

Further, in the case of the pixel 10 shown in FIG. 15B, the same operation can be performed according to the timing chart of the potentials given to the wiring GLa, the wiring GLb, the wiring GLc, and the wiring SL shown in FIG. Further, the operation of the external correction can be performed in the same manner as the pixels shown in FIG. 14 (B).

<Transistor configuration example 1>
Next, a transistor (OS transistor) in which the channel formation region is formed of an oxide semiconductor film will be described.

27 (A), 27 (B), and 27 (C) show a top view (layout view) of three transistors (TA1, TA2, TB1) having different device structures, and their respective circuit symbols. FIG. 28 is a cross-sectional view of the transistors (TA1, TA2, TB1). Cross-sectional view of transistor TA1 by lines a1-a2 and b1-b2, a3- of transistor TA2
Sectional view taken along line a4 and line b3-b4, and line a5-a6 of transistor TB1.
Cross-sectional views taken along line b5-b6 are shown in FIGS. 28 (A) and 28 (B). The cross-sectional structure of these transistors in the channel length direction is shown in FIG. 28 (A), and the cross-sectional structure in the channel width direction of these transistors is shown in FIG. 28 (B).

As shown in FIGS. 28 (A) and 28 (B), the transistors (TA1, TA2, TB1) are integrated on the same insulating surface, and these transistors can be manufactured in the same manufacturing process. It is possible. Here, in order to clarify the device structure, the electrical connection to the gate (G), source (S), and drain (D) of each transistor and the wiring for supplying power is omitted. doing.

Transistor TA1 (FIG. 27 (A)) and transistor TA2 (FIG. 27 (B)) are transistors having a gate (G) and a back gate (BG). One of the gate (G) and the back gate (BG) corresponds to the first gate, and the other corresponds to the second gate. The transistor TA1 and the transistor TA2 have a structure in which a back gate is connected to the gate. Transistor TB1 (FIG. 27 (C)) is a transistor having no BG.
As shown in FIG. 28, these transistors (TA1, TA2, TB1) are formed on the substrate 30. Hereinafter, the configurations of these transistors will be described with reference to FIGS. 27 and 28.

(Transistor TA1)
The transistor TA1 has a gate electrode GE1, a source electrode SE1, a drain electrode DE1, a back gate electrode BGE1, and an oxide semiconductor film OS1.

In the following description, the transistor TA1 is referred to as TA1, and the back gate is referred to as BG.
The oxide semiconductor film OS1 may be referred to as an OS1 or a film OS1, and the element or a component of the element may be omitted. Further, signals, potentials, circuits and the like may be omitted in the same manner.

Further, in the present embodiment, the channel length of the OS transistor is the distance between the source electrode and the drain electrode. The channel width of the OS transistor is the width of the source electrode or the drain electrode in the region where the oxide semiconductor film and the gate electrode overlap. The channel length of the transistor TA1 is La1 and the channel width is Wa1.

The film OS1 overlaps with the electrode GE1 via the insulating film 34. A pair of electrodes (SE1, DE1) are formed in contact with the upper surface and the side surface of the film OS1. As shown in FIG. 27 (A)
The film OS1 has a portion that does not overlap with the electrode GE1 and the pair of electrodes (SE1, DE1). The film OS1 has a length in the channel length direction longer than the channel length La1 and a length in the channel width direction longer than the channel width Wa1.

An insulating film 35 is formed so as to cover the film OS1, the electrode GE1, the electrode SE1, and the electrode DE1. The electrode BGE1 is formed on the insulating film 35. The electrode BGE1 is provided so as to overlap the membrane OS1 and the electrode GE1. Here, as an example, the electrode BGE1 is provided so as to have the same shape as the electrode GE1 and to be arranged at the same position. The electrode BGE1 is in contact with the electrode GE1 at the opening CG1 penetrating the insulating film 34 insulating film 35 and the insulating film 36. With this structure, the gate and the back gate of the transistor TA1 are electrically connected.

By connecting the back gate electrode BGE1 to the gate electrode GE1, the on-current of the transistor TA1 can be increased. By providing the back gate BGE1, the strength of the transistor TA1 can be improved. Electrode BG against deformation such as bending of the substrate 30
E1 serves as a reinforcing member, and the transistor TA1 can be made hard to break.

The film OS1 including the channel forming region has a multi-layer structure, and here, as an example, it has a three-layer structure composed of three oxide semiconductor films (31, 32, 33). The oxide semiconductor film constituting the film OS1 is preferably a metal oxide film containing at least one metal element, and is preferably In.
Is particularly preferable. Examples of the In-containing metal oxide capable of forming the semiconductor film of the transistor include an In-Ga oxide film and an In-M-Zn oxide film (M is Al, Ga,
Y, Zr, La, Ce, or Nd) is typical. Further, a film obtained by adding other elements or materials to such a metal oxide film can also be used.

“32” is a film forming a channel forming region of the transistor TA1. Also, "33
Is also a film forming a channel forming region of the transistor TA2 and the transistor TB1 described later. Therefore, an oxide semiconductor film having an appropriate composition may be used according to the electrical characteristics required for the transistor TA2 and the transistor TB1 (for example, field effect mobility, threshold voltage, etc.). For example, it is preferable to adjust the composition of the metal element which is the main component of the oxide semiconductor film 31-32 so that the channel is formed in "33".

By forming a channel at "32" in the transistor TA1, the channel forming region can be prevented from contacting the insulating films 34 and 35. Further, by making the oxide semiconductor film 31-32 a metal oxide film containing at least one metal element, "32"
At the interface between "31" and "32" and "33", interfacial scattering can be prevented from occurring. As a result, the electric field effect mobility of the transistor TA1 can be made higher than that of the transistor TA2 and the transistor TB1, and the drain current (on current) in the on state can be increased.

(Transistor TA2)
The transistor TA2 has a gate electrode GE2, a source electrode SE2, a drain electrode DE2, a back gate electrode BGE2, and an oxide semiconductor film OS2. The electrode BGE2 is in contact with the electrode GE2 at an opening CG2 penetrating the insulating film 34 to the insulating film 36. The transistor TA2 is a modification of the transistor TA1 and is different from the transistor TA1 in that the film OS2 has a single-layer structure composed of an oxide semiconductor film 33, and is the same as the others. Here, the channel length La2 and the channel width Wa2 of the transistor TA2 are the transistor TA.
The channel length La1 and the channel width Wa1 of 1 are equal to each other.

(Transistor TB1)
The transistor TB1 has a gate electrode GE3, a source electrode SE3, a drain electrode DE3, and an oxide semiconductor film OS3. The transistor TB1 is a modification of the transistor TA2. Similar to the transistor TA2, the film OS3 has a single-layer structure composed of an oxide semiconductor film 33. It differs from the transistor TA2 in that it does not have a back gate electrode. In addition, the layout of the membrane OS3 and the electrodes (GE3, SE3, DE3) is different. As shown in FIG. 27 (C), in the region where the film OS3 does not overlap with the electrode GE3, the electrode SE3 or the electrode DE
It overlaps with any of 3. Therefore, the channel width Wb1 of the transistor TB1 is the film O.
It is determined by the width of S3. The channel length Lb1 has the same electrode SE as the transistor TA2.
It is determined by the distance between 3 and the electrode DE3, and here, the channel length La2 of the transistor TA2 is determined.
Is longer than.

[Insulating film]
The insulating film 34, the insulating film 35, and the insulating film 36 are the transistors (TA1, TA2) of the substrate 30.
, TB1) is a film formed over the entire region where it is formed. The insulating film 34, the insulating film 35, and the insulating film 36 are formed of a single-layer or a plurality of layers of the insulating film. The insulating film 34 is a film that constitutes the gate insulating film of the transistors (TA1, TA2, TB1). The insulating film 35 and the insulating film 36 are films that form a gate insulating film on the back channel side of the transistors (TA1, TA2, TB1). Further, the insulating film 36 on the uppermost surface is preferably formed of a material that functions as a protective film for the transistor formed on the substrate 30. The insulating film 36 may be provided as appropriate. In order to insulate the third layer electrode BGE1 and the second layer electrode (SE1, DE1), at least one layer insulating film may be present between them.

The insulating film 34 to 36 can be formed of a single-layer insulating film or a multi-layer insulating film having two or more layers. Examples of the insulating film constituting the insulating film 34 to 36 include aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, and the like.
Examples thereof include films made of lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide and the like. Further, these insulating films can be formed by using a sputtering method, a CVD method, an MBE method, an ALD method or a PLD method.

[Oxide semiconductor film]
Here, the oxide semiconductor film constituting the semiconductor film of the OS transistor will be described. When the semiconductor film has a multilayer structure as in the film OS1, the oxide semiconductor film constituting these is preferably a metal oxide film containing at least one of the same metal elements, and preferably contains In.

For example, when "31" is an In-Ga oxide film, the atomic number ratio of In is made smaller than the atomic number ratio of Ga. In the case of an In—M—Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), the atomic number ratio of In is made smaller than the atomic number ratio of M. In this case, the atomic number ratio of Zn can be maximized.

For example, when "32" is an In-Ga oxide film, the atomic number ratio of In is made larger than the atomic number ratio of Ga. In the case of an In—M—Zn oxide film, the atomic number ratio of In is made larger than the atomic number ratio of M. In the In—M—Zn oxide film, it is preferable that the atomic number ratio of In is larger than the atomic number ratio of M and Zn.

For example, when "33" is an In-Ga oxide film, the atomic number ratio of In is made the same as or smaller than the atomic number ratio of Ga. In the case of an In—M—Zn oxide film, the atomic number ratio of In is the same as the atomic number ratio of M. In this case, the atomic number ratio of Zn can be made larger than that of In and M. Here, "33" is also a film forming a channel forming region of the transistor TA2 and the transistor TB1 described later.

The atomic number ratio of the oxide semiconductor film 31 to the oxide semiconductor film 33 can be adjusted by adjusting the atomic number ratio of the constituent material of the target when the film is formed by the sputtering method. Also, CVD
When forming a film by the method, it is possible by adjusting the flow rate ratio of the raw material gas. Hereinafter, the target used for film formation will be described by taking as an example a case where an In-M—Zn oxide film is formed as the oxide semiconductor film 31 to the oxide semiconductor film 33 by a sputtering method. In order to form these films, a target made of In-M-Zn oxide is used.

Assuming that the atomic number ratio of the target metal element of "31" is In: M: Zn = x1: y1: z1 _, x1 / y1 is preferably 1/6 or more and less than 1. Further, z1 / y1 is 1 /.
It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less.

Typical examples of the atomic number ratio of the target metal element are In: M: Zn = 1: 3: 2, In.
: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, In: M: Zn = 1: 3: 8,
In: M: Zn = 1: 4: 4, In: M: Zn = 1: 4: 5, In: M: Zn = 1: 4:
6, In: M: Zn = 1: 4: 7, In: M: Zn = 1: 4: 8, In: M: Zn = 1:
5: 5, In: M: Zn = 1: 5: 6, In: M: Zn = 1: 5: 7, In: M: Zn =
There are 1: 5: 8, In: M: Zn = 1: 6: 8, and the like.

Assuming that the atomic number ratio of the target metal element of "32" is In: M: Zn = x2: y2: z2 _, x2 / y2 is preferably larger than 1 and 6 or less. Further, z2 / y2 is preferably larger than 1 and 6 or less. Typical examples of the atomic number ratio of the target metal element are In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Z.
n = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 3: 1: 3, In: M
: Zn = 3: 1: 4, etc.

Assuming that the atomic number ratio of the target metal element of "33" is In: M: Zn = x3: y3: z3 _, x3 / y3 is preferably 1/6 or more and 1 or less. Further, z3 / y3 is 1 /.
It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Typical examples of the atomic number ratio of the target metal element are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.
2, In: M: Zn = 1: 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1:
3: 6, In: M: Zn = 1: 3: 8, In: M: Zn = 1: 4: 4, In: M: Zn =
1: 4: 5, In: M: Zn = 1: 4: 6, In: M: Zn = 1: 4: 7, In: M: Z
n = 1: 4: 8, In: M: Zn = 1: 5: 5, In: M: Zn = 1: 5: 6, In: M
: Zn = 1: 5: 7, In: M: Zn = 1: 5: 8, In: M: Zn = 1: 6: 8, and the like.

In the target for film formation of In-M-Zn oxide film, the atomic number ratio of the metal element is In: M:
When Zn = x: y: z, setting 1 ≦ z / y ≦ 6 is preferable because a CAAC-OS film is easily formed as an In—M—Zn oxide film. The CAAC-OS film will be described later.

As the oxide semiconductor film 31 to the oxide semiconductor film 33, an oxide semiconductor film having a low carrier density is used. For example, the oxide semiconductor film 31 to the oxide semiconductor film 33 has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, and more preferably 1 × 10 ¹³ / cm. ^Use an oxide semiconductor film of ³ or less. In particular, the oxide semiconductor film 31
The oxide semiconductor film 33 has a carrier density of less than 8 × 10 ¹¹ pieces / cm ³ , more preferably less than 1 × 10 ¹¹ pieces / cm ³ , and even more preferably less than 1 × 10 ¹⁰ pieces / cm ³ . Moreover, it is preferable to use an oxide semiconductor film of 1 × 10 ^-9 pieces / cm ³ or more.

By using an oxide semiconductor film having a low impurity concentration and a low defect level density as the oxide semiconductor film 31 to the oxide semiconductor film 33, a transistor having further excellent electrical characteristics can be produced. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxide semiconductors having high-purity intrinsic or substantially high-purity intrinsic may have a low carrier density due to the small number of carrier sources. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film is unlikely to have an electrical characteristic (also referred to as normalion) in which the threshold voltage is negative. In addition, oxide semiconductor films that are highly pure or substantially highly pure are
Due to the low defect level density, the trap level density may also be low. Moreover, highly purified intrinsic or substantially oxide semiconductor film is highly purified intrinsic, the off current is extremely small, even with an element with a channel width channel length L of 10μm at 1 × 10 ⁶ [mu] m, and a source electrode When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, it is possible to obtain the characteristic that the off current is below the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ^-13 A or less. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film is a highly reliable transistor with little fluctuation in electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals and the like.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, and an oxygen deficiency is formed in the oxygen-desorbed lattice (or oxygen-desorbed portion). When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be bonded to oxygen, which is bonded to a metal atom, to generate electrons as carriers.
Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normalion characteristics.

Therefore, it is preferable that hydrogen is reduced as much as possible in the oxide semiconductor film 31 to the oxide semiconductor film 33 together with oxygen deficiency. Specifically, in the oxide semiconductor film 31 to the oxide semiconductor film 33, secondary ion mass spectrometry (SIMS: Secondary Ion Ma)
Hydrogen concentration obtained by ss Spectrometer) is 5 × 10 ¹⁹ atoms.
/ Cm ³ or less, more preferably 1 x 10 ¹⁹ atoms / cm ³ or less, 5 x 10 ¹⁸ at
less than oms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, still more preferably 1 × 10 ¹⁶ atoms / cm.
³ or less.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor film 31 to the oxide semiconductor film 33, oxygen deficiency in the film increases, and these films become n-shaped. Therefore, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) in the oxide semiconductor film 31 to the oxide semiconductor film 33 is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2.
× 10 ¹⁷ atoms / cm ³ or less.

Further, in the oxide semiconductor film 31 to the oxide semiconductor film 33, the concentration of the alkali metal or alkaline earth metal obtained by the secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / c.
It should be m ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. Alkaline metals and alkaline earth metals may form carriers when combined with oxide semiconductors, which may increase the off-current of the transistor. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film 31 to the oxide semiconductor film 33.

When nitrogen is contained in the oxide semiconductor film 31 to the oxide semiconductor film 33, electrons as carriers are generated, the carrier density increases, and the n-type is easily formed. Therefore, a transistor using an oxide semiconductor containing nitrogen tends to have normalion characteristics, so that the oxide semiconductor film 31
The nitrogen content of the oxide semiconductor film 33 is preferably reduced as much as possible. For example, the nitrogen concentration obtained by the secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The oxide semiconductor film 31 to the oxide semiconductor film 33 have been described above, but the present invention is not limited to these, and is appropriate depending on the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. An oxide semiconductor film having a different composition may be used. Further, in order to obtain the required semiconductor characteristics and electrical characteristics of the transistor, the oxide semiconductor film 31 to the oxide semiconductor film 3
It is preferable that the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of No. 3 are appropriate.

Since the transistor TA1 has a channel formed by the oxide semiconductor film 32 in which the atomic number ratio of In is larger than the atomic number ratio of Ga or M (M is Al, Ga, Y, Zr, La, Ce, or Nd). , The field effect mobility can be increased. Typically, the electric field effect mobility, 10 cm ² / Vs greater than less than 60cm ² / Vs, preferably less than 15cm ² / Vs or more 50 cm ² / Vs. Therefore, when the transistor TA1 is used in the circuit of the active matrix type display device, it is suitable for a drive circuit that requires high-speed operation.

Further, the transistor TA1 is preferably provided in a light-shielded region. Further, by providing the transistor TA1 having high field effect mobility in the drive circuit, the drive frequency can be increased, so that a higher definition display device can be realized.

Transistors TA2 and TB1 whose channel formation region is formed of the oxide semiconductor film 33 have lower field-effect mobility than transistor TA1, and their size is 3 cm ² / Vs or more and 10
It is about cm ² / Vs or less. Since the transistors TA2 and TB1 do not have the oxide semiconductor film 32, they are less likely to be deteriorated by light than the transistors TA1, and the amount of increase in off-current due to light irradiation is small. Therefore, the transistors TA2 and TB1 whose channel forming region is formed of the oxide semiconductor film 33 are suitable for the pixel portion to be irradiated with light.

The transistor TA1 is compared with the transistor TA2 which does not have the oxide semiconductor film 32.
When illuminated with light, the current in the off state tends to increase. This is one of the reasons why the transistor TA1 is suitable for a peripheral drive circuit that is less affected by light than a pixel portion that cannot sufficiently block light such as a pixel portion. Further, of course, transistors having a configuration such as transistors TA2 and TB1 can also be provided in the drive circuit.

The transistors (TA1, TA2, TB1) and the oxide semiconductor film 31 to the oxide semiconductor film 33 have been described above, but the present invention is not limited to these, and the transistor configuration is determined according to the required semiconductor characteristics and electrical characteristics of the transistor. Should be changed. For example, the presence or absence of the back gate electrode, the laminated structure of the oxide semiconductor film, the shape and arrangement of the oxide semiconductor film, the gate electrode, the source electrode and the drain electrode can be appropriately changed.

(Structure of oxide semiconductor)
Next, the structure of the oxide semiconductor will be described.

In the present specification, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Also,"
"Approximately parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombic crystal, it is represented as a hexagonal system.

The oxide semiconductor film is divided into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Alternatively, the oxide semiconductor is divided into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

As a non-single crystal oxide semiconductor, CAAC-OS (C Axis Aligned)
Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, and the like. Further, examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystal oxide semiconductor.

First, the CAAC-OS film will be described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis oriented crystal portions.

Transmission electron microscope (TEM: Transmission Electron Micro)
A composite analysis image of the bright-field image and diffraction pattern of the CAAC-OS film (scope).
Also called a high-resolution TEM image. ) Can be confirmed to confirm a plurality of crystal parts.
On the other hand, even with a high-resolution TEM image, a clear boundary between crystal portions, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to have a decrease in electron mobility due to grain boundaries.

When observing a high-resolution TEM image of the cross section of the CAAC-OS film from a direction substantially parallel to the sample surface,
It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer of metal atom
The shape reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film to be formed, and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

On the other hand, when the high-resolution TEM image of the plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample plane, it can be confirmed that the metal atoms are arranged in a triangular or hexagonal shape in the crystal portion. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film having InGaZnO ₄ crystals by the out-of-plane method, A peak may appear near the diffraction angle (2θ) of 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. It can be confirmed that

In the analysis of the CAAC-OS film having InGaZnO ₄ crystals by the out-of-plane method, a peak may appear in the vicinity of 3 ° in 2θ in addition to the peak in the vicinity of 31 ° in 2θ. The peak with 2θ near 36 ° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. In the CAAC-OS film, it is preferable that 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 °.

The CAAC-OS film is an oxide semiconductor film having a low impurity concentration. Impurities are hydrogen, carbon,
It is an element other than the main component of the oxide semiconductor film such as silicon and transition metal elements. In particular, elements such as silicon, which have a stronger bond with oxygen than the metal elements constituting the oxide semiconductor film, disturb the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and are crystalline. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), so if they are contained inside the oxide semiconductor film, they disturb the atomic arrangement of the oxide semiconductor film and are crystalline. It becomes a factor to reduce. Impurities contained in the oxide semiconductor film may serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film having a low defect level density. For example, oxygen deficiency in an oxide semiconductor film may become a carrier trap or a carrier generation source by capturing hydrogen.

A low impurity concentration and a low defect level density (less oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has few carrier sources, the carrier density can be lowered. Therefore,
Transistors using the oxide semiconductor film have electrical characteristics with a negative threshold voltage (
Also known as normal on. ) Is rare. Further, the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has few carrier traps. Therefore, the transistor using the oxide semiconductor film has a small fluctuation in electrical characteristics and is a highly reliable transistor. The electric charge captured by the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed electric charge. Therefore, a transistor using an oxide semiconductor film having a high impurity concentration and a high defect level density may have unstable electrical characteristics.

Further, the transistor using the CAAC-OS film has a small fluctuation in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, the microcrystalline oxide semiconductor film will be described.

The microcrystalline oxide semiconductor film has a region in which a crystal portion can be confirmed and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal portion contained in the microcrystalline oxide semiconductor film often has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystals), which are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is nc.
-OS (nanocrystalline Oxide Semiconductor)
Called a membrane. Further, in the nc-OS film, for example, the crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, the nc-OS film does not show regularity in crystal orientation between different crystal portions. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, an XR that uses X-rays with a diameter larger than that of the crystal part for the nc-OS film
When the structural analysis is performed using the D apparatus, the peak indicating the crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter larger than the crystal portion (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Will be done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter close to the size of the crystal portion or smaller than the crystal portion, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS film, a region having high brightness (in a ring shape) may be observed in a circular motion. Also,
When nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film having higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower defect level density than the amorphous oxide semiconductor film. However,
In the nc-OS film, there is no regularity in crystal orientation between different crystal portions. Therefore, nc-O
The S film has a higher defect level density than the CAAC-OS film.

Next, the amorphous oxide semiconductor film will be described.

The amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal portion. An example is an oxide semiconductor film having an amorphous state such as quartz.

The crystal part of the amorphous oxide semiconductor film cannot be confirmed in the high-resolution TEM image.

A structural analysis of the amorphous oxide semiconductor film using an XRD device shows that out-of-p.
In the analysis by the lane method, no peak indicating the crystal plane is detected. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

The oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. Oxide semiconductor membranes having such a structure are particularly suitable for amorphous-like oxide semiconductors (a-like OS: amorphous-like Oxide Semi).
It is called a conductor) membrane.

In the a-like OS film, voids (also referred to as voids) may be observed in a high-resolution TEM image. Further, in the high-resolution TEM image, it has a region where the crystal portion can be clearly confirmed and a region where the crystal portion cannot be confirmed. The a-like OS film is
Crystallization may occur and growth of the crystal part may be observed by a small amount of electron irradiation as observed by TEM. On the other hand, if it is a high-quality nc-OS film, crystallization by a small amount of electron irradiation as observed by TEM is hardly observed.

The size of the crystal part of the a-like OS film and the nc-OS film is measured with high resolution T.
This can be done using an EM image. For example, the crystal of InGaZnO ₄ has a layered structure and has a layered structure.
It has two Ga—Zn—O layers between the In—O layers. The unit cell of the crystal of InGaZnO ₄ has a structure in which a total of 9 layers are stacked in a layered manner in the c-axis direction, which has 3 In-O layers and 6 Ga-Zn-O layers. Therefore, the distance between these adjacent layers is about the same as the grid plane distance (also referred to as d value) of the (009) plane, and the value is 0.29 nm from the crystal structure analysis.
Is required. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe is InG in the place where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.
Corresponds to the ab plane of the crystal of aZnO ₄ .

Further, the density of the oxide semiconductor film may differ depending on the structure. For example, if the composition of a certain oxide semiconductor film is known, it can be compared with the density of a single crystal having the same composition as the composition.
The structure of the oxide semiconductor film can be estimated. For example, with respect to the density of a single crystal, a-
The density of the like OS film is 78.6% or more and less than 92.3%. Further, for example, the density of the nc-OS film and the density of the CAAC-OS film are 92.3% or more with respect to the density of the single crystal.
It will be less than 0%. The oxide semiconductor film having a density of less than 78% with respect to the density of the single crystal is
It is difficult to form a film.

The above will be described with reference to specific examples. For example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], a single crystal InGaZnO ₄ having a rhombic crystal structure.
The density of is 6.357 g / cm ³ . Therefore, for example, In: Ga: Zn = 1: 1: 1
In the oxide semiconductor film satisfying [atomic number ratio], the density of the a-like OS film is 5.0 g.
/ Cm ³ or more and less than 5.9 g / cm ³ . Also, for example, In: Ga: Zn = 1: 1:
In the oxide semiconductor film satisfying 1 [atomic number ratio], the density of the nc-OS film and CAAC-
The density of the OS film is 5.9 g / cm ³ or more and less than 6.3 g / cm ³ .

In some cases, single crystals having the same composition do not exist. In that case, the density corresponding to the single crystal having a desired composition can be calculated by combining the single crystals having different compositions at an arbitrary ratio. The density of a single crystal having a desired composition may be calculated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, the density is preferably calculated by combining as few types of single crystals as possible.

The oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. ..

As described above, the OS transistor can realize extremely excellent off-current characteristics.

[Board 30]
Various substrates can be used as the substrate 30, and the substrate 30 is not limited to a specific one. As an example of the substrate 30, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), SOI
Substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates,
There are substrates with stainless steel still foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, base films, and the like. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates, laminated films, base films, etc. include the following. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (
There are plastics represented by PES). Alternatively, as an example, there is a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, and the like. Or, as an example, polyamide, polyimide,
There are aramid, epoxy, inorganic vapor deposition film, or paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture a transistor having a high current capacity and a small size with little variation in characteristics, size, or shape. .. When the circuit is composed of such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

An underlying insulating film may be formed on the substrate 30 before the gate electrodes (GE1, GE2, GE3) are formed. Examples of the underlying insulating film include silicon oxide, silicon nitride, silicon nitride, silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, and aluminum nitride. By using silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or the like as the underlying insulating film, the substrate 30
Impurities (typically alkali metals, water, hydrogen, etc.) from oxide semiconductor film (OS1-OS3)
) Can be suppressed.

[Gate electrodes (GE1, GE2, GE3)]
The gate electrode (GE1, GE2, GE3) is a single-layer conductive film or a multi-layered film in which two or more conductive films are laminated. The conductive film formed as the gate electrodes (GE1, GE2, GE3) is a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-mentioned metal element as a component, or the above-mentioned alloy. It can be formed by using an alloy or the like in which the above-mentioned metal elements are combined. Further, a metal element selected from any one or more of manganese and zirconium may be used. Further, an alloy film or a nitride film obtained by combining one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used for aluminum. It also contains indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide. A translucent conductive material such as indium tin oxide can also be applied.

For example, as a gate electrode (GE1, GE2, GE3), an aluminum film containing silicon can be formed. When the gate electrodes (GE1, GE2, GE3) have a two-layer structure, for example, a titanium film is formed on an aluminum film, a titanium film is formed on a titanium nitride film, and a tungsten film is formed on a titanium nitride film. A tungsten film may be formed on the tantalum nitride film or the tungsten nitride film. Also, the gate electrodes (GE1, GE2, GE)
When 3) has a three-layer structure, for example, a titanium film, an aluminum film may be laminated on the titanium film, and a titanium film may be formed on the titanium film.

Gate electrodes (GE1, GE2, GE3) are formed by a sputtering method, a vacuum vapor deposition method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like.

The tungsten film can be formed by a film forming apparatus using ALD. In this case, the WF ₆ gas and the B ₂ H ₆ gas are sequentially and repeatedly introduced to form the initial tungsten film, and then the WF ₆ gas and the H ₂ gas are simultaneously introduced to form the tungsten film. In addition, B
SiH ₄ gas may be used instead of ₂ H ₆ gas.

The gate electrodes GE1-GE3 can be formed by an electrolytic plating method, a printing method, an inkjet method, or the like, in addition to the above-mentioned forming method.

[Insulating film 34 (gate insulating film)]
An insulating film 34 is formed by covering the gate electrodes GE1-GE3. The insulating film 34 is a single-layer insulating film or an insulating film having a multilayer structure of two or more layers. The insulating film formed as the insulating film 34 is
Examples thereof include an oxide insulating film, a nitride insulating film, an oxide nitride insulating film, and a nitride oxide insulating film.
In the present specification, the oxide nitride is a material having a higher oxygen content than nitrogen, and the nitride oxide is a material having a higher nitrogen content than oxygen.

The insulating film formed as the insulating film 34 includes, for example, an insulating film made of silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn-based metal oxide, or the like. Can be formed. Further, as such an insulating film, a hafnium silicate (HfSiO _x), hafnium silicate to which nitrogen is added _{(HfSi x O y N z)} , nitrogen is added, hafnium aluminate (Hf
A film made of a high-k material such as Al _x O _y N _z ), hafnium oxide, and yttrium oxide can be formed. By using a high-k material, the gate leak of the transistor can be reduced.

Since the insulating film 34 is a film constituting the gate insulating film, the oxide semiconductor film (OS1, OS2,
In order to improve the interface characteristics between the OS3) and the gate insulating film, the region of the insulating film 34 in contact with these layers (OS1, OS2, OS3) is preferably formed of an oxide insulating film or an oxide nitride insulating film. For example, the uppermost film of the insulating film 34 may be a silicon oxide film or a silicon nitride nitride film.

The thickness of the insulating film 34 may be, for example, 5 nm or more and 400 nm or less. The thickness is preferably 10 nm or more and 300 nm or less, and more preferably 50 nm or more and 250 nm or less.

When the oxide semiconductor film (OS1, OS2, OS3) is formed by the sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be appropriately used as the power supply device for generating plasma.

As the sputtering gas, a rare gas (typically argon) atmosphere, an oxygen atmosphere, and a mixed gas of a rare gas and oxygen are appropriately used. In the case of a mixed gas of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Further, the target may be appropriately selected according to the composition of the oxide semiconductor film (OS1, OS2, OS3) to be formed.

When the sputtering method is used to form the oxide semiconductor film (OS1, OS2, OS3), the substrate temperature is 150 ° C. or higher and 750 ° C. or lower, preferably 150 ° C. or higher and 450 ° C. or lower, and more preferably 200 ° C. or higher and 350 ° C. or lower. As a result, the CAAC-OS film can be formed as the oxide semiconductor film 31-32.

Further, it is preferable to apply the following conditions in order to form a CAAC-OS film.

By suppressing the mixing of impurities during film formation, it is possible to prevent the crystal state from being disrupted by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the film forming chamber may be reduced. Further, the concentration of impurities in the film-forming gas may be reduced. Specifically, the dew point is-
A film-forming gas having a temperature of 80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the electric power. The oxygen ratio in the film-forming gas is preferably 30% by volume or more, more preferably 100% by volume.

By forming an oxide semiconductor film while heating it, or after forming an oxide semiconductor film,
By performing the heat treatment, the hydrogen concentration of the oxide semiconductor film is reduced to 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ at.
oms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm less than ³ , preferably 1 × 10 ¹⁸ a
It can be toms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, and even more preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

The heat treatment is performed at a temperature higher than 350 ° C. and 650 ° C. or lower, preferably 450 ° C. or higher and 600 ° C. or lower, so that the CAAC conversion rate described later is 70% or more and less than 100%, preferably 80%.
More than 100%, preferably 90% or more and less than 100%, more preferably 95% or more 98
An oxide semiconductor film of% or less can be obtained. Further, it is possible to obtain an oxide semiconductor film having a reduced content of hydrogen, water and the like. That is, it is possible to form an oxide semiconductor film having a low impurity concentration and a low defect level density.

An oxide semiconductor film can be formed by a film forming apparatus using ALD. For example, InG
When forming an aZnO _X (X> 0) film, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an InO ₂ layer, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are simultaneously introduced to form a GaO layer, and forming a subsequent Zn _{(CH 3)} ZnO layer by introducing simultaneously ₂ gas and the _{O 3} gas. The order of these layers is not limited to this example. Further, these gases are mixed to form an InGaO ₂ layer, an InZNO ₂ layer, a GaInO layer, a ZnInO layer, and a GaZnO.
A mixed compound layer such as a layer may be formed. Incidentally, instead of the O ₃ gas may be used bubbled with the H _{2 O} gas with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Also, Z
n (CH ₃ ) ₂ gas may be used.

The oxide semiconductor film 32 and the oxide semiconductor film 33 are films on which transistor channels are formed, and the film thickness thereof can be 3 nm or more and 200 nm or less. Their thickness is preferably 3 nm or more and 100 nm or less, and more preferably 30 nm or more and 50 nm.
It is as follows. The film thickness of the oxide semiconductor film 31 can be, for example, 3 nm or more and 100 nm or less, preferably 3 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less.
It is as follows. The oxide semiconductor film 31 is preferably formed thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33.

Here, the In-Ga-Zn film is formed as the oxide semiconductor films 31, 32, 33 by a sputtering method. Atomic number ratio (In: G) of the target metal element used for these film formations
a: Zn) is, for example, the oxide semiconductor film 31 is 1: 3: 6, the oxide semiconductor film 32 is 3: 1: 2, and the oxide semiconductor film 33 is 1: 1: 1.2. Alternatively, it can be 1: 1: 1. The thicknesses of the oxide semiconductor films 31, 32, and 33 are 5 nm and 35 n, respectively.
It can be m and 35 nm.

[Source electrode, drain electrode]
The electrodes (SE1, DE1, SE2, DE2, SE3, DE3) are gate electrodes (GE1, GE).
2. It can be formed in the same manner as GE3).

For example, a copper-manganese alloy film with a thickness of 50 nm, a copper film with a thickness of 400 nm, and a thickness of 100 n.
By laminating these films in the order of m copper-manganese alloy films by the sputtering method,
Electrodes having a three-layer structure (SE1, DE1, SE2, DE2, SE3, DE3) can be formed.

Transistors that operate at high speed, such as transistors used in drive circuits of light emitting devices, include transistors (TA1, TA2) or transistors (TA3, TA4,
It is preferable to shorten the channel length as in TC1). The channel length of such a transistor is preferably less than 2.5 μm. For example, it may be 2.2 μm or less. In the transistor of the present embodiment, the channel length is determined by the distance between the source electrode and the drain electrode, so that the minimum value of the channel length is the electrodes (SE1, DE1, SE2, DE2, S).
It is limited by the accuracy of processing the conductive film that becomes E3, DE3). In the transistor of the present embodiment, for example, the channel length can be 0.5 μm or more, or 1.0 μm or more.

[Insulating films 35 and 36]
For example, as "35", an insulating film having a two-layer structure can be formed. Here, "3
The first layer film of "5" is referred to as an insulating film 35a, and the second layer film is referred to as an insulating film 35b.

As the insulating film 35a, for example, an oxide insulating film made of silicon oxide or the like, or an oxide insulating film containing nitrogen and having a small amount of defects can be formed. Typical examples of the oxide insulating film containing nitrogen and having a small amount of defects include a silicon nitride film and an aluminum nitride film.

The oxide insulating film having few defects has a first signal having a g value of 2.037 or more and 2.039 or less in a spectrum obtained by measuring with an ESR of 100 K or less, and a g value of 2.001 or more.
A second signal of 003 or less and a third signal having a g value of 1.964 or more and 1.966 or less are observed. The split width of the first signal and the second signal, and the second signal
The split width of the signal and the third signal is about 5 m in the X-band ESR measurement.
It is T. Further, the first signal having a g value of 2.037 or more and 2.039 or less, and a g value of 2.0
01 or 2.003 or less of the second signal, and g values the sum is less than 1 × ¹⁰ 18 spins / cm ³ of the spin density of the third signal is 1.964 or more 1.966 or less, representing It is 1 × 10 ¹⁷ spins / cm ³ or more and less than 1 × 10 ¹⁸ spins / cm ³ .

In the ESR spectrum of 100 K or less, the first signal having a g value of 2.037 or more and 2.039 or less, the second signal having a g value of 2.001 or more and 2.003 or less, and the g value of 1.
The third signal of 964 or more and 1.966 or less corresponds to a signal caused by nitrogen oxides (NOx, x is 0 or more and 2 or less, preferably 1 or more and 2 or less). A typical example of nitrogen oxides is
There are nitric oxide, nitrogen dioxide, etc. That is, the first signal having a g value of 2.037 or more and 2.039 or less, the second signal having a g value of 2.001 or more and 2.003 or less, and the g value of 1.96.
It can be said that the smaller the total spin density of the third signal, which is 4 or more and 1.966 or less, the smaller the content of nitrogen oxides contained in the oxide insulating film.

Since the insulating film 35a is a film having a low content of nitrogen oxides, the insulating film 35a and the layer (OS)
It is possible to reduce carrier traps at the interface with 1, OS2, OS3). As a result, it is possible to reduce the shift of the threshold voltage of the transistor, and it is possible to reduce the fluctuation of the electrical characteristics of the transistor.

Further, in order to improve the reliability of the transistor, the insulating film 35a is provided with SIMS (Secondar).
The nitrogen concentration measured by y Ion Mass Spectrometer) is 6 × 10 ²
It is preferably ⁰ / cm ³ or less. It is an insulating film 35 during the transistor fabrication process.
This is because nitrogen oxides are less likely to be produced in a.

As an example of the oxide insulating film containing nitrogen and having a small amount of defects as the insulating film 35a, CV
A silicon oxide nitride film can be formed by the D method. In this case, the raw material gas is
It is preferable to use a sedimentary gas containing silicon and an oxidizing gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include nitrous oxide and nitrogen dioxide.

Further, the oxidizing gas with respect to the sedimentary gas is larger than 20 times and less than 100 times, preferably 40 times.
By using a CVD method in which the pressure in the processing chamber is set to less than 100 Pa, preferably 50 Pa or less, the oxide insulating film containing nitrogen and having a small amount of defects is formed as the insulating film 35a. Can be done.

As the insulating film 35b, for example, an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition can be used. An oxide insulating film containing more oxygen than oxygen satisfying a stoichiometric composition is partially desorbed by heating. Oxide insulating films containing more oxygen than oxygen satisfying the stoichiometric composition have an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more in terms of oxygen atoms in TDS analysis. , Preferably 3.0 × 10 ²⁰ ato
It is an oxide insulating film having ms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

The insulating film 35b has a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more 4
Silicon oxide, silicon oxide nitride, or the like having a diameter of 00 nm or less can be used. Insulating film 35
When b is formed using an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition, it is oxidized as an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. The silicon nitride film can be formed by using the CVD method.

When a silicon oxide film or a silicon oxide nitride film is formed as the insulating film 35b, the film can be formed under the following conditions. The substrate placed in the vacuum-exhausted processing chamber of the plasma CVD apparatus is held at 180 ° C. or higher and 280 ° C. or lower, more preferably 200 ° C. or higher and 240 ° C. or lower, and the raw material gas is introduced into the treatment chamber to introduce the pressure in the treatment chamber. 100Pa or more 250P
a following, more preferably not more than 200Pa above 100 Pa, the processing to electrodes provided in the indoor 0.17 W / cm ² or more 0.5 W / cm ² or less, more preferably 0.25 W / cm
^It supplies high-frequency power of ² or more and 0.35 W / cm ² or less.

As the insulating film 36, at least a film having a blocking effect on hydrogen and oxygen is used. Further, it preferably has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals and the like. Typically, a nitride insulating film such as silicon nitride may be formed. In addition to the silicon nitride film, a silicon nitride film, an aluminum nitride film, an aluminum nitride film and the like can also be used.

Further, as a film constituting the insulating film 36, an oxide insulating film having a blocking effect on oxygen, hydrogen, water and the like may be provided. As such an oxide insulating film, aluminum oxide,
There are aluminum nitride, gallium oxide, gallium nitride oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide and the like.

The thickness of the insulating film 36 may be 50 nm or more and 300 nm or less, preferably 100.
It is nm or more and 200 nm or less. By forming the insulating film 36 having a blocking effect against oxygen, hydrogen, water, etc., the diffusion of oxygen from the oxide semiconductor film 31 to the oxide semiconductor film 33 to the outside can be prevented, and the oxide semiconductor film from the outside can be prevented. It is possible to prevent hydrogen, water, etc. from entering the 31 to the oxide semiconductor film 33.

When a silicon nitride film is formed as the insulating film 36 by the plasma CVD method, it is preferable to use a sedimentary gas containing silicon, nitrogen, and ammonia as raw material gases. By using these raw material gases, ammonia is dissociated in the plasma and active species are generated. The active species cleaves the bond between silicon and hydrogen contained in the sedimentary gas containing silicon, and the triple bond with nitrogen. As a result, the bond between silicon and nitrogen is promoted, the bond between silicon and hydrogen is small, the number of defects is small, and a dense silicon nitride film can be formed. On the other hand, when the amount of ammonia with respect to nitrogen in the raw material gas is large, the decomposition of each of the sedimentary gas containing silicon and nitrogen does not proceed, silicon and hydrogen bonds remain, and defects increase.
Moreover, a coarse silicon nitride film is formed. Therefore, in the raw material gas, the flow rate ratio of nitrogen to ammonia is preferably 5 or more and 50 or less, preferably 10 or more and 50 or less.

After forming the insulating film 35, heat treatment may be performed. The temperature of the heat treatment is typically
150 ° C. or higher and lower than the substrate strain point, preferably 200 ° C. or higher and 450 ° C. or lower, more preferably 3
The temperature is 00 ° C or higher and 450 ° C or lower. By the heat treatment, oxygen contained in the oxide insulating film constituting the second layer of the insulating film 35 is moved to the oxide semiconductor film 31 to the oxide semiconductor film 33 to reduce oxygen deficiency contained therein. be able to. The heat treatment may be performed in a mixed gas atmosphere containing nitrogen and oxygen, for example, with a heating temperature of 350 ° C. and a heating time of 1 hour.

Further, after forming the insulating film 36, heat treatment may be performed for the purpose of releasing hydrogen or the like from the oxide semiconductor film 31 to the oxide semiconductor film 33. This heat treatment may be performed, for example, in a mixed gas atmosphere containing nitrogen and oxygen, with a heating temperature of 350 ° C. and a heating time of 1 hour.

[Backgate electrode]
The back gate electrodes (BGE1, BGE2) can be formed in the same manner as the gate electrodes (GE1, GE2, GE3).

Hereinafter, some other configuration examples of the transistor will be shown.

(Transistors TA3, TA4)
29 (A) and 29 (B) show a top view (layout view) of the transistor TA3 and the transistor TA4 and their circuit symbols, respectively. 30 (A) and 30 (B) are cross-sectional views of the transistor TA3 along the lines a7-a8 and b7-b8, and the transistor T.
A cross-sectional view taken along the line a9-a10 and line b9-b10 of A4 is shown.

The transistor TA3 includes a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, and the like.
It has a drain electrode DE4 and a back gate electrode BGE4. The transistor TA3 is a modification of the transistor TA1 and differs from the transistor TA1 in that the electrode BGE4 is in contact with the electrode GE4 at the two openings CG4 and CG5, and the other transistors TA3.
It is the same as 1. As shown in FIG. 30B, the film OS4 is the electrode GE4 in the channel width direction.
And the electrode BGE4, the strength of the transistor TA3 can be further improved.

The transistor TA4 includes a gate electrode GE5, an oxide semiconductor film OS5, a source electrode SE5, and the like.
It has a drain electrode DE5 and a back gate electrode BGE5. The transistor TA4 is a modification of the transistor TA2, and the electrode BGE5 is not connected to the electrode GE5, and the electrode BG is not connected.
The E5 can input different signals and potentials to the electrode GE5. For example, a signal for controlling the conduction state of the transistor TA4 is input to the electrode GE5, and the transistor TA4 is input to the electrode BGE5.
It is possible to input a signal or potential that corrects the threshold voltage of.

(Transistors TC1, TB2, TD1)
31 (A), 31 (B), and 31 (C) show a top view (layout view) of the transistor TC1, the transistor TB2, and the transistor TD1, and their circuit symbols, respectively. 32 (A) and 32 (B) show the a11-a12 line and b of the transistor TC1.
Sectional view taken along line 11b12, lines a13-a14 and b13-b1 of transistor TB2
Cross-sectional view by 4 lines, and a15-a16 line and b15-b16 of transistor TD1
The cross-sectional view by a line is shown.

The transistor TC1 includes a gate electrode GE6, an oxide semiconductor film OS6, a source electrode SE6, and the like.
It has a drain electrode DE6 and a back gate electrode BGE6. Electrode BGE6 has an opening C
It is in contact with the electrode GE6 at G6. The transistor TC1 is a modified example of the transistor TA1, and the film OS6 has a two-layer structure. The membrane OS 6 is composed of "32" and "33". Like the transistor TA1, the transistor TC1 is also a transistor whose channel formation region is "32". Therefore, the transistor TC1 is also a transistor having a field effect mobility as high as that of the transistor TA1, and typically has a field effect mobility of 10c.
Greater than m ² / Vs and less than 60 cm ² / Vs, preferably 15 cm ² / Vs or more and 50 cm
It is a transistor of less than ² / Vs. Therefore, the transistor TC1 is also the transistor TA1.
Similarly, it is suitable for a transistor that operates at high speed such as a drive circuit.

The transistor TB2 includes a gate electrode GE7, an oxide semiconductor film OS7, a source electrode SE7, and the like.
It has a drain electrode DE7 and a back gate electrode BGE7. Electrode BGE7 has an opening C
In G7, it is in contact with the electrode GE7. The transistor TB2 is a modification of the transistor TB1 and differs from the transistor TB2 in that it has an electrode BGE7. Transistor TB
Since No. 2 has an electrode BGE7 connected to the electrode GE7, the on-current is higher than that of the transistor TB1 and the mechanical strength is improved.

The transistor TD1 includes a gate electrode GE8, an oxide semiconductor film OS8, a source electrode SE8, and the like.
And has a drain electrode DE8. The transistor TD1 is a modification of the transistor TB1, in which the entire film OS8 overlaps the electrode GE8 and does not have a portion outside the end of the electrode GE8. As described above, in the transistor TD1, the film OS8 is the transistor TB1.
Since it has a structure that is less exposed to light, it is suitable for a transistor in a pixel portion.

The films (insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) constituting the transistor TA1, the transistor TA2, and the transistor TB1 are prepared by a sputtering method, a chemical vapor deposition (CVD) method, or a vacuum vapor deposition method. It can be formed using the pulsed laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may also be used. As an example of the thermal CVD method, a MOCVD (organometallic chemical deposition) method or an ALD (atomic layer deposition) method may be used.

In the thermal CVD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and the raw material gas and the oxidizing agent are sent into the chamber at the same time, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate to form a film. As described above, since the thermal CVD method is a film forming method that does not generate plasma, it has an advantage that defects are not generated due to plasma damage.

Further, in the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, the raw material gas for the reaction is sequentially introduced into the chamber, and the film formation is performed by repeating the order of gas introduction. For example
Each switching valve (also called a high-speed valve) is switched to supply two or more types of raw material gas to the chamber in order, and an inert gas is simultaneously or after the first raw material gas so that multiple types of raw material gas are not mixed. (Argon, nitrogen, etc.) is introduced, and a second raw material gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the first raw material gas may be discharged by vacuum exhaust, and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first monatomic layer, and reacts with the second raw material gas introduced later, so that the second monoatomic layer becomes the first monoatomic layer. A thin film is formed by being laminated on the atomic layer.

By repeating this process a plurality of times until a desired thickness is obtained while controlling the gas introduction order, a thin film having excellent step covering property can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, the film thickness can be precisely adjusted, which is suitable for manufacturing a fine transistor.

<Specific configuration example 3 of pixels>

FIG. 17 shows a specific configuration of the pixel 10 shown in FIG. 1 as an example. The pixel 10 shown in FIG. 17 is different from the pixel 10 shown in FIG. 4A in the position of the transistor 19t. Specifically
In the pixel 10 shown in FIG. 17, FIG. 4A shows that the transistor 19t is connected between the wiring VL and the other of the source and drain of the transistor 11 and one of the source and drain of the transistor 16t. The configuration is different from the pixel 10 shown.

FIG. 18 shows a specific configuration of the pixel 10 shown in FIG. 1 as an example. The pixel 10 shown in FIG. 18 is different from the pixel 10 shown in FIG. 15A in the position of the transistor 19t. Specifically, in the pixel 10 shown in FIG. 18, the transistor 19t is connected between the wiring VL and the other of the source and drain of the transistor 11 and one of the source and drain of the transistor 16t. The configuration is different from that of the pixel 10 shown in (A).

In the pixel 10 of the light emitting device according to one aspect of the present invention, the transistor other than the transistor 11 may have at least a gate on one side of the semiconductor film, but the transistor is superimposed on the gate via the semiconductor film. It may also have another gate to do. When a transistor other than the transistor 11 has a pair of gates, if one of the pair of gates is a back gate, a potential of the same height may be given to the normal gate and the back gate, or the back gate may be given. A fixed potential such as a ground potential may be given only to the gate.
By controlling the height of the potential applied to the back gate, the threshold voltage of the transistor can be controlled. Further, by providing the back gate, the channel formation region can be increased and the drain current can be increased. Further, by providing the back gate, a depletion layer is likely to be formed on the semiconductor film, so that the S value can be improved.

<Transistor configuration example 2>
The transistor used in the light emitting device according to one aspect of the present invention has a channel forming region on a semiconductor film or semiconductor substrate such as silicon or germanium, which is amorphous, microcrystal, polycrystalline or single crystal. Is also good. When a transistor is formed using a thin film of silicon, amorphous silicon or amorphous silicon produced by a vapor phase growth method such as a plasma CVD method or a sputtering method is crystallized on the thin film by a treatment such as laser annealing. It is possible to use amorphous polycrystalline silicon, single crystal silicon in which hydrogen ions or the like are injected into a single crystal silicon wafer and the surface layer portion is peeled off.

FIG. 34 illustrates a cross-sectional view of a transistor using a thin silicon film that can be used in the light emitting device according to one aspect of the present invention. In FIG. 34, the n-channel transistor 70
And the p-channel type transistor 71.

The transistor 70 is a conductive film 73 that functions as a gate on a substrate 72 having an insulating surface.
The semiconductor film 74 on the conductive film 73, the semiconductor film 75 overlapping the conductive film 73 with the insulating film 74 in between, the insulating film 76 on the semiconductor film 75, and the semiconductor with the insulating film 76 in between. The conductive film 77a and 77b which overlap with the film 75 and function as a gate, the insulating film 78 on the conductive film 77a and 77b, the insulating film 79 on the insulating film 78, and the insulating film 78 and the insulating film. 7
It has a conductive film 80 and a conductive film 81 that are electrically connected to the semiconductor film 75 at the opening provided in 9 and also function as a source or a drain.

The width of the conductive film 77b in the channel length direction is shorter than that of the conductive film 77a, and the conductive film 77a and the conductive film 77b are laminated in order from the insulating film 76 side. Further, the semiconductor film 75 has a channel forming region 82 at a position overlapping the conductive film 77b, a pair of LDD (Light Doped Drain) regions 83 located so as to sandwich the channel forming region 82, and a channel forming region 82. It has a pair of impurity regions 84 located so as to sandwich the LDD region 83 in between. The pair of impurity regions 84 function as a source region or a drain region. Also, L
Impurity elements such as boron (B), aluminum (Al), and gallium (Ga) that impart an n-type conductive type to the semiconductor film 75 are added to the DD region 83 and the impurity region 84.

Further, the transistor 71 is a semiconductor film in which the conductive film 85 that functions as a gate, the insulating film 74 on the conductive film 85, and the conductive film 85 are superimposed on the substrate 72 having an insulating surface with the insulating film 74 in between. The semiconductor film 86 is interposed between the 86, the insulating film 76 on the semiconductor film 86, and the insulating film 76.
And the conductive film 87a and 87b that superimpose with and also function as a gate, and the conductive film 87.
The insulating film 78 on the a and the conductive film 87b, the insulating film 79 on the insulating film 78, and the openings provided in the insulating film 78 and the insulating film 79 are electrically connected to the semiconductor film 86, and the source or drain. It has a conductive film 88 and a conductive film 89 that function as a conductive film.

The width of the conductive film 87b in the channel length direction is shorter than that of the conductive film 87a, and the conductive film 87a and the conductive film 87b are laminated in order from the insulating film 76 side. Further, the semiconductor film 75 has a channel forming region 90 at a position overlapping the conductive film 87b and a pair of impurity regions 91 located so as to sandwich the channel forming region 90 in between. The pair of impurity regions 91 function as a source region or a drain region. Further, the impurity region 91 is a p-type conductive type semiconductor film 86.
Impurity elements such as phosphorus (P) and arsenic (As) are added.

The semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. As various crystallization methods, there are a laser crystallization method using laser light and a crystallization method using a catalytic element. Alternatively, a crystallization method using a catalytic element and a laser crystallization method can be used in combination. When a substrate having excellent heat resistance such as quartz is used as the substrate 72, a thermal crystallization method using an electric heating furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalyst element, A crystallization method combined with high temperature annealing of about 950 ° C. may be used.

<Manufacturing method of light emitting device 1>
Next, FIGS. 19 and 20 show a method for manufacturing the light emitting device 400 according to one aspect of the present invention.
Will be described using.

First, the insulating film 420 is formed on the substrate 462, and the first element layer 410 is formed on the insulating film 420 (see FIG. 19A). A semiconductor element is provided on the first element layer 410.
Alternatively, the first element layer 410 may be provided with a part of a display element such as a display element or a pixel electrode in addition to the semiconductor element.

The substrate 462 needs to have at least heat resistance enough to withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc.
It may be used as 62.

When a glass substrate is used for the substrate 462, if an insulating film such as a silicon oxide film, a silicon nitride film, a silicon nitride film, or a silicon nitride film is formed between the substrate 462 and the insulating film 420, the glass substrate is contaminated. Can be prevented, which is preferable.

For the insulating film 420, for example, an organic resin film such as an epoxy resin, an aramid resin, an acrylic resin, a polyimide resin, a polyamide resin, or a polyamide-imide resin can be used. Of these, polyimide resin is preferable because it has high heat resistance. As the insulating film 420, for example
When a polyimide resin is used, the film thickness of the polyimide resin is 3 nm or more and 20 μm or less, preferably 500 nm or more and 2 μm or less. When a polyimide resin is used as the insulating film 420, it can be formed by a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when a polyimide resin is used as the insulating film 420, an insulating film 420 having a desired thickness can be obtained by removing a part of the film using the polyimide resin by the doctor blade method.

The temperature of the first element layer 410 in the manufacturing process is preferably room temperature or higher and 300 ° C. or lower. For example, the insulating film or conductive film using an inorganic material contained in the first element layer 410 is preferably formed at a film formation temperature of 150 ° C. or higher and 300 ° C. or lower, and further preferably 200 ° C. or higher and 270 ° C. or lower. .. Further, the insulating film or the like using an organic resin material contained in the first element layer 410 is preferably formed at a film forming temperature of room temperature or more and 100 ° C. or less.

Further, the oxide semiconductor film of the transistor included in the first element layer 410 is covered with the above-mentioned CA.
It is preferable to use AC-OS. CAAC-O on the oxide semiconductor film of the transistor
When S is used, for example, when the light emitting device 400 is bent, cracks and the like are less likely to enter the channel forming region, and it is possible to increase the resistance to bending.

Further, it is preferable to use indium tin oxide to which silicon oxide is added as the conductive film contained in the first element layer 410, because cracks and the like are less likely to occur in the conductive film when the light emitting device 400 is bent.

Next, the first element layer 410 and the temporary support substrate 466 are adhered to each other using the peeling adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the substrate 462. As a result, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 19B).
..

The temporary support substrate 466 includes a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, and the like.
A metal substrate or the like can be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used, or a flexible substrate such as a film may be used.

As the peeling adhesive 464, the temporary support substrate 466 and the element layer 410 are chemically or when necessary, such as those that are soluble in water or a solvent and those that can be plasticized by irradiation with ultraviolet rays or the like. Use an adhesive that can be physically separated.

In the transfer step to the temporary support substrate 466, various methods can be appropriately used. For example, by irradiating the insulating film 420 with laser light 468 from the side where the insulating film 420 of the substrate 462 is not formed, that is, from the lower side shown in FIG. 19 (B), the insulating film 420 is weakened to weaken the substrate 462. And the insulating film 420 can be peeled off. Further, by adjusting the irradiation energy density of the laser beam 468, a region having high adhesion between the substrate 462 and the insulating film 420 and a region having low adhesion between the substrate 462 and the insulating film 420 are separated and then peeled off. May be good.

In the present embodiment, a method of peeling at the interface between the substrate 462 and the insulating film 420 has been illustrated, but the present invention is not limited to this. For example, it may be peeled off at the interface between the insulating film 420 and the first element layer 410.

Further, the liquid is permeated into the interface between the substrate 462 and the insulating film 420, and the insulating film 42 from the substrate 462
0 may be peeled off. Alternatively, the liquid may be permeated into the interface between the insulating film 420 and the first element layer 410 to peel off the first element layer 410 from the insulating film 420. As the liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface where the insulating film 420 is peeled off, specifically, the interface between the substrate 462 and the insulating film 420 or the interface between the insulating film 420 and the first element layer 410, the first element layer 410 It is possible to suppress the influence of static electricity and the like generated by the given peeling.

Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (FIG. 19 (FIG. 19).
See C)).

Next, the peeling adhesive 464 is melted or plasticized, and the peeling adhesive 464 and the temporary support substrate 466 are removed from the first element layer 410 (see FIG. 19 (D)).

It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

As described above, the first element layer 410 can be produced on the first substrate 401.

Next, the second substrate 4 is formed by the same forming method as the steps shown in FIGS. 19A to 19D.
05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second
411 and the element layer 411 of the above (see FIG. 20 (A)).

The insulating film 440 included in the second element layer 411 can be formed by using the same material as the insulating film 420, here an organic resin.

Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together (FIG. 20 (FIG. 20). B) See).

The sealing layer 432 can be used for solid sealing, for example. However, the sealing layer 432 preferably has a flexible structure. As the sealing layer 432, for example, a glass material such as glass frit, a curable resin such as a two-component mixed resin that cures at room temperature, a photocurable resin, or a resin material such as a thermosetting resin is used. Can be done.

From the above, the light emitting device 400 can be manufactured.

<Manufacturing method 2 of light emitting device>
Next, another method for manufacturing the light emitting device 400 according to one aspect of the present invention will be described with reference to FIG. Note that FIG. 21 describes a configuration in which an inorganic insulating film is used as the insulating film 420 and the insulating film 440.

First, the release layer 463 is formed on the substrate 462. Next, the insulating film 420 is formed on the release layer 463, and the first element layer 410 is formed on the insulating film 420 (see FIG. 21 (A)).

The release layer 463 includes, for example, an element selected from tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, and silicon, and an alloy material containing the element. Alternatively, a monolayer or laminated structure containing a compound material containing the element can be used. Further, in the case of a layer containing silicon, the crystal structure of the layer containing silicon may be amorphous, microcrystal, polycrystal, or single crystal.

The release layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, or the like. The coating method includes a spin coating method, a droplet ejection method, and a dispensing method.

When the release layer 463 has a single layer structure, it is preferable to form a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum. Further, a layer containing an oxide or oxide of tungsten, a layer containing an oxide or nitride of molybdenum, or a layer containing an oxide or nitride of a mixture of tungsten and molybdenum may be formed. The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

Further, when forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 463, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed on the upper layer. Therefore, it may be utilized that a layer containing a tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. Further, the surface of the layer containing tungsten, thermal oxidation treatment, oxygen plasma treatment, nitrous oxide (N 2 _O) plasma treatment, an oxide of tungsten processing or the like in the strong oxidizing solution such as ozone water A layer containing may be formed. Further, the plasma treatment and the heat treatment may be carried out by oxygen, nitrogen, nitrous oxide alone, or in a mixed gas atmosphere of the gas and another gas. By the above plasma treatment and heat treatment, the release layer 463
By changing the surface state of the above, it is possible to control the adhesion between the release layer 463 and the insulating film 420 formed later.

As the insulating film 420, for example, an inorganic insulating film having low moisture permeability such as a silicon oxide film, a silicon nitride film, a silicon nitride film, a silicon nitride film, or an aluminum oxide film can be used. The inorganic insulating film can be formed by, for example, a sputtering method, a PECVD method, or the like.

Next, the first element layer 410 and the temporary support substrate 466 are adhered to each other using the peeling adhesive 464, and the insulating film 420 and the first element layer 410 are peeled from the peeling layer 463. As a result, the insulating film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 21 (B)).

In the transfer step to the temporary support substrate 466, various methods can be appropriately used. For example, when a layer containing a metal oxide film is formed at the interface between the release layer 463 and the insulating film 420, the metal oxide film can be fragile by crystallization and the insulating film 420 can be peeled from the release layer 463. .. When the release layer 463 is formed of a tungsten film, the release layer 463 may be peeled while etching the tungsten film with a mixed solution of aqueous ammonia and hydrogen peroxide.

Further, the insulating film 420 may be peeled from the peeling layer 463 by infiltrating the liquid into the interface between the peeling layer 463 and the insulating film 420. As the liquid, for example, water, a polar solvent, or the like can be used. By infiltrating the liquid into the interface where the insulating film 420 is peeled off, specifically, the interface between the peeling layer 463 and the insulating film 420, the influence of static electricity or the like generated by the peeling given to the first element layer 410 is suppressed. can do.

Next, the first substrate 401 is adhered to the insulating film 420 using the adhesive layer 418 (FIG. 21 (C)).
reference).

Next, the peeling adhesive 464 is melted or plasticized to remove the peeling adhesive 464 and the temporary support substrate 466 from the first element layer 410 (see FIG. 21 (D)).

It is preferable to remove the peeling adhesive 464 with water, a solvent, or the like so that the surface of the first element layer 410 is exposed.

As described above, the first element layer 410 can be produced on the first substrate 401.

Next, the second substrate 4 is formed by the same forming method as the steps shown in FIGS. 21 (A) to 21 (D).
05, the adhesive layer 412 on the second substrate 405, the insulating film 440 on the adhesive layer 412, and the second
And the element layer 411 of the above. After that, the sealing layer 432 is filled between the first element layer 410 and the second element layer 411, and the first element layer 410 and the second element layer 411 are bonded together.

Finally, the anisotropic conductive film 380 and the FPC 408 are attached to the connection electrode 360. If necessary, an IC chip or the like may be mounted.

From the above, the light emitting device 400 can be manufactured.

<Cross-sectional structure of light emitting device>
FIG. 22 shows, as an example, the cross-sectional structure of the pixel portion of the light emitting device according to one aspect of the present invention. In FIG. 22, the transistor 11, the capacitive element 18, and the pixel 10 shown in FIG. 3A have the transistor 11.
And the cross-sectional structure of the light emitting element 14 is illustrated.

Specifically, the light emitting device shown in FIG. 22 has a transistor 11 and a capacitance element 18 on the substrate 500.
And have. The transistor 11 is electrically connected to the conductive film 501 that functions as the first gate, the insulating film 502 on the conductive film 501, the semiconductor film 503 that overlaps the conductive film 501 with the insulating film 502 in between, and the semiconductor film 503. Conductive 504 and conductive film 505 that function as a source or drain connected to the conductor, an insulating film 550 on the semiconductor film 503, the conductive film 504 and the conductive film 505, and the conductive film 501 with the insulating film 550 in between. It has a conductive film 551 that superimposes and functions as a second gate.

The capacitive element 18 has a conductive film 501 that functions as an electrode, an insulating film 502 on the conductive film 501, and a conductive film 504 that overlaps the conductive film 501 with the insulating film 502 sandwiched between them and also functions as an electrode.

The insulating film 502 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. Insulating films containing one or more may be used as a single layer or laminated. In addition, in this specification,
Oxidized nitride refers to a material having a higher oxygen content than nitrogen in its composition, and nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

Further, an insulating film 511 is provided on the semiconductor film 503, the conductive film 504, and the conductive film 505. When an oxide semiconductor is used as the semiconductor film 503, the insulating film 511 is the semiconductor film 5.
It is desirable to use a material capable of supplying oxygen to 03. Insulating film 5 made of the above material
When used in 11, the oxygen contained in the insulating film 511 can be transferred to the semiconductor film 503, and the amount of oxygen deficiency in the semiconductor film 503 can be reduced. The transfer of oxygen contained in the insulating film 511 to the semiconductor film 503 can be efficiently performed by performing a heat treatment after forming the insulating film 511.

An insulating film 520 is provided on the insulating film 511, and a conductive film 524 is provided on the insulating film 520. The conductive film 524 is connected to the conductive film 504 at the openings provided in the insulating film 511 and the insulating film 520.

An insulating film 525 is provided on the insulating film 520 and the conductive film 524. The insulating film 525 is
It has an opening at a position where it overlaps with the conductive film 524. Further, on the insulating film 525, the insulating film 5
The insulating film 526 is provided at a position different from the opening of 25. And the insulating film 525
The EL layer 527 and the conductive film 528 are provided on the insulating film 526 so as to be laminated in this order. The portion where the conductive film 524 and the conductive film 528 overlap with each other with the EL layer 527 in between functions as a light emitting element 14. One of the conductive film 524 and the conductive film 528 functions as an anode and the other functions as a cathode.

Further, the light emitting device has a substrate 530 that faces the substrate 500 with a light emitting element 14 sandwiched between them. A shielding film 531 having a function of shielding light is provided on the substrate 530, that is, on the surface of the substrate 530 on the side close to the light emitting element 14. The shielding film 531 is formed by the light emitting element 1.
It has an opening in the area overlapping with 4. In the opening overlapping the light emitting element 14, the substrate 53
A colored layer 532 that transmits visible light in a specific wavelength range is provided on 0.

<Appearance of light emitting device>
FIG. 23A is a perspective view showing an example of the appearance of the light emitting device according to one aspect of the present invention. The light emitting device shown in FIG. 23A includes a panel 1601, a circuit board 1602 provided with a controller, a power supply circuit, an image processing circuit, an image memory, a CPU, and the like, and a connection portion 1603. The panel 1601 includes a pixel unit 1604 provided with a plurality of pixels, a drive circuit 1605 that selects a plurality of pixels for each row, and a drive circuit 1606 that controls input of an image signal Sigma to the pixels in the selected row. Have.

Various signals and potentials of the power supply are input to the panel 1601 from the circuit board 1602 via the connection unit 1603. The connection unit 1603 has an FPC (Flexible Printe).
d Circuit) and the like can be used. CO with a chip mounted on FPC
Called F-tape, COF tape can be used for higher density mounting in a smaller area. When a COF tape is used for the connection portion 1603, a part of the circuit in the circuit board 1602, or a part of the drive circuit 1605 and the drive circuit 1606 of the panel 1601 is formed on a separately prepared chip, and the COF is formed. The chip may be connected to the COF tape by using the (Chip On Film) method.

Further, FIG. 23 (B) shows a perspective view showing an example of the appearance of the light emitting device using the COF tape 1607.
Shown in.

The chip 1608 is a semiconductor bare chip (IC, LSI, etc.) having terminals such as bumps on its surface. Furthermore, CR components can also be mounted on the COF tape 1607, and the circuit board 1602
The area of can be reduced. A plurality of wiring patterns of the flexible substrate are formed corresponding to the terminals of the chip to be mounted. The chip 1608 is mounted by positioning and arranging it on a flexible substrate having a wiring pattern by a bonder device or the like and thermocompression bonding.

FIG. 23B shows an example of one COF tape 1607 on which one chip 1608 is mounted, but the present invention is not particularly limited. Multiple rows of chips can be mounted on one side or both sides of one COF tape 1607, but in order to reduce costs, it is preferable to mount one row in order to reduce the number of chips to be mounted, and more preferably one. It is desirable to do.

<Circuit board configuration example>
FIG. 25 shows an external view of the circuit board 2003. The circuit board 2003 is on an FPC 2201 having a slit 2211 with Bluetooth®® IEEE802.5.1.
Same as. ) Standard communication device 2101, microcomputer 2102, storage device 2103, FPGA 2
It has a configuration provided with 104, a DA converter 2105, a charge control IC 2106, and a level shifter 2107. Further, the circuit board 2003 is electrically connected to the light emitting device according to one aspect of the present invention via the input / output connector 2108. In addition, slit 2211 in FPC2201
The flexibility of the circuit board 2003 using the FPC 2201 is increased by providing the above.

By using a flexible substrate for the light emitting device according to one aspect of the present invention, the circuit board 200
Along with 3, the light emitting device can also be curved. Therefore, the light emitting device using the flexible substrate and the circuit board 2003 can be repeatedly deformed according to the shape of the mounting portion, and thus can be used for electronic devices that can be mounted on the body such as arms and legs. Suitable for

<Configuration example of information processing device>
FIG. 26A is a schematic view illustrating the appearance of the information processing apparatus 1000 according to one aspect of the present invention.
FIG. 26 (B) is a cross-sectional view illustrating the structure of the cross section of the cutting lines X1-X2 shown in FIG. 26 (A). Further, FIGS. 26 (C) and 26 (D) show the information processing device 1 of one aspect of the present invention.
It is a schematic diagram explaining the appearance of 000, and FIG. 26 (E) shows FIGS. 26 (C) and 26 (D).
It is sectional drawing explaining the structure of the cross section in the cutting line X3-X4 shown by). FIG. 26C is a schematic view illustrating the front surface of the information processing device 1000. FIG. 26 (D) shows the information processing device 10.
It is a schematic diagram explaining the back surface of 00.

As shown in FIGS. 26 (C) and 26 (D), the position input unit 1001 or the display unit 1002 may be provided not only on the front surface of the information processing device 1000 but also on the side surface or the back surface. Further, the position input unit 1001 or the display unit 1002 may be provided on the upper surface of the information processing device 1000. Further, the position input unit 1001 or the display unit 1002 is the information processing device 100.
It may be provided on the bottom surface of 0.

In addition to the position input unit 1001, the surface of the housing 1003 may have a hardware button, an external connection terminal, or the like.

With such a configuration, it is possible to display not only on the surface parallel to the front surface of the housing 1003 as in the conventional information processing apparatus, but also on the side surface of the housing 1003. In particular, it is preferable to provide the display area along two or more side surfaces of the housing 1003 because the variety of display is further increased.

The display area arranged along the front surface of the information processing apparatus and each display area arranged along the side surface may be used as independent display areas to display different images or the like, or any 2
One image or the like may be displayed over one or more display areas. For example, the images to be displayed in the display area arranged along the front surface of the information processing device may be continuously displayed in the display area provided along the side surface of the information processing device.

Further, the arithmetic unit 1005 is provided inside the housing 1003. In FIG. 26 (B),
The arithmetic unit 1005 is provided at a position separated from the display unit 1002. In FIG. 26 (E), the arithmetic unit 1005 is provided at a position overlapping the display unit 1002.

As an example, the position input unit 1001 has a first area 1001 (1) and a first area 100.
A second region 1001 (2) facing 1 (1) and a first region 1001 (1) and a second
It has the flexibility to be bent so that a third region 1001 (3) is formed between the regions 1001 (2) of the above (see FIG. 26 (B)). Further, as another example, a first region 1001 (1), a third region 1001 (3), and a fourth region 1001 (4) facing the third region 1001 (3) are formed. It has the flexibility to be bent so that it can be bent (see FIG. 26E).

Further, as another example, a third region 1001 (3), a fifth region 1001 (5), and a fourth region 1001 (4) facing the third region 1001 (3) are formed. It may have flexibility that can be bent so as to be.

The arrangement of the second region 1001 (2) facing the first region 1001 (1) is not limited to the arrangement facing the first region 1001 (1), but is limited to the arrangement of the first region 1001 (1). It shall include the arrangement of facing each other with an inclination. Further, the arrangement of the fourth region 1001 (4) facing the third region 1001 (3) is not limited to the arrangement facing the third region 1001 (3), and the arrangement is not limited to the arrangement facing the third region 1001 (3).
It is assumed that the arrangement facing the region 1001 (3) with an inclination is also included.

The display unit 1002 includes at least the first region 1001 (1), the second region 1001 (2), and the like.
It is arranged so as to overlap a part of the third region 1001 (3) or the fourth region 1001 (4).

The information processing device 1000 is a flexible position input unit 100 that detects an object that is close to or comes into contact with the information processing device 1000.
1 is included. Then, the position input unit 1001 is, for example, the first region 1001 (
1), a second region 1001 (2) facing the first region, and a first region 1001 (1).
And a third region 1001 (3) that overlaps the display unit 1002 between the second region 1001 (2).
) And can be bent to form. This makes it possible to know, for example, whether either the palm or the fingers of the hand is close to either the first region 1001 (1) or the second region 1001 (2). As a result, it is possible to provide a human interface having excellent operability. Alternatively, it is possible to provide a new information processing device having excellent operability.

As the substrate used for the display unit 1002, a resin having a thickness sufficient to have flexibility can be applied. Examples of the resin include polyester, polyolefin, polyamide, polyimide, aramid, epoxy, polycarbonate, acrylic resin and the like. Further, as a normal substrate having no flexibility, a glass substrate, a quartz substrate, a semiconductor substrate and the like can be used.

<Example of electronic device configuration>
The light emitting device according to one aspect of the present invention is an image reproduction device (typically, DVD: Digital Versaille D) including a display device, a notebook personal computer, and a recording medium.
It can be used for a device having a display capable of reproducing a recording medium such as isc and displaying the image). In addition, as electronic devices that can use the light emitting device according to one aspect of the present invention, cameras such as mobile phones, portable game machines, personal digital assistants, electronic books, video cameras, digital still cameras, and goggle-type displays ( Head-mounted display)
, Navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. Specific examples of these electronic devices are shown in FIG.

FIG. 24A is a display device, which includes a housing 5001, a display unit 5002, a support base 5003, and the like. The light emitting device according to one aspect of the present invention can be used for the display unit 5002. In addition, it should be noted
The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 24B shows a mobile information terminal, which includes a housing 5101, a display unit 5102, and an operation key 5103.
Etc. The light emitting device according to one aspect of the present invention can be used for the display unit 5102.

FIG. 24C is a display device, which includes a housing 5701 having a curved surface, a display unit 5702, and the like. By using a flexible substrate for the light emitting device according to one aspect of the present invention, the light emitting device can be used for the display unit 5702 supported by the housing 5701 having a curved surface, and the light emitting device is flexible, light and easy to use. A good display device can be provided.

FIG. 24D shows a portable game machine, which includes a housing 5301, a housing 5302, and a display unit 5303.
It has a display unit 5304, a microphone 5305, a speaker 5306, an operation key 5307, a stylus 5308, and the like. The light emitting device according to one aspect of the present invention can be used for the display unit 5303 or the display unit 5304. By using the light emitting device according to one aspect of the present invention for the display unit 5303 or the display unit 5304, it is possible to provide a portable game machine that is excellent in usability for the user and is unlikely to deteriorate in quality. The portable game machine shown in FIG. 24D has two display units 5303 and a display unit 5304, but the number of display units included in the portable game machine is not limited to this.

FIG. 24 (E) is an electronic book, which has a housing 5601, a display unit 5602, and the like. The light emitting device according to one aspect of the present invention can be used for the display unit 5602. By using a flexible substrate, the light emitting device can be made flexible, so that it is possible to provide a flexible, light and easy-to-use electronic book.

FIG. 24F is a mobile phone, and the housing 5901 is provided with a display unit 5902, a microphone 5907, a speaker 5904, a camera 5903, an external connection unit 5906, and an operation button 5905. A light emitting device according to one aspect of the present invention can be used for the display unit 5902.
Further, when the light emitting device according to one aspect of the present invention is formed on a flexible substrate, FIG. 24 (
It is possible to apply the light emitting device to the display unit 5902 having a curved surface as shown in F).

<Example>
In this embodiment, a display device manufactured by using the pixels shown in the above embodiment will be described.

First, the characteristics of the transistor used for the pixel were measured. The transistor used for the pixel is CA
The OS transistor is formed by using the AC-OS film, and the CAAC-OS film is In-Ga.
Formed using −Zn oxide.

FIG. 42 (A) shows the measurement results of the IV characteristics of the OS transistor. Here, the source-
The measurement results are shown when the voltage (Vds) between the drains is 0.1 V and 10 V. The channel length L of the OS transistor was 6 μm, and the channel width W was 6 μm. Further, the OS transistor is provided with a back gate, and the measurement is performed in a state where the voltage (Vbgs) between the back gate and the source is 0 V.

The measurement was performed at 20 points on the same substrate. The median threshold voltage of the OS transistor obtained by the measurement was 4.38V, and the variation of the threshold voltage was 3σ = 0.88V.

By providing a back gate, DIBL (Drain Induced Ba)
rrier Lowering) The effect is reduced. In the case of the single gate structure without the back gate, the channel length modulation coefficient was about 0.05V ^-1 , whereas when the back gate was used, it was about 0.009V ^-1 , and the saturation was high. It was improving.

Next, the measurement result of the Vbgs dependence of the threshold voltage Vth of the OS transistor is shown in FIG. 42 (B).
Shown in. FIG. 42 (B) is a graph obtained by measuring the IV characteristics by changing Vbgs with the source potential of the OS transistor fixed, calculating the threshold voltage from the measurement results, and plotting the graph. Note that FIG. 42B is a measurement result when Vds = 10V.

It can be seen that when Vbgs changes to the positive side, the threshold voltage shifts to the negative side, and when Vbgs changes to the negative side, the threshold voltage shifts to the positive side. Furthermore, Vth is V
It can be seen that the shift is linear with respect to bgs. The amount of shift of the threshold voltage also depends on the film thickness of the interlayer film between the channel portion and the back gate portion and the dielectric constant of the interlayer film. The thicker the film thickness of the interlayer film and the lower the dielectric constant, the smaller the influence of Vbgs on the threshold voltage.

Pixels were constructed using the above OS transistors. FIG. 43 (A) shows the circuit configuration of the pixels. The pixels shown in FIG. 43 (A) correspond to the pixels 10 shown in FIGS. 3 (B) and 4 (B). Then, the threshold voltage was corrected by driving the pixels shown in FIG. 43A according to the timing chart shown in FIG. 43B. The operation of the threshold voltage correction can refer to the description of the above-described embodiment. In the period I, G3 is at a high level, Tr4 is in the ON state, and the source potential of the drive transistor DrTr is the potential obtained by adding the threshold value Vth _OLED of the OLED to the CATHODE potential.

Table 1 shows the specifications of the display device manufactured by using the above pixels. The resolution of the display device is 302
It was ppi and the aperture ratio was 61%. Also, the scan driver is built into the glass,
COF is used as the source driver.

The display device is a top emission type using a white EL element and a color filter (CF). The structure of the display device is shown in FIG. 44 (A).

Further, the white EL element has a laminated structure as shown in FIG. 44 (B). The white EL element has a two-layer tandem element structure in which a light emitting unit made of a blue fluorescent material and a light emitting unit made of a green and red phosphorescent material are connected in series.

FIG. 45 shows a display photograph of the actually manufactured display device. There is no display unevenness in the display photo,
You can see that it can be displayed normally.

FIG. 46 shows the calculation result when the threshold voltage of the drive transistor DrTr shown in FIG. 43 (A) is changed. Here, ΔVth, which is the horizontal axis of the graph, is the amount of Vth shift due to the correction of the threshold voltage. The vertical axis of the graph, Vgs-Vth, is the period IV in FIG. 43 (B).
It is a value obtained by subtracting the threshold voltage of the driving transistor DrTr after correcting the threshold voltage from Vgs of the driving transistor DrTr in the light emitting period of. If the threshold voltage is corrected normally, the slope of the graph becomes 0 because the value of Vgs-Vth does not depend on the threshold voltage.

From the calculation results shown in FIG. 46, Vgs in the range of ΔVth from −1.5V to + 1.5V
It can be seen that the variation in the value of −Vth is suppressed to about 10% of the value of Vgs−Vth at ΔVth = 0.

In the pixel shown in FIG. 43 (A), assuming that the threshold value of the _OLED is Vth _OLED , when the threshold voltage Vth of the drive transistor DrTr is a positive value, Vth = 0 to V0.
-(Casode + Vth _OLED ) can be corrected up to the range shifted to the positive side by the potential, and if the threshold voltage of the drive transistor DrTr is a negative value, Vt
It is possible to correct the variation in the threshold voltage from h = 0 to the range shifted to the minus side by the potential of Anode-V0. Further, when the variation of the threshold voltage of the drive transistor DrTr is within the positive value range, the power supply of V0 can be set to Anode. In this case, the power line V0 in the pixel can be reduced by one.

As described above, by using the present invention, it is possible to manufacture a display device in which the threshold voltage is corrected and display unevenness is reduced.

10 Pixels 11 Transistor 12 Switch 12t Transistor 13 Capacitive element 14 Light emitting element 15 Switch 15t Transistor 16 Switch 16t Transistor 17 Switch 17t Conductor 18 Capacitive element 19 Switch 19t Transistor 30 Substrate 31 Oxide semiconductor film 31-32 Oxide semiconductor film 32 Oxide Semiconductor film 33 Oxide semiconductor film 34 Insulation film 35 Insulation film 35a Insulation film 35b Insulation film 36 Insulation film 40 Pixel section 41 Selection circuit 42 Wiring 43 Switch 44 Switch 45 Monitor circuit 46 Operator 47 Capacitive element 48 Switch 49 Wiring 60A Switch 60B Switch 60C Switch 61 Circuit 62A Switch 62B Switch 62C Switch 63A Wiring 63B Wiring 70 Transistor 71 Transistor 72 Substrate 73 Conductive 74 Insulating film 75 Semiconductor film 76 Insulating film 77a Conductive 77b Conductive 78 Insulating film 79 Insulating film 80 Conductive 81 Conductive 82 Channel formation region 83 LDD region 84 Impurity region 85 Conductive 86 Semiconductor film 87a Conductive 87b Conductive 88 Conductive 89 Conductive 90 Channel formation region 91 Impure region 360 Connection electrode 380 Anisometric conductive film 400 Light emitting device 401 Substrate 405 Substrate 408 FPC
410 Element layer 411 Element layer 412 Adhesive layer 418 Adhesive layer 420 Insulation film 432 Sealing layer 440 Insulation film 462 Substrate 463 Peeling layer 464 Peeling adhesive 466 Temporary support substrate 468 Laser light 500 Substrate 501 Conductive film 502 Insulation film 503 Semiconductor film 504 Conductive film 505 Conductive film 511 Insulating film 520 Insulating film 524 Conducting film 525 Insulating film 526 Insulating film 527 EL layer 528 Conducting film 530 Substrate 531 Shielding film 532 Colored layer 550 Insulating film 551 Conducting film 802 IEEE
1000 Information processing device 1001 Position input unit 1001 (1) First area 1001 (2) Second area 1001 (3) Third area 1001 (4) Fourth area 1002 Display unit 1003 Housing 1005 Computing device 1601 Panel 1602 Circuit board 1603 Connection part 1604 Pixel part 1605 Drive circuit 1606 Drive circuit 1607 COF tape 1608 Chip 2003 Circuit board 2101 Communication device 2102 Microcomputer 2103 Storage device 2104 FPGA
2105 DA converter 2106 Charge control IC
2107 Level shifter 2108 I / O connector 2201 FPC
2211 Slit 5001 Housing 5002 Display 5003 Support 5101 Housing 5102 Display 5103 Operation key 5301 Housing 5302 Housing 5303 Display 5304 Display 5305 Microphone 5306 Speaker 5307 Operation key 5308 Stylus 5601 Housing 5602 Display 5701 Housing 5702 Display 5901 Housing 5902 Display 5903 Camera 5904 Speaker 5905 Button 5906 External connection 5907 Microphone

Claims (2)

It has a first transistor to a sixth transistor, a first capacitive element, a second capacitive element, and a light emitting element.
One of the source or drain of the first transistor is electrically connected to the first wire.
The other of the source or drain of the first transistor is electrically connected to the first gate of the third transistor.
One of the source or drain of the second transistor is electrically connected to the first gate of the third transistor.
The other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor.
One of the source or drain of the fourth transistor is electrically connected to the second wire.
The other of the source or drain of the fourth transistor is electrically connected to the other of the source or drain of the third transistor.
One of the source or drain of the fifth transistor is electrically connected to the second gate of the third transistor.
The other of the source or drain of the fifth transistor is electrically connected to the other of the source or drain of the third transistor.
One of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the third transistor.
The other of the source or drain of the sixth transistor is electrically connected to the third wire.
One of the source or drain of the third transistor is electrically connected to the pixel electrode of the light emitting element.
The first electrode of the first capacitive element is electrically connected to the first gate of the third transistor.
The second electrode of the first capacitive element is electrically connected to the pixel electrode of the light emitting element.
The first electrode of the second capacitive element is electrically connected to the second gate of the third transistor.
The second electrode of the second capacitive element is an electronic device that is electrically connected to the pixel electrode of the light emitting element .
An electronic device having a period in which the second transistor is in a conductive state and the first transistor and the sixth transistor are in a non-conducting state . It has a first transistor to a sixth transistor, a first capacitive element, a second capacitive element, and a light emitting element.
The first gate of the third transistor can be electrically connected to the first wiring through the first transistor.
The first gate of the third transistor can conduct with either the source or drain of the third transistor through the second transistor.
The other of the source or drain of the third transistor can be conducted with the second wire through the fourth transistor.
The second gate of the third transistor can conduct with the other of the source or drain of the third transistor through the fifth transistor.
One of the source and drain of the third transistor can conduct with the third wiring through the sixth transistor.
One of the source or drain of the third transistor is electrically connected to the pixel electrode of the light emitting element.
The first electrode of the first capacitive element is electrically connected to the first gate of the third transistor.
The second electrode of the first capacitive element is electrically connected to the pixel electrode of the light emitting element.
The first electrode of the second capacitive element is electrically connected to the second gate of the third transistor.
The second electrode of the second capacitive element is an electronic device that is electrically connected to the pixel electrode of the light emitting element .
An electronic device having a period in which the second transistor is in a conductive state and the first transistor and the sixth transistor are in a non-conducting state .