JP6782339B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

In wireless communication, MIMO (Multiple Input and Multiple Output) has been proposed as a standard for communicating using a plurality of channels on both the transmitting side and the receiving side. Furthermore, research and development for the practical use of multi-user MIMO, which is a partial multi-user of MIMO, is being actively carried out.

In order to realize such a communication environment, two oscillation signals whose frequencies are close to the IQ signal generator that generates the IQ modulation signal required by the transmitter and receiver in one semiconductor device. Need to be supplied. However, when the transmission lines of two oscillation signals having adjacent frequencies run in parallel, a problem of crosstalk occurs between the transmission lines.

Further, it is necessary to provide a changeover switch in order to switch and supply two oscillation signals to a plurality of IQ signal generators, but this changeover switch also has a problem of crosstalk between adjacent changeover switches. Occurs.

Patent No. 4627033

An object of the present embodiment is to provide a semiconductor device that suppresses the influence of crosstalk between oscillation signals having different frequencies.

The semiconductor device according to the present embodiment includes a first circuit unit to which power is supplied from the first power supply system and a second circuit unit to which power is supplied from a second power supply system different from the first power supply system. It has at least a part. The first circuit unit is a first buffer in which power is supplied from the first power supply system and the first oscillation signal generated by the first oscillation signal generation circuit is input. Power is supplied from the first buffer that can control whether or not to output the oscillation signal of 1 to the second circuit unit and the second power supply system based on the control signal of, and the second oscillation. The second oscillation signal generated by the signal generation circuit is the second buffer input from the second circuit unit, and the input second oscillation signal is input to the first based on the second control signal. It is provided with a second buffer capable of controlling whether or not to output to a first processing unit to which power is supplied from the power supply system of the above.

It is a layout diagram of the power supply system in the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram and a block diagram explaining a part of the circuit structure in the semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the circuit state at the time of supplying the 2nd oscillation signal generated by the 2nd oscillation signal generation circuit to the 1st to 4th circuit part. The first oscillation signal generated by the first oscillation signal generation circuit is supplied to the first circuit unit, and the second oscillation signal generated by the second oscillation signal generation circuit is supplied to the second to fourth circuits. It is a figure for demonstrating the circuit state at the time of supplying to the circuit part of. The first oscillation signal generated by the first oscillation signal generation circuit is supplied to the first to second circuit units, and the second oscillation signal generated by the second oscillation signal generation circuit is supplied to the third circuit unit. It is a figure for demonstrating the circuit state at the time of supplying to the 4th circuit part. The first oscillation signal generated by the first oscillation signal generation circuit is supplied to the first to third circuit units, and the second oscillation signal generated by the second oscillation signal generation circuit is used as the fourth oscillation signal. It is a figure for demonstrating the circuit state at the time of supplying to the circuit part of. It is a figure for demonstrating the circuit state at the time of supplying the 1st oscillation signal generated by the 1st oscillation signal generation circuit to the 1st to 4th circuit part. It is a figure which shows an example of the specific circuit structure of the buffer which can individually control whether or not to output an input signal based on a control signal. It is a block circuit diagram for functionally explaining the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the modification of the semiconductor device which concerns on 1st Embodiment, and is the figure which corresponds to FIG. It is a figure which shows another modification of the semiconductor device which concerns on 1st Embodiment, and is the figure which corresponds to FIG. It is a circuit diagram and a block diagram explaining a part of the circuit structure in the semiconductor device which concerns on 2nd Embodiment. It is a figure for demonstrating the circuit state at the time of supplying the 1st oscillation signal to the 1st to 4th circuit part, or the case of supplying the 2nd oscillation signal to 1st to 4th circuit part. is there. When the first oscillation signal is supplied to the first circuit section and the second oscillation signal is supplied to the second to fourth circuit sections, or the second oscillation signal is supplied to the first circuit section. It is a figure for demonstrating the circuit state in the case of supplying and supplying the 1st oscillation signal to the 2nd to 4th circuit part. When the first oscillation signal is supplied to the first to second circuit units and the second oscillation signal is supplied to the third to fourth circuit units, or when the second oscillation signal is supplied to the first to second circuit units. It is a figure for demonstrating the circuit state at the time of supplying to the 2nd circuit part, and supplying the 1st oscillation signal to 3rd to 4th circuit part. It is a figure which shows the modification of the semiconductor device which concerns on 2nd Embodiment, and is the figure which corresponds to FIG. It is a figure which shows another modification of the semiconductor device which concerns on 2nd Embodiment, and is the figure which corresponds to FIG.

Hereinafter, the semiconductor device according to the embodiment will be described with reference to the drawings. In the following description, components having substantially the same function and configuration are designated by the same reference numerals, and duplicate explanations will be given only when necessary.

[First Embodiment]
The semiconductor device according to the first embodiment is provided with a plurality of circuit units having different power supply systems, and each circuit unit has a buffer that outputs an oscillation signal to adjacent circuit units and an oscillation signal is input from the adjacent circuit units. By providing buffers and operating these buffers in the power supply system of each circuit unit, crosstalk between different oscillation signals is suppressed. More details will be described below.

FIG. 1 is a layout diagram of a power supply system in the semiconductor device 1 according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment has a plurality of power supply systems. Specifically, power is supplied from the power supply circuits 20 to 26 that receive power from the power supply 10, the first oscillation signal generation circuit 30 that receives power from the power supply circuit 20, and the power supply circuits 21 to 24, respectively. The first to fourth circuit units 40 to 43 to be supplied, the second oscillation signal generation circuit 31 to receive the power supply from the power supply circuit 25, and the control circuit 50 to receive the power supply from the power supply circuit 26 are provided. It is composed of.

The power supply 10 is a power supply source provided outside the semiconductor device 1, and is composed of, for example, a primary battery such as an alkaline manganese dry battery, a secondary battery such as a lithium ion battery, a DC-converted household power supply, and the like. ..

The power supply circuits 20 to 26 stabilize the electric power supplied from the power supply 10 and perform voltage conversion or the like as necessary, and the first and second oscillation signal generation circuits 30, 31, 1st to 4th. A power supply system for supplying to the circuit units 40 to 43 and the control circuit 50 is formed. Further, the power supply circuits 20 to 26 have a role of blocking the influence of signals generated in the circuits provided in different power supply systems so as not to affect each other. For example, even if the voltage of the power supply system of the power supply circuit 21 fluctuates due to the operation of the first circuit unit 40, the voltage of the power supply system of another power supply circuit is not affected. Has been done.

The first and second oscillation signal generation circuits 30 and 31 generate oscillation signals used in the first to fourth circuit units 40 to 43. Specifically, the first oscillation signal generation circuit 30 generates the first oscillation signal of the first frequency and supplies the first oscillation signal to the first to fourth circuit units 40 to 43. The second oscillation signal generation circuit 31 generates a second oscillation signal having a second frequency different from that of the first frequency, and supplies the second oscillation signal to the first to fourth circuit units 40 to 43.

The control circuit 50 controls the overall control of various operations performed in the semiconductor device 1. In the present embodiment, in particular, control signals for controlling the first and second oscillation signal generation circuits 30 and 31 are generated, and the first to fourth circuit units 40 to 43 are controlled. To generate a control signal for.

When the semiconductor device 1 is used for communication, it is generally practiced to provide a plurality of power supply systems in this way to reduce signal interference between different systems. The number of power supply systems varies depending on the specifications of the semiconductor device 1, the communication standard, and the like.

FIG. 2 is a circuit diagram and a block diagram for explaining a part of the circuit configuration in the semiconductor device 1 according to the present embodiment.

As shown in FIG. 2, the first oscillation signal generation circuit 30 generates the first oscillation signal of the first frequency and outputs it to the first circuit unit 40. In the present embodiment, for example, the first frequency is 2 GHz, and the 2 GHz oscillation signal is input to the first circuit unit 40.

On the other hand, the second oscillation signal generation circuit 31 generates the second oscillation signal of the second frequency and outputs it to the fourth circuit unit 43. In the present embodiment, for example, the second frequency is 5 GHz, and the 5 GHz oscillation signal is input to the fourth circuit unit 43. Note that 2 GHz and 5 GHz are merely examples of the first frequency and the second frequency. For example, the first frequency is 5.50 GHz and the second frequency is 5.52 GHz. The case where the first frequency of the oscillating signal and the second frequency of the second oscillating signal are closer to each other is also within the assumed range in this embodiment.

The first circuit unit 40 includes an IQ signal generator 60, a transmitter 70, and a receiver 80. The IQ signal generator 60 is a circuit that generates an I signal which is an in-phase phase component and a Q signal which is an orthogonal phase component used for modulation and demodulation.

The transmitter 70 is a circuit that uses the I signal and the Q signal generated by the IQ signal generator 60 to quadraturely modulate the transmission signal to generate a transmission wave. The generated transmitted wave is output from an antenna or the like (not shown).

The receiver 80 is a circuit that generates a received signal by orthogonally demodulating the received wave received through the antenna or the like using the I signal and the Q signal generated by the IQ signal generator 60. The generated received signal is used in various processes in the semiconductor device 1.

The IQ signal generator 60, the transmitter 70, and the receiver 80 are examples of the first processing unit of the first circuit unit 40 in the present embodiment, and operate by the electric power supplied from the power supply system of the power supply circuit 21. To do. Further, the first circuit unit 40 may include a circuit for performing other processing as the first processing unit in addition to the IQ signal generator 60, the transmitter 70, and the receiver 80.

Similar to the first circuit unit 40, the second circuit unit 41 includes an IQ signal generator 61, a transmitter 71, and a receiver 81 as a second processing unit, and the third circuit unit 42 The IQ signal generator 62, the transmitter 72, and the receiver 82 are provided as the third processing unit, and the fourth circuit unit 43 includes the IQ signal generator 63, the transmitter 73, and the receiver as the fourth processing unit. It is equipped with 83.

Further, in addition to the IQ signal generator 60, the transmitter 70, and the receiver 80, the first circuit unit 40 includes a capacitor 90a, a buffer 90b, a capacitor 90c, a buffer 90d, a capacitor 90e, and a buffer. It includes 90f, a capacitor 90g, a capacitor 90h, and a buffer 90i.

The output of the first oscillation signal in the first oscillation signal generation circuit 30 is connected to the buffer 90b via the capacitor 90a. Therefore, the first oscillation signal of the first frequency is input to the buffer 90b from the first oscillation signal generation circuit 30. Here, in the present embodiment, "input" means a case where a signal is indirectly input via another element or the like, and a case where a signal is directly input without passing through another element or the like. It is used in the sense of including both of.

The output of the buffer 90b is connected to the input of the buffer 90d via the capacitor 90c, and is connected to the input of the buffer 90i via the capacitor 90h. Further, the output of the buffer 90f is also connected to the input of the buffer 90i via the capacitor 90g. The output of the buffer 90i is input to the IQ signal generator 60.

Each of the buffers 90b, 90d, and 90f is a buffer that can individually control whether or not to output the input signal based on the control signal. These control signals are individually generated by the control circuit 50 shown in FIG. 1 and input to the buffers 90b, 90d, and 90f, respectively. That is, for the buffers 90b, 90d, and 90f in which the control signal of the instruction to output the input signal is input, the input oscillation signal is buffered and output. On the other hand, the input control signal is not output to the buffers 90b, 90d, 90f in which the control signal of the instruction not to output the input signal is input.

The buffer 90i does not have to be a buffer that can individually control whether or not to output the input signal based on a separate control signal. That is, a buffer that outputs the input signal non-selectively is sufficient. However, similarly to the buffers 90b, 90d, and 90f, the buffer 90i may be configured by a buffer that can individually control whether or not to output the input signal based on a separate control signal. In this case, the buffer 90i is constantly input with a control signal instructing to output the input signal during operation.

The buffers 90b, 90d, 90f, and 90i operate by the electric power supplied from the first power supply system, which is the power supply system of the power supply circuit 21, like the IQ signal generator 60, the transmitter 70, and the receiver 80. ..

In addition to the IQ signal generator 61, the transmitter 71, and the receiver 81 described above, the second circuit unit 41 also includes a capacitor 91a, a buffer 91b, a capacitor 91c, a buffer 91d, a capacitor 91e, and a buffer 91f. , A capacitor 91g, a capacitor 91h, a buffer 91i, a capacitor 91j, and a buffer 91k.

The capacitor 91a, the buffer 91b, the capacitor 91c, the buffer 91d, the capacitor 91e, the buffer 91f, the capacitor 91g, the capacitor 91h, and the buffer 91i in the second circuit unit 41 are the capacitors 90a and the buffer 90b in the first circuit unit 40 described above. The capacitors 90c, the buffer 90d, the capacitor 90e, the buffer 90f, the capacitor 90g, the capacitor 90h, and the capacitor 90i are supported, respectively.

Further, the output of the buffer 91f is connected to the input of the buffer 91k via the capacitor 91j in addition to being connected to the input of the buffer 91i via the capacitor 91g. Like the buffers 91b, 91d, and 91f, the buffer 91k is a buffer that can individually control whether or not to output the input signal based on the control signal.

The output of the buffer 90d of the first circuit unit 40, the input of the buffer 90f via the capacitor 90e of the first circuit unit 40, the input of the buffer 91b via the capacitor 91a of the second circuit unit 41, and the first It is commonly connected to the output of the buffer 91k of the circuit unit 41 of 2. That is, the transmission line between the buffer 90d and the buffer 91b and the transmission line between the buffer 91k and the buffer 90f are shared into one line. Here, when the oscillation signal exchanged between the first circuit unit 40 and the second circuit unit 41 is a single-phase signal, there is only one physical signal wiring in one transmission line. , When the oscillation signal exchanged between the first circuit unit 40 and the second circuit unit 41 is a differential signal, there are two physical signal wirings in one transmission line.

The buffers 91b, 91d, 91f, 91k, and 91i are based on the power supplied from the second power supply system, which is the power supply system of the power supply circuit 22, like the IQ signal generator 61, the transmitter 71, and the receiver 81. Operate.

The third circuit unit 42 has the same configuration as the second circuit unit 41, and in addition to the IQ signal generator 62, the transmitter 72, and the receiver 82 described above, the capacitor 92a, the buffer 92b, and the capacitor 92c The buffer 92d, the capacitor 92e, the capacitor 92f, the capacitor 92g, the capacitor 92h, the capacitor 92i, the capacitor 92j, and the buffer 92k are provided.

The capacitor 92a, the buffer 92b, the capacitor 92c, the buffer 92d, the capacitor 92e, the buffer 92f, the capacitor 92g, the capacitor 92h, the buffer 92i, the capacitor 92j, and the buffer 92k in the third circuit unit 42 are in the second circuit unit 41 described above. It corresponds to the capacitor 91a, the buffer 91b, the capacitor 91c, the buffer 91d, the capacitor 91e, the capacitor 91f, the capacitor 91g, the capacitor 91h, the capacitor 91i, the capacitor 91j, and the buffer 91k, respectively.

Further, the output of the buffer 91d of the second circuit unit 41, the input of the buffer 91f via the capacitor 91e of the second circuit unit 41, and the input of the buffer 92b via the capacitor 92a of the third circuit unit 42. , The output of the buffer 92k of the third circuit unit 42 is commonly connected. That is, the transmission line between the buffer 91d and the buffer 92b and the transmission line between the buffer 92k and the buffer 91f are standardized and become one.

The buffers 92b, 92d, 92f, 92k, and 92i are based on the power supplied from the third power supply system, which is the power supply system of the power supply circuit 23, like the IQ signal generator 62, the transmitter 72, and the receiver 82. Operate.

In addition to the IQ signal generator 63, the transmitter 73, and the receiver 83 described above, the fourth circuit unit 43 includes a capacitor 93a, a buffer 93b, a capacitor 93e, a buffer 93f, a capacitor 93g, and a capacitor 93h. , The buffer 93i, the capacitor 93j, and the buffer 93k are provided.

The capacitor 93a, the buffer 93b, the capacitor 93e, the buffer 93f, the capacitor 93g, the capacitor 93h, the buffer 93i, the capacitor 93j, and the buffer 93k in the fourth circuit unit 43 are the capacitors 92a and the buffer 92b in the third circuit unit 42 described above. The capacitors 92e, the buffer 92f, the capacitor 92g, the capacitor 92h, the buffer 92i, the capacitor 92j, and the buffer 92k are supported, respectively.

However, the output of the second oscillation signal in the second oscillation signal generation circuit 31 is connected to the input of the buffer 93f via the capacitor 93e. Therefore, the second oscillation signal of the second frequency is input to the buffer 93f from the second oscillation signal generation circuit 31.

Further, the output of the buffer 92d of the third circuit unit 42, the input of the buffer 92f via the capacitor 92e of the third circuit unit 42, and the input of the buffer 93b via the capacitor 93a of the fourth circuit unit 43. , The output of the buffer 93k of the fourth circuit unit 43 is commonly connected. That is, the transmission line between the buffer 92d and the buffer 93b and the transmission line between the buffer 93k and the buffer 92f are shared into one line.

The buffers 93b, 93f, 93k, and 93i operate by the power supplied from the fourth power supply system, which is the power supply system of the power supply circuit 24, like the IQ signal generator 63, the transmitter 73, and the receiver 83. ..

A capacitor is connected to the input of each buffer, and this is provided to cut off the DC component of the signal by the capacitor. That is, the DC components of the first oscillation signal and the second oscillation signal are cut off by each capacitor.

The above is the circuit configuration of the semiconductor device 1 according to the present embodiment. Next, the operation of the semiconductor device 1 will be described.

FIG. 3 is a diagram for explaining a circuit state when the second oscillation signal generated by the second oscillation signal generation circuit 31 is supplied to the first to fourth circuit units 40 to 43. In the present embodiment, this state is referred to as the first mode.

As shown in FIG. 3, in the first mode, control signals indicating that the input signal is not output are input to the buffers 90b, 90d, 91b, 91d, 92b, 92d, 93d, and the buffer 90f , 91k, 91f, 92k, 92f, 93k, 93f are input with control signals instructing to output the input signal.

Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is cut off by the buffer 90b and is not supplied to any of the first to fourth circuit units 40 to 43. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 passes through the buffers 93f, 93k, 92f, 92k, 91f, 91k, and 90f in order, and the first to fourth circuit units 40 It is supplied to IQ signal generators 60 to 63 of ~ 43.

In FIG. 4, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first circuit unit 40, and the second oscillation signal generated by the second oscillation signal generation circuit 31 is supplied. Is a diagram for explaining a circuit state when supplying the second to fourth circuit units 41 to 43. In the present embodiment, this state is referred to as a second mode.

As shown in FIG. 4, in the second mode, control signals indicating that the input signals are not output are input to the buffers 90d, 90f, 91b, 91d, 91k, 92b, 92d, 93d. Control signals for instructing to output the input signal are input to the buffers 90b, 91f, 92k, 92f, 93k, and 93f.

Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generator 60 of the first circuit unit 40, but is cut off by the buffer 90d. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 passes through the buffers 93f, 93k, 92f, 92k, and 91f in order, and the IQ of the second to fourth circuit units 41 to 43 It is supplied to the signal generators 61 to 63, but is cut off by the buffer 91k.

At this time, the buffers 90d, 90f, 91b, and 91k in the area A1 are all in an inactive state in which the input signal is not output. That is, the first circuit unit 40 and the second circuit unit 41 are separated by two buffers, buffer 90d and buffer 91b, which have different power supply systems, and buffer 90f and buffer 91k, which have different power supply systems. It will be separated by one buffer. Therefore, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk is suppressed.

In FIG. 5, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first to second circuit units 40 to 41, and is generated by the second oscillation signal generation circuit 31. It is a figure for demonstrating the circuit state at the time of supplying the 2nd oscillation signal to the 3rd to 4th circuit parts 42 to 43. In the present embodiment, this state is referred to as a third mode.

As shown in FIG. 5, in the third mode, control signals indicating that the input signals are not output are input to the buffers 90f, 91d, 91f, 91k, 92b, 92d, 92k, 93b. Control signals for instructing to output the input signal are input to the buffers 90b, 90d, 91b, 92f, 93k, and 93f.

Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generators 60 to 61 of the first and second circuit units 40 to 41, but in the buffer 91d. It is blocked. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 passes through the buffers 93f, 93k, and 92f in order, and the IQ signal generators 62 of the third to fourth circuit units 42 to 43 It is supplied to ~ 63, but is cut off by the buffer 92k.

At this time, the buffers 91d, 91f, 92b, and 92k in the area A2 are all in an inactive state in which the input signal is not output. That is, the second circuit unit 41 and the third circuit unit 42 are separated by two buffers, buffer 91d and buffer 92b, which have different power supply systems, and buffer 91f and buffer 92k, which have different power supply systems. It will be separated by one buffer. Therefore, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk is suppressed.

In FIG. 6, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first to third circuit units 40 to 42, and is generated by the second oscillation signal generation circuit 31. It is a figure for demonstrating the circuit state at the time of supplying the 2nd oscillation signal to the 4th circuit part 43. In the present embodiment, this state is referred to as a fourth mode.

As shown in FIG. 6, in the fourth mode, control signals indicating that the input signals are not output are input to the buffers 90f, 91f, 91k, 92d, 92f, 92k, 93b, and 93k. Control signals for instructing to output the input signal are input to the buffers 90b, 90d, 91b, 91d, 92b, and 93f.

Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generators 60 to 62 of the first to third circuit units 40 to 42, but in the buffer 92d. It is blocked. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 is supplied to the IQ signal generator 63 of the fourth circuit unit 43 via the buffer 93f, but is cut off by the buffer 93k. Will be done.

At this time, the buffers 92d, 92f, 93b, and 93k in the area A3 are all in an inactive state in which the input signal is not output. That is, the third circuit unit 42 and the fourth circuit unit 43 are separated by two buffers, buffer 92d and buffer 93b, which have different power supply systems, and buffer 92f and buffer 93k, which have different power supply systems. It will be separated by one buffer. Therefore, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk is suppressed.

FIG. 7 is a diagram for explaining a circuit state when the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first to fourth circuit units 40 to 43. In the present embodiment, this state is referred to as a fifth mode.

As shown in FIG. 7, in the fifth mode, control signals indicating that the input signal is not output are input to the buffers 90f, 91f, 91k, 92f, 92k, 93f, and 93k, and the buffer 90b , 90d, 91b, 91d, 92b, 92d, 93b are input with control signals instructing to output the input signal.

Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generators 60 to 63 of the first to fourth circuit units 40 to 43. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 is cut off by the buffer 93f and is not supplied to any of the first to fourth circuit units 40 to 43.

Next, a circuit configuration of a buffer capable of individually controlling whether or not to output an input signal will be described with reference to FIG. FIG. 8 is a diagram showing an example of a specific circuit configuration of a buffer capable of individually controlling whether or not to output an input signal based on a control signal.

As shown in FIG. 8, the buffer includes P-channel MOS transistors P1, P2, P3, N-channel MOS transistors N1, N2, N3, a resistor R1, and an inverter circuit IN1.

The control terminal of the P-channel MOS transistor P1, the control terminal of the N-channel MOS transistor N1, and one end of the resistor R1 are each connected to an input terminal, and an input signal IN is input from this input terminal. The first terminal of the P-channel MOS transistor P1 is connected to the first power supply Vdd, and the first terminal of the N-channel MOS transistor N1 is connected to the second power supply Vcc.

Further, P-channel MOS transistors P2 and P3 and N-channel MOS transistors N2 and N3 are connected in series between the first power supply Vdd and the second power supply Vcc. The control terminal of the P-channel MOS transistor P3 and the control terminal of the N-channel MOS transistor N2 are commonly connected to the second terminal of the P-channel MOS transistor P1, the second terminal of the N-channel MOS transistor N1, and the other end of the resistor R1. ing.

The control signal Enable generated by the control circuit 50 is input to the control terminal of the N-channel MOS transistor N3. Further, the control signal Enable is also input to the inverter circuit IN1, inverted, and then input to the control terminal of the P-channel MOS transistor P2.

Therefore, when a high-level control signal Enable is input, the P-channel MOS transistor P2 and the N-channel MOS transistor N3 are turned on, and this buffer buffers the input signal IN. It is a circuit that outputs as an output signal OUT. On the other hand, when the low-level control signal Enable is input, the P-channel MOS transistor P2 and the N-channel MOS transistor N3 are turned off, and this buffer becomes a circuit that does not output the input signal. That is, the high-level control signal becomes the control signal for the instruction to output the input signal, and the low-level control signal becomes the control signal for the instruction not to output the input signal.

In the present embodiment, the input signal IN and the output signal OUT are either the first oscillation signal or the second oscillation signal. Further, the first power supply Vdd and the second power supply Vcc are supplied from the power supply circuits 20 to 26 of FIG. More specifically, the first power supply Vdd and the second power supply Vcc are supplied from the power supply circuit 21 to the buffers 90b, 90d, 90f in the first circuit unit 40, and the buffer 91b in the second circuit unit 41. , 91d, 91f, 91k are supplied with the first power supply Vdd and the second power supply Vcc from the power supply circuit 22, and the buffers 92b, 92d, 92f, 92k in the third circuit unit 42 are supplied from the power supply circuit 23 to the second. The first power supply Vdd and the second power supply Vcc are supplied, and the first power supply Vdd and the second power supply Vcc are supplied from the power supply circuit 24 to the buffers 93b, 93f, and 93k in the fourth circuit unit 43.

As described above, according to the semiconductor device 1 according to the present embodiment, the buffer for buffering the first oscillation signal or the second oscillation signal is supplied to each of the first to fourth circuit units 40 to 43. It was decided to operate with the power generated. Further, it was decided to separate each of the first to fourth circuit units 40 to 43 by two inactive buffers. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk can be suppressed.

Further, since it was decided to exchange the first oscillation signal and the second oscillation signal between each of the first to fourth circuit units 40 to 43 using one transmission line. The layout area can be reduced. In particular, when the frequency of the first oscillation signal and the frequency of the second oscillation signal are close to each other, it is necessary to lay out the transmission lines of the two signals as far apart as possible, which increases the layout area. However, the layout area can be reduced by sharing the transmission lines as one transmission line as in the present embodiment.

FIG. 9 is a block circuit diagram for functionally explaining the semiconductor device 1 according to the present embodiment. As shown in FIG. 9, in the semiconductor device 1, the first oscillating signal or the second oscillating signal arriving at the first to fourth circuit units 40 to 43 by an alternative path does not intersect. , IQ signal generators 60 to 63 can be regarded as having a function of being supplied. In order to realize such a function, it can be said that the first to fourth circuit units 40 to 43 include selection circuits SL1, SL2, SL3 and buffers BF1 and BF2, respectively.

The selection circuits SL1, SL2, and SL3 are circuits that output one of the input first oscillation signal and the second oscillation signal, and which oscillation signal is output is input from the control circuit 50. It can be switched based on the control signal. The buffers BF1 and BF2 are circuits that buffer and output the input first oscillation signal or second oscillation signal, respectively.

The first oscillation signal generated by the first oscillation signal generation circuit 30 and the second oscillation signal generated by the second oscillation signal generation circuit 31 are selected by switching control of the selection circuits SL1 and SL2. The uniformly formed paths reach the first to fourth circuit units 40 to 43, and are supplied to the IQ signal generators 60 to 63 without intersecting by the switching control of the selection circuit SL3. That is, by controlling the selection circuits SL1, SL2, and SL3 by the control signal, the first oscillation signal and the second oscillation signal are supplied to the IQ signal generators 60 to 63 without intersecting.

As shown in FIG. 10, the semiconductor device 1 according to the present embodiment can have two transmission lines between each of the first to fourth circuit units 40 to 43. That is, the transmission line of the first oscillation signal and the transmission line of the second oscillation signal may be provided separately. In this case, the layout area of the transmission line is increased by that amount, but the first oscillation signal and the second oscillation signal are supplied to the circuit units of any combination of the first to fourth circuit units 40 to 43. You will be able to do it. For example, the first oscillation signal generation circuit 30 supplies the first oscillation signal to the first circuit unit 40 and the third circuit unit 42, and the second circuit unit 41 and the fourth circuit unit 43 receive the second oscillation signal. The second oscillation signal can be supplied from the oscillation signal generation circuit 31 of the above.

Further, as shown in FIG. 11, in the semiconductor device 1 according to the present embodiment, the capacitor 90a and the buffer 90b are provided in the vicinity of the output of the first oscillation signal generation circuit 30, and the same power supply as that of the first oscillation signal generation circuit 30. The buffer 90b operates based on the electric power obtained from the power supply system of the circuit 20, and the capacitor 93e and the buffer 93f are provided near the output of the second oscillation signal generation circuit 31, which is the same as the second oscillation signal generation circuit 31. The buffer 93f may be operated based on the electric power obtained from the power supply system of the power supply circuit 25.

[Second Embodiment]
The second embodiment is a modification of the first embodiment described above, in which the first oscillation signal generation circuit 30 generates the first oscillation signal and the second oscillation signal, and the first and second circuit units. It is configured so that it can be supplied to 40 to 41, and the second oscillation signal generation circuit 31 also generates the first oscillation signal and the second oscillation signal and supplies them to the first to fourth circuit units 40 to 43. The layout area is reduced by configuring it so that it can be used. Hereinafter, parts different from the above-described first embodiment will be described.

FIG. 12 is a circuit diagram and a block diagram for explaining a part of the circuit configuration in the semiconductor device 1 according to the present embodiment, and is a diagram corresponding to FIG. 2 of the above-described first embodiment.

As shown in FIG. 12, the first oscillation signal generation circuit 30 in the present embodiment generates both the first oscillation signal of the first frequency and the second oscillation signal of the second frequency. Output to the selection circuit MUX1. Similar to the first embodiment described above, for example, the first frequency is 2 GHz and the second frequency is 5 GHz.

A control signal for selection is input to the selection circuit MUX1 from the control circuit 50 shown in FIG. 1, and based on this control signal, the selection circuit MUX1 has a first oscillation signal and a second oscillation signal. Either, or the selection circuit MUX1 does not output either the input first oscillation signal or the second oscillation signal. The selection circuit MUX1 operates by the electric power supplied from the power supply system of the power supply circuit 20, similarly to the first oscillation signal generation circuit 30.

The second oscillation signal generation circuit 31 also generates both the first oscillation signal of the first frequency and the second oscillation signal of the second frequency, and outputs them to the selection circuit MUX2. Similar to the first oscillation signal generation circuit 30, for example, the first frequency is 2 GHz and the second frequency is 5 GHz. As in the first embodiment described above, 2 GHz and 5 GHz are merely examples of the first frequency and the second frequency. For example, the first frequency is 5.50 GHz and the second frequency is Even when the first frequency of the first oscillation signal and the second frequency of the second oscillation signal are closer to each other, such as 5.52 GHz, it is within the assumed range in this embodiment.

A control signal for selection is also input to the selection circuit MUX2 from the control circuit 50 shown in FIG. 1, and based on this control signal, the selection circuit MUX2 has a second oscillation signal and a second oscillation signal. Output either. The selection circuit MUX2 operates by the electric power supplied from the power supply circuit 25, similarly to the second oscillation signal generation circuit 31.

The first oscillation signal or the second oscillation signal output from the selection circuit MUX1 is supplied to the first circuit unit 40. Specifically, it is input to the buffer 90d via the capacitor 90c, and is input to the buffer 90i via the capacitor 90h.

The first circuit unit 40 includes a first IQ signal generator 100a, a second IQ signal generator 100b, a first transmitter / receiver 110a, and a second transmitter / receiver 110b, and includes a buffer 90i. The first oscillation signal or the second oscillation signal is input from. That is, when the first oscillation signal is input from the buffer 90i, the first IQ signal generator 100a operates, and transmission / reception is performed using the first transmitter / receiver 110a. On the other hand, when the second oscillation signal is input from the buffer 90i, the second IQ signal generator 100b operates, and transmission / reception is performed using the second transmitter / receiver 110b.

In FIG. 12, the "transmitter" and the "receiver" are merged and represented as a "transmitter" in one block, but the "transmitter" and the "receiver" are represented as separate blocks. It is functionally the same as the first embodiment expressed.

Similarly, the first oscillation signal or the second oscillation signal is output from the buffers 91i, 92i, and 93i of the second to fourth circuit units 41 to 43, respectively, and the first oscillation signal is output. If so, the first IQ signal generators 101a, 102a, 103a are operating, the first transmitter / receiver 111a, 112a, 113a are used for transmission / reception, and the second oscillation signal is output. The second IQ signal generators 101b, 102b, 103b operate, and the second transmitter / receiver 111b, 112b, 113b is used for transmission / reception.

However, in the first circuit unit 40 and the second circuit unit 41, the first oscillation signal or the second oscillation signal is transmitted from both the first oscillation signal generation circuit 30 and the second oscillation signal generation circuit 31. Can be supplied, whereas the first oscillation signal or the second oscillation signal can be supplied from the second oscillation signal generation circuit 31 to the third circuit unit 42 and the fourth circuit unit 43. Neither the first oscillation signal nor the second oscillation signal can be supplied from the first oscillation signal generation circuit 30.

Further, unlike the first embodiment described above, two transmission lines are provided between the first circuit unit 40 and the second circuit unit 41. That is, one dedicated transmission line is provided between the buffer 90d and the buffer 91b, and one dedicated transmission line is provided between the buffer 90f and the buffer 91k.

Further, since the buffer 93k provided in the fourth circuit unit 43 outputs the input first oscillation signal or the second oscillation signal non-selectively, it is input based on a separate control signal. It is not a buffer that can control whether or not to output a signal. However, the buffer 93k can be configured by a buffer capable of controlling whether or not to output the input signal based on a separate control signal, as in the first embodiment described above. In this case, the control signal of the instruction to output the input signal is constantly input to the buffer 93k during the operation.

The above is the circuit configuration of the semiconductor device 1 according to the present embodiment. Next, the operation of the semiconductor device 1 will be described.

<1st oscillation signal x 4 or 2nd oscillation signal x 4>
FIG. 13 shows a case where the first oscillation signal is supplied to the first to fourth circuit units 40 to 43, or a case where the second oscillation signal is supplied to the first to fourth circuit units 40 to 43. , It is a figure for demonstrating the circuit state. In the present embodiment, this state is referred to as the first mode.

As shown in FIG. 13, in the first mode, the control signal of the instruction not to output the input signal is input to the buffers 90d and 91b, and is input to the buffers 90f, 91k, 91f and 92k. The control signal of the instruction to output the signal is input. Further, a control signal that does not output either the first oscillation signal or the second oscillation signal is input to the selection circuit MUX1.

Therefore, when a control signal for selecting the first oscillation signal is input to the selection circuit MUX2, the first to fourth circuit units pass through the buffers 93k, 92k, 91f, 91k, and 90f in order. The first oscillation signal is supplied to 40 to 43.

On the other hand, when the control signal for selecting the second oscillation signal is input to the selection circuit MUX2, the first to fourth circuit units 40 pass through the buffers 93k, 92k, 91f, 91k, and 90f in order. A second oscillation signal is supplied to ~ 43.

<1st oscillation signal x 1 + 2nd oscillation signal x 3 or 1st oscillation signal x 3 + 2nd oscillation signal x 1>
FIG. 14 shows a case where the first oscillation signal is supplied to the first circuit unit 40 and the second oscillation signal is supplied to the second to fourth circuit units 41 to 43, or the second oscillation. It is a figure for demonstrating the circuit state at the time of supplying the signal to the 1st circuit part 40, and supplying the 1st oscillation signal to the 2nd to 4th circuit parts 41-43. In the present embodiment, this state is referred to as a second mode.

As shown in FIG. 14, in the second mode, control signals indicating that the input signal is not output are input to the buffers 90d, 90f, 91b, 91k, and are input to the buffers 91f, 92k. The control signal of the instruction to output the signal is input.

Therefore, when the control signal for selecting the first oscillation signal is input to the selection circuit MUX1 and the control signal for selecting the second oscillation signal is input to the selection circuit MUX2, the selection circuit MUX1 is used. , The first oscillation signal is supplied to the first circuit unit 40, and the second to the second to fourth circuit units 41 to 43 pass through the buffers 93k, 92k, and 91f in order from the selection circuit MUX2. An oscillation signal is supplied.

On the other hand, when the control signal for selecting the second oscillation signal is input to the selection circuit MUX1 and the control signal for selecting the first oscillation signal is input to the selection circuit MUX2, the selection circuit MUX1 can be used. The second oscillation signal is supplied to the first circuit unit 40, and the first oscillation is sent from the selection circuit MUX2 to the second to fourth circuit units 41 to 43 via the buffers 93k, 92k, and 91f in order. The signal is supplied.

At this time, the buffers 90d, 90f, 91b, and 91k in the area A4 are all in an inactive state in which the input signal is not output. That is, the first circuit unit 40 and the second circuit unit 41 are separated by two buffers, buffer 90d and buffer 91b, which have different power supply systems, and buffer 90f and buffer 91k, which have different power supply systems. It will be separated by one buffer. Therefore, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk is suppressed.

<1st oscillation signal x 2 + 2nd oscillation signal x 2>
FIG. 15 shows a case where the first oscillation signal is supplied to the first to second circuit units 40 to 41 and the second oscillation signal is supplied to the third to fourth circuit units 42 to 43, or , The circuit state in the case where the second oscillation signal is supplied to the first to second circuit units 40 to 41 and the first oscillation signal is supplied to the third to fourth circuit units 42 to 43 will be described. It is a figure for. In the present embodiment, this state is referred to as a third mode.

As shown in FIG. 15, in the third mode, control signals indicating that the input signal is not output are input to the buffers 90f, 91f, 91k, and 92k, and are input to the buffers 90d and 91b. The control signal of the instruction to output the signal is input.

Therefore, when the control signal for selecting the first oscillation signal is input to the selection circuit MUX1 and the control signal for selecting the second oscillation signal is input to the selection circuit MUX2, the selection circuit MUX1 is used. , The first oscillation signal is supplied to the first to second circuit units 40 to 41, and the second oscillation signal is supplied from the selection circuit MUX2 to the third to fourth circuit units 42 to 43 via the buffer 93k. An oscillation signal is supplied.

Further, although the numbers are the same as a result, the control signal for selecting the second oscillation signal is input to the selection circuit MUX1, and the control signal for selecting the first oscillation signal is input to the selection circuit MUX2. In this case, the second oscillation signal is supplied from the selection circuit MUX1 to the first to second circuit units 40 to 41, and the third to fourth circuit units are supplied from the selection circuit MUX2 via the buffer 93k. The first oscillation signal is supplied to 42 to 43.

At this time, the buffers 91f and 92k in the area A5 are both in an inactive state in which the input signal is not output. That is, the second circuit unit 41 and the third circuit unit 42 are separated by two buffers, a buffer 91f and a buffer 92k, which have different power supply systems. Therefore, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk is suppressed.

As described above, according to the semiconductor device 1 according to the present embodiment, the buffer for buffering the first oscillation signal or the second oscillation signal is supplied to each of the first to fourth circuit units 40 to 43. It was decided to operate with the power generated. Further, it was decided to separate each of the first to third circuit units 40 to 42 by two inactive buffers. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be ensured, and the occurrence of crosstalk can be suppressed.

Further, both the first oscillation signal generation circuit 30 and the second oscillation signal generation circuit 31 generate both the first oscillation signal and the second oscillation signal from the first oscillation signal generation circuit 30. The first oscillation signal or the second oscillation signal is selectively supplied to the first to second circuit units 40 to 41, and the first to fourth circuit units are selectively supplied from the second oscillation signal generation circuit 31. Since the first oscillation signal or the second oscillation signal is supplied to 40 to 43, the first oscillation signal can be supplied to the required number of circuit units by arbitrarily combining the active / inactive states of the buffer. Can be supplied and a second oscillation signal can be supplied. Further, the transmission path of the oscillation signal between the second circuit unit 41 and the third circuit unit 42 can be unified, and the oscillation signal between the third circuit unit 43 and the fourth circuit unit 43 can be unified. Since the number of transmission lines can be one, the layout area of the circuit can be reduced.

As shown in FIG. 16, the semiconductor device 1 according to the present embodiment has one transmission line between the first circuit unit 40 and the second circuit unit 41, as in the first embodiment. It is also possible to exchange the first oscillation signal or the second oscillation signal by connecting with. As a result, the circuit area can be further reduced.

Further, as shown in FIG. 17, instead of supplying power to the selection circuit MUX1 from the power supply system of the power supply circuit 20 which is the same as the first oscillation signal generation circuit 30, the power supply circuit 21 which is the same as the first circuit unit 40 Power may be supplied from the power supply system to the selection circuit MUX1. Similarly, instead of supplying power to the selection circuit MUX2 from the power supply system of the power supply circuit 25 which is the same as the second oscillation signal generation circuit 31, the selection circuit MUX2 is not supplied from the power supply system of the power supply circuit 24 which is the same as the fourth circuit unit 43. May be supplied with power.

Although some embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described herein can be implemented in a variety of other forms. In addition, various omissions, substitutions, and changes can be made to the forms of the apparatus and method described in the present specification without departing from the gist of the invention. The appended claims and their equivalent scope are intended to include such forms and variations contained within the scope and gist of the invention.

10 ... Power supply, 20 to 26: Power supply circuit, 30: First oscillation signal generation circuit, 31: Second oscillation signal generation circuit, 40 to 43: First to fourth circuit units, 50: Control circuit, 60 ~ 63: IQ signal generator, 70 to 73: transmitter, 80 to 83: receiver, 90a, 90c, 90e, 90g, 90h: capacitor, 90b, 90d, 90f, 90i: buffer, 91a, 91c, 91e, 91g, 91h, 91j: Capacitor, 91b, 91d, 91f, 91i, 91k: Buffer, 92a, 92c, 92e, 92g, 92h, 92j: Capacitor, 92b, 92d, 92f, 92i, 92k: Buffer, 93a, 93e, 93g, 93h, 93j: Capacitor, 93b, 93f, 93i, 93k: Buffer

Claims (3)

A first circuit unit that is a first circuit unit to which power is supplied from the first power supply system and has a first buffer, a second buffer, and a first processing unit.
A second circuit unit in which power is supplied from a second power supply system different from the first power supply system, and a second circuit unit having a third buffer.
The first oscillation signal generation circuit to which power is supplied from the first power supply system and
A second oscillation signal generation circuit to which power is supplied from the second power supply system, and
Is equipped with
The first oscillation signal generated by the first oscillation signal generation circuit is input to the first buffer.
The second oscillation signal generated by the second oscillation signal generation circuit is input to the second buffer via the third buffer.
Whether or not the first buffer outputs the input first oscillation signal to the second circuit unit, or whether the second buffer outputs the input second oscillation signal to the first circuit unit. It is possible to control whether or not to output to the processing unit of
A fourth buffer into which the first oscillation signal is input is further provided in the first circuit section, and power is supplied to the fourth buffer from the first power supply system.
Said fourth buffer, the input of the first oscillation signal, Ri controllable der whether to output to the first processing unit and said first buffer,
The second circuit unit further includes a fifth buffer and a second processing unit.
The first oscillation signal is input to the fifth buffer via the first buffer.
A semiconductor device capable of controlling whether or not the fifth buffer outputs the input first oscillation signal to the second processing unit . The transmission line between the first buffer and the fifth buffer and the transmission line between the second buffer and the third buffer are shared, according to claim 1 . Semiconductor device. A first transmission line is provided between the first buffer and the fifth buffer, and the first transmission line is provided between the second buffer and the third buffer. The semiconductor device according to claim 1 , wherein a second transmission line is separately provided.

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