JP6758470B2 - Information processing device - Google Patents

Description

The present invention relates to an information processing apparatus and an information processing system, for example, an information processing apparatus including a programmable logic represented by an FPGA (Field Programmable Gate Array), and an information processing system including the information processing apparatus.

A dynamic reconfiguring technique using a field programmable logic LSI is known in order to realize high-speed and high-performance operations. In this technology, data designed by the user in advance is expanded from the ROM to the configuration memory in the FPGA, and the FPGA is made to execute a desired operation. The data stored in the configuration memory is stored in the configuration memory while the LSI is in operation. It is a technology for dynamic rewriting.

For example, Non-Patent Document 1 discloses a technique for mounting an FPGA on each server constituting a data center. In this technology, throughput can be improved by appropriately performing dynamic reconfiguration on FPGA. Further, Non-Patent Document 2 discloses a configuration of a CMOS type Ising chip that performs processing based on an Ising model regardless of FPGA.

“A reconfigurable fabric for accelerating large-scale datacenter services,” ACM / IEEE 41st International Symposium on Computer Architecture (ISCA), 2014. “20k-spin Ising chip for combinational optimization problem with CMOS annealing,” Solid-State Circuits Conference-(ISSCC), 2015 IEEE International, Session 24.3.

It cannot be said that the currently known architecture is optimal for speeding up information processing. This is because, among the many possibilities, a better solution method devised by humans is realized by a logic LSI and an operation is executed. Since arithmetic optimization depends on the problem to be solved, it is desirable that the hardware configuration changes so as to proceed with self-optimization depending on the problem to be solved. However, it is difficult to achieve full self-optimization at this point, and it will be realistic to make changes based on the designed data.

So far, evolutionary algorithms as software such as genetic algorithms have been developed. Under these circumstances, the present inventors wondered if such a self-optimization technique could be introduced into the FPGA configuration. Changing the configuration means changing the logical connection information, which can be expected to be faster than when the evolutionary algorithm is executed programmatically on the processor. At that time, it is desirable that the configuration can be changed autonomously in consideration of the relation of the calculated data.

The present invention has been made in view of the above, and one of the objects thereof is to realize improvement of calculation efficiency in an information processing apparatus and an information processing system including programmable logic.

The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.

A brief description of typical embodiments of the inventions disclosed in the present application is as follows.

The information processing apparatus according to the present embodiment includes an FPGA fabric unit, a configuration memory, a data monitoring unit, a config control unit, and a CRAM controller. The FPGA fabric unit implements a user logic circuit, and the configuration memory holds config data that defines the circuit configuration of the user logic circuit. The data monitoring unit monitors the operating state of the user logic circuit, and the config control unit determines whether or not the config data needs to be changed based on the monitoring result. The CRAM controller changes the config data of the configuration memory based on the determination result of the config control unit.

A brief description of the effects obtained by a typical embodiment of the inventions disclosed in the present application makes it possible to improve the calculation efficiency.

It is a block diagram which shows the overall schematic structure example in the information processing system according to Example 1 of this invention. It is a block diagram which shows the structural example of the CRAM controller in FIG. It is a flow diagram which shows an example of the control flow at the time of changing the config data in the information processing apparatus of FIG. It is a sequence diagram which shows an example of the input / output signal of the information processing apparatus of FIG. 1 accompanying the flow of FIG. It is the schematic which shows the structural example of the address map of CRAM in the information processing apparatus by Example 2 of this invention. (A) and (b) are conceptual diagrams illustrating an example of a method of changing config data in the information processing apparatus according to the third embodiment of the present invention. FIG. 5 is a conceptual diagram illustrating an example of a method of changing config data in the information processing system according to the fourth embodiment of the present invention. FIG. 5 is a block diagram showing a schematic configuration example of the entire information processing system according to the fifth embodiment of the present invention. FIG. 5 is a conceptual diagram illustrating an example of a method of changing config data in the information processing apparatus according to the sixth embodiment of the present invention. FIG. 5 is a block diagram showing a schematic configuration example of a main part of the information processing system according to the seventh embodiment of the present invention. It is a circuit diagram which shows the structural example of a general LUT. It is the schematic which shows the structural example of the main part of the information processing apparatus according to Example 8 of this invention. It is a waveform diagram which shows an example of the specific operation sequence in FIG. It is a figure which shows an example of PE (Primitive Element) which is the basic unit of the 2D Ising model to map to the Ising chip. It is a figure explaining an example of EU (Execlusion Unit) which is a basic unit of operation in PE. It is a figure which shows the detailed configuration example of EU of FIG. It is a schematic diagram which shows the configuration example when PE of FIG. 15 is mapped to FPGA. It is a figure which shows the overall operation example when performing the calculation using the structure of FIG.

In the following examples, when necessary for convenience, the description will be divided into a plurality of sections or examples, but unless otherwise specified, they are not unrelated to each other, and one is a part of the other. Or, there is a relationship of all modifications, details, supplementary explanations, etc. In addition, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, the specific number is used. It is not limited, and may be more than or less than a specific number.

Furthermore, in the following examples, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. No. Similarly, when referring to the shape, positional relationship, etc. of a component, etc., it is substantially similar to or similar to the shape, etc., unless otherwise specified or when it is considered that it is not clearly the case in principle. Etc. shall be included. This also applies to the above numerical values and ranges.

Hereinafter, examples of the present invention will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the examples, the same members are in principle given the same reference numerals, and the repeated description thereof will be omitted.

<< Overview of FPGA >>

Generally, FPGA is designed using a logic description language (for example, Verilog HDL (Hardware Description Language) or VHDL), and this logic circuit is described by a method called RTL (Register Transfer Level). Generally, integration from RTL to LSI is carried out by the following procedure. That is, the logical connection information of the RTL is converted into a so-called netlist in consideration of the physical arrangement of the transistors integrated in the actual LSI, and further, the static timing analysis simulation (static timing analysis simulation) in consideration of the timing constraint of each signal line. After performing STA) and optimizing the arrangement, it is integrated into the LSI.

The procedure is almost the same for FPGA, and after designing this RTL, logic synthesis is performed, and while adjusting the signal line timing, the adjusted data is transferred to the FPGA configuration memory (hereinafter referred to as CRAM). Convert to data to be stored. This conversion is hereinafter referred to as mapping to CRAM.

More specifically, the mapping to the CRAM considers the physical arrangement of the configuration of the basic logic circuit and the wiring connection switch integrated inside the FPGA, and the transistor level connection information (net list) converted from the logical description information. It is realized by converting into a bit string (bit stream) to the CRAM of FPGA based on. By storing the bitstream in the CRAM of the FPGA, the desired operation can be realized in the target FPGA. There is a one-to-one correspondence between the netlist converted from the RTL in order to realize the desired function in the FPGA and the data string (bit stream) of the CRAM stored in the FPGA.
<< Overall configuration of information processing system >>

FIG. 1 is a block diagram showing a schematic configuration example of the entire information processing system according to the first embodiment of the present invention. The information processing system shown in FIG. 1 includes one or more information processing devices (in this case, FPGA chip FPGA_CH), an evaluation unit interface EVAL_IF, an external config storage device CTRL, and various signal lines connecting them. The various signal lines include a control signal line (SCTL), a config signal line (SCFG), and a data signal line (SDAT).

The configuration example of FIG. 1 can configure a desired information processing system only in the form of the configuration, but can be applied to, for example, a part of a processor system and used as a hardware accelerator of the processor system. is there. Note that FIG. 1 does not show the storage and network normally provided in a general information processing apparatus for information processing, and only the main parts related to the configuration change of the FPGA are shown.

The FPGA chip FPGA_CH includes a plurality of FPGA fabric units FPGA_FAB, CRAM, CRAM controller CRAMC, data monitoring unit CUNT, chip control controller CHPC, on-chip bus DBUS, and config control unit CNFGC. The CRAM holds config data for determining the circuit configuration of the user logic circuit. The FPGA fabric unit FPGA_FAB implements a user logic circuit based on the config data of the CRAM. In detail, the FPGA fabric unit FPGA_FAB includes a programmable logic unit LOG that implements a desired logic truth table by a plurality of LUTs (Lookup tables), and a switch unit SW that arbitrarily connects each LUT by a plurality of switches. Be prepared.

The CRAM controller CRAMC reads / writes config data to / from the CRAM or, in addition, the external config storage device STRG. The on-chip bus DBUS transmits the input / output signal of the FPGA fabric unit FPGA_FAB. Specifically, the on-chip bus DBUS transmits communication data between each FPGA fabric unit FPGA_FAB or between each FPGA fabric unit FPGA_FAB and a data signal line (SDAT). The data monitoring unit CUNT monitors the operating state of the user logic circuit mounted on the FPGA fabric unit FPGA_FAB, for example, by measuring the distribution of data. The chip control controller CHPC controls the operation of the entire chip.

In FIG. 1, for convenience, only the FPGA fabric unit FPGA_FAB is composed of programmable logic, but in addition to this, a part of the data monitoring unit CUNT, the config control unit CNFGC, the CRAM controller CRAMC, and the chip control controller CHPC. May also be configured with programmable logic. In addition, the part excluding the FPGA fabric part FPGA_FAB is a hardcore processor (a processor hardware is mounted in advance) or a soft-core processor (a processor configured by using programmable logic) built in the FPGA. ) May be used.

Further, in FIG. 1, for convenience, the FPGA fabric portion FPGA_FAB is described as if it were divided. This is to clearly show that each functional block mounted on the FPGA is logically divided. Of course, in practice, the FPGA fabric FPGA_FAB may be uniformly arranged inside the FPGA.

The data signal line (SDAT) is a signal line for transmitting and receiving a data signal SDAT between a plurality of FPGA chips FPGA_CH, and is realized by, for example, a high-speed serial communication line. The config signal line (SCFG) is a CRAM config signal (config data) between a plurality of FPGA chips FPGA_CH, or between each FPGA chip FPGA_CH and an external config storage device STRG composed of a non-volatile memory, a hard disk drive, or the like. ) A signal line for transmitting and receiving SCFG. The control signal line (SCTL) is a signal line that transmits a change request or change notification of config data to each FPGA chip FPGA_CH. Here, these signal lines are explicitly described separately, but it is also possible to transmit them using shared wiring by a time division multiplexing method or the like.

In the example of FIG. 1, the data monitoring unit CUNT is connected to the on-chip bus DBUS and monitors the amount of data communication on the on-chip bus DBUS by, for example, a counter circuit or the like. For example, when packet communication, I2C (Inter Integrated Circuit) communication, or the like is used in the on-chip bus DBUS, the data monitoring unit CUNT refers to the source and destination information in the data, and data communication is performed for each combination of source and destination. Measure the amount. However, the data monitoring unit CUNT is not necessarily limited to the relevant position, and may be provided, for example, inside each FPGA fabric unit FPGA_FAB (specifically, an interface unit with the on-chip bus DBUS). In this case, the data monitoring unit CUNT refers to, for example, the source information in the received data, and measures the data communication amount for each source.

Based on the monitoring result of the data monitoring unit CUNT, the config control unit CNFGC determines whether or not the config data needs to be changed while referring to the threshold table TBL. When it is determined that the change is necessary, the config control unit CNFGC issues a config data change request to the CRAM controller CRAMC. For example, statistical data of communication rate is stored in the threshold table TBL, and the config control unit CNFGC causes the communication rate based on the monitoring result or the fluctuation amount of the communication rate to exceed the threshold value based on the statistical data. , Issue a config data change request. Upon receiving the change request, the CRAM controller CRAMC rewrites the holding contents (that is, config data) of the CRAM.

FIG. 2 is a block diagram showing a configuration example of the CRAM controller in FIG. The CRAM controller CRAMC transfers data between the CRAM access controller CRAMAC that controls reading and writing of the CRAM, the address map holding unit ADRMAP that holds the address map of the CRAM, and the CRAM, and transfers data between the external config storage device STRG. It has a port PT. After changing the config data, the CRAM controller CRAMC performs a coding code check such as CRC of the config data on the code check unit CODECHK via the port PORT, and stores the calculated coded code in the RAM. By using the coding code stored in the RAM, for example, the config data of the CRAM can be periodically read, and error detection / correction can be performed.

Here, in the method of the first embodiment, as described above, the config control unit CNFGC issues a config data change request based on the monitoring result of the data monitoring unit CUNT, and the CRAM controller CRAMC responds to the config data. To change. Upon receiving the config data change request, the CRAM access controller CRAMAC refers to the address map holding unit ADRMAP and reads data to a predetermined CRAM address via the command address signal CMD.

The config data (RD) read from the CRAM in response to this is input to the config update unit CNFG_MDFY via the port PORT. The config update unit CNFG_MDFY changes the config data and writes the changed config data (WT) to the CRAM via the port PORT. At this time, the config data (WT) is also input to the code check unit CODECHK via the port PORT. The code check unit CODECHK generates a code for the config data (WT) and stores it in the RAM.

The config data (WT) is stored in the external config storage device STRG together with the change history, for example. Further, the CRAM controller CRAMC reads the config data from the external config storage device STRG and stores it in the CRAM as necessary, or updates the read config data with the config update unit CNFG_MDFY, and then stores it. It can also be stored in the CRAM. At that time as well, processing is performed by the code check unit CODECHK.

As described above, one of the main features of the method of the first embodiment is that the data monitoring unit CUNT and the config control unit CNFGC monitor and determine the operating state of each FPGA fabric unit FPGA_FAB, and based on the determination result. CRAM controller The point is that the CRAMC updates the config data of the CRAM. The operating state of each FPGA fabric unit FPGA_FAB is, for example, as described above, the amount of data communication between each FPGA fabric unit FPGA_FAB, the amount of data processing for each FPGA fabric unit FPGA_FAB, and the like. The amount of data processed for each FPGA fabric unit FPGA_FAB is usually considered to be proportional to the amount of data input / output by each FPGA fabric unit, and can be obtained from, for example, the amount of data communication between each FPGA fabric unit.

Further, another main feature of the method of the first embodiment is that the config data read from the CRAM or the external config storage device STRG is changed and the config data is changed to the CRAM, as in the config update unit CNFG_MDFY of FIG. Alternatively, it is provided with a mechanism (platform) for writing to the external config storage device CTRL. Although not particularly limited, as a specific method of changing the config data, it is possible to change some bits of the config data based on an evolutionary algorithm or the like. Such processing can be realized by appropriately leaving a history of config data in the external config storage device CTRL. Alternatively, as a specific change method, reinforcement may be performed for critical functional blocks or the like based on the monitoring result of the amount of data. An example of a specific method for changing the config data will be described later as appropriate.

Here, for example, in a general dynamic reconfigure as shown in Non-Patent Document 1, a plurality of user logic circuits (in other words, config data) are defined in advance, and the defined user logic circuits are arranged in a predetermined sequence. It's like switching sequentially along. For example, when a user logic circuit A that executes the arithmetic processing A and a user logic circuit B that executes the arithmetic processing B are provided in advance and the arithmetic processing A is switched to the arithmetic processing B based on a predetermined sequence, the user is set accordingly. The logic circuit A is reconfigured to the user logic circuit B. As described above, the general information processing apparatus (FPGA chip FPGA_CH) heteronomously changes the user logic circuit based on a predetermined procedure without making any particular determination.

On the other hand, in the method of the first embodiment, starting from a certain user logic circuit (in other words, config data), the user logic circuit is autonomously directed toward the improvement of the operating state while monitoring the operating state. It is to be optimized. That is, the information processing device (FPGA chip FPGA_CH) autonomously changes the user logic circuit based on its own judgment. Further, for example, when an evolutionary algorithm or the like is used, the method of the first embodiment is, so to speak, a circuit location in which the operating state is improved while monitoring the operating state starting from a certain user logic circuit. It is like searching for and autonomously optimizing the user logic circuit based on the search result.

In this way, the user logic implemented in the information processing device (FPGA chip FPGA_CH) is provided by providing a mechanism that can autonomously optimize the user logic circuit that executes a predetermined arithmetic processing in a form specialized for the arithmetic processing. It becomes possible to improve the calculation efficiency of the circuit. Here, the case of monitoring the amount of data between each FPGA fabric unit FPGA_FAB in the information processing device is mainly taken as an example, but similarly, the amount of data between the information processing devices is monitored in the information processing system. It is also possible to do.

For example, in FIG. 1, when a plurality of information processing devices (FPGA chip FPGA_CH) execute the same operation, it is desirable to evaluate the performance of the entire subsystem composed of the plurality of FPGA chips FPGA_CH. In this case, the evaluation unit interface EVAL_IF monitors the amount of data between each FPGA chip FPGA_CH, and determines whether or not the config data needs to be changed by using a threshold table or the like as in the config control unit CNFGC described above. Then, the evaluation unit interface EVAL_IF makes a request for changing the config data to the predetermined FPGA chip FPGA_CH via the control signal line (SCTL) based on the determination result. When determining the monitoring result, for example, by appropriately changing the parameters of the threshold table, it is possible to determine the parameters that have a large effect on the overall performance.
<< Operation of information processing device >>

FIG. 3 is a flow diagram showing an example of a control flow when changing the config data in the information processing apparatus of FIG. In FIG. 3, the information processing apparatus (FPGA chip FPGA_CH) monitors data distribution between functional blocks by using the data monitoring unit CUNT while performing predetermined arithmetic processing on each FPGA fabric unit (functional block) FPGA_FAB. Monitor the data distribution during calculation (step S101). At this time, as described above, the data monitoring unit CUNT counts, for example, the number of times data is transmitted / received to each functional block and the elapsed time.

The information processing apparatus determines whether or not it is necessary to rewrite the config data when, for example, the number of times of data transmission / reception reaches a predetermined number of times or a predetermined elapsed time is reached (step S102). Specifically, the config control unit CNFGC compares, for example, the communication rate based on the monitoring result of the data monitoring unit CUNT with the threshold value of the communication rate stored in the threshold table TBL or the threshold value of the fluctuation amount of the communication rate. Judge by things.

As a result, when rewriting is unnecessary, the information processing apparatus returns to step S101 and continues monitoring. On the other hand, when rewriting is required, the information processing apparatus proceeds to step S103 to start the CRAM config data change process. Specifically, the CRAM access controller CRAMAC and the config update unit CNFG_MDFY read the config data from the CRAM, change the data (step S103), and write the new config data to the CRAM (step S104).

Next, the CRAM controller CRAMC generates a coded code using the code check unit CODECHK and stores it in the RAM (step S105), and further performs a process of storing the new config data in the external config storage device STRG (step). S106). Such processing is repeated until the predetermined arithmetic processing is completed (step S107). Although the processes of steps S105 and S106 are sequentially performed here, these processes may be performed in parallel in the background of the process of step S104. By doing so, even higher speed can be realized.

FIG. 4 is a sequence diagram showing an example of input / output signals of the information processing apparatus of FIG. 1 according to the flow of FIG. First, at time T1, the data monitoring unit CUN asserts the CNT_S signal (here, it is controlled to the'H'level), and transmits the monitoring result of the bus monitor (DBUS) to the config control unit CNFGC. In response to this, the config control unit CNFGC determines whether or not the config data needs to be changed, and if it needs to be changed, asserts the RCONF_S signal at time T2.

The CRAM controller CRAMC receives the assertion of the RCONF_S signal and asserts the CCS_S signal at time T3. In response to this, the chip control controller CHPC controls the FPGA fabric unit FPGA_FAB accompanying the reconfiguration. Specifically, the chip control controller CHPC transmits the FFS_S signal to the FPGA fabric unit FPGA_FAB.

Here, the FFS_S signal is composed of a reset signal (RESB_S signal), a logical operation execution signal (EXE_S signal), and a state hold signal (HOLD_S signal). When the EXE_S signal is negated at time T4, the user logic circuit mounted on the FPGA fabric unit FPGA_FAB interrupts the arithmetic processing. Then, at time T5, when the HOLD_S signal is asserted, the FPGA fabric unit FPGA_FAB holds the data communication via the on-chip bus DBUS.

Next, with the signal transmission / reception via the on-chip bus DBUS stopped, the chip control controller CHPC issues a reconfigurable startable signal (CCSA_S signal) at time T7, and in response to this, the CRAM controller CRAMC receives the signal. At time T8, the reconfig signal (CRAMC_S signal) is asserted (that is, the config data of the CRAM is changed). Further, at time T8, the user logic circuit in the FPGA fabric unit FPGA_FAB is reconstructed in response to the change in the config data (CRAMD_S).

Then, at time T9, when the configuration of the CRAM (in other words, FPGA fabric unit FPGA_FAB) is completed, the CRAMC_S signal is negated, and at time T10, the reconfig signal (RCONF_S signal) is negated. Subsequently, the state hold signal (HOLD_S signal) is negated at time T11, the reset signal (RESB_S signal) is asserted at time T12, and then the logical operation execution signal (EXE_S signal) is asserted at time T13. As a result, the reconstructed user logic circuit resumes the operation. In the on-chip bus DBUS, data communication is interrupted here from time T1 to time T13 and resumed at time T13.

Here, for the sake of simplicity, the sequence of configuration execution for one FPGA fabric part (functional block) FPGA_FAB has been described. However, a plurality of functional blocks are mounted on the FPGA chip FPGA_CH, and the processing as shown in FIGS. 3 and 4 is possible even when some of them are in operation. Therefore, during the period from time T1 to time T13 in FIG. 4, data communication may be performed between the functional blocks that are not subject to reconfiguration via the on-chip bus DBUS.

Further, here, the case of changing the user logic circuit of the FPGA fabric part FPGA_FAB is taken as an example, but the present invention is not limited to this, and the bus width of the internal bus may be increased or decreased, or a new user logic circuit may be added. Can also be implemented as long as the resources in the FPGA chip FPGA_CH are allowed. For example, it may be determined that the number of functional blocks needs to be increased according to the time T1 in FIG. 4, and in this case, it may be desirable to increase the bus width as the number of functional blocks increases. Alternatively, even if there are a plurality of functional blocks that originally perform the same operation, a determination may be made to increase the bandwidth of data communication between the functional blocks. In such a case, since the configuration change is performed so as to increase the bus width, the data communication in the form of increasing the bus width is carried out after the time T13.

As described above, by using the information processing device and the information processing system of the first embodiment, it is possible to typically improve the calculation efficiency.

In the second embodiment, the configuration of the bit stream of the CRAM will be described. FIG. 5 is a schematic view showing a structural example of an address map of a CRAM in the information processing apparatus according to the second embodiment of the present invention. As described in the first embodiment, when changing the user logic circuit of the FPGA fabric unit FPGA_FAB, for example, the number of LUTs is increased or decreased while maintaining the configuration of the LUTs, and the connection relationship between the LUTs is increased accordingly. That is, there are cases where it is desired to change the configuration of the switch unit SW in FIG.

In such a case, as shown in FIG. 5, it is desirable to explicitly separate the CRAM address that determines the configuration of the switch unit SW of the FPGA fabric unit FPGA_FAB and the CRAM address that determines the configuration of the programmable logic unit LOG. Here, a case where a CRAM capacity of 256 Mbit is assigned to each of a plurality of switches constituting the switch unit SW and a plurality of LUTs constituting the programmable logic unit LOG, and each switch and each LUT are composed of 16 bits. It is an example. However, of course, the CRAM capacity and the number of bits of each switch and each LUT are not limited to this.

In the third embodiment, an example of a method of changing the config data will be described. 6 (a) and 6 (b) are conceptual diagrams illustrating an example of a method of changing config data in the information processing apparatus according to the third embodiment of the present invention. Here, for example, a case where the config control unit CNFGC of FIG. 1 determines that the processing capacity of the functional block A is insufficient and the circuit block A constituting the functional block A is enhanced accordingly is taken as an example.

In FIG. 6A, circuit blocks A (CRCITBK_A) to circuit blocks C (CRCITBK_C), spare circuit blocks X (CRCITBK_X), switch blocks 1 (SWBK1) and switch blocks 2 (SWBK2), and each circuit block. And the CRAM corresponding to each switch block are shown. In this figure, for simplicity, an example is shown in which data processing flows from left to right.

Here, a method of generating the logic of the circuit block X (CRCITBK_X) will be described. This block is an area prepared in advance as a spare in the third embodiment, and by generating a circuit block A (CRCITBK_A) in this area, the lack of processing capacity can be solved. Specifically, the CRAM controller CRAMC of FIG. 1 first reads the CRAM and stores the CRAM address and data corresponding to the circuit block A to be changed in the user memory provided in the FPGA chip FPGA_CH. Then, at this time, as shown in FIG. 6B, the CRAM controller CRAMC of FIG. 1 sets the data of the CRAM address (CADR_X) corresponding to the circuit block X to the same data (CDATA_A) as the circuit block A. ..

Further, as shown in FIG. 6B, the CRAM controller CRAMC defines the data of the CRAM addresses (CADR_SW1, CADR_SW2) corresponding to the switch blocks 1 and 2 in the predetermined data (CDATA_SW1', CDATA_SW2'), respectively. .. For example, the data CDATA_SW1'is changed from the connection data for the circuit block A included in the data CDATA_SW1 before the change to the connection data for the circuit block X in addition to the circuit block A. The same applies to the data CDATA_SW2'.

The CRAM controller CRAMC writes each config data determined in this way in the user memory to the CRAM. At this time, the CRAM controller CRAMC also generates a coding code such as ECC or CRC as described in the first embodiment. The memory outside the FPGA chip FPGA_CH may be used to generate such config data. It is desirable to provide a transfer path from RAM to CRAM in the chip, but if it does not exist, it is also possible to temporarily transfer via the external config storage device CTRL.

As described above, when the method of the third embodiment is used, the resources in the FPGA chip FPGA_CH can be effectively utilized, and autonomous control can be performed so as to maximize the performance.

In the fourth embodiment, another example of the method of changing the config data will be described. FIG. 7 is a conceptual diagram illustrating an example of a method of changing config data in the information processing system according to the fourth embodiment of the present invention. The information processing system shown in FIG. 7 includes an FPGA subsystem FPGA_SSYS composed of n + 1 FPGA chips FPGA_CH0 to FPGA_CHn, an evaluation unit interface EVAL_IF shown in FIG. 1, and an external config storage device STRG. Functional blocks FUNC_A0 to FUNC_A2 are mounted on the FPGA chip FPGA_CH0, functional blocks FUNC_B0 to FUNC_B2 are mounted on the FPGA chip FPGA_CH1, and functional blocks FUNC_C0 to FUNC_C2 are mounted on the FPGA chip FPGA_CH2.

The evaluation unit interface EVAL_IF includes an optimization control unit CTLP that optimizes the system. The optimization control unit CTLP has the same functions as the data monitoring unit CUNT, the config control unit CNFGC, and the CRAM controller CRAMC shown in FIG. Further, each FPGA chip FPGA_CH0 to FPGA_CHn is also provided with an optimization control unit CTLC corresponding to the function.

Here, the optimization control unit CTLP of the evaluation unit interface EVAL_IF may, for example, monitor the data signal line (SDAT) or acquire the monitoring result by the optimization control unit CTLC in each chip. , FPGA subsystem Monitors computing power in FPGA_SSYS. Then, the optimization control unit CTLP generates a new functional block when, for example, it is determined that the arithmetic processing capacity tends to be insufficient by statistical processing using the threshold table.

In this example, the functional block FUNC_A0 of the FPGA chip FPGA_CH0, the functional block FUNC_B2 of the FPGA chip FPGA_CH1, and the functional block FUNC_C1 of the FPGA chip FPGA_CH2 are frequently used, and the optimization control unit CTLP efficiently enhances these blocks. It is assumed that it is determined to be. In this case, the optimization control unit CTLP reads, for example, the config data of each functional block FUNC_A0, FUNC_B2, and FUNC_C1 from each chip via the config signal line (SCFG), and implements the control signal. Instruct the optimization control unit CTLC of the FPGA chip FPGA_CHn via a line (SCTL).

When copying such config data, it is convenient if the interface of each functional block is unified, and it is desirable to have the same number of input / output pins. However, even if the number of input pins is not uniform, it can be mounted without any problem by performing processing such as "H" level fixing, "L" level fixing, and opening on the surplus pins in the switch unit SW.

As described above, when the method of the fourth embodiment is used, the resources in the information processing system can be effectively utilized and autonomous control can be performed so as to maximize the performance.

In the fifth embodiment, a modification of the information processing apparatus (FPGA chip FPGA_CH) shown in FIG. 1 and still another example of a method of changing the config data will be described. FIG. 8 is a block diagram showing a schematic configuration example of the entire information processing system according to the fifth embodiment of the present invention. FIG. 1 shows an example of changing the config data by using statistical data of data transfer on the on-chip bus DBUS, but in the fifth embodiment, it depends on the data processing, not the data flow. Change the config data.

In the information processing device (FPGA chip FPGA_CH) of FIG. 8, unlike FIG. 1, the data monitoring unit CUNT is not connected to the on-chip bus DBUS, but is directly connected to each FPGA fabric unit FPGA_FAB. The data monitoring unit CUNT transmits a config switching signal to the config control unit CNFGC in response to the completion signal of the arithmetic processing from the FPGA fabric unit FPGA_FAB. The end signal of the arithmetic processing is transmitted by the FPGA fabric unit FPGA_FAB every time the arithmetic processing of a predetermined unit is completed.

When switching the configuration, the end signal of the arithmetic processing itself may be used, but the time interval from the start to the end of the arithmetic processing, the number of executions of the arithmetic processing, etc. are measured (that is, the load weight of the arithmetic processing and the arithmetic). (Measuring the frequency of processing) is more effective. Further, for example, when the time-series transition of the arithmetic processing can be predicted in advance based on the analysis of the program, it is possible to incorporate a timer and switch when the set time is reached.

Further, the user logic circuit can be autonomously changed so as to have an optimum logic configuration according to the number of interrupt processing and the type of interrupt processing. That is, when the interrupt processing calculation is fixed and the frequency is high, it is possible to implement a user logic circuit that executes the interrupt processing in the FPGA fabric unit FPGA_FAB that hardly executes the calculation processing.

This concept of interrupt processing can be extended to the concept of updating the arithmetic processing unit. Generally speaking, interrupts have a strong image of branching software in order to respond to urgent processing routines and additional arithmetic processing requests in a normal control sequence. On the other hand, the method of this embodiment can include not only such a fixed so-called designed program branching but also the concept of expansion of additional functions that were not considered at the beginning of the design.

For example, a new arithmetic process called interrupt processing is a service that processes even if it is designed with a low priority or is not included in the original design because it is infrequent or out of the expected range at the beginning of design. And can occur frequently as the application evolves. That is, a situation may occur in which the priority of new arithmetic processing is dynamically increased. By using the method of this embodiment, it is possible to evolve the hardware processing so as to adapt to the change in the situation in response to such a dynamic increase in priority. By performing the arithmetic processing with the dedicated hardware in this way, it is possible to realize high speed and low power consumption as compared with the case where the arithmetic processing is performed by the software.

As described above, when the method of the fifth embodiment is used, the resources in the information processing apparatus can be effectively utilized and autonomous control can be performed so as to maximize the performance.

In the sixth embodiment, still another example of the method of changing the config data will be described. In the above-described embodiment, an example in which the config data of the user logic circuit (functional block) is mainly changed based on the number of data communications (or the number of arithmetic processes) between the user logic circuits mounted on the FPGA chip FPGA_CH is shown. It was. In the sixth embodiment, an example of changing the config data of the switch unit will be described. FIG. 9 is a conceptual diagram illustrating an example of a method of changing config data in the information processing apparatus according to the sixth embodiment of the present invention.

The information processing apparatus FPGA_CH shown in FIG. 9 includes a plurality of functional blocks FUNC_A to FUNC_F, a switch unit SW for connecting each functional block, and an optimization control unit CTLC as described in FIG. 7. Here, for the sake of simplicity, the number of signals between each functional block will be limited to four. The functional block FUNC_A includes an output interface IFO, and one signal from the output interface IFO is connected to the functional block FUNC_D, one is connected to the functional block FUNC_E, and two signals are connected to the functional block FUNC_F.

Similarly, two signals from the output interface IFO of the functional block FUNC_B are connected to the functional block FUNC_D, one to the functional block FUNC_E, and one to the functional block FUNC_F. Further, one signal from the functional block FUNC_C is connected to the functional block FUNC_D, one is connected to the functional block FUNC_E, and two are connected to the functional block FUNC_F.

Here, for example, when the optimization control unit CTLC determines that the relationship between the functional block FUNC_A and the functional block FUNC_D is strong, the optimization control unit CTLC changes the degree of coupling between the functional block FUNC_A and the functional block FUNC_D. In this example, the signal from the functional block FUNC_A is changed so that two are connected to the functional block FUNC_D, one is connected to the functional block FUNC_E, and one is connected to the functional block FUNC_F. Since this connection can be flexibly changed depending on the degree of data connectivity between functional blocks, it is expected that the calculation speed of the entire chip will be improved while utilizing the limited transistor and wiring assets. In order to easily make such a change, it is desirable to use a bit stream of CRAM as shown in the second embodiment.

As described above, when the method of the sixth embodiment is used, the resources in the information processing apparatus can be effectively utilized and autonomous control can be performed so as to maximize the performance.

In the seventh embodiment, a modified example of the information processing system shown in FIG. 1 and still another example of a method of changing the config data will be described. In this embodiment, information such as the performance of functional blocks and the transfer of data between functional blocks is used to improve the calculation efficiency and the calculation speed. The examples so far have mainly been related to reusing existing design data, increasing / decreasing the number of functional blocks, redefining connection relationships, and autonomously incorporating newly designed hardware after operation. .. In the seventh embodiment, a mechanism for intentionally causing bit inversion of the CRAM and improving the calculation performance by changing the logic will be described.

FIG. 10 is a block diagram showing a schematic configuration example of a main part of the information processing system according to the seventh embodiment of the present invention. The information processing system shown in FIG. 10 includes an FPGA subsystem FPGA_SSYS including a plurality of FPGA chips FPGA_CH0 to FPGA_CHn, as in the case of FIG. 7. The difference from FIG. 7 is that an evolution block EVOL that controls the evolution of the subsystem is newly provided, a signal line (SEVL) that promotes evolution is added, and each FPGA chip is configured as necessary. The point is that a config data generation unit GEN for evolving data is provided.

The config data generation unit GEN of each chip independently receives the enable signal and the setting information from the evolution block EVOL via the signal SEVL, and updates the CRAM. In the example of FIG. 10, the same functional blocks FUNC_A0, FUNC_A1, and FUNC_A2 are first mounted on the FPGA chips FPGA_CH0 and FPGA_CH1, and the config data of the FPGA chip FPGA_CH1 is intentionally changed during the subsequent arithmetic processing. An action is taken to find out what the result will be. The FPGA chip FPGA_CH0 is a functional block that advances data processing in a designed state, and the FPGA chip FPGA_CH1 is an evaluation block that starts from the designed data and seeks a better logical configuration. As described above, in the seventh embodiment, a method for changing the hardware to a better state while utilizing the actual data is shown.

Random bit inversion and partial modification of the CRAM by a genetic algorithm can be considered for updating the CRAM. When random bit inversion is used, for example, the config data generation unit GEN may be provided in the config update unit CNFG_MDFY of FIG. The config update unit CNFG_MDFY randomly selects bits from the config data read from the CRAM using random numbers or pseudo-random numbers, inverts the selected bits, and then writes them back to the CRAM.

On the other hand, when a genetic algorithm is used, the fitness is high as a whole (operating state is high) while repeating operations such as selection, crossover, and mutation for a plurality of predetermined chromosomes (config data in this case). Processing is performed to search for the best) chromosome. Crossover is, for example, an operation in which some bits in one chromosome are exchanged with some bits in another chromosome, and mutation is an operation in which some bits in one chromosome are inverted. is there. In addition, selection is an operation that leaves chromosomes with high fitness and eliminates chromosomes with low fitness.

After performing crossover and mutation operations, the remaining chromosomes are further crossed and mutated to search for the chromosome with the highest fitness (that is, the config data with the best operating state). can do. In the process of such an operation, the config data that is not eliminated is stored in the external config storage device CTRL, and the config data that has been selected is deleted from the external config storage device CTRL.

In the example of FIG. 10, the evaluation unit interface EVAL_IF sequentially compares the FPGA chip FPGA_CH0 and the FPGA chip FPGA_CH1 (comparison of data correctness, processing capacity, etc.). Based on this comparison result, the evolution block EVOL performs, for example, the above-mentioned selection, and instructs the config data generation unit GEN of the FPGA chip FPGA_CH1 to update the CRAM. The config data generation unit GEN updates the CRAM by performing operations such as crossover and mutation using the config data that has not been selected by the external config storage device CTRL. Here, as a specific example of the comparison method in the evaluation unit interface EVAL_IF, comparison of time intervals of arithmetic processing, performance of arithmetic results, and the like can be considered.

For the time interval of the former arithmetic processing, the start and end of the processing may be simply measured. At that time, higher-speed processing can be realized (that is, higher fitness) by comparing the time intervals before and after the trial while sequentially performing trials on the FPGA chip FPGA_CH1 based on the data at the time of design. You can get the config data. Further, regarding the performance of the latter calculation result, for example, when performing a process such as image recognition, a method such as determining the degree of improvement of the recognition rate as a threshold value can be considered.

Such processing is accumulated while utilizing commercial-based actual data, and better config data is stored in the external config storage device CTRL. So to speak, we will proceed with learning while utilizing live data and seek more efficient processing. At that time, it is desirable to be able to simultaneously store the evaluation result, the processing time, and the processing data information in the evaluation unit interface EVAL_IF. Further, although not shown in the evaluation by the evaluation unit interface EVAL_IF, it is possible to evaluate the power efficiency by taking into account the measurement results of the power monitor or the like.

FIG. 11 is a circuit diagram showing a general LUT configuration example. A general LUT is configured so that CRAM information is selectively output via a selector, and in the case of 4 inputs, it is composed of a 16-bit CRAM. The settable value of the CRAM that can be realized by this LUT is 2 ^ 16 = 65536, and the possible values of the inputs I0 to I3 are 2 ^ 4 = 16. By changing these independently, 1048576 combinations can be realized. Generally, about 1 million LUTs are accumulated in FPGA, and the number of data processing bits is enormous. The method of the seventh embodiment is one means for autonomously evolving the functional block designed by human experience and the logic synthesis tool beyond the range assumed by human beings and obtaining better performance.

Here, the optimization of a predetermined FPGA chip was attempted based on the comparison result between the FPGA chips in the information processing system, but similarly, the comparison result between the FPGA fabric parts in the FPGA chip was attempted. It is also possible to optimize a predetermined FPGA fabric portion based on the above. In addition, here, in order to surely obtain data without errors, a functional block for advancing data processing and an evaluation block for advancing optimization are provided, but some errors such as image / audio processing are provided. If acceptable, it is possible to proceed with both data processing and optimization in a single block.

The examples so far have been examples in which the performance of the hardware as an arithmetic unit is improved by the evolution of the CRAM. Here, an example relating to the realization of a high-speed arithmetic chip will be described as a new effect due to frequent updates of config data. FIG. 12 is a schematic view showing a configuration example of a main part of the information processing apparatus according to the eighth embodiment of the present invention. The configuration shown in FIG. 12 realizes an Ising chip by using programmable logic and evolves the data stored in the CRAM.

In this example, the CRAM itself is treated like a data memory, and arithmetic processing is performed using the configuration of the FPGA. FIG. 12 shows an example in which four CRAMs each having 16 bits and four LUTs corresponding to the four CRAMs are provided for simplicity. Data to be processed is mounted on this CRAM, and by connecting the inputs of the four LUTs in common, for example, a predetermined 1 bit (for example, bit # 0) in each of the four CRAMs constitutes a LUT. It is possible to select and output at the same time via the selector. In this example, since the predetermined 1 bit has 16 bits, if the information composed of 4 bits is defined as one surface, the information on the 16 surfaces can be selected. For example, in the case of a computer that advances operations while changing the 4-bit information, 16 types of operations can be realized with four LUTs.

FIG. 13 is a waveform diagram showing an example of a specific calculation sequence in FIG. The input signals I0 to I3 are changed by clock synchronization, and at the same time, the clock is input to the interaction determination circuit INTRAC and the data generation unit DGEN. Synchronized with the clock, the CRAM config is executed while performing the calculation on the 16th surface of the CRAM. As shown in the waveform diagram of FIG. 13, the input signals I0 to I3 can perform 16 operations, and when each operation is called a state, the bits of the four CRAMs corresponding to the four LUTs are used. Information is output in order from 0 to 15 for each state and calculated.

In this example, the output signals from the four LUTs are also input to the interaction determination circuit INTRAC, and the interaction determination circuit INTRAC is stored in the CRAM by determining the interaction of the output signals from the four LUTs. Evaluate the correlation of the data. The interaction determination circuit INTRAC, for example, adds correlation and weighting parameters between each bit, and executes a product-sum operation and an averaging process. Upon receiving the calculation result, the data generation unit DGEN decides whether to invert the bit information stored in the CRAM or leave it as it is. As described above, in the eighth embodiment, the CRAM is updated by detecting the relationship between the bit information of the CRAM.

14 to 16 are diagrams for explaining the concept of the Ising tip. A method called the Ising model has been proposed as a method for calculating the ground state of a physical phenomenon. This is a computational model for calculating the energy state of the particles that make up a substance, especially depending on the direction of spin, and finding a more stable state. For example, particles with spin are arranged on a plane and their closest ones. It calculates the interaction between spins and leads to a stable state. FIG. 14 shows an example of mapping a two-dimensional Ising model to an FPGA.

In FIG. 14, each Ising spin particle (referred to as an Ising node (Ind)) is represented by a circle and is uniformly arranged on a plane. In this figure, they are grouped in 6 × 6 matrix units and defined as PE (Primitive Element). An example of mapping this to FPGA will be described below.

FIG. 15 is a diagram showing a connection relationship between neighboring Ising nodes Ind by extracting one PE. Focusing on one Ising node Ind and keeping in mind that the vertical, horizontal, and diagonal relationships are calculated, eight interaction lines Ib (Interaction bond) can be considered as shown in FIG. The calculation is executed for each basic unit (hereinafter referred to as EU: Execution Unit) connected by these eight interaction lines Ib.

At this time, as a combination of operations, there are 16 combinations of operations in performing the operation using the data stored in the initial CRAM bit, and it is shown in FIG. 15 in one PE. 16 EUs (EU0 to EU15) are defined so as to be. In FIG. 15, for the sake of clarity, the relationships are shown so as not to overlap, and all 16 combinations are represented in the nine figures (A) to (I). That is, when considering one PE, it is necessary to be able to perform 16 kinds of calculations. Details of the EU configuration are shown in FIG. In this model, the EU is composed of nine Ising nodes Ind0 to Ind8 and eight interaction lines Ib0 to Ib7. In the eighth embodiment, each Ising node is assigned to the LUT, and the operation of the interaction is performed by the user logic circuit.

FIG. 17 is a schematic view showing a configuration example when the PE of FIG. 15 is mapped to the FPGA. FIG. 17 shows nine LUTs (LUT0 to LUT8) and four bits which are inputs to each LUT. Input signals I0 to I3, a switch circuit SWC that connects the input signals to nine LUTs, a flip-flop FF that temporarily holds arithmetic data, a correlation evaluation circuit IEU, a memory RAM, and an address conversion unit ADRCV. , CRAM write circuit CRWT is shown.

The correlation evaluation circuit IEU corresponds to the interaction determination circuit INTRAC and the data generation unit DGEN in FIG. 12, calculates the interaction of Ising nodes, and calculates the calculation result of the interaction (E) and each derived from the calculation result. The data of the Ising nodes (σi, σj) is stored in the memory RAM. The memory RAM is installed in the FPGA in advance, for example. The CRAM write circuit CRWT writes back the data of the calculation result of the Ising node written in the memory RAM to the CRAM by designating the address. The address conversion unit ADRCV has a function of changing the address when the CRAM writing circuit CRWT writes back. Each LUT is provided with a corresponding CRAM, and in the eighth embodiment, a 4-input LUT is assumed, and a 16-bit CRAM is associated with one LUT. CRAM0 corresponds to LUT0, and the CRAM includes 16 bits of bits # 0 to # 15.

The configuration of FIG. 17 will be described in correspondence with FIG. In FIG. 15, in one EU, there are nine Ising node Inds that perform interactions and eight interaction lines Ib. Eight interaction lines are defined for the Ising node Ind, and nine Ising node Inds that are the source of this interaction are realized by nine LUTs. In the example of FIG. 17, four input signals I0 to I3 are commonly input to each of the nine LUTs. As in the case of FIG. 13, when 16 types of inputs are performed with the four input signals, the nine LUTs select one bit from the corresponding CRAMs and go to the flip-flop FF in the subsequent stage. The output operation is performed 16 times.

Here, the 16 EUs to EU15 shown in FIG. 15 correspond to bits # 0 to bits # 15 of the CRAM of each LUT, respectively. That is, EU0 in FIG. 15 corresponds to bit # 0 of CRAM0 to CRAM8, and bit # 0 of the CRAM0 to CRAM8 corresponds to Ising nodes Ind0 to Ind8 (FIG. 16) of the EU0, respectively. Further, EU1 in FIG. 15 corresponds to bit # 1 of CRAM0 to CRAM8, and bit # 1 of the CRAM0 to CRAM8 corresponds to Ising nodes Ind0 to Ind8 (FIG. 16) of the EU1, respectively.

In the Ising model, the interaction with the Ising node (σi, σj) is calculated, so in a simple calculation, the weighting coefficient (interaction coefficient) (wij) and σi, σj (each σ = -1 or 1) Multiply to calculate the sum. At this time, since the data stored in the CRAM is 0, 1, 0 is converted to -1 at the time of the four arithmetic operations. As a result of the summation calculation, the increase or decrease of energy is calculated. At that time, by comparing with the previous value, the direction of the spin of the particle is changed so that the energy state is lower. Since the spin directions of the particles are described by σi and σj, the σi and σj updated by the calculation result are written to the memory RAM.

In the Ising model, the interaction between all particles is calculated to find the state where the energy is the lowest or the lowest. Therefore, the PE shown in FIG. 14 needs to be calculated by defining not only the classification shown in this figure but also the PE in which the PE is shifted up, down, left and right by one Ising node. Therefore, instead of changing the basic configuration of the hardware shown in FIG. 17, by changing the memory address of the CRAM that stores the information of the EU Ising node, it is expressed as if the position of the Ising node to be evaluated was changed. ..

This makes it possible to sequentially and uniformly calculate the interaction between Ising nodes while fixing the basic hardware. As a means for that, when writing back the updated Ising node data in the memory RAM to the CRAM, the data is stored in the CRAM via the address conversion unit ADRCV. For example, it is conceivable that the data initially stored in bit # 0 of CRAM0 is stored in bit # 1 of CRAM0 as a result of the calculation. By doing so, for example, in the example shown in FIG. 14 or FIG. 15, the first Ising node is shifted by 1 bit to the right, and the EU is relatively shifted to the left by one Ising node. As a result, the relationship for calculating the interaction is shifted by one Ising node.

In the example shown in FIG. 17, the case of calculating one PE has been described, but in reality, many of these PEs are deployed on the FPGA. Therefore, other PEs are similarly calculated in the same calculation cycle, and after the calculation result is stored in the memory, address conversion is performed in order to newly store the calculation result in the CRAM. However, since PEs are only separated for convenience, it is necessary to interact with adjacent PEs via the Ising node. That is, it is necessary to exchange calculation results with other PEs. FIG. 17 shows a simplified signal path for that purpose. In fact, data transfer may be transfer between memories. This is because after the transfer between the memories, the address conversion for setting in the CRAM may be performed and stored in the CRAM.

Although FIG. 17 shows an example in which the CRAM writing circuit CRWT is contained in the PE, the CRAM writing circuit CRWT may be collectively integrated in the chip. By integrating to some extent in the chip, there is an effect that the degree of integration of the logic circuit can be improved. Further, in the method of the eighth embodiment, the FPGA can be used as an LSI for integrating logic circuits in the so-called normal sense, and no problem occurs even in general-purpose use. As described above, by using the method of the eighth embodiment, it is possible to realize a high-performance LSI using a general-purpose COTS (Commercial Off The Shelf) product.

FIG. 18 is a diagram showing an overall operation example when performing an operation using the configuration of FIG. In FIG. 18, the state of the pattern A is a state in which 36 Ising nodes are collected to form a PE, which are arranged vertically and horizontally. In the state of pattern B, the group of Ising nodes is shifted to the right by one Ising node to define PE, and the PEs are arranged vertically and horizontally. Similarly, the state of pattern C is a state in which a group of Ising nodes is further shifted to the right by one Ising node to define PE, and the PEs are arranged vertically and horizontally.

Here, in the operation waveform diagram shown in FIG. 18, at time T1, all PEs are calculated in the state of pattern A, the calculation results are stored in the memory RAM, and then address conversion is performed and stored in the CRAM. The operations up to are performed sequentially. After that, at time T2, all operations related to PE are performed in the state of pattern B. Hereinafter, at time T3, in the state of pattern C, all operations related to PE are performed, and thereafter, in the same manner, operations shifted up, down, left and right by one Ising node are performed a plurality of times, and between all Ising nodes. The calculation will be performed.

Although the 4-input LUT has been described as an example in the eighth embodiment, the number of LUT inputs is not limited to four. When the number of inputs is 5, the number of EUs can be doubled to 32, and 2 PEs can be realized by 9 LUTs, which has the effect of achieving higher integration. As described above, the method of the eighth embodiment can be applied even if the number of LUT inputs is other than four.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. For example, the above-described embodiments have been described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

CNFGC config control unit CRAM configuration memory CRAMC CRAM controller CUNT data monitoring unit DBUS on-chip bus EVAL_IF evaluation unit interface FPGA_CH FPGA chip FPGA_FAB FPGA fabric unit STRG external config storage device

Claims (2)

K lookup tables, each with n inputs,
M configuration memories corresponding to each of the K lookup tables,
A correlation evaluation circuit that determines the interaction of K output signals output from the K lookup table and generates new data based on the determination result.
A CRAM write circuit that writes back the new data generated by the correlation evaluation circuit to the M configuration memories by designating an address.
It is an information processing device that has
Each of the M configuration memories is composed of 2 n bits.
Each of the K look-up tables selects and outputs one bit in the corresponding configuration memory according to the n-bit input signal.
The n-bit input signals are commonly input to the K look-up tables.
Data of the calculation result of each Ising node based on the Ising model is mapped to each bit of the M configuration memories.
Information processing device. In the information processing apparatus according to claim 1,
Further, it has an address conversion unit that shifts the address specified by the CRAM writing circuit.
Information processing device.

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