JP6757128B2 - Storage device for game machines - Google Patents

Description

The present invention relates to a storage device for a game machine, for example, a storage device for a game machine provided with a non-volatile memory for storing data for the game machine.

Non-volatile memory for storing game machine data is used in gaming machines such as pachinko and pachislot machines. For example, Patent Document 1 describes that character data of a game machine is stored in a NAND type non-volatile memory.

Japanese Unexamined Patent Publication No. 2010-137019

In a game machine, access may be concentrated on data for a specific game machine. If the data to which access is concentrated is not stored in the cache memory, the number of reads of a specific address in the non-volatile memory increases, and the read limit number of the non-volatile memory may be exceeded. In addition, when small-sized data is replaced with large-sized data, the access time becomes slow. As described above, it is required to appropriately control the cache memory in the storage device for a game machine.

The purpose of the game machine storage device is to appropriately control the cache memory for storing the game machine data.

The present invention is stored in the non-volatile memory for storing game machine data, a cache memory for storing the game machine data, and the non-volatile memory or the cache memory based on a command from the host device of the game machine. The game machine data is read, the read game machine data is transferred to the host device, and when the game machine data read from the non-volatile memory is less than the first size, the read game machine is read. The data for the game machine includes a control unit for registering the read data for the game machine in the cache memory with priority over the data for the first size or larger, and the data for the game machine is displayed on the game machine. and image data of an image to be displayed device, viewed including the audio data is data of a sound output from the sound output device of the gaming machine, at least one of said non-volatile memory includes a plurality of regions, the It is a storage device for a game machine, characterized in that the first size is set corresponding to a plurality of regions, and the first size corresponding to at least two regions out of the plurality of regions is different .

In the above configuration, when the read game machine data is the first size or larger, the control unit does not register the read game machine data in the cache memory and reads the read game machine data. When the game machine data is smaller than the first size, the read game machine data can be registered in the cache memory.

In the above configuration, the control unit may be configured to limit the number of game machine data of the first size or larger registered in the cache memory to a predetermined number or less.

In the above configuration, in the control unit, the number of game machine data whose read-out game machine data is the first size or more and which is registered in the cache memory is the predetermined number of game machine data of the first size or more. When the number is the number, the read game machine data can be replaced with at least one of the game machine data of the first size or larger registered in the cache memory.

In the above configuration, the control unit is configured to limit the number of game machine data of the second size or larger, which is smaller than the first size and smaller than the first size, to be registered in the cache memory to a predetermined number or less. Can be done.

In the above configuration, the control unit has the read game machine data less than the first size and larger than the second size, and less than the first size registered in the cache memory and the second size. When the number of game machine data of the size or larger is the predetermined number, the read game machine data is registered in the cache memory and is smaller than the first size and larger than the second size. It can be configured to replace at least one of.

The present invention is for a game machine in which a non-volatile memory for storing game machine data, a cache memory for storing the game machine data, and a game machine data stored in the non-volatile memory are read and read. When the data is less than the first size, the control unit which registers the read game machine data in the cache memory with priority over when the read game machine data is the first size or more. The non-volatile memory includes a plurality of areas, corresponds to the plurality of areas, the first size is set, and the first size corresponding to at least two of the plurality of areas is different. It is a storage device for a game machine, which is characterized in that .

In the above configuration, when the image data read from the non-volatile memory is less than the first size , the control unit preferentially reads the read image data over when the read image data is the first size or more. The image data can be registered in the cache memory .

According to the game machine storage device, the cache memory for storing the game machine data can be appropriately controlled.

FIG. 1 is a block diagram showing a game machine in which the game machine storage device according to the first embodiment is used. FIG. 2 is a block diagram showing a storage device according to the first embodiment. 3 (a) to 3 (c) are schematic views showing data in the non-volatile memory and the cache memory in Comparative Example 1. 4 (a) and 4 (b) are diagrams for explaining the relationship between the size of data and the transfer time. FIG. 5 is a flowchart showing the control of the cache control unit in the first embodiment. 6 (a) to 6 (c) are schematic views showing data in the non-volatile memory and the cache memory in the first embodiment. FIG. 7 is a flowchart showing the control of the cache control unit in the first modification of the first embodiment. 8 (a) to 8 (c) are schematic views showing data in the non-volatile memory and the cache memory in the first modification of the first embodiment. 9 (a) is a schematic diagram showing the non-volatile memory in the second modification of the first embodiment, and FIG. 9 (b) is a diagram showing the threshold values S1, S2 and N in each region. FIG. 10 is a flowchart showing the control of the cache control unit in the second modification of the first embodiment.

Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a game machine in which the game machine storage device according to the first embodiment is used. As shown in FIG. 1, the game machine 100 includes a storage device 10, a peripheral control unit 11, a main control unit 12, a payout control unit 13, a voice output device 14, a lamp 15, a display device 16, a winning sensor 17, and a handle 18. Be prepared. The storage device 10 stores data for a game machine. The peripheral control unit 11 controls peripheral devices such as a storage device 10, an audio output device 14, a lamp 15, and a display device 16. The main control unit 12 acquires a part of the program data stored in the storage device 10 via the peripheral control unit 11. The main control unit 12 controls the peripheral control unit 11 and the payout control unit 13 based on the signals from the winning sensor 17 and the handle 18. For example, when the game machine 100 is a pachislot device, the main control unit 12 controls a reel that displays the lottery result at the stop position of the symbol. The payout control unit 13 controls the payout based on the instruction of the main control unit 12. For example, when the game machine 100 is a pachislot device, the payout control unit 13 causes the hopper to pay out coins based on the instructions of the main control unit 12. The winning sensor 17 detects winning. When the main control unit 12 acquires the winning detection information from the winning sensor 17, the main control unit 12 instructs the payout control unit 13 to pay out. The steering wheel 18 outputs a signal for operating the steering wheel of the user. The main control unit 12 causes the peripheral control unit 11 to operate the audio output device 14, the lamp 15, and the display device 16 based on the signal from the steering wheel 18.

The voice output device 14 is, for example, a speaker, and outputs voice based on the voice data stored in the storage device 10. The lamp 15 is, for example, an LED (Light Emitting Diode), and lights up based on the lighting data stored in the storage device 10. The display device 16 is, for example, a liquid crystal display device, and displays an image based on the image data stored in the storage device 10. The peripheral control unit 11 reads out image data, lighting data, and audio data from the storage device 10 based on the program data stored in the storage device 10.

FIG. 2 is a block diagram showing a storage device according to the first embodiment. As shown in FIG. 2, the storage device 10 includes a cache memory 20, a non-volatile memory 21, a RAM (Random Access Memory) control unit 22, a ROM (Read Only Memory) control unit 23, a cache control unit 24, a processor 25, and I. A / F (interface) control unit 26 is provided. The storage device 10 is connected to the host device 28. The host device 28 is, for example, the peripheral control unit 11 of FIG. The cache memory 20 is, for example, an SRAM (Static RAM), and stores frequently accessed data among the game machine data stored in the non-volatile memory 21. The non-volatile memory 21 is, for example, a ROM such as a NAND flash memory, and stores data for a game machine.

The RAM control unit 22 stores and reads data in the cache memory 20. The ROM control unit 23 stores and reads data in the non-volatile memory 21. The I / F control unit 26 outputs a command output from the host device 28 to the processor 25 or the cache control unit 24. The I / F control unit 26 outputs the data output from the cache control unit 24 to the host device 28. The processor 25 outputs a command to the cache control unit 24 based on the command from the host device 28. The cache control unit 24 receives the command output by the processor 25 or the command output by the I / F control unit 26. The cache control unit 24 uses the ROM control unit 23 to read data from the non-volatile memory 21, and uses the RAM control unit 22 to store and read data in the cache memory 20.

First, the problems of the comparative example will be described. 3 (a) to 3 (c) are schematic views showing data in the non-volatile memory and the cache memory in Comparative Example 1. As shown in FIG. 3A, large-sized content data 30 and small-sized content data 32 are stored in the non-volatile memory 21. The non-volatile memory 21 stores data of various sizes, but the description will be simplified by using the large size data 30 and the small size data 32. The data 30 and 32 are, for example, image data, audio data, lighting data, and program data. The image data is image data displayed on the display device 16. The image data is stored for each part in the image to be displayed, for example. The audio data is audio data output from the audio output device 14. The lighting data is data for lighting the lamp 15. The program data is a part of an OS (Operating System) or application program executed by the main control unit 12 and the peripheral control unit 11. That is, the program data is data for controlling the host device 28.

In the game machine data, data having different sizes are mixed in the same data type, such as data 30 and 32. For example, in the image data, the size of the background image data is large. The background image data is accessed infrequently. In particular, when the background image data is a moving image, the image data has a large data size and a low access frequency. On the other hand, the size of the image data for the moving image of the small image part displayed on the background is small. Image parts are often accessed frame by frame (eg, every 1/60 second). For this reason, image parts have a high frequency of access. In the voice data, the voice data to be reproduced in the background has a large size and the access frequency is low, and the sound data of the sound effect has a small size and the access frequency is high. As described above, the large-sized data 30 has a low access frequency, and the small-sized data 32 has a high access frequency.

The cache control unit 24 performs cache control. In the LFU (Least Frequently Used) control, data having a high access frequency is stored in the cache memory 20, and is replaced with data having a low access frequency. In LRU (Least Recently Used) control, the longest inaccessible data is replaced with new data. When the data 32 is frequently accessed, the game machine data stored in the cache memory 20 is almost small size data 32. For example, as data 32, eight data from "1" to "8" are stored in the cache memory 20.

As shown in FIG. 3B, when "10" is accessed as large-sized data 30, the cache control unit 24 reads the data 30 of "10" from the non-volatile memory 21 and data as shown by an arrow 50. 30 is transferred to the host device 28. At the same time, the cache control unit 24 replaces the data 32 in the cache memory 20 with the read "10" data 30. At this time, since the size of the data 30 is large, one data 30 is replaced with many data 32. For example, the size of the data 30 is approximately four times that of the data 32. At this time, the cache control unit 24 erases the four data 32 from "1" to "4" from the cache memory 20 as shown by the arrow 54, and erases the data 30 of "10" as shown by the arrow 52 in the cache memory 20. Store in.

After that, when the host device 28 accesses the data 30 “10”, the cache control unit 24 reads the data 30 of the “10” in the cache memory 20 and transfers the data 30 to the host device 28 as shown by the arrow 56. When the host device 28 accesses any data 32 from "1" to "4", the cache control unit 24 reads out any data 32 from "1" to "4" in the non-volatile memory 21. Transfer to the host device 28 as shown by arrow 58. The cache control unit 24 registers the cache.

As shown in FIG. 3C, when "11" is accessed as the large size data 30 in the state of FIG. 3B, the cache control unit 24 starts the non-volatile memory 21 to the data 30 of "11". Is read, and the data 30 of "11" is transferred to the host device 28 as shown by the arrow 50. At the same time, as shown by arrows 52 and 54, the cache control unit 24 replaces the four data 32 of "5" to "8" in the cache memory 20 with the data 30 of "11" read out.

After that, when the host device 28 accesses the data 30 “11”, the cache control unit 24 reads the data 30 of the “11” in the cache memory 20 and transfers the data 30 to the host device 28 as shown by the arrow 56. When the host device 28 accesses any data 32 from "5" to "8", the cache control unit 24 reads out any data 32 from "5" to "8" in the non-volatile memory 21. Transfer to the host device 28 as shown by arrow 56. The cache control unit 24 performs cache control.

When accessing the data 32 of "1" to "4" after FIG. 3B and the data 32 of "1" to "8" after FIG. 3C, the data 32 is accessed in the non-volatile memory 21. It will be. In this way, by frequently accessing the non-volatile memory 21 with the frequently accessed data 32, the read limit number of the non-volatile memory 21 may be exceeded in a short time. When the read limit number of times of the non-volatile memory 21 is exceeded, a problem such as a read disturb (a phenomenon in which the retained data changes due to electrical stress) that occurs in a flash memory occurs.

Further, when a plurality of small size data 32s are replaced with one large size data 30 in the cache memory 20, the data transfer becomes slow. This will be described below.

4 (a) and 4 (b) are diagrams for explaining the relationship between the size of data and the transfer time. The horizontal axis is time. FIG. 4A compares the case where the small size data 32 and the large size data 30 are read from the non-volatile memory 21. When accessing the non-volatile memory 21 such as the NAND flash memory, the latency 35 takes a long time. For example, at time t0, the host device 28 sends a read command to the storage device 10. The time at which the data transfer from the storage device 10 to the host device 28 starts is t1. The data transfer time after time t1 is substantially proportional to the size of the data 30 and 32. For example, in the data 32, the data transfer to the host device 28 ends at time t2. In the data 30, the data transfer ends at time t3.

FIG. 4B shows a case where four small size data 32 and one large size data 32 are transferred. Assuming that the size of the data 32 is four times that of the data 30, the time for transferring the four data 32 and the one data 30 is the same. It is assumed that the time required for the latency when accessing the cache memory 20 is very short and can be almost ignored. When the data 30 is stored in the cache memory 20 and the data 32 is stored in the non-volatile memory 21, it takes a latency 35 time before transferring the four data 32s. When the data 32 is stored in the cache memory 20 and the data 30 is stored in the non-volatile memory 21, the latency 35 time is one time before the transfer of the data 30. When one data 30 is replaced with four data 32, the transfer time of the four data 32 and the data 30 having the same data size is delayed by T0, which corresponds to the latency of three times. As described above, when the large size data 30 is stored in the cache memory 20 and replaced with a plurality of small size data 32, the data transfer becomes slow.

In the first embodiment, as described above, the problem of exceeding the read limit number of times of the non-volatile memory 21 in a short time and / or slowing down the data transfer is solved.

Hereinafter, the operation of the storage device according to the first embodiment will be described. FIG. 5 is a flowchart showing the control of the cache control unit in the embodiment. As shown in FIG. 5, the cache control unit 24 receives a read command for reading the data in the non-volatile memory 21 (step S10). For example, when the processor 25 receives the read command output by the host device 28 from the I / F control unit 26, the processor 25 outputs a command to cause the cache control unit 24 to read the data in the non-volatile memory 21.

The cache control unit 24 determines whether the data to be read has been registered in the cache memory 20 (step S12). In the case of Yes, the cache control unit 24 transfers the data in the cache memory 20 to the host device (step S14). For example, the cache control unit 24 causes the RAM control unit 22 to read data from the cache memory 20, and transfers the read data to the host device 28 via the I / F control unit 26. Then it ends.

If No in step S12, the cache control unit 24 reads data from the non-volatile memory 21 (step S16). The cache control unit 24 transfers the read data to the host device 28 (step S18). The cache control unit 24 determines whether the size of the read data is the threshold value S1 or more (step S20). When Yes, the cache control unit 24 ends without registering the cache. When No, the cache control unit 24 registers the read data in the cache memory 20 (step S22). For example, the cache control unit 24 selects the data in the cache memory 20 to be replaced with the read data. The cache control unit 24 causes the RAM control unit 22 to erase the selected data from the cache memory 20. The cache control unit 24 causes the RAM control unit 22 to store the data read into the cache memory 20. For the control of the cache control unit 24, for example, LFU control or LRU control is used. The order of steps S18, S20 and S22 may be reversed, and steps S18, S20 and S22 may be executed at the same time. Then it ends.

6 (a) to 6 (c) are schematic views showing data in the non-volatile memory and the cache memory in the first embodiment. As shown in FIG. 6A, large-sized content data 30 and small-sized content data 32 are stored in the non-volatile memory 21. Data 30 to 32 are, for example, image data, audio data, lighting data, and program data. Data 32 is stored in the cache memory 20.

As shown in FIG. 6B, when the host device 28 reads out the large size data 30, the cache control unit 24 determines No in step S12 of FIG. 5 because the data 30 is not registered in the cache memory 20. To do. In steps S16 and S18, the cache control unit 24 reads the data 30 in the non-volatile memory 21 and transfers the data 30 to the host device 28 as shown by the arrow 50. In step S20, the cache control unit 24 determines that the size of the data 30 is equal to or greater than the threshold value S1. Therefore, the data 30 ends without being stored in the cache memory 20. After that, when the host device 28 accesses any of the data 32 from "1" to "8", the data 32 is registered in the cache memory 20. Therefore, in step S12, the cache control unit 24 determines Yes. As in step S14, the cache control unit 24 reads out any data 32 from “1” to “8” in the cache memory 20 and transfers the data 32 to the host device 28 as shown by the arrow 56.

As shown in FIG. 6C, when the host device 28 next reads “9” as the data 32 not stored in the cache memory 20, the cache control unit 24 determines No in step S12 of FIG. In steps S16 and S18, the cache control unit 24 reads out the data 32 of "9" in the non-volatile memory 21 and transfers the data 32 to the host device 28 as shown by the arrow 58. In step S20, the cache control unit 24 determines that the size of the data 32 is less than the threshold value S1. In step S22, the cache control unit 24 registers the cache. For example, the cache control unit 24 erases the "1" data 32 from the cache memory 20 as shown by the arrow 54, and stores the "9" data 32 in the cache memory 20 as shown by the arrow 60.

As described above, in the first embodiment, since the large size data 30 is not registered in the cache memory 20, the read limit number of the non-volatile memory 21 is exceeded in a short time, and / or the data transfer becomes slow. Can be suppressed.

[Modification 1 of Example 1]
FIG. 7 is a flowchart showing the control of the cache control unit in the first modification of the first embodiment. As shown in FIG. 7, after step S18, the cache control unit 24 determines whether the size of the read data is the threshold value S2 or more (step S24). When No, the cache control unit 24 registers the read data in the cache memory 20 (step S22).

At the time of Yes, the cache control unit 24 limits the number of data whose size is registered in the cache memory 20 to the threshold value S2 or more to the threshold value N, and registers the read data in the cache (step S26). For example, when the number of data whose size is stored in the cache memory 20 is the threshold value S2 or more is less than the threshold value N, the cache control unit 24 performs cache control such as LFU control or LRU control regardless of the size of the read data. To do. When the number of data whose size is stored in the cache memory 20 is the threshold value S2 or more is the threshold value N, the cache control unit 24 performs cache control such as LFU control or LRU control in the data whose size is the threshold value S2 or more. For example, the cache control unit 24 selects data having a size of the threshold value S2 or more in the cache memory 20 to be replaced with data having a read size of the threshold value S2 or more. The cache control unit 24 causes the RAM control unit 22 to erase the selected data from the cache memory 20. The cache control unit 24 causes the RAM control unit 22 to store the data read into the cache memory 20. The order of steps S18 and S22 to S26 may be reversed, and steps S18 and S22 to S26 may be executed at the same time. Then it ends. Other flows are the same as those in the first embodiment, and the description thereof will be omitted.

8 (a) to 8 (c) are schematic views showing data in the non-volatile memory and the cache memory in the first modification of the first embodiment. FIG. 8A is the same as FIG. 6A.

As shown in FIG. 8B, when the host device 28 reads out the large size data 30, the cache control unit 24 determines No in step S12 of FIG. 5 because the data 30 is not registered in the cache memory 20. To do. In steps S16 and S18, the cache control unit 24 reads the data 30 in the non-volatile memory 21 and transfers the data 30 to the host device 28 as shown by the arrow 50. In step S20, the cache control unit 24 determines that the size of the data 32 is equal to or greater than the threshold value S2. The large size data 30 is not stored in the cache memory 20. Therefore, in step S26, the cache control unit 24 determines that the data 30 registered in the cache is less than the threshold value N. In step S22, the cache control unit 24 registers the cache. For example, the cache control unit 24 erases the data 32 of "1" to "4" from the cache memory 20 as shown by the arrow 54, and stores the data 30 of "10" in the cache memory 20 as shown by the arrow 52.

As shown in FIG. 8C, when the host device 28 next reads the large size data 30, the cache control unit 24 transfers the read “11” data 30 to the arrow 50 as in step S18. Transfer to the host device 28 as described above. In step S20, the cache control unit 24 determines that the size of the data 32 is equal to or greater than the threshold value S2. N threshold values of data 30 having a large size are stored in the cache memory 20. Therefore, in step S26, the cache control unit 24 selects one of the large size data 30. The data 30 of "10" selected as shown by the arrow 54 is deleted from the cache memory 20, and the data 30 of "11" is stored in the cache memory 20 as shown by the arrow 52.

In the first modification of the first embodiment, more than N pieces of the large size data 30 are not registered in the cache memory 20. Therefore, it is possible to prevent the non-volatile memory 21 from exceeding the read limit number of times in a short time and / or slowing down the data transfer. Further, since the frequently accessed large-sized data 30 is registered in the cache memory 20, the frequently accessed large-sized data 30 can be read out at a higher speed than in the first embodiment.

[Modification 2 of Example 1]
9 (a) is a schematic diagram showing the non-volatile memory in the second modification of the first embodiment, and FIG. 9 (b) is a diagram showing the threshold values S1, S2 and N in each region. As shown in FIG. 9A, the non-volatile memory 21 is divided into a plurality of areas A to C. Areas A to C are divided according to, for example, the type of data. For example, the area A stores image data, the area B stores audio data, and the area C stores program data. Areas A to C may be separated by other types.

As shown in FIG. 9B, the threshold values S1, S2, and N are set to be different depending on the regions A to C. S1 of regions A to C are 128KB, 32KB and 32KB, respectively. S2 of regions A to C are 64KB, 16KB and 16KB, respectively. The Ns of regions A to C are 4, 16 and 32, respectively.

FIG. 10 is a flowchart showing the control of the cache control unit in the second modification of the first embodiment. As shown in FIG. 10, after step S18, the cache control unit 24 selects the read data area (step S28). The cache control unit 24 determines whether the size of the read data is equal to or greater than the threshold value S1 (step S20). If Yes, it ends. When No, the same operation as in steps S22 to S26 of FIG. 8 of the modified example 1 of the first embodiment is performed. The order of steps S18 and S20 to 26 may be reversed, and steps S18 and S20 to S26 may be executed at the same time. Then it ends. Other controls are the same as those of the first embodiment and the first modification of the first embodiment, and the description thereof will be omitted.

In the second modification of the first embodiment, when data having a size equal to or larger than the threshold value S1 is stored in the cache memory 20, a large amount of data having a small size is replaced. Therefore, the data having the threshold value S1 or more is not stored in the cache memory 20. The data whose size is less than the threshold value S1 and whose size is S2 or more includes data whose access frequency is higher than that of the data whose size is the threshold value S1 or more. Therefore, the number of data stored in the cache memory 20 is limited, and data is stored in the cache memory 20. As a result, frequently accessed data can be read at high speed.

Further, the threshold values S1, S2 and N can be set for each of the areas A to C. The relationship between the data, the size, and the access frequency of the game machine data differs depending on the data type such as image data, voice data, lighting data, and program data. Therefore, the threshold values S1, S2, and N are set for each type of data. As a result, cache control can be performed more appropriately depending on the type of data.

For example, consider a case where image data has a high access frequency of data of 16 Kbytes or less, and audio data has a high access frequency of data of 4 Kbytes or less. In this case, the cache control unit 24 preferentially stores 16 Kbytes or less of data in the cache memory 20 for image data, and preferentially stores 4 Kbytes or less of audio data in the cache memory 20. Can be done. In this way, threshold values having different sizes are set for each type of data, and when the data size is equal to or less than the threshold value, the data can be stored in the cache memory 20.

Further, as another example, the areas A to C may be set for each scene of the game machine. A scene is, for example, a set of a background and a small image part displayed on the background, and different scenes have different relationships between data size and access frequency. Therefore, the threshold values S1, S2, and N are set for each scene. As a result, cache control can be performed more appropriately depending on the scene. The data included in the areas A to C may be only image data, or image data, audio data, lighting data, and the like may be mixed in the areas A to C.

According to the first embodiment and its modifications, the cache control unit 24 (control unit) reads out the game machine data stored in the non-volatile memory 21 as in step S16 of FIGS. 5, 7, and 10. .. As in steps S20 to S26, when the size of the read data is less than the threshold value S1 or S2 (first size), the data is preferentially registered in the cache memory 20 over when the size of the data is the threshold value S1 or S2 or more. As a result, data having a relatively small size is registered in the cache memory 20. Therefore, it is possible to prevent the non-volatile memory 21 from exceeding the read limit number of times in a short time and / or slowing down the data transfer.

Further, as in steps S20 and S22 in FIG. 5 of the first embodiment, the cache control unit 24 does not register data in the cache memory 20 when the read size is equal to or larger than the threshold value S1 (first size). When the size of the read data is less than the threshold value S1, the cache control unit 24 registers the data in the cache memory 20. As a result, the data having the threshold value S1 or more is not registered in the cache memory 20. Therefore, it is possible to prevent the non-volatile memory 21 from exceeding the read limit number of times in a short time and / or slowing down the data transfer.

Further, as in steps S22, S24 and S26 in FIG. 7 of the first modification of the first embodiment, the cache control unit 24 determines the number of data whose size registered in the cache memory 20 is the threshold value S2 (first size) or more. It is limited to the threshold value N (predetermined number) or less. As a result, since more than N large-sized data are not registered in the cache memory 20, it is possible to prevent the non-volatile memory 21 from exceeding the read limit number of times in a short time and / or slowing down the data transfer. ..

Further, as in the modification 1 of the first embodiment, the cache control unit 24 has the number of data whose read data size is the threshold value S2 or more and the size registered in the cache memory 20 is the threshold value S2 or more. When there are N thresholds, the read data is replaced with at least one of the data whose size registered in the cache memory 20 is the threshold S2 or more, and is not replaced with the data whose size is less than the threshold S2. Thereby, the number of data whose size stored in the cache memory 20 is equal to or larger than the threshold value S2 can be limited to the threshold value N. As a result, among the large size data, the frequently accessed data can be stored in the cache memory 20. Therefore, the data transfer speed can be improved.

The cache control of the first embodiment is advantageous when the access frequency of large-sized data is low. On the other hand, the cache control of the first modification of the first embodiment is advantageous when the data having a high access frequency is included in the large size data. The thresholds S1, S2 and N can be set based on the correlation between the size of the data and the access frequency. For example, the threshold values S1 and S2 are set to the sizes before and after the access frequency sharply decreases as the size of the data increases. For example, if there are many frequently accessed data in a large size data, the threshold value N is increased, and if the data is small, the threshold value N is decreased. The threshold value N is 1 or more.

Further, as in steps S20 to S26 in FIG. 10 of the second modification of the first embodiment, the cache control unit 24 does not register the read data in the cache when the size of the read data is equal to or larger than the threshold value S1. In addition, the cache control unit 24 limits the number of game machine data whose size registered in the cache memory 20 is less than the threshold value S1 and equal to or larger than the threshold value S2 (second size) to N or less. As a result, the data whose size is equal to or larger than the threshold value S1 and whose access frequency is the lowest is not registered in the cache memory 20. Data having a size less than S1 and S2 or more may include frequently accessed data. Data having such a medium size and high access frequency can be stored in the cache memory 20. Therefore, the data transfer speed can be improved.

Further, in the cache control unit 24, the number of data whose size of the read data is less than the threshold value S1 and the threshold value S2 or more and the size registered in the cache memory 20 is less than the threshold value S1 and the threshold value S2 or more is the threshold value N. At this time, the read data is replaced with at least one of the data whose size registered in the cache memory 20 is less than the threshold value S1 and the threshold value S2 or more, and is not replaced with the data having a size less than the threshold value S2. As a result, the number of data 30 whose size stored in the cache memory 20 is less than the threshold value S1 and equal to or larger than the threshold value S2 can be limited to the threshold value N. As a result, among the medium-sized data, the frequently accessed data can be stored in the cache memory 20. Therefore, the data transfer speed can be improved.

Further, as shown in FIGS. 9A and 9B, the non-volatile memory 21 includes a plurality of areas A to C, corresponds to the plurality of areas A to C, and a threshold value S1 or S2 is set. There is. As described above, S1 or S2 corresponding to at least two regions A and B among the plurality of regions A to C are different. As a result, cache control can be appropriately performed for each of the areas A to C.

In the second modification of the first embodiment, an example in which at least one of the threshold values S1, S2 and N is different in at least two regions from the regions A to C has been described. In the first embodiment, the threshold value S1 may be different in at least two regions out of the plurality of regions. In the first modification of the first embodiment, at least one of the threshold values S2 and N may be different in at least two of the plurality of regions.

In the first embodiment and its modifications, the flash memory has been described as an example of the non-volatile memory 21, but the non-volatile memory 21 may be a memory other than the flash memory. When the non-volatile memory 21 is a flash memory, the read disturb caused by the high frequency access of the same data can be suppressed. Image data, audio data, and program data have been described as examples of data types, but the data types are not limited to these.

Although the examples of the present invention have been described in detail above, the present invention is not limited to the specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10 Storage device 20 Cache memory 21 Non-volatile memory 30 Large size data 32 Small size data

Claims (8)

Non-volatile memory for storing game machine data and
A cache memory for storing the game machine data and
Based on a command from the host device of the game machine, the game machine data stored in the non-volatile memory or the cache memory is read, the read game machine data is transferred to the host device, and the read game machine data is transferred from the non-volatile memory. When the read game machine data is less than the first size, the read game machine data is preferentially stored in the cache memory than when the read game machine data is the first size or more. The control unit to be registered and
Equipped with
The data for a game machine, the image data of the image displayed on the display device of the gaming machine, viewed including the audio data is data of a sound output from the sound output device of the gaming machine, at least one of,
The non-volatile memory includes a plurality of areas.
The first size is set corresponding to the plurality of areas,
A storage device for a game machine, characterized in that the first size corresponding to at least two regions out of the plurality of regions is different . The control unit
When the read game machine data is the first size or larger, the read game machine data is not registered in the cache memory.
The storage device for a game machine according to claim 1, wherein when the read data for the game machine is smaller than the first size, the read data for the game machine is registered in the cache memory. The storage device for a game machine according to claim 1, wherein the control unit limits the number of data for a game machine of the first size or larger registered in the cache memory to a predetermined number or less. When the read data for the game machine is the first size or more and the number of data for the game machine of the first size or more registered in the cache memory is the predetermined number, the control unit may use the control unit. The storage device for a game machine according to claim 3, wherein the read data for the game machine is replaced with at least one of the data for the game machine of the first size or larger registered in the cache memory. 2. The control unit is characterized in that the number of data for a game machine of a second size or larger, which is smaller than the first size and smaller than the first size, registered in the cache memory is limited to a predetermined number or less. The described gaming machine storage device. In the control unit, the read game machine data is less than the first size and the second size or more, and the game is less than the first size and the second size or more registered in the cache memory. When the number of machine data is the predetermined number, the read game machine data is used as at least one of the game machine data of less than the first size and the second size or more registered in the cache memory. The storage device for a game machine according to claim 5, wherein the storage device is replaced. Non-volatile memory for storing game machine data and
A cache memory for storing the game machine data and
The game machine data stored in the non-volatile memory is read, and when the read game machine data is less than the first size, priority is given to the read game machine data having the first size or more. A control unit that registers the read game machine data in the cache memory, and
Equipped with
The non-volatile memory includes a plurality of areas.
The first size is set corresponding to the plurality of areas,
A storage device for a game machine, characterized in that the first size corresponding to at least two regions out of the plurality of regions is different. When the image data read from the non-volatile memory is less than the first size, the control unit preferentially reads the read image data over when the read image data is the first size or more. The storage device for a game machine according to any one of claims 1 to 7, wherein the data is registered in the cache memory.

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